Linux_SDK_V1.5.4

Signed-off-by: thead_admin <occ_thead@service.alibaba.com>

Kconfig

@@ -302,7 +302,7 @@ menu "Boot images"
 
 config ANDROID_BOOT_IMAGE
 	bool "Enable support for Android Boot Images"
-	default y if FASTBOOT
+	default n if FASTBOOT
 	help
 	  This enables support for booting images which use the Android
 	  image format header.

Makefile

@@ -219,7 +219,7 @@ endif
 
 ifeq ($(KBUILD_SRC),)
         # building in the source tree
-        srctree := .
+        srctree := $(shell pwd)
 else
         ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR)))
                 # building in a subdirectory of the source tree
@@ -726,6 +726,7 @@ UBOOTINCLUDE    := \
 			$(if $(CONFIG_HAS_THUMB2),, \
 				-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
 		-I$(srctree)/arch/$(ARCH)/include \
+		$(if $(CONFIG_TARGET_LIGHT_C910), -I$(srctree)/lib/sec_library/include) \
 		-include $(srctree)/include/linux/kconfig.h
 
 NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
@@ -811,7 +812,7 @@ PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`
 endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
 ifeq ($(CONFIG_TARGET_LIGHT_C910),y)
-PLATFORM_LIBS += -L $(shell pwd)/lib/sec_library -lsec_library
+PLATFORM_LIBS += -L $(srctree)/lib/sec_library -lsec_library
 endif
 
 ifdef CONFIG_CC_COVERAGE

arch/riscv/cpu/c9xx/Makefile

@@ -6,3 +6,4 @@
 
 obj-y += dram.o
 obj-y += cpu.o
+obj-y += feature.o

arch/riscv/cpu/c9xx/cpu.c

@@ -141,8 +141,9 @@ void dcache_enable(void)
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
 	asm volatile (
-        "li x29, 0x11ff\n\t"
-        "csrw mhcr, x29\n\t"
+		"csrr x29, mhcr\n\t"
+        "ori x28, x29, 0x2\n\t"
+        "csrw mhcr, x28\n\t"
     );
 #endif
 #endif

arch/riscv/cpu/c9xx/dram.c

@@ -14,9 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
 int dram_init(void)
 {
 #ifdef CONFIG_DDR_BOARD_CONFIG
-extern unsigned long get_ddr_density(void);
-	// update ram_size from board config info
-	gd->ram_size = get_ddr_density();
+	// already setup during ddr initial flow
+	gd->bd->bi_memsize = gd->ram_size;
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
 	return 0;
 #else
 	return fdtdec_setup_mem_size_base();

arch/riscv/cpu/c9xx/feature.c

@@ -0,0 +1,114 @@
+#include <common.h>
+#include <asm/types.h>
+#include <asm/asm.h>
+#include <asm/csr.h>
+
+void setup_features(void)
+{
+	unsigned int i, cpu_type, cpu_ver;
+	unsigned long version[8];
+
+	for (i = 0; i < 8; i++)
+		version[i] = csr_read(CSR_MCPUID);
+
+	cpu_type = (version[0] >> 18) & 0xf;
+	cpu_ver  = (version[1] >> 12) & 0xffff;
+
+	/*
+	 * Warning: CSR_MCCR2 contains an L2 cache latency setting,
+	 * you need to confirm it by your own soc design.
+	 */
+	switch (cpu_type) {
+	case 0x3:
+		if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) { //1.2.0~1.2.x
+			csr_write(CSR_MCCR2, 0xe0010009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x6e30c);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver == 0x10ca) { //1.3.10
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe2490009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x66e30c);
+			csr_write(CSR_MHCR, 0x17f);
+			csr_write(CSR_MHINT2, 0x420000);
+			csr_write(CSR_MHINT4, 0x410);
+		} else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) { //1.4.0~1.4.x
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe2490009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x16e30c);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) { //1.5.0~1.5.x
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe2490009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0xe6e30c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) { //1.6.0~1.6.3
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe249000b);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x1ee30c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) { //1.6.4~1.8.x
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe249000b);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x1ee30c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x11ff);
+		} else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) { //2.0.0~
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe249000b);
+			csr_write(CSR_MXSTATUS, 0x438000);
+			csr_write(CSR_MHINT, 0x31ea32c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x11ff);
+		} else {
+			while(1);
+		}
+		break;
+	case 0x4:
+		if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) {
+			csr_write(CSR_MHCR, 0x17f);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x650c);
+		} else {
+			while(1);
+		}
+		break;
+	case 0x5:
+		if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) { //0.0.0~0.0.7
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe0420008);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x2c50c);
+			csr_write(CSR_MHCR, 0x11ff);
+		} else if (cpu_ver >= 0x0040 && cpu_ver <= 0xffff) { //0.1.0~
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xa042000a);
+			csr_write(CSR_MXSTATUS, 0x438000);
+			csr_write(CSR_MHINT, 0x21aa10c);
+			csr_write(CSR_MHCR, 0x10011ff);
+		} else {
+			while(1);
+		}
+		break;
+	case 0x6:
+		if (cpu_ver >= 0x0) {
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xA042000A);
+			csr_write(CSR_MXSTATUS, 0x638001);
+			csr_write(CSR_MHINT, 0x3A1AA10C);
+			csr_write(CSR_MHCR, 0x10011BF);
+		} else {
+			while(1);
+		}
+		break;
+	default:
+		while(1);
+	}
+}

arch/riscv/cpu/cpu.c

@@ -27,6 +27,15 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
 u32 available_harts_lock = 1;
 #endif
 
+void arch_setup_gd(struct global_data *gd_ptr)
+{
+	// sync specific info from spl
+	gd_ptr->ram_size = gd->ram_size;
+
+	// setup gd ptr
+	gd = gd_ptr;
+}
+
 static inline bool supports_extension(char ext)
 {
 #ifdef CONFIG_CPU

arch/riscv/cpu/mtrap.S

@@ -104,3 +104,45 @@ trap_entry:
 	LREG x2,   2 * REGBYTES(sp)
 	addi sp, sp, 32 * REGBYTES
 	MODE_PREFIX(ret)
+
+	/* trap secondary_entry */
+	.align 10
+	.global secondary_entry
+secondary_entry:
+	/*
+	 * Clear L1 cache & BTB & BHT ...
+	 */
+	li      t0, 0x70013
+	csrw    CSR_MCOR, t0
+
+	/*
+	 * Enable cache coherency
+	 */
+	li	t0, 1
+	csrw	CSR_MSMPR, t0
+
+	/*
+	 *Prepare percpu stack
+	 */
+	csrr	t0, mhartid
+	li	t1, 0x100
+	mul	t1, t1, t0
+	lla	sp, stacks
+	add	sp, sp, t1
+
+	/*
+	 * Call C routine
+	 */
+	call	setup_features
+	call	next_stage
+
+	/*
+	 * Never get here, dead loop
+	 */
+	j .
+
+	.align 10
+stacks:
+	.rept 0x1000
+	.long
+	.endr

arch/riscv/cpu/start.S

@@ -41,6 +41,12 @@ secondary_harts_relocation_error:
 _start:
 
 #if (defined CONFIG_SPL_BUILD) && (defined CONFIG_TARGET_LIGHT_C910)
+	/* Disable indirect branch prediction once entering into uboot world */
+	li t0, 0x117f
+	csrw 0x7c1, t0
+	/* Disable fence broadcase and HW TLB */
+	li t0, 0x66e30c
+	csrw 0x7c5, t0
 	/* Enable cache ASAP as LIGHT's requirement */
 	jal	icache_enable
 	jal	dcache_enable
@@ -98,12 +104,6 @@ call_board_init_f_0:
 	mv	a0, sp
 	jal	board_init_f_alloc_reserve
 
-	/*
-	 * Set global data pointer here for all harts, uninitialized at this
-	 * point.
-	 */
-	mv	gp, a0
-
 	/* setup stack */
 #ifdef CONFIG_SMP
 	/* tp: hart id */
@@ -121,16 +121,34 @@ call_board_init_f_0:
 	la	t0, hart_lottery
 	li	s2, 1
 	amoswap.w s2, t1, 0(t0)
-	bnez	s2, wait_for_gd_init
+	beqz	s2, call_board_init_f_1
+
+	/*
+	 * Set global data pointer here for secondary harts, uninitialized at this
+	 * point.
+	 */
+	mv	gp, a0
+
+	jal wait_for_gd_init
 #else
-	bnez	tp, secondary_hart_loop
+	beqz	tp, call_board_init_f_1
+
+	/*
+	 * Set global data pointer here for secondary harts, uninitialized at this
+	 * point.
+	 */
+	mv	gp, a0
+
+	jal secondary_hart_loop
 #endif
 
+call_board_init_f_1:
 #ifdef CONFIG_OF_PRIOR_STAGE
 	la	t0, prior_stage_fdt_address
 	SREG	s1, 0(t0)
 #endif
 
+	 /* Set global data pointer here for main hart */
 	jal	board_init_f_init_reserve
 
 	/* save the boot hart id to global_data */

arch/riscv/dts/Makefile

@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
-dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb
 
 targets += $(dtb-y)
 

arch/riscv/dts/light-a-val.dts

@@ -1,4 +1,7 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -306,8 +309,8 @@
 			spi-max-frequency = <100000000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			flash@0 {
-				compatible = "jedec,spi-nor";
+			tpm@0{
+				compatible = "z32h330tc,z32h330tc-spi";
 				reg = <0>;
 				spi-max-frequency = <40000000>;
 			};
@@ -359,6 +362,20 @@
 			};
 		};
 
+		usb: usb@ffe7040000 {
+			compatible = "snps,dwc3";
+			reg = <0xff 0xe7040000 0x0 0x10000>;
+			interrupts = <68>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			maximum-speed = "super-speed";
+			dr_mode = "host";
+			dma-mask = <0xf 0xffffffff>;
+			snps,usb3_lpm_capable;
+			snps,usb_sofitpsync;
+			status = "okay";
+		};
+
 		pwm: pwm@ffec01c000 {
 			compatible = "thead,pwm-light";
 			reg = <0xff 0xec01c000 0x0 0x4000>;
@@ -479,6 +496,430 @@
 			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
 			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "dialog,da9063,v1";
+			  pmic-addr = <0x5a 0x5b>;
+			  pmic_wdt_on;
+			  errio_gpio = <0 14 3>;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "dialog,da9121,v1";
+			  pmic-addr = <0x68>;
+			  status = "okay";
+			};
+
+			pmic_dev_2: pmic-dev@2 {
+			  pmic-name = "dialog,slg51000,v1";
+			  pmic-addr = <0x75>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
+					auto_on_info = <0 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
+					auto_on_info = <1 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 1 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
+				};
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
+				};
+
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dovdd18_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
+					auto_on_info = <2 1 1800000>;
+					auto_off_info = <7 1>;
+				};
+			};
+
+			regu_config_13 {
+                reg_info = <&soc_vext_2v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
+					auto_on_info = <3 1 2800000>;
+					auto_off_info = <8 1>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_dvdd12_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
+					auto_on_info = <4 1 1200000>;
+					auto_off_info = <9 1>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_avdd28_scan_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>;
+					auto_on_info = <5 1 2800000>;
+					auto_off_info = <6 1>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
+                    parent_pmic_dev = <&pmic_dev_0 2 0>;
+				};
+			};
+
+			regu_config_17 {
+                reg_info = <&soc_avdd28_rgb_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO1>;
+                    auto_on_info = <6 0 2800000>;
+					auto_off_info = <0 1>;
+				};
+			};
+
+			regu_config_18 {
+                reg_info = <&soc_avdd25_ir_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO2>;
+                    auto_on_info = <7 0 2500000>;
+					auto_off_info = <1 1>;
+				};
+			};
+
+			regu_config_19 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO3>;
+					parent_pmic_dev = <&pmic_dev_0 7 0>;
+				};
+			};
+
+			regu_config_20 {
+                reg_info = <&soc_dovdd18_rgb_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO4>;
+				    auto_on_info = <8 0 1800000>;
+					auto_off_info = <2 1>;
+				};
+			};
+
+			regu_config_21 {
+                reg_info = <&soc_dvdd12_rgb_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO5>;
+				    auto_on_info = <9 0 1200000>;
+					auto_off_info = <3 1>;
+				};
+			};
+
+			regu_config_22 {
+                reg_info = <&soc_dvdd12_ir_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO6>;
+				    auto_on_info = <10 0 1200000>;
+					auto_off_info = <4 1>;
+				};
+			};
+
+			 regu_config_23 {
+                reg_info = <&soc_dovdd18_ir_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO7>;
+				    auto_on_info = <11 0 1800000>;
+					auto_off_info = <5 1>;
+				};
+			};
+		};
+	};
+
 	};
 
 	chosen {

arch/riscv/dts/light-b-product.dts

@@ -1,4 +1,7 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -469,6 +472,362 @@
 			lcd-en-gpios    = <&gpio1_porta 9 0>; /* active high */
 			lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+				status = "disabled";
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+				status = "disabled";
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				status = "disabled";
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_adc_vref_reg: soc_adc_vref {
+				regulator-name = "soc_adc_vref";
+			};
+			soc_lcd0_en_reg: soc_lcd0_en {
+				regulator-name = "soc_lcd0_en";
+			};
+			soc_vext_1v8_reg: soc_vext_1v8 {
+				regulator-name = "soc_vext_1v8";
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "ricoh,rn5t567,v0";
+			  pmic-addr = <0x31>;
+			  pmic_wdt_on;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "ricoh,rn5t567,v1";
+			  pmic-addr = <0x32>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO4>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO1>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO3>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC3>;
+					auto_on_info = <2 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC4>;
+					auto_on_info = <3 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 1 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC1>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO2>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC2>;
+				};
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC1>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO2>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO3>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO4>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO1>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_GPIO3>;
+				};
+			};
+
+			regu_config_13 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC3>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_adc_vref_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO5>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_lcd0_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO5>;
+					auto_on_info = <0 0 1800000>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_vext_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC4>;
+					auto_on_info = <1 0 1800000>;
+				};
+			};
+		};
+	};
 	};
 
 	chosen {

arch/riscv/dts/light-lpi4a.dts

@@ -0,0 +1,868 @@
+/dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_d: gpio@20 {
+				compatible = "nxp,pca9557";
+				reg = <0x18>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "okay";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		usb: usb@ffe7040000 {
+			compatible = "snps,dwc3";
+			reg = <0xff 0xe7040000 0x0 0x10000>;
+			interrupts = <68>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			maximum-speed = "super-speed";
+			dr_mode = "host";
+			dma-mask = <0xf 0xffffffff>;
+			snps,usb3_lpm_capable;
+			snps,usb_sofitpsync;
+			status = "okay";
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		jadard_jd9365da {
+			compatible      = "jadard,jd9365da-h3";
+			backlight       = <&lcd_backlight>;
+			reset-gpio     = <&pcal6408ahk_d 7 0>;
+			hsvcc-gpio   = <&pcal6408ahk_d 6 1>;
+			vspn3v3-gpio = <&pcal6408ahk_d 5 1>;
+		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "dialog,da9063,v1";
+			  pmic-addr = <0x5a 0x5b>;
+			  pmic_wdt_on;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "dialog,da9121,v1";
+			  pmic-addr = <0x68>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
+					auto_on_info = <0 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
+					auto_on_info = <1 0 800000>;
+				};
+
+				regu_id@2 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
+					auto_on_info = <2 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 2 5 30>;
+				};
+
+				coupling_info@1 {
+					negative-min;
+                    info = <1 2 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
+				};
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dovdd18_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
+					auto_on_info = <3 1 1800000>;
+					auto_off_info = <1 1>;
+				};
+			};
+
+
+			regu_config_13 {
+                reg_info = <&soc_dvdd12_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
+					auto_on_info = <4 1 1200000>;
+					auto_off_info = <2 1>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_avdd28_scan_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
+					auto_on_info = <5 1 2800000>;
+					auto_off_info = <0 1>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
+                    parent_pmic_dev = <&pmic_dev_0 2 0>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
+					parent_pmic_dev = <&pmic_dev_0 7 0>;
+				};
+			};
+		};
+	};
+
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/include/asm/arch-thead/boot_mode.h

@@ -34,7 +34,9 @@ typedef enum image_type {
 	T_ROOTFS = 4,
 	T_TF = 2,
 	T_TEE = 5,
-	T_UBOOT = 6
+	T_UBOOT = 6,
+	T_USER = 7,
+	T_SBMETA = 8,
 } img_type_t;
 
 static const char header_magic[4] = {'T', 'H', 'E', 'D'};

arch/riscv/include/asm/arch-thead/light-reset.h

@@ -0,0 +1,17 @@
+#ifndef __LIGHT_RESET_H__
+#define __LIGHT_RESET_H__
+
+#define APSYS_RSTGEN_BASE	0xFFEF014000
+#define REG_C910_SWRST		(APSYS_RSTGEN_BASE + 0x4)
+#define APSYS_REG_BASE		0xFFEF018000
+#define REG_C910_CORE0_RVBA_L	(APSYS_REG_BASE + 0x50)
+#define REG_C910_CORE0_RVBA_H	(APSYS_REG_BASE + 0x54)
+#define REG_C910_CORE1_RVBA_L	(APSYS_REG_BASE + 0x58)
+#define REG_C910_CORE1_RVBA_H	(APSYS_REG_BASE + 0x5C)
+#define REG_C910_CORE2_RVBA_L	(APSYS_REG_BASE + 0x60)
+#define REG_C910_CORE2_RVBA_H	(APSYS_REG_BASE + 0x64)
+#define REG_C910_CORE3_RVBA_L	(APSYS_REG_BASE + 0x68)
+#define REG_C910_CORE3_RVBA_H	(APSYS_REG_BASE + 0x6C)
+#define REG_PLIC_DELEGATE	0xffd81ffffc
+
+#endif /* __LIGHT_RESET_H__ */

arch/riscv/include/asm/atomic.h

@@ -0,0 +1,53 @@
+#ifndef _ASM_RISCV_ATOMIC_H
+#define _ASM_RISCV_ATOMIC_H
+
+#include <linux/types.h>
+#include <asm/barrier.h>
+
+typedef struct {
+	volatile long counter;
+} atomic_t;
+
+#define ATOMIC_INIT(_lptr, val) (_lptr)->counter = (val)
+
+#define ATOMIC_INITIALIZER(val)   \
+	{                         \
+		.counter = (val), \
+	}
+
+long atomic_read(atomic_t *atom)
+{
+	long ret = atom->counter;
+	rmb();
+	return ret;
+}
+
+void atomic_write(atomic_t *atom, long value)
+{
+	atom->counter = value;
+	wmb();
+}
+
+long atomic_add_return(atomic_t *atom, long value)
+{
+	long ret;
+#if __SIZEOF_LONG__ == 4
+	__asm__ __volatile__("	amoadd.w.aqrl  %1, %2, %0"
+			     : "+A"(atom->counter), "=r"(ret)
+			     : "r"(value)
+			     : "memory");
+#elif __SIZEOF_LONG__ == 8
+	__asm__ __volatile__("	amoadd.d.aqrl  %1, %2, %0"
+			     : "+A"(atom->counter), "=r"(ret)
+			     : "r"(value)
+			     : "memory");
+#endif
+	return ret + value;
+}
+
+long atomic_sub_return(atomic_t *atom, long value)
+{
+	return atomic_add_return(atom, -value);
+}
+
+#endif /* _ASM_RISCV_ATOMIC_H */

arch/riscv/include/asm/csr.h

@@ -104,15 +104,23 @@
 #define CSR_CYCLEH		0xc80
 #define CSR_TIMEH		0xc81
 #define CSR_INSTRETH		0xc82
+#define CSR_MVENDORID		0xf11
+#define CSR_MARCHID		0xf12
+#define CSR_MIMPID		0xf13
 #define CSR_MHARTID		0xf14
+#define CSR_MCPUID		0xfc0
 
-#define CSR_SMPEN			0x7f3
-#define CSR_MTEE			0x7f4
+#define CSR_SMPEN        0x7f3
+#define CSR_MTEE         0x7f4
 #define CSR_MCOR         0x7c2
 #define CSR_MHCR         0x7c1
 #define CSR_MCCR2        0x7c3
 #define CSR_MHINT        0x7c5
+#define CSR_MHINT2       0x7cc
+#define CSR_MHINT3       0x7cd
+#define CSR_MHINT4       0x7ce
 #define CSR_MXSTATUS     0x7c0
+#define CSR_MSMPR        0x7f3
 #define CSR_PLIC_BASE    0xfc1
 
 #define sync_is()   asm volatile (".long 0x01b0000b")

arch/riscv/include/asm/dma-mapping.h

@@ -10,6 +10,7 @@
 #define __ASM_RISCV_DMA_MAPPING_H
 
 #include <linux/dma-direction.h>
+#include "common.h"
 
 #define dma_mapping_error(x, y)	0
 

arch/riscv/lib/bootm.c

@@ -14,7 +14,11 @@
 #include <opensbi.h>
 #include <asm/byteorder.h>
 #include <asm/csr.h>
+#include <asm/io.h>
 #include <asm/smp.h>
+#include <asm/barrier.h>
+#include <asm/atomic.h>
+#include <asm/arch-thead/light-reset.h>
 #include <dm/device.h>
 #include <dm/root.h>
 #include <u-boot/zlib.h>
@@ -22,6 +26,12 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct fw_dynamic_info opensbi_info;
+static atomic_t _harts_count = ATOMIC_INITIALIZER(3);
+static ulong _load_start;
+static ulong _dtb_addr;
+static ulong _dyn_info_addr;
+
+extern void secondary_entry();
 
 __weak void board_quiesce_devices(void)
 {
@@ -81,6 +91,58 @@ static void boot_prep_linux(bootm_headers_t *images)
 	}
 }
 
+void next_stage(void)
+{
+	void (*next_entry)(unsigned long arg0,unsigned long arg1,unsigned long arg2);
+
+	next_entry	= (void (*))(_load_start);
+	ulong hartid = csr_read(CSR_MHARTID);
+
+	atomic_sub_return(&_harts_count, 1);
+	/*
+	 * set $a0 = hartid
+	 * set $a1 = $dtb_addr
+	 * set $a2 = $dyn_info_addr
+	 */
+	next_entry(hartid, _dtb_addr , _dyn_info_addr);
+}
+
+bool has_reset_sample(ulong dtb_addr)
+{
+	int node_offset;
+	node_offset = fdt_path_offset(dtb_addr, "/soc/reset-sample");
+	if (node_offset < 0) {
+		printf("## fdt has no reset_sample\n");
+		return false;
+	} else {
+		printf("## fdt has reset_sample\n");
+		return true;
+	}
+}
+
+static void reset_sample(void)
+{
+	ulong addr;
+	uint addr_l, addr_h;
+
+	// RESET ADDR
+	addr = (unsigned long)(void *)secondary_entry;
+	addr_h = (uint)(addr >> 32);
+	addr_l = (uint)(addr & 0xFFFFFFFF);
+	// writel(addr_h, (volatile void *)REG_C910_CORE0_RVBA_H);
+	// writel(addr_l, (volatile void *)REG_C910_CORE0_RVBA_L);
+	writel(addr_h, (volatile void *)REG_C910_CORE1_RVBA_H);
+	writel(addr_l, (volatile void *)REG_C910_CORE1_RVBA_L);
+	writel(addr_h, (volatile void *)REG_C910_CORE2_RVBA_H);
+	writel(addr_l, (volatile void *)REG_C910_CORE2_RVBA_L);
+	writel(addr_h, (volatile void *)REG_C910_CORE3_RVBA_H);
+	writel(addr_l, (volatile void *)REG_C910_CORE3_RVBA_L);
+
+	// RESET
+	writel(0x1F, (volatile void *)REG_C910_SWRST);
+	writel(0x1, (volatile void *)REG_PLIC_DELEGATE);
+}
+
 static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
 	void (*kernel)(ulong hart, void *dtb, struct fw_dynamic_info *p);
@@ -98,12 +160,25 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 
 	announce_and_cleanup(fake);
 
-	opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
-	opensbi_info.version = 0x1;
-	opensbi_info.next_addr = images->os.start;
-	opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
-	opensbi_info.options = 0;
-	opensbi_info.boot_hart = 0;
+	_load_start = kernel;
+	_dtb_addr = images->ft_addr;
+	_dyn_info_addr = (ulong)&opensbi_info;
+	if (!has_reset_sample(_dtb_addr)) {
+		opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
+		opensbi_info.version = 0x2;
+		opensbi_info.next_addr = images->os.start;
+		opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
+		opensbi_info.options = 0;
+		opensbi_info.boot_hart = 0;
+		reset_sample();
+	} else {
+		opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
+		opensbi_info.version = 0x1;
+		opensbi_info.next_addr = images->os.start;
+		opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
+		opensbi_info.options = 0;
+		opensbi_info.boot_hart = 0;
+	}
 
 	if (!fake) {
 		if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {

arch/riscv/lib/reset.c

@@ -5,9 +5,21 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/io.h>
+
+#define AONSYS_RSTGEN_BASE			((void __iomem *)0xFFFFF44000UL)
+#define REG_RST_REQ_EN_0			(AONSYS_RSTGEN_BASE + 0x140)
+#define WDT0_SYS_RST_REQ			(1 << 8)
 
 static __attribute__((naked))void sys_wdt_reset(void)
 {
+    uint32_t data;
+
+	/* wdt0 reset enable */
+    data = readl(REG_RST_REQ_EN_0);
+	data |= WDT0_SYS_RST_REQ;
+	writel(data, REG_RST_REQ_EN_0);
+
     asm volatile (
     "1: \n\r"
         "li      a0, 0xFFEFC30000 \n\r"
@@ -21,7 +33,7 @@ static __attribute__((naked))void sys_wdt_reset(void)
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	printf("resetting ...\n");
+    printf("resetting ...\n");
 
 	sys_wdt_reset();
 	hang();

board/thead/light-c910/Kconfig

@@ -34,19 +34,57 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
     default "light-c910"
 
+config LIGHT_BOOT_FORCE_SEQ
+	bool "light boot force sequence"
+	default n
+
 config LIGHT_SEC_UPGRADE
     bool "light secure upgrade"
     default n
 
+config LIGHT_ANDROID_BOOT_IMAGE_VAL_A
+    bool "light board-a android image"
+    default n
+
+config AVB_USE_OEM_KEY
+    bool "AVB signature with OEM key"
+    default n
+
+config AVB_ROLLBACK_ENABLE
+    bool "AVB rollback index in RPMB"
+    default n
+
+config AVB_HW_ENGINE_ENABLE
+    bool "AVB Hardware cryptographic engine enable"
+    default n
+
+config LIGHT_ANDROID_BOOT_IMAGE_VAL_B
+    bool "light board-b android image"
+    default n
+
+config LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A
+    bool "light board-lpi4a android image"
+    default n
+
+config LIGHT_ANDROID_BOOT_IMAGE_ANT_REF
+    bool "light board ant ref android image"
+    default n
+
 config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A
     bool "light board-a security boot with verification"
     default n
 
 config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B
-	bool "light board-b security boot with verification"
+    bool "light board-b security boot with verification"
+    default n
 
 config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
-	bool "light ant ref security boot with verification"
+    bool "light ant ref security boot with verification"
+    default n
+
+config LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
+    bool "light lpi4a security boot with verification"
+    default n
 
 config TARGET_LIGHT_FPGA_FM_C910
     bool "light fullmask FPGA board"
@@ -84,6 +122,10 @@ config TARGET_LIGHT_FM_C910_BEAGLE
     bool "light fullmask for beagle board "
     default n
 
+config TARGET_LIGHT_FM_C910_LPI4A
+    bool "light fullmask for Lichee Pi 4A board "
+    default n
+
 config TARGET_LIGHT_FM_C910_B_POWER
     bool "light fullmask for light-b-power board "
     default n
@@ -94,8 +136,7 @@ config SYS_TEXT_BASE
 
 config SPL_TEXT_BASE
     hex
-    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
-    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
+    default 0xffe0000800
 
 config SPL_MAX_SIZE
     hex
@@ -206,6 +247,17 @@ config DDR_LP4_2133_SINGLERANK
         help
           Enabling this will support lpddr4 2133 singlerank configuration.
 
+config DDR_DDP
+	bool "LPDDR4/4X Dual Die Package support"
+	help
+	  Enabling this will support ddr Dual Die Package configuration.
+	  e.g. to support 8GB ddr device with 17-bit row address (16:0)
+
+config FIXUP_MEMORY_REGION
+	bool "self-adapt to query and fixup memory region"
+	help
+	  Enabling this will support self-adapt to query and fixup memory region
+
 config DDR_H32_MODE
         bool "LPDDR4/4X 32bit mode configuration"
         help

board/thead/light-c910/Makefile

@@ -23,6 +23,7 @@ obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/init_ddr.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/pinmux.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/waitfwdone.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
+obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/lpddr4_init.o
 ifdef CONFIG_DDR_DBI_OFF
@@ -60,12 +61,15 @@ obj-$(CONFIG_THEAD_LIGHT_DIGITAL_SENSOR) += digital_sensor.o digital_sensor_test
 obj-y += clock_config.o
 obj-y += sec_check.o
 obj-y += boot.o
+obj-y += sbmeta/sbmeta.o
 ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
+obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 endif
 
 obj-y += light-sv/pll_io_test.o
 obj-y += light-sv/adc_test.o
 obj-y += version_rollback.o
+obj-$(CONFIG_AVB_VERIFY) += secimg_load.o
 endif

board/thead/light-c910/board.c

@@ -8,11 +8,19 @@
 #include <asm/io.h>
 #include <dwc3-uboot.h>
 #include <usb.h>
+#include <usb/xhci.h>
 #include <cpu_func.h>
+#include <abuf.h>
+#include "sec_library.h"
+
+#ifdef CONFIG_LIGHT_AON_CONF
+#include "../../../drivers/misc/light_regu.h"
+#include "dm/device.h"
+#endif
 
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
-	.maximum_speed = USB_SPEED_HIGH,
+	.maximum_speed = USB_SPEED_SUPER,
 	.dr_mode = USB_DR_MODE_PERIPHERAL,
 	.index = 0,
 };
@@ -26,6 +34,13 @@ int usb_gadget_handle_interrupts(int index)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	dwc3_device_data.base = 0xFFE7040000UL;
+
+	if (init == USB_INIT_DEVICE) {
+		dwc3_device_data.dr_mode = USB_DR_MODE_PERIPHERAL;
+	} else {
+		dwc3_device_data.dr_mode = USB_DR_MODE_HOST;
+	}
+
 	return dwc3_uboot_init(&dwc3_device_data);
 }
 
@@ -35,6 +50,28 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	return 0;
 }
 
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+
+
+	int ret = board_usb_init(index, USB_INIT_HOST);
+	if (ret != 0) {
+		puts("Failed to initialize board for USB\n");
+		return ret;
+	}
+
+	*hccr = (struct xhci_hccr *)dwc3_device_data.base;
+	*hcor = (struct xhci_hcor *)(dwc3_device_data.base +
+			HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));;
+
+	return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+	board_usb_cleanup(index, USB_INIT_HOST);
+}
+
 int g_dnl_board_usb_cable_connected(void)
 {
 	return 1;
@@ -42,17 +79,24 @@ int g_dnl_board_usb_cable_connected(void)
 #endif
 
 #ifdef CONFIG_CMD_BOOT_SLAVE
+#ifdef CONFIG_LIGHT_AON_CONF
+#define E902_AON_CONFIG_SIZE 0xC00
+#else
+#define E902_AON_CONFIG_SIZE 0x000
+#endif
 #define E902_SYSREG_START	0xfffff48044
 #define E902_SYSREG_RESET	0xfffff44024
-#define E902_START_ADDRESS	0xFFEF8000
+#define E902_START_ADDRESS	(0xFFEF8000 + E902_AON_CONFIG_SIZE)
 #define C910_E902_START_ADDRESS 0xFFFFEF8000
 #define E902_IOPMP_BASE		0xFFFFC21000
 
 #define C906_RST_ADDR_L		0xfffff48048
 #define C906_RST_ADDR_H		0xfffff4804C
-#define C906_START_ADDRESS_L	0xc0000000
-#define C906_START_ADDRESS_H	0xff
-#define C910_C906_START_ADDRESS	0xffc0000000
+
+#define C906_START_ADDRESS_L	0x32000000
+#define C906_START_ADDRESS_H	0x00
+#define C910_C906_START_ADDRESS	0x0032000000
+
 #define C906_CPR_IPCG_ADDRESS   0xFFCB000010
 #define C906_IOCTL_GPIO_SEL_ADDRESS     0xFFCB01D000
 #define C906_IOCTL_AF_SELH_ADDRESS      0xFFCB01D008
@@ -82,32 +126,160 @@ void set_c906_cpu_entry(phys_addr_t entry_h, phys_addr_t entry_l)
 
 void boot_audio(void)
 {
-        writel(0x37, (volatile void *)C906_RESET_REG);
+	writel(0x37, (volatile void *)C906_RESET_REG);
 
-        set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
-        flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
+	set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
+	flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
 
-        writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
-        writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
-        writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
+	writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
+	writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
+	writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
 
-        writel(0x3f, (volatile void *)C906_RESET_REG);
+	writel(0x3f, (volatile void *)C906_RESET_REG);
 }
 
-void boot_aon(void)
+#ifdef CONFIG_LIGHT_AON_CONF
+
+int get_and_set_aon_config_data()
 {
+	int ret =0;
+    struct udevice *dev;
+	struct mic_regu_platdata *config_data =NULL;
+
+	ret = uclass_first_device_err(UCLASS_MISC, &dev);
+	if(ret){
+        printf("get light aon config faild %d\n", ret);
+		return ret;
+	}
+
+	config_data = (struct mic_regu_platdata *)(dev->platdata);
+
+    volatile aon_config_t* read_config = (aon_config_t* )C910_E902_START_ADDRESS;
+	if(strncmp(read_config->magic , AON_CONFIG_MAGIC, strlen(AON_CONFIG_MAGIC))) {
+        printf("No aon config magic found in aon bin, please check the aon bin\n");
+		return -1;
+	}
+
+	if(strncmp(read_config->version, AON_CONFIG_VERSION, strlen(AON_CONFIG_VERSION))) {
+       printf("Err aon config version, aon bin is:%s, u-boot is:%s\n", read_config->version, AON_CONFIG_VERSION);
+	   return -1;
+	}
+
+	if(PMIC_MAX_HW_ID_NUM >  read_config->max_hw_id_num) {
+        printf("Invald max hw id num, aon bin support %d , u-boot is %d\n",read_config->max_hw_id_num, PMIC_MAX_HW_ID_NUM);
+		return -1;
+	}
+
+	/*set pmic dev info */
+	int pmic_dev_num =  config_data->pmic_list.pmic_num;
+    int pmic_dev_list_offset   = sizeof(aon_config_t);
+	uintptr_t pmic_dev_start_addr  =  C910_E902_START_ADDRESS + pmic_dev_list_offset;
+
+	int  regu_num            = config_data->regu_id_list.regu_id_num;
+	int  regu_id_list_offset = pmic_dev_list_offset + pmic_dev_num * sizeof(pmic_dev_info_t);
+	uintptr_t regu_start_addr  = C910_E902_START_ADDRESS + regu_id_list_offset;
+    int aon_bin_size  =  regu_id_list_offset + regu_num* sizeof(csi_regu_id_t);
+    if( aon_bin_size > read_config->aon_config_partition_size) {
+         printf("Invalid aon partition size, aon bin support:%d, u-boot is %d\n", read_config->aon_config_partition_size, aon_bin_size);
+		 return -1;
+	}
+
+	printf("pmic_dev_num:%d offset:%d addr:0x%10x\n",pmic_dev_num, pmic_dev_list_offset, pmic_dev_start_addr);
+
+	memcpy(pmic_dev_start_addr, config_data->pmic_list.pmic_list, pmic_dev_num * sizeof(pmic_dev_info_t));
+    printf("regu_num:%d offset:%d addr:0x%10x\n",regu_num,regu_id_list_offset, regu_start_addr);
+
+	memcpy(regu_start_addr, config_data->regu_id_list.regu_id_list, regu_num * sizeof(csi_regu_id_t));
+    
+	read_config->wakeup_flag = config_data->wakeup_flag;
+	read_config->aon_pmic.pmic_dev_num =  pmic_dev_num;
+    read_config->aon_pmic.pmic_dev_list_offset   = pmic_dev_list_offset;
+
+	/*set regu list info*/
+	read_config->aon_pmic.regu_num =  regu_num;
+	read_config->aon_pmic.regu_id_list_offset = regu_id_list_offset;
+
+    flush_cache((uintptr_t)C910_E902_START_ADDRESS, aon_bin_size);
+
+	printf("-->pmic_dev_num:%d offset:%d\n",read_config->aon_pmic.pmic_dev_num, read_config->aon_pmic.pmic_dev_list_offset);
+	printf("-->regu_num:%d offset:%d\n",read_config->aon_pmic.regu_num,read_config->aon_pmic.regu_id_list_offset);
+
+	return 0;
+}
+#endif
+
+int do_boot_aon(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_LIGHT_AON_CONF
+    int ret = 0;
+	ret = get_and_set_aon_config_data();
+	if(ret) {
+        printf("aon config and set faild %d", ret);
+		hang();
+		return ret;
+	}
+#endif
 	writel(0xffffffff, (void *)(E902_IOPMP_BASE + 0xc0));
 	disable_slave_cpu();
 	set_slave_cpu_entry(E902_START_ADDRESS);
 	flush_cache((uintptr_t)C910_E902_START_ADDRESS, 0x10000);
 	enable_slave_cpu();
+	return 0;
 }
 
+U_BOOT_CMD(
+	bootaon, CONFIG_SYS_MAXARGS, 0, do_boot_aon,
+	"Boot aon from memory  ",
+	" "
+);
+
 int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
-	boot_aon();
-	mdelay(100);
 	boot_audio();
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_BOARD_RNG_SEED
+const char pre_gen_seed[128] = {211, 134, 226, 116, 1, 13, 224, 196, 88, 213, 188, 219, 128, 41, 231, 228, 129, 123, 173, 234, 219, 79, 152, 154, 169, 27, 183, 166, 52, 21, 118, 7, 155, 89, 124, 156, 102, 92, 96, 190, 49, 28, 154, 177, 69, 129, 149, 199, 253, 66, 177, 216, 146, 73, 114, 59, 100, 41, 225, 152, 62, 88, 160, 217, 177, 28, 117, 23, 120, 213, 213, 169, 242, 111, 90, 55, 241, 239, 254, 238, 50, 175, 198, 196, 248, 56, 255, 92, 97, 224, 245, 160, 56, 149, 121, 233, 177, 239, 0, 41, 196, 214, 210, 182, 69, 44, 238, 54, 27, 236, 36, 77, 156, 234, 17, 148, 34, 16, 241, 132, 241, 230, 36, 41, 123, 157, 19, 44};
+/* Use hardware rng to seed Linux random. */
+int board_rng_seed(struct abuf *buf)
+{
+	size_t len = 128;
+	uint8_t *data = NULL;
+	int sc_err = SC_FAIL;
+
+	/* abuf is working up in asynchronization mode, so the memory usage for random data storage must
+	   be allocated first. */
+	data = malloc(len);
+	if (!data) {
+		printf("Fail to allocate memory, using pre-defined entropy\n");
+		return -1;
+	}
+
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+	/* We still use pre-define entropy data in case hardware random engine does not work */
+	sc_err = csi_sec_library_init();
+	if (sc_err != SC_OK) {
+		printf("Fail to initialize sec library, using pre-defined entropy\n");
+		goto _err;
+	}
+
+	sc_err = sc_rng_get_random_bytes(data, len);
+	if (sc_err != SC_OK) {
+		printf("Fail to retrieve random data, using pre-defined entropy\n");
+		goto _err;
+	}
+
+	abuf_init_set(buf, data, len);
+	return 0;
+
+_err:
+#endif
+	/* use pre-defined random data in case of the random engine is disable */
+	memcpy(data, pre_gen_seed, len);
+	abuf_init_set(buf, data, len);
+
+	return 0;
+}
+#endif

board/thead/light-c910/boot.c

@@ -7,26 +7,31 @@
 #include <dm.h>
 #include <fdt_support.h>
 #include <fdtdec.h>
+#include <mmc.h>
 #include <opensbi.h>
 #include <asm/csr.h>
 #include <asm/arch-thead/boot_mode.h>
 #include "../../../lib/sec_library/include/csi_efuse_api.h"
-
-
+#include "../../../lib/sec_library/include/sec_crypto_sha.h"
+#include "../../../lib/sec_library/include/kdf.h"
+#include "../../../lib/sec_library/include/sec_crypto_mac.h"
 
 #if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 
-/* The micro is used to enable NON-COT boot with non-signed image */
+/* The macro is used to enable NON-COT boot with non-signed image */
 #define LIGHT_NON_COT_BOOT	1
 
-/* The micro is used to enable uboot version in efuse */
+/* The macro is used to enable uboot version in efuse */
 #define	LIGHT_UBOOT_VERSION_IN_ENV	1
 
-/* The micro is used to enble RPMB ACCESS KEY from KDF */
+/* The macro is used to enble RPMB ACCESS KEY from KDF */
 //#define LIGHT_KDF_RPMB_KEY	1
 
+/* The macro is used to enable secure image version check in boot */
+//#define LIGHT_IMG_VERSION_CHECK_IN_BOOT	1
+
 /* the sample rpmb key is only used for testing */
-#ifndef LIGHT_KDF_RPMB_KEY 
+#ifndef LIGHT_KDF_RPMB_KEY
 static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
 												0xbb, 0xaa, 0x99, 0x88, 0xff, 0xee, 0xdd, 0xcc, \
 												0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
@@ -34,18 +39,88 @@ static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0
 #endif
 static unsigned int upgrade_image_version = 0;
 
-int csi_rpmb_write_access_key(void) 
+#define RPMB_EMMC_CID_SIZE 16
+#define RPMB_CID_PRV_OFFSET             9
+#define RPMB_CID_CRC_OFFSET             15
+#ifdef LIGHT_KDF_RPMB_KEY
+static int tee_rpmb_key_gen(uint8_t* key, uint32_t * length)
 {
+	uint32_t data[RPMB_EMMC_CID_SIZE / 4];
+    uint8_t huk[32];
+    uint32_t huk_len;
+	struct mmc *mmc = find_mmc_device(0);
+	int i;
+	sc_mac_t mac_handle;
+	int ret = 0;
+
+	if (!mmc)
+		return -1;
+
+	if (!mmc->ext_csd)
+		return -1;
+
+	for (i = 0; i < ARRAY_SIZE(mmc->cid); i++)
+		data[i] = cpu_to_be32(mmc->cid[i]);
+	/*
+	 * PRV/CRC would be changed when doing eMMC FFU
+	 * The following fields should be masked off when deriving RPMB key
+	 *
+	 * CID [55: 48]: PRV (Product revision)
+	 * CID [07: 01]: CRC (CRC7 checksum)
+	 * CID [00]: not used
+	 */
+	memset((void *)((uint64_t)data + RPMB_CID_PRV_OFFSET), 0, 1);
+	memset((void *)((uint64_t)data + RPMB_CID_CRC_OFFSET), 0, 1);
+
+    /* Step1: Derive HUK from KDF function */
+	ret = csi_kdf_gen_hmac_key(huk, &huk_len);
+	if (ret) {
+		printf("kdf gen hmac key faild[%d]\r\n", ret);
+		return -1;
+	}
+
+    /* Step2: Using HUK and data to generate RPMB key */
+	ret = sc_mac_init(&mac_handle, 0);
+	if (ret) {
+		printf("mac init faild[%d]\r\n", ret);
+		ret = -1;
+		return -1;
+	}
+
+	/* LSB 16 bytes are used as key */
+	ret = sc_mac_set_key(&mac_handle, huk, 16);
+	if (ret) {
+		printf("mac set key faild[%d]\r\n", ret);
+		ret = -1;
+		goto func_exit;
+	}
+
+	ret = sc_mac_calc(&mac_handle, SC_SHA_MODE_256, (uint8_t *)&data, sizeof(data), key, length);
+	if (ret) {
+		printf("mac calc faild[%d]\r\n", ret);
+		ret = -1;
+		goto func_exit;
+	}
+
+func_exit:
+	sc_mac_uninit(&mac_handle);
+
+	return ret;
+
+}
+#endif
+
+int csi_rpmb_write_access_key(void)
+{
+#ifdef LIGHT_KDF_RPMB_KEY
     unsigned long *temp_rpmb_key_addr = NULL;
     char runcmd[64] = {0};
     uint8_t blkdata[256] = {0};
-    uint8_t kdf_rpmb_key[32];
-	uint32_t kdf_rpmb_key_length = 0;
+    __attribute__((__aligned__(8))) uint8_t kdf_rpmb_key[32];
+    uint32_t kdf_rpmb_key_length = 0;
 	int ret = 0;
-
-#ifdef LIGHT_KDF_RPMB_KEY
     /* Step1: retrive RPMB key from KDF function */
-	ret = csi_kdf_gen_hmac_key(kdf_rpmb_key, &kdf_rpmb_key_length);
+	ret = tee_rpmb_key_gen(kdf_rpmb_key, &kdf_rpmb_key_length);
 	if (ret != 0) {
 		return -1;
 	}
@@ -79,13 +154,16 @@ int csi_tf_get_image_version(unsigned int *ver)
 {
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
 
 	/* tf version reside in RPMB block#0, offset#16*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
-	run_command(runcmd, 0);
-	*ver = (blkdata[16] << 8) + blkdata[17];
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[16] << 8) + blkdata[17];
+	}
 
-	return 0;
+	return ret;
 }
 
 int csi_tf_set_image_version(unsigned int ver)
@@ -101,9 +179,9 @@ int csi_tf_set_image_version(unsigned int ver)
 	blkdata[17] = ver & 0xFF;
 
 	/* tf version reside in RPMB block#0, offset#16*/
-#ifndef LIGHT_KDF_RPMB_KEY 
+#ifndef LIGHT_KDF_RPMB_KEY
 	temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
-#else 
+#else
 	uint8_t kdf_rpmb_key[32];
 	uint32_t kdf_rpmb_key_length = 0;
 	int ret = 0;
@@ -129,13 +207,16 @@ int csi_tee_get_image_version(unsigned int *ver)
 {
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
 
 	/* tf version reside in RPMB block#0, offset#0*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
-	run_command(runcmd, 0);
-	*ver = (blkdata[0] << 8) + blkdata[1];
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[0] << 8) + blkdata[1];
+	}
 
-	return 0;
+	return ret;
 }
 
 int csi_kernel_get_image_version(unsigned int *ver)
@@ -164,9 +245,9 @@ int csi_tee_set_image_version(unsigned int ver)
 	blkdata[1] = ver & 0xFF;
 
 	/* tf version reside in RPMB block#0, offset#16*/
-#ifndef LIGHT_KDF_RPMB_KEY 
+#ifndef LIGHT_KDF_RPMB_KEY
 	temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
-#else 
+#else
 	uint8_t kdf_rpmb_key[32];
 	uint32_t kdf_rpmb_key_length = 0;
 	int ret = 0;
@@ -187,6 +268,57 @@ int csi_tee_set_upgrade_version(void)
 	return csi_tee_set_image_version(upgrade_image_version);
 }
 
+int csi_sbmeta_get_image_version(unsigned int *ver)
+{
+	char runcmd[64] = {0};
+	unsigned char blkdata[256];
+	int ret = 0;
+
+	/* sbmeta version reside in RPMB block#0, offset#48*/
+	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[48] << 8) + blkdata[49];
+	}
+
+	return ret;
+}
+
+int csi_sbmeta_set_image_version(unsigned int ver)
+{
+	char runcmd[64] = {0};
+	unsigned char blkdata[256];
+	unsigned long *temp_rpmb_key_addr = NULL;
+
+	/* sbmeta version reside in RPMB block#0, offset#48*/
+	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
+	run_command(runcmd, 0);
+	blkdata[48] = (ver & 0xFF00) >> 8;
+	blkdata[49] = ver & 0xFF;
+	/* sbmeta version reside in RPMB block#0, offset#48*/
+#ifndef LIGHT_KDF_RPMB_KEY
+	temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
+#else
+	uint8_t kdf_rpmb_key[32];
+	uint32_t kdf_rpmb_key_length = 0;
+	int ret = 0;
+	ret = csi_kdf_gen_hmac_key(kdf_rpmb_key, &kdf_rpmb_key_length);
+	if (ret != 0) {
+		return -1;
+	}
+	temp_rpmb_key_addr = (unsigned long *)kdf_rpmb_key;
+#endif
+	sprintf(runcmd, "mmc rpmb write 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
+	run_command(runcmd, 0);
+
+	return 0;
+}
+
+int csi_sbmeta_set_upgrade_version(void)
+{
+	return csi_sbmeta_set_image_version(upgrade_image_version);
+}
+
 int csi_uboot_get_image_version(unsigned int *ver)
 {
 #ifdef	LIGHT_UBOOT_VERSION_IN_ENV
@@ -214,7 +346,7 @@ int csi_uboot_get_image_version(unsigned int *ver)
 	unsigned int ver_x = 0;
 	int ret = 0;
 
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse api init fail \n");
 		return -1;
@@ -240,7 +372,6 @@ int csi_uboot_set_image_version(unsigned int ver)
 	//TODO
 	unsigned long long uboot_ver = 0;
 	unsigned char ver_x = (ver & 0xff00) >> 8;
-    char ver_str[32] = {0};
 
 	uboot_ver = env_get_hex("uboot_version", 0xffffffffffffffff);
 
@@ -263,7 +394,7 @@ int csi_uboot_set_image_version(unsigned int ver)
 		return 0;
 	}
 
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse api init fail \n");
 		return -1;
@@ -320,6 +451,109 @@ int verify_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
 	return 0;
 }
 
+int check_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
+{
+	unsigned char new_ver_x = 0, new_ver_y = 0;
+	unsigned char cur_ver_x = 0, cur_ver_y = 0;
+
+	/* Get secure version X from image version X.Y */
+	new_ver_x = (new_ver & 0xFF00) >> 8;
+	new_ver_y = new_ver & 0xFF;
+	cur_ver_x = (cur_ver & 0xFF00) >> 8;
+	cur_ver_y = cur_ver & 0xFF;
+
+    (void)new_ver_y;
+    (void)cur_ver_y;
+
+	/* Ensure image version must be less than expected version */
+	if (new_ver_x < cur_ver_x) {
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_tf_version_in_boot(unsigned long tf_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+	
+	img_version = get_image_version(tf_addr);
+	if (img_version == 0) {
+		printf("get tf image version fail\n");
+		return -1;
+	}
+
+	ret = csi_tf_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get tf expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_tee_version_in_boot(unsigned long tee_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+	
+	img_version = get_image_version(tee_addr);
+	if (img_version == 0) {
+		printf("get tee image version fail\n");
+		return -1;
+	}
+
+	ret = csi_tee_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get tee expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_sbmeta_version_in_boot(unsigned long sbmeta_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+
+	img_version = get_image_version(sbmeta_addr);
+	if (img_version == 0) {
+		printf("get sbmeta image version fail\n");
+		return -1;
+	}
+
+	ret = csi_sbmeta_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get sbmeta expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 int light_vimage(int argc, char *const argv[])
 {
 	int ret = 0;
@@ -327,14 +561,14 @@ int light_vimage(int argc, char *const argv[])
 	unsigned int new_img_version = 0;
 	unsigned int cur_img_version = 0;
     char imgname[32] = {0};
-    
-	if (argc < 3) 
+
+	if (argc < 3)
 		return CMD_RET_USAGE;
-	
+
 	/* Parse input parameters */
 	vimage_addr = simple_strtoul(argv[1], NULL, 16);
 	strcpy(imgname, argv[2]);
-	
+
 	/* Retrieve desired information from image header */
 	new_img_version = get_image_version(vimage_addr);
 	if (new_img_version == 0) {
@@ -368,13 +602,20 @@ int light_vimage(int argc, char *const argv[])
 			printf("Get kernel img version fail\n");
 			return CMD_RET_FAILURE;
 		}
-	} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
+	} else if (strcmp(imgname, SBMETA_PART_NAME) == 0){
+
+		ret = csi_sbmeta_get_image_version(&cur_img_version);
+		if (ret != 0) {
+			printf("Get sbmeta img version fail\n");
+			return CMD_RET_FAILURE;
+		}
+	}  else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
 		ret = csi_uboot_get_image_version(&cur_img_version);
 		if (ret != 0) {
 			printf("Get uboot img version fail\n");
 			return CMD_RET_FAILURE;
-		} 
-		
+		}
+
 		// Check uboot maximization version > 64
 		if (((new_img_version & 0xFF00) >> 8) > UBOOT_MAX_VER) {
 			printf("UBOOT Image version has reached to max-version\n");
@@ -422,6 +663,11 @@ int light_vimage(int argc, char *const argv[])
 		if (ret != 0) {
 			return CMD_RET_FAILURE;
 		}
+	} else if (strcmp(imgname, SBMETA_PART_NAME) == 0) {
+		ret = verify_customer_image(T_SBMETA, vimage_addr);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
 	} else {
 		printf("Error: unknow image name\n");
 		return CMD_RET_FAILURE;
@@ -435,10 +681,8 @@ int light_secboot(int argc, char * const argv[])
 	int ret = 0;
 	unsigned long tf_addr = LIGHT_TF_FW_ADDR;
 	unsigned long tee_addr = LIGHT_TEE_FW_ADDR;
-    unsigned long kernel_addr = LIGHT_KERNEL_ADDR;
 	unsigned int tf_image_size = 0;
 	unsigned int tee_image_size = 0;
-	unsigned int kernel_image_size = 0;
 
 	printf("\n\n");
 	printf("Now, we start to verify all trust firmware before boot kernel !\n");
@@ -454,6 +698,13 @@ int light_secboot(int argc, char * const argv[])
 
 	/* Step1. Check and verify TF image */
 	if (image_have_head(LIGHT_TF_FW_TMP_ADDR) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		printf("check TF version in boot \n");
+		ret = check_tf_version_in_boot(LIGHT_TF_FW_TMP_ADDR);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
 
 		printf("Process TF image verification ...\n");
 		ret = verify_customer_image(T_TF, LIGHT_TF_FW_TMP_ADDR);
@@ -479,6 +730,14 @@ int light_secboot(int argc, char * const argv[])
 
 	/* Step2. Check and verify TEE image */
 	if (image_have_head(tee_addr) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		printf("check TEE version in boot \n");
+		ret = check_tee_version_in_boot(tee_addr);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
+
 		printf("Process TEE image verification ...\n");
 		ret = verify_customer_image(T_TEE, tee_addr);
 		if (ret != 0) {
@@ -529,16 +788,40 @@ void sec_firmware_version_dump(void)
 	unsigned int tf_ver = 0;
 	unsigned int tee_ver = 0;
 	unsigned int uboot_ver = 0;
+	unsigned int sbmeta_ver = 0;
+	unsigned int tf_ver_env = 0;
+	unsigned int tee_ver_env = 0;
+	unsigned int sbmeta_ver_env = 0;
 
 	csi_uboot_get_image_version(&uboot_ver);
 	csi_tf_get_image_version(&tf_ver);
 	csi_tee_get_image_version(&tee_ver);
+	csi_sbmeta_get_image_version(&sbmeta_ver);
+	/* Keep sync with version in RPMB, the Following version could be leveraged by OTA client */
+	tee_ver_env = env_get_hex("tee_version", 0);
+	tf_ver_env = env_get_hex("tf_version", 0);
+	sbmeta_ver_env = env_get_hex("sbmeta_version", 0);
+	if ((tee_ver_env != tee_ver) && (tee_ver != 0)) {
+		env_set_hex("tee_version", tee_ver);
+		run_command("saveenv", 0);
+	}
+
+	if ((tf_ver_env != tf_ver) && (tf_ver != 0)) {
+		env_set_hex("tf_version", tf_ver);
+		run_command("saveenv", 0);
+	}
+
+	if ((sbmeta_ver_env != sbmeta_ver) && (sbmeta_ver != 0)) {
+		env_set_hex("sbmeta_version", sbmeta_ver);
+		run_command("saveenv", 0);
+	}
 
 	printf("\n\n");
 	printf("Secure Firmware image version info: \n");
 	printf("uboot Firmware v%d.0\n", (uboot_ver & 0xff00) >> 8);
 	printf("Trust Firmware v%d.%d\n", (tf_ver & 0xff00) >> 8, tf_ver & 0xff);
 	printf("TEE OS v%d.%d\n", (tee_ver & 0xff00) >> 8, tee_ver & 0xff);
+	printf("SBMETA v%d.%d\n", (sbmeta_ver & 0xff00) >> 8, sbmeta_ver & 0xff);
 	printf("\n\n");
 }
 
@@ -546,6 +829,8 @@ void sec_upgrade_thread(void)
 {
 	const unsigned long temp_addr=0x200000;
 	char runcmd[80];
+    uint8_t * image_buffer = NULL;
+    uint8_t * image_malloc_buffer = NULL;
 	int ret = 0;
 	unsigned int sec_upgrade_flag = 0;
 	unsigned int upgrade_file_size = 0;
@@ -553,13 +838,11 @@ void sec_upgrade_thread(void)
 	sec_upgrade_flag = env_get_hex("sec_upgrade_mode", 0);
 	if (sec_upgrade_flag == 0)
 		return;
-	
 	printf("bootstrap: sec_upgrade_flag: %x\n", sec_upgrade_flag);
 	if (sec_upgrade_flag == TF_SEC_UPGRADE_FLAG) {
-		
 		/* STEP 1: read upgrade image (trust_firmware.bin) from stash partition */
 		printf("read upgrade image (trust_firmware.bin) from stash partition \n");
-		sprintf(runcmd, "ext4load mmc 0:5 0x%p trust_firmware.bin", (void *)temp_addr);
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p trust_firmware.bin", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -570,6 +853,15 @@ void sec_upgrade_thread(void)
 		upgrade_file_size = env_get_hex("filesize", 0);
 		printf("upgrade file size: %d\n", upgrade_file_size);
 
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
+
 		/* STEP 2: verify its authentiticy here */
 		sprintf(runcmd, "vimage 0x%p tf", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
@@ -581,7 +873,7 @@ void sec_upgrade_thread(void)
 
 		/* STEP 3: update tf partition */
 		printf("read upgrade image (trust_firmware.bin) into tf partition \n");
-		sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)temp_addr, upgrade_file_size);
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)image_buffer, upgrade_file_size);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -603,11 +895,15 @@ _upgrade_tf_exit:
 		run_command("saveenv", 0);
 		run_command("reset", 0);
 
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
 	} else if (sec_upgrade_flag == TEE_SEC_UPGRADE_FLAG) {
 
  		/* STEP 1: read upgrade image (tee.bin) from stash partition */
 		printf("read upgrade image (tee.bin) from stash partition \n");
-		sprintf(runcmd, "ext4load mmc 0:5 0x%p tee.bin", (void *)temp_addr);
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p tee.bin", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -618,6 +914,15 @@ _upgrade_tf_exit:
 		upgrade_file_size = env_get_hex("filesize", 0);
 		printf("TEE upgrade file size: %d\n", upgrade_file_size);
 
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
+
 		/* STEP 2: verify its authentiticy here */
 		sprintf(runcmd, "vimage 0x%p tee", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
@@ -628,8 +933,8 @@ _upgrade_tf_exit:
 		}
 
 		/* STEP 3: update tee partition */
-		printf("read upgrade image (tee.bin) into tf partition \n");
-		sprintf(runcmd, "ext4write mmc 0:4 0x%p /tee.bin 0x%x", (void *)temp_addr, upgrade_file_size);
+		printf("read upgrade image (tee.bin) into sbmeta partition \n");
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /tee.bin 0x%x", (void *)image_buffer, upgrade_file_size);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -651,7 +956,72 @@ _upgrade_tee_exit:
 		run_command("saveenv", 0);
 		run_command("reset", 0);
 
-	} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) { 
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
+	} else if (sec_upgrade_flag == SBMETA_SEC_UPGRADE_FLAG) {
+
+ 		/* STEP 1: read upgrade image (sbmeta.bin) from stash partition */
+		printf("read upgrade image (sbmeta.bin) from stash partition \n");
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p sbmeta.bin", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("SBMETA Upgrade process is terminated due to some reason\n");
+			goto _upgrade_sbmeta_exit;
+		}
+		/* Fetch the total file size after read out operation end */
+		upgrade_file_size = env_get_hex("filesize", 0);
+		printf("SBMETA upgrade file size: %d\n", upgrade_file_size);
+
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
+
+		/* STEP 2: verify its authentiticy here */
+		sprintf(runcmd, "vimage 0x%p sbmeta", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("SBMETA Image verification fail and upgrade process terminates\n");
+			goto _upgrade_sbmeta_exit;
+		}
+
+		/* STEP 3: update sbmeta partition */
+		printf("read upgrade image (SBMETA.bin) into sbmeta partition \n");
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /sbmeta.bin 0x%x", (void *)image_buffer, upgrade_file_size);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("SBMETA upgrade process is terminated due to some reason\n");
+			goto _upgrade_sbmeta_exit;
+		}
+
+		/* STEP 4: update sbmeta version */
+		ret = csi_sbmeta_set_upgrade_version();
+		if (ret != 0) {
+			printf("Set sbmeta upgrade version fail\n");
+			goto _upgrade_sbmeta_exit;
+		}
+
+		printf("\n\nSBMETA image ugprade process is successful\n\n");
+_upgrade_sbmeta_exit:
+		/* set secure upgrade flag to 0 that indicate upgrade over */
+		run_command("env set sec_upgrade_mode 0", 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
+	} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) {
 		unsigned int block_cnt;
 		struct blk_desc *dev_desc;
 		const unsigned long uboot_temp_addr=0x80000000;
@@ -660,7 +1030,7 @@ _upgrade_tee_exit:
 
 		/* STEP 1: read upgrade image (u-boot-with-spl.bin) from stash partition */
 		printf("read upgrade image (u-boot-with-spl.bin) from stash partition \n");
-		sprintf(runcmd, "ext4load mmc 0:5 0x%p u-boot-with-spl.bin", (void *)temp_addr);
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p u-boot-with-spl.bin", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {

board/thead/light-c910/clock_config.c

@@ -1146,6 +1146,7 @@ void ap_mipi_dsi1_clk_endisable(bool en)
 	writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
 }
 
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
 {
 	unsigned long div_reg;
@@ -1209,6 +1210,7 @@ static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned in
 	div_cfg |= div_en;
 	writel(div_cfg, (void __iomem *)div_reg);
 }
+#endif
 
 int clk_config(void)
 {
@@ -1218,7 +1220,7 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("C910 CPU FREQ: %ldMHz\n", rate / 1000000);
-
+#ifdef PERI_BUS_PLL_FREQ_PRINT
 	rate = clk_light_get_rate("ahb2_cpusys_hclk", CLK_DEV_MUX);
 	if (!rate)
 		return -EINVAL;
@@ -1260,6 +1262,7 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("DPU1 PLL POSTDIV FREQ: %ldMHZ\n", rate / 1000000);
+#endif
 
 #ifdef AUDIO_PLL_FREQ_PRINT
 	rate = clk_light_get_rate("audio_pll_foutpostdiv", CLK_DEV_PLL);
@@ -1302,9 +1305,9 @@ int clk_config(void)
 
 	/* The boards other than the LightA board perform the bus down-speed operation */
 
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 	ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
-	ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 15); /* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 12); /* Input frquency: 2376MHZ */
 	ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */
 	ap_multimedia_div_num_set(VI_ISP_RY_CORE_DIV, 12); /* Input frquency: 2376MHZ */
 	ap_multimedia_div_num_set(VO_DPU_CORE_DIV, 4);	/* Input frquency: 2376MHZ */

board/thead/light-c910/ddr.c

@@ -12,3 +12,17 @@ void init_ddr(void)
 {
 	writel(0x1ff << 4, (void *)0xffff005000);
 }
+
+int fixup_ddr_addrmap(unsigned long size)
+{
+	return 0;
+}
+
+int query_ddr_boundary(unsigned long size)
+{
+	return 0;
+}
+unsigned long get_ddr_density(void)
+{
+	return 0x100000000;
+}

board/thead/light-c910/light.c

@@ -11,6 +11,10 @@
 #include <thead/clock_config.h>
 #include <linux/bitops.h>
 #include <asm/arch-thead/light-iopmp.h>
+#include <memalign.h>
+#include <fdt_support.h>
+#include <fs.h>
+#include <asm/global_data.h>
 
 #define SOC_PIN_AP_RIGHT_TOP          (0x0)
 #define SOC_PIN_AP_LEFT_TOP           (0x1)
@@ -31,6 +35,7 @@
 #define GMAC0_APB3S_BADDR	0xffec003000
 #define GMAC1_APB3S_BADDR	0xffec004000
 static uint64_t apb3s_baddr;
+extern int check_image_board_id(uint8_t *image_data);
 
 typedef enum {
 	UART0_TXD = PAD_GRP_BASE_SET(SOC_PIN_AP_RIGHT_TOP),
@@ -555,12 +560,14 @@ static void gmac_phy_rst(void)
 	       (void *)LIGHT_GPIO3_BADDR);
 	writel(readl((void *)LIGHT_GPIO1_BADDR) & ~LIGHT_GPIO1_13,
 	       (void *)LIGHT_GPIO1_BADDR);
+	wmb();
 	/* At least 10ms */
-	mdelay(12);
+	mdelay(50);
 	writel(readl((void *)LIGHT_GPIO3_BADDR) | LIGHT_GPIO3_21,
 	       (void *)LIGHT_GPIO3_BADDR);
 	writel(readl((void *)LIGHT_GPIO1_BADDR) | LIGHT_GPIO1_13,
 	       (void *)LIGHT_GPIO1_BADDR);
+	wmb();
 }
 
 static void gmac_glue_init(uint64_t apb3s_baddr)
@@ -910,14 +917,14 @@ static void light_iopin_init(void)
 	light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
-#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+#if ! defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
 	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2); //soc_vdd18_lcd0_en_reg --backup regulator
 #else
 	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PU,2); //soc_vdd18_lcd0_en_reg
 #endif
 	light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2);//soc_lcd0_bias_en_reg
 	light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
-#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+#if ! defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
 	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);//reg_tp_pwr_en --touch pannel
 #else
 	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PU,2);//reg_tp_pwr_en --touch pannel
@@ -1406,17 +1413,296 @@ static void light_iopin_init(void)
 	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 }
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+static void light_iopin_init(void)
+{
+	/* aon-padmux config */
+	light_pin_cfg(I2C_AON_SCL, PIN_SPEED_NORMAL, PIN_PN, 8);
+	light_pin_cfg(I2C_AON_SDA, PIN_SPEED_NORMAL, PIN_PN, 8);
+
+	light_pin_mux(CPU_JTG_TCLK, 3);
+	light_pin_cfg(CPU_JTG_TCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(CPU_JTG_TMS, 3);
+	light_pin_cfg(CPU_JTG_TMS, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(CPU_JTG_TDI, 3);
+	light_pin_cfg(CPU_JTG_TDI, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	light_pin_mux(AOGPIO_7, 1);
+	light_pin_mux(AOGPIO_8, 1);
+	// light_pin_mux(AOGPIO_9, 0);
+	light_pin_mux(AOGPIO_10, 1);
+	light_pin_mux(AOGPIO_11, 1);
+	light_pin_mux(AOGPIO_12, 1);
+	light_pin_mux(AOGPIO_13, 1);
+	light_pin_mux(AOGPIO_14, 0);
+	// light_pin_mux(AOGPIO_15,0);
+	light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
+	light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
+	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_13, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
+	// light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(AUDIO_PA0, 0);
+	light_pin_cfg(AUDIO_PA0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA1, 0);
+	light_pin_cfg(AUDIO_PA1, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA3, 0);
+	light_pin_cfg(AUDIO_PA3, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA4, 0);
+	light_pin_cfg(AUDIO_PA4, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA5, 0);
+	light_pin_cfg(AUDIO_PA5, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA6, 0);
+	light_pin_cfg(AUDIO_PA6, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA7, 0);
+	light_pin_cfg(AUDIO_PA7, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA14, 0);
+	light_pin_cfg(AUDIO_PA14, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA15, 0);
+	light_pin_cfg(AUDIO_PA15, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA16, 0);
+	light_pin_cfg(AUDIO_PA16, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA17, 0);
+	light_pin_cfg(AUDIO_PA17, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA29, 0);
+	light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA30, 0);
+	light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2);
+	#warning "aon set to 3"
+	light_pin_mux(AUDIO_PA30, 3);
+
+	// light_pin_mux(AUDIO_PA9,3);                         ///AUDIO-PA-RESET
+	// light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_mux(AUDIO_PA10,3);                        /// AUD-3V3-EN
+	// light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
+	// light_pin_mux(AUDIO_PA12,3);                        /// AUD-1V8-EN
+	// light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
+	// light_pin_mux(AUDIO_PA13,0);
+
+	/*ap-padmux on left/top */
+	light_pin_mux(QSPI1_SCLK, 4);
+	light_pin_cfg(QSPI1_SCLK, PIN_SPEED_NORMAL,PIN_PN, 8);  ///se-spi
+	light_pin_mux(QSPI1_CSN0, 4);
+	light_pin_cfg(QSPI1_CSN0, PIN_SPEED_NORMAL, PIN_PN, 8);  ///se-spi
+	light_pin_mux(QSPI1_D0_MOSI, 4);
+	light_pin_cfg(QSPI1_D0_MOSI, PIN_SPEED_NORMAL, PIN_PU, 8);  ///se-spi
+	light_pin_mux(QSPI1_D1_MISO, 4);
+	light_pin_cfg(QSPI1_D1_MISO, PIN_SPEED_NORMAL, PIN_PU, 8);  ///se-spi
+	light_pin_mux(QSPI1_D2_WP, 4);
+	light_pin_cfg(QSPI1_D2_WP, PIN_SPEED_NORMAL, PIN_PN, 8);    ///NC
+	// light_pin_mux(QSPI1_D3_HOLD, 4);
+	// light_pin_cfg(QSPI1_D3_HOLD, PIN_SPEED_NORMAL, PIN_PN, 8);  ///NC
+
+	light_pin_cfg(I2C0_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C0_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C1_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C1_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+
+	light_pin_cfg(UART1_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART1_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_CTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_RTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(UART3_TXD, 1);
+	light_pin_cfg(UART3_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(UART3_RXD, 1);
+	light_pin_cfg(UART3_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	// light_pin_mux(GPIO0_18,1);
+	// light_pin_mux(GPIO0_19,1);
+	// light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
+	// light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
+
+	// light_pin_mux(GPIO0_20,0);
+	// light_pin_mux(GPIO0_21,0);
+	// light_pin_mux(GPIO0_22,1);
+	// light_pin_mux(GPIO0_23,1);
+	// light_pin_mux(GPIO0_24,1);
+	// light_pin_mux(GPIO0_25,1);
+	// light_pin_mux(GPIO0_26,1);
+	// light_pin_mux(GPIO0_27,0);
+	// light_pin_mux(GPIO0_28,0);
+	// light_pin_mux(GPIO0_29,0);
+	// light_pin_mux(GPIO0_30,0);
+	// light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_24, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO0_25, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO0_27, PIN_SPEED_NORMAL, PIN_PN, 2);                          ///< NC(not used)
+	light_pin_cfg(GPIO0_28, PIN_SPEED_NORMAL, PIN_PN, 2);                          ///< AVDD25_IR_EN
+	// light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2);                          ///< DVDD12_IR_EN
+	light_pin_cfg(GPIO0_30, PIN_SPEED_NORMAL, PIN_PU, 2);                          ///< gmac,uart,led
+	light_pin_cfg(GPIO0_31, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	light_pin_mux(GPIO1_0, 0);
+	// light_pin_mux(GPIO1_1,1);
+	// light_pin_mux(GPIO1_2,1);
+	light_pin_mux(GPIO1_3, 0);
+	light_pin_mux(GPIO1_4, 0);
+	light_pin_mux(GPIO1_5, 0);
+	light_pin_mux(GPIO1_6, 0);
+	light_pin_mux(GPIO1_9, 0);
+	light_pin_mux(GPIO1_10, 0);
+	// light_pin_mux(GPIO1_11,0);
+	// light_pin_mux(GPIO1_12,0);
+	light_pin_mux(GPIO1_13, 0);
+	light_pin_mux(GPIO1_14, 0);
+	// light_pin_mux(GPIO1_15,0);
+	// light_pin_mux(GPIO1_16,0);
+	light_pin_cfg(GPIO1_0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	// light_pin_cfg(GPIO1_1,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_3, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_4, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_5, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_6, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_9, PIN_SPEED_NORMAL, PIN_PN, 2);                          ///<VDD18_LCD0_EN
+	light_pin_cfg(GPIO1_10, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<LCD0_BIAS_EN
+	// light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<TOUCH-PANNEL VDD28_TP0_EN
+	light_pin_cfg(GPIO1_13, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<DOVDD18_RGB_EN
+	light_pin_cfg(GPIO1_14, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<DVDD12_RGB_EN
+	// light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<AVDD28_RGB_EN
+	// light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(CLK_OUT_0, 1);
+	light_pin_cfg(CLK_OUT_0, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_mux(CLK_OUT_1, 1);
+	light_pin_cfg(CLK_OUT_1, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_mux(CLK_OUT_2, 0);
+	light_pin_cfg(CLK_OUT_2, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_mux(CLK_OUT_3, 0);
+	light_pin_cfg(CLK_OUT_3, PIN_SPEED_NORMAL, PIN_PU, 2);
+
+	// light_pin_mux(GPIO1_21,3);
+	light_pin_mux(GPIO1_22, 3);
+	// light_pin_mux(GPIO1_23,3);
+	light_pin_mux(GPIO1_24, 3);
+	// light_pin_mux(GPIO1_25,3);
+	// light_pin_mux(GPIO1_26,3);
+	// light_pin_mux(GPIO1_27,3);
+	light_pin_mux(GPIO1_28, 0);
+	// light_pin_mux(GPIO1_29,3);
+	light_pin_mux(GPIO1_30, 0);
+	// light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_22, PIN_SPEED_NORMAL, PIN_PN,2);
+	// light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<LED_PDN
+	light_pin_cfg(GPIO1_24, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_28, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_30, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<DBB2LEDDRIVER_EN
+
+	light_pin_cfg(UART0_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART0_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	/*ap-pdmux on righ/top*/
+	// light_pin_mux(QSPI0_SCLK,3);            ///NC
+	// light_pin_mux(QSPI0_CSN0,3);            ///NC
+	// light_pin_mux(QSPI0_CSN1,3);            ///NC
+	// light_pin_mux(QSPI0_D0_MOSI,3);         ///NC
+	// light_pin_mux(QSPI0_D1_MISO,3);         ///NC
+	// light_pin_mux(QSPI0_D2_WP,3);           ///NC
+	// light_pin_mux(QSPI0_D3_HOLD,3);         ///NC
+
+	light_pin_cfg(I2C2_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C2_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C3_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C3_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+
+	// light_pin_mux(SPI_CSN,3);                                                /// W_DISABLE_CATE1
+	// light_pin_mux(SPI_MOSI,3);                                               /// NC
+	// light_pin_mux(SPI_MISO,3);                                               /// RERST1_N_CAT1
+	// light_pin_mux(SPI_SCLK,3);
+	light_pin_cfg(SPI_CSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(SPI_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(SPI_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(SPI_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	light_pin_mux(GPIO2_13, 0);
+	light_pin_mux(GPIO2_18, 1);
+	light_pin_mux(GPIO2_19, 1);
+	light_pin_mux(GPIO2_20, 1);
+	light_pin_mux(GPIO2_21, 1);
+	light_pin_mux(GPIO2_22, 1);
+	light_pin_mux(GPIO2_23, 1);
+	light_pin_mux(GPIO2_24, 1);
+	light_pin_mux(GPIO2_25, 1);
+
+	light_pin_cfg(GPIO2_13, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO2_18, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO2_19, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO2_20, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO2_21, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<NC
+	light_pin_cfg(GPIO2_22, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<WIFI_BT_GPIO2
+	light_pin_cfg(GPIO2_23, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<WIFI_BT_GPIO3
+	light_pin_cfg(GPIO2_24, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<WIFI_BT_RST_N
+	light_pin_cfg(GPIO2_25, PIN_SPEED_NORMAL, PIN_PU, 0xF);                        ///KEY1
+
+	light_pin_mux(SDIO0_DETN, 0);
+	light_pin_cfg(SDIO0_DETN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	// light_pin_mux(SDIO0_WPRTN,3);
+	// light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2);                    ///< NC
+	// light_pin_mux(SDIO1_WPRTN,3);
+	// light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);                   ///VBUS_EN
+	// light_pin_mux(SDIO1_DETN,3);
+	// light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2);                    ///WCN_33_EN
+
+	light_pin_mux(GPIO2_30, 1);
+	light_pin_mux(GPIO2_31, 1);
+	light_pin_mux(GPIO3_0, 1);
+	light_pin_mux(GPIO3_1, 1);
+	light_pin_mux(GPIO3_2, 1);
+	light_pin_mux(GPIO3_3, 1);
+	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0xF);                 ///NC
+	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0xF);                 ///NC
+	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0xF);                  ///NC
+	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+
+	light_pin_cfg(HDMI_SCL, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(HDMI_SDA, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(HDMI_CEC, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+
+	/* GMAC0 pad drive strength configurate to 0xF */
+	light_pin_cfg(GMAC0_TX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXEN, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXDV, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	// light_pin_cfg(GMAC0_MDC, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	// light_pin_cfg(GMAC0_MDIO, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+
+	light_pin_mux(GMAC0_COL, 3);
+	light_pin_mux(GMAC0_CRS, 3);
+	light_pin_cfg(GMAC0_COL, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_cfg(GMAC0_CRS, PIN_SPEED_NORMAL, PIN_PU, 2);
+}
 #else
+
 static void light_iopin_init(void)
 {
 	light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_mux(AOGPIO_10,1);
 	light_pin_mux(AOGPIO_11,1);
 	light_pin_mux(AOGPIO_12,1);
 	light_pin_mux(AOGPIO_13,1);
+	light_pin_mux(AOGPIO_14, 0);
 	light_pin_mux(AUDIO_PA30,3);
 
 	/*qspi1 cs0 gpio0-1 pad strength and pin-pull mode*/
@@ -1586,10 +1872,18 @@ static void light_usb_boot_check(void)
 	uchar env_enetaddr[6]={0};
 	uchar env_enet1addr[6]={0};
 	int env_ethaddr_flag,env_eth1addr_flag;
+	int ret = 0;
+
 	boot_mode = readl((void *)SOC_OM_ADDRBASE) & 0x7;
 	if (boot_mode & BIT(2))
 		return;
 
+	/*check board id of uboot image*/
+	ret = check_image_board_id((uint8_t*)SRAM_BASE_ADDR);
+	if (ret != 0) {
+		while(1);
+	}
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("usb_fastboot", "yes");
 #endif
@@ -1660,3 +1954,208 @@ U_BOOT_CMD(
 	"check ethaddrs in environment variables is valid",
 	""
 );
+
+
+#define PAGE_SIZE 4096
+#define HIBERNATE_SIG	"S1SUSPEND"
+#define HIBERNATE_SIG2	"S1SUSPEN2" //sign for 2nd time load image
+
+static inline int fdt_disabled_node(void *blob,const char *path)
+{
+	int offset;
+	offset = fdt_path_offset(blob,path);
+	if (offset < 0) {
+		printf("ERROR:failed to find %s node in dtb (ret %d)\n",path,offset);
+		return offset;
+	}
+	return fdt_status_disabled(blob,offset);
+}
+
+static int do_board_check_hibernate(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	int ret;
+	char runcmd[128];
+	ulong addr;
+	void *blob = NULL;
+	ulong mask = 0;
+	int mmc_parts;
+	int resume_part;
+	bool fastresume = 0;
+	#define ON_RET_ERROR(str) if(ret < 0) printf("set node %s status failed %d\n",str,ret)
+	ALLOC_CACHE_ALIGN_BUFFER(u8,swsusp_header_buf,PAGE_SIZE);
+	u8 *header = &swsusp_header_buf[0];
+
+	mmc_parts = env_get_hex("mmcpart",3);
+	resume_part = mmc_parts - 2;
+
+	if(argc >= 4) { // is user pass in ,use that
+		sprintf(runcmd, "read %s %s %s 0 8",
+			argv[1],argv[2],argv[3]);
+		header = (u8 *)simple_strtoul(argv[3],NULL,16);
+		if(argc >= 5)
+			mask = simple_strtoul(argv[4],NULL,16);
+		printf("read swsusp_header to %p,dtb disbale mask 0x%lx\n",header,mask);
+	} else {
+		sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
+			resume_part,(unsigned long)&header[0]);
+	}
+
+	ret = run_command(runcmd, 0);
+	if(ret != CMD_RET_SUCCESS)
+		goto failed;
+	if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
+		!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
+		printf("found sign\n");
+	}
+	else {
+		sprintf(runcmd, "0:%s",env_get("mmcbootpart"));
+		if(file_exists("mmc",runcmd,"no_fastresume",FS_TYPE_EXT)) {
+			printf("do not fastresume\n");
+			goto default_set;
+		}
+
+		sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
+			resume_part+1,(unsigned long)&header[0]);
+		ret = run_command(runcmd, 0);
+		if(ret != CMD_RET_SUCCESS)
+			goto failed;
+		if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
+			!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
+			printf("found fastresume sign\n");
+			resume_part = resume_part+1;
+			fastresume = true;
+		}
+		else {
+			printf(" not find hibernate sign\n");
+			goto default_set;
+		}
+	}
+
+	/*get dtb address*/
+	if(env_get("dtb_addr") == NULL)
+	{
+		printf("Cannot get dtb_addr,check flow !\n");
+		goto failed;
+	}
+	addr = env_get_hex("dtb_addr",0);
+	sprintf(runcmd, "fdt addr 0x%lx", env_get_hex("dtb_addr",0));
+	ret = run_command(runcmd, 0);
+	if(ret != CMD_RET_SUCCESS)
+		goto failed;
+	sprintf(runcmd, "fdt resize");
+	ret = run_command(runcmd, 0);
+	if(ret != CMD_RET_SUCCESS)
+		goto failed;
+
+	/*set unneed devices node disabled for hibernate resume in kernel dtb*/
+	blob = (void *)addr;
+	ret = fdt_status_disabled_by_alias(blob,"i2c0");
+	ON_RET_ERROR("i2c0");
+	ret = fdt_status_disabled_by_alias(blob,"i2c1");
+	ON_RET_ERROR("i2c1");
+	ret = fdt_status_disabled_by_alias(blob,"i2c2");
+	ON_RET_ERROR("i2c2");
+
+	ret = fdt_status_disabled_by_alias(blob,"audio_i2c0");
+	ON_RET_ERROR("audio_i2c0");
+	ret = fdt_status_disabled_by_alias(blob,"audio_i2c1");
+	ON_RET_ERROR("audio_i2c1");
+	ret = fdt_status_disabled_by_alias(blob,"ethernet0");
+	ON_RET_ERROR("ethernet0");
+	ret = fdt_status_disabled_by_alias(blob,"ethernet1");
+	ON_RET_ERROR("ethernet1");
+	ret = fdt_status_disabled_by_alias(blob,"spi0");
+	ON_RET_ERROR("spi0");
+	ret = fdt_status_disabled_by_alias(blob,"spi1");
+	ON_RET_ERROR("spi1");
+	ret = fdt_status_disabled_by_alias(blob,"spi2");
+	ON_RET_ERROR("spi2");
+
+	ret = fdt_disabled_node(blob,"/soc/adc");
+	ON_RET_ERROR("/soc/adc");
+
+	//default mask is 0, need set this node disbaled
+	if(0 == (mask & 0x01)) {
+		ret = fdt_disabled_node(blob,"/soc/light_i2s");
+		ON_RET_ERROR("/soc/light_i2s");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s0");
+		ON_RET_ERROR("/soc/audio_i2s0");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s1");
+		ON_RET_ERROR("/soc/audio_i2s1");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s2");
+		ON_RET_ERROR("/soc/audio_i2s2");
+	}
+	if(0 == (mask & 0x02)) {
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd0");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd0");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd1");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd1");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd2");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd2");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd3");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd3");
+	}
+	/*set resume_bootargs for kernel do fast bootup */
+	sprintf(runcmd,"resume=/dev/mmcblk0p%d notrace noftrace nopty noclkdebug ",resume_part);
+	env_set("resume_bootargs",runcmd);
+
+	return CMD_RET_SUCCESS;
+
+default_set:
+	sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
+	env_set("resume_bootargs",runcmd);
+	return CMD_RET_SUCCESS;
+
+failed:
+	printf("ERROR:runcmd %s failed!\n",runcmd);
+	sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
+	env_set("resume_bootargs",runcmd);
+	return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD(
+	chk_hibernate, 6, 0,	do_board_check_hibernate,
+	"check hibernate image sign,if valid set dtb nodes and bootargs for fast boot resume",
+	" [<interface> <dev[:part]>] [mask]"
+);
+
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+static int do_fixup_memory_region(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	ulong addr;
+	void *blob = NULL;
+	DECLARE_GLOBAL_DATA_PTR;
+	u64 base, size;
+
+	base = gd->ram_base;
+	size = gd->ram_size;
+
+	/*get dtb address*/
+	if(env_get("dtb_addr") == NULL)
+	{
+		printf("Cannot get dtb_addr,check flow !\n");
+		return CMD_RET_FAILURE;
+	}
+	addr = env_get_hex("dtb_addr",0);
+
+	/*set unneed devices node disabled for hibernate resume in kernel dtb*/
+	blob = (void *)addr;
+	fdtdec_setup_mem_size_base_fdt(blob);
+	size -= gd->ram_base;
+
+	if (size != gd->ram_size) {
+		printf("fixup memory region from [0x%09lx ~ 0x%09lx] to [0x%09lx ~ 0x%09lx]\n",
+				gd->ram_base, gd->ram_base+gd->ram_size, gd->ram_base, gd->ram_base+size);
+		gd->ram_size = size;
+		fdt_fixup_memory(blob, gd->ram_base, gd->ram_size);
+	}
+	return CMD_RET_SUCCESS;
+}
+U_BOOT_CMD(
+	fixup_memory_region, 2, 0,	do_fixup_memory_region,
+	"modify linux memory region via gd->ram_size",
+	""
+);
+#endif

board/thead/light-c910/lpddr-regu/ddr_regu.c

@@ -136,7 +136,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
 		REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
 	},
 };
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 /**
  * board for ant-ref
  *
@@ -165,6 +165,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
 	}
 };
 #else
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 /**
  * board for EB064A10/EB064A11
  *
@@ -183,6 +184,7 @@ static const struct regulator_t g_regu_id_list[] = {
 		REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_1V1,0x5A,0xA7,0,1,CONFIG_DDR_REGU_1V1,800000,1500000,20000,0),
 	}
 };
+#endif
 
 static const struct regulator_t g_apcpu_regu_id_list[] = {
 	{
@@ -236,7 +238,7 @@ static int wait_iic_receive(dw_iic_regs_t *iic_base, uint32_t wait_data_num, uin
 }
 
 
-unsigned long soc_get_iic_freq(uint32_t idx)
+static unsigned long soc_get_iic_freq(uint32_t idx)
 {
 	if (idx == IIC_IDX_AONIIC){
 		return 49152000U;
@@ -651,6 +653,7 @@ int32_t csi_iic_mem_receive_sr(csi_iic_t *iic, uint32_t devaddr, uint16_t memadd
     return read_count;
 }
 
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A) ||defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 static int pmic_read_reg_sr(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
 {
 	int32_t num;
@@ -662,6 +665,7 @@ static int pmic_read_reg_sr(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t off
 	*val = temp[0];
 	return 0;
 }
+#endif
 
 static int pmic_write_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t val)
 {
@@ -688,6 +692,7 @@ static int pmic_write_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offse
 	return 0;
 }
 
+#if !defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A) && !defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 static int pmic_read_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
 {
 	int32_t num;
@@ -716,6 +721,7 @@ static int pmic_read_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset
 	*val = temp[0];
 	return 0;
 }
+#endif 
 
 static int _pmic_ddr_regu_init(uint32_t idx)
 {
@@ -788,7 +794,7 @@ static void light_iopmp_config(void)
 	}
 }
 
-int pmic_ddr_regu_init(void)
+int aon_local_init(void)
 {
 #define AON_PADMUX_BASE (0xfffff4a000)
 	int ret;
@@ -818,13 +824,14 @@ int pmic_ddr_regu_init(void)
 int pmic_ddr_set_voltage(void)
 {
 	int ret = 0;
+
+#if 0 //currently,no need to modify ddr regulator voltage
 	uint32_t val = 0;
 	uint32_t regu_num = ARRAY_SIZE(g_regu_id_list);
 	uint32_t i;
 	struct regulator_t *pregu;
 	csi_iic_t          *dev_handle;
 
-#if 0 //currently,no need to modify ddr regulator voltage
 	pregu = (struct regulator_t*)g_regu_id_list;
 	for (i = 0; i < regu_num; i++, pregu++) {
 		if (pregu->regu_vol_target < pregu->regu_vol_min || pregu->regu_vol_target > pregu->regu_vol_max)
@@ -838,6 +845,10 @@ int pmic_ddr_set_voltage(void)
 #endif
 
 #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+	uint32_t val = 0;
+	struct regulator_t *pregu;
+	csi_iic_t          *dev_handle;
+
 	/*enable lcd0_en ldo*/
 	pregu = (struct regulator_t*)&g_regu_id_list[LCD0_EN];
 	dev_handle = pmic_get_iic_handle(pregu->iic_id);
@@ -944,7 +955,7 @@ int pmic_reset_apcpu_voltage(void)
 		return ret;
 	return 0;
 }
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 int pmic_reset_apcpu_voltage(void)
 {
 	int                ret = -1;

board/thead/light-c910/lpddr-regu/ddr_regu.h

@@ -9,5 +9,5 @@
 #define __DDR_REGU_H__
 
 int pmic_ddr_set_voltage(void);
-int pmic_ddr_regu_init(void);
+int aon_local_init(void);
 #endif

board/thead/light-c910/lpddr4/include/aonsys_reg_define.h

@@ -0,0 +1,218 @@
+//------------------------------------------------------------
+// DONOT MODIFY THIS FILE
+// generated by JISHENGJU automatically
+//------------------------------------------------------------
+
+#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H
+#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H
+
+#define AONSYS_REG_BASE			0xFFFFF48000
+
+#define REG_AON_CPU_LP_MODE         (AONSYS_REG_BASE + 0x0  )
+#define REG_AON_CHIP_LP_MODE        (AONSYS_REG_BASE + 0x4  )
+#define REG_AON_AO_SERAM_TRN        (AONSYS_REG_BASE + 0x10 )
+#define REG_AON_AO_SERAM_INT        (AONSYS_REG_BASE + 0x14 )
+#define REG_AON_STR_SERAM_TRN       (AONSYS_REG_BASE + 0x18 )
+#define REG_AON_STR_SERAM_INT       (AONSYS_REG_BASE + 0x1c )
+#define REG_AON_STR_INDICATOR_0     (AONSYS_REG_BASE + 0x20 )
+#define REG_AON_STR_INDICATOR_1     (AONSYS_REG_BASE + 0x24 )
+#define REG_AON_STR_INDICATOR_2     (AONSYS_REG_BASE + 0x28 )
+#define REG_AON_STR_INDICATOR_3     (AONSYS_REG_BASE + 0x2c )
+#define REG_AON_PVTC_WR_LOCK        (AONSYS_REG_BASE + 0x30 )
+#define REG_AON_PVTC_TS_ALARM       (AONSYS_REG_BASE + 0x34 )
+#define REG_AON_PVTC_VM_ALARM       (AONSYS_REG_BASE + 0x38 )
+#define REG_AON_PVTC_PD_ALARM       (AONSYS_REG_BASE + 0x3c )
+#define REG_AON_E902_CNT_CLR        (AONSYS_REG_BASE + 0x40 )
+#define REG_AON_E902_RST_ADDR       (AONSYS_REG_BASE + 0x44 )
+#define REG_AON_C906_RST_ADDR_L     (AONSYS_REG_BASE + 0x48 )
+#define REG_AON_C906_RST_ADDR_H     (AONSYS_REG_BASE + 0x4c )
+#define REG_AON_RESERVED_REG_0      (AONSYS_REG_BASE + 0x50 )
+#define REG_AON_RESERVED_REG_1      (AONSYS_REG_BASE + 0x54 )
+#define REG_AON_RESERVED_REG_2      (AONSYS_REG_BASE + 0x58 )
+#define REG_AON_RESERVED_REG_3      (AONSYS_REG_BASE + 0x5c )
+#define REG_AON_AON_AHB_ADEXT       (AONSYS_REG_BASE + 0x60 )
+#define REG_AON_RC_EN               (AONSYS_REG_BASE + 0x70 )
+#define REG_AON_RC_FCAL             (AONSYS_REG_BASE + 0x74 )
+#define REG_AON_RC_MODE             (AONSYS_REG_BASE + 0x78 )
+#define REG_AON_RC_READY            (AONSYS_REG_BASE + 0x7c )
+#define REG_AON_ISO_CFG             (AONSYS_REG_BASE + 0x80 )
+#define REG_AON_OCRAM_ERR           (AONSYS_REG_BASE + 0x90 )
+#define REG_AON_TIMER_LINK          (AONSYS_REG_BASE + 0x100)
+#define REG_AON_PD_REQ              (AONSYS_REG_BASE + 0x110)
+#define REG_AON_PD_ISO_EN_SET       (AONSYS_REG_BASE + 0x114)
+#define REG_AON_PD_ISO_EN_CLR       (AONSYS_REG_BASE + 0x118)
+#define REG_AON_PD_SW_EN_SET        (AONSYS_REG_BASE + 0x11c)
+#define REG_AON_PD_SW_EN_CLR        (AONSYS_REG_BASE + 0x120)
+#define REG_AON_PD_SW_ACK           (AONSYS_REG_BASE + 0x124)
+#define REG_AON_PD_SW_CNT_EN        (AONSYS_REG_BASE + 0x128)
+#define REG_AON_PD_FSM_RST          (AONSYS_REG_BASE + 0x12c)
+#define REG_AON_PD_INT_MASK         (AONSYS_REG_BASE + 0x130)
+#define REG_AON_PD_FSM_STS_L        (AONSYS_REG_BASE + 0x134)
+#define REG_AON_PD_FSM_STS_H        (AONSYS_REG_BASE + 0x138)
+#define REG_AON_PD_INT_STS          (AONSYS_REG_BASE + 0x13c)
+#define REG_AON_PD_INT_CLR          (AONSYS_REG_BASE + 0x140)
+#define REG_AON_PD_BLK0_SW_CNT      (AONSYS_REG_BASE + 0x144)
+#define REG_AON_PD_BLK1_SW_CNT      (AONSYS_REG_BASE + 0x148)
+#define REG_AON_PD_BLK2_SW_CNT      (AONSYS_REG_BASE + 0x14c)
+#define REG_AON_PD_BLK3_SW_CNT      (AONSYS_REG_BASE + 0x150)
+#define REG_AON_PD_BLK4_SW_CNT      (AONSYS_REG_BASE + 0x154)
+#define REG_AON_PD_BLK5_SW_CNT      (AONSYS_REG_BASE + 0x158)
+#define REG_AON_PD_BLK6_SW_CNT      (AONSYS_REG_BASE + 0x15c)
+#define REG_AON_PD_BLK7_SW_CNT      (AONSYS_REG_BASE + 0x160)
+#define REG_AON_PD_BLK8_SW_CNT      (AONSYS_REG_BASE + 0x164)
+#define REG_AON_PD_BLK9_SW_CNT      (AONSYS_REG_BASE + 0x168)
+#define REG_AON_PD_BLK10_SW_CNT     (AONSYS_REG_BASE + 0x16c)
+#define REG_AON_PD_BLK0_INTV_CNT    (AONSYS_REG_BASE + 0x180)
+#define REG_AON_PD_BLK1_INTV_CNT    (AONSYS_REG_BASE + 0x184)
+#define REG_AON_PD_BLK2_INTV_CNT    (AONSYS_REG_BASE + 0x188)
+#define REG_AON_PD_BLK3_INTV_CNT    (AONSYS_REG_BASE + 0x18c)
+#define REG_AON_PD_BLK4_INTV_CNT    (AONSYS_REG_BASE + 0x190)
+#define REG_AON_PD_BLK5_INTV_CNT    (AONSYS_REG_BASE + 0x194)
+#define REG_AON_PD_BLK6_INTV_CNT    (AONSYS_REG_BASE + 0x198)
+#define REG_AON_PD_BLK7_INTV_CNT    (AONSYS_REG_BASE + 0x19c)
+#define REG_AON_PD_BLK8_INTV_CNT    (AONSYS_REG_BASE + 0x1a0)
+#define REG_AON_PD_BLK9_INTV_CNT    (AONSYS_REG_BASE + 0x1a4)
+#define REG_AON_PD_BLK10_INTV_CNT   (AONSYS_REG_BASE + 0x1a8)
+#define REG_AON_AUDIO_PMU_REQ       (AONSYS_REG_BASE + 0x1f8)
+#define REG_AON_AUDIO_PMU_STS       (AONSYS_REG_BASE + 0x1fc)
+#define REG_AON_AUDIO_PMU_INTR      (AONSYS_REG_BASE + 0x204)
+#define REG_AON_PMU_AUDIO_REQ       (AONSYS_REG_BASE + 0x208)
+#define REG_AON_PMU_AUDIO_STS       (AONSYS_REG_BASE + 0x20c)
+#define REG_AON_MEM_LP_MODE         (AONSYS_REG_BASE + 0x210)
+#define REG_AON_C910_DBG_MASK       (AONSYS_REG_BASE + 0x214)
+#define REG_AON_C910_L2CACHE        (AONSYS_REG_BASE + 0x218)
+#define REG_AON_BISR_CTRL           (AONSYS_REG_BASE + 0x220)
+#define REG_AON_EFUSE_PRELOAD_DONE  (AONSYS_REG_BASE + 0x224)
+#define REG_AON_GPIO_RTE            (AONSYS_REG_BASE + 0x228)
+#define REG_AON_PLL_DSKEW_LOCK      (AONSYS_REG_BASE + 0x22c)
+#define REG_AON_SRAM_AXI_CFG        (AONSYS_REG_BASE + 0x230)
+#define REG_AON_SRAM_AXI_ST         (AONSYS_REG_BASE + 0x234)
+#define REG_AON_SRAM_AXI_ERR_STS_0  (AONSYS_REG_BASE + 0x238)
+#define REG_AON_SRAM_AXI_ERR_STS_1  (AONSYS_REG_BASE + 0x23c)
+#define REG_AON_SRAM_AXI_ERR_STS_2  (AONSYS_REG_BASE + 0x240)
+#define REG_AON_SRAM_AXI_ERR_STS_3  (AONSYS_REG_BASE + 0x244)
+#define REG_AON_SRAM_AXI_ERR_STS_4  (AONSYS_REG_BASE + 0x248)
+#define REG_AON_SE_MUX_LOCK         (AONSYS_REG_BASE + 0x24c)
+#define REG_AON_CPU_DBG_DIS_LOCK    (AONSYS_REG_BASE + 0x270)
+#define REG_AON_RESERVED_REG_4      (AONSYS_REG_BASE + 0x300)
+#define REG_AON_RESERVED_REG_5      (AONSYS_REG_BASE + 0x304)
+#define REG_AON_RESERVED_REG_6      (AONSYS_REG_BASE + 0x308)
+#define REG_AON_RESERVED_REG_7      (AONSYS_REG_BASE + 0x30c)
+#define REG_AON_RESERVED_REG_8      (AONSYS_REG_BASE + 0x400)
+#define REG_AON_RESERVED_REG_9      (AONSYS_REG_BASE + 0x404)
+#define REG_AON_RESERVED_REG_10     (AONSYS_REG_BASE + 0x408)
+#define REG_AON_RESERVED_REG_11     (AONSYS_REG_BASE + 0x40c)
+#define REG_AON_RESERVED_REG_12     (AONSYS_REG_BASE + 0x500)
+#define REG_AON_RESERVED_REG_13     (AONSYS_REG_BASE + 0x504)
+#define REG_AON_RESERVED_REG_14     (AONSYS_REG_BASE + 0x508)
+#define REG_AON_RESERVED_REG_15     (AONSYS_REG_BASE + 0x50c)
+#define REG_AON_RESERVED_REG_16     (AONSYS_REG_BASE + 0x600)
+#define REG_AON_RESERVED_REG_17     (AONSYS_REG_BASE + 0x604)
+#define REG_AON_RESERVED_REG_18     (AONSYS_REG_BASE + 0x608)
+#define REG_AON_RESERVED_REG_19     (AONSYS_REG_BASE + 0x60c)
+
+#define CPU_LP_MODE_DFLT_VAL          0x3ff
+#define CHIP_LP_MODE_DFLT_VAL         0x0
+#define AO_SERAM_TRN_DFLT_VAL         0x0
+#define AO_SERAM_INT_DFLT_VAL         0x0
+#define STR_SERAM_TRN_DFLT_VAL        0x0
+#define STR_SERAM_INT_DFLT_VAL        0x0
+#define STR_INDICATOR_0_DFLT_VAL      0x0
+#define STR_INDICATOR_1_DFLT_VAL      0x0
+#define STR_INDICATOR_2_DFLT_VAL      0x0
+#define STR_INDICATOR_3_DFLT_VAL      0x0
+#define PVTC_WR_LOCK_DFLT_VAL         0x0
+#define PVTC_TS_ALARM_DFLT_VAL        0x0
+#define PVTC_VM_ALARM_DFLT_VAL        0x0
+#define PVTC_PD_ALARM_DFLT_VAL        0x0
+#define E902_CNT_CLR_DFLT_VAL         0x0
+#define E902_RST_ADDR_DFLT_VAL        0xffef8000
+#define C906_RST_ADDR_L_DFLT_VAL      0xc0000000
+#define C906_RST_ADDR_H_DFLT_VAL      0xff
+#define RESERVED_REG_0_DFLT_VAL       0x0
+#define RESERVED_REG_1_DFLT_VAL       0x0
+#define RESERVED_REG_2_DFLT_VAL       0x0
+#define RESERVED_REG_3_DFLT_VAL       0x0
+#define AON_AHB_ADEXT_DFLT_VAL        0x0
+#define RC_EN_DFLT_VAL                0x1
+#define RC_FCAL_DFLT_VAL              0x77f
+#define RC_MODE_DFLT_VAL              0x1
+#define RC_READY_DFLT_VAL             0x0
+#define ISO_CFG_DFLT_VAL              0x0
+#define OCRAM_ERR_DFLT_VAL            0x0
+#define TIMER_LINK_DFLT_VAL           0x0
+#define PD_REQ_DFLT_VAL               0x0
+#define PD_ISO_EN_SET_DFLT_VAL        0x0
+#define PD_ISO_EN_CLR_DFLT_VAL        0x0
+#define PD_SW_EN_SET_DFLT_VAL         0x0
+#define PD_SW_EN_CLR_DFLT_VAL         0x0
+#define PD_SW_ACK_DFLT_VAL            0x3fffff
+#define PD_SW_CNT_EN_DFLT_VAL         0x0
+#define PD_FSM_RST_DFLT_VAL           0x0
+#define PD_INT_MASK_DFLT_VAL          0x3fffff
+#define PD_FSM_STS_L_DFLT_VAL         0x0
+#define PD_FSM_STS_H_DFLT_VAL         0x0
+#define PD_INT_STS_DFLT_VAL           0x0
+#define PD_INT_CLR_DFLT_VAL           0x0
+#define PD_BLK0_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK1_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK2_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK3_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK4_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK5_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK6_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK7_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK8_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK9_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK10_SW_CNT_DFLT_VAL      0xff00ff
+#define PD_BLK0_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK1_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK2_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK3_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK4_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK5_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK6_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK7_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK8_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK9_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK10_INTV_CNT_DFLT_VAL    0xff0ffff
+#define AUDIO_PMU_REQ_DFLT_VAL        0x0
+#define AUDIO_PMU_STS_DFLT_VAL        0x0
+#define AUDIO_PMU_INTR_DFLT_VAL       0x0
+#define PMU_AUDIO_REQ_DFLT_VAL        0x0
+#define PMU_AUDIO_STS_DFLT_VAL        0x0
+#define MEM_LP_MODE_DFLT_VAL          0x0
+#define C910_DBG_MASK_DFLT_VAL        0x0
+#define C910_L2CACHE_DFLT_VAL         0x0
+#define BISR_CTRL_DFLT_VAL            0x0
+#define EFUSE_PRELOAD_DONE_DFLT_VAL   0x0
+#define GPIO_RTE_DFLT_VAL             0x0
+#define PLL_DSKEW_LOCK_DFLT_VAL       0x0
+#define SRAM_AXI_CFG_DFLT_VAL         0x0
+#define SRAM_AXI_ST_DFLT_VAL          0x0
+#define SRAM_AXI_ERR_STS_0_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_1_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_2_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_3_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_4_DFLT_VAL   0x0
+#define SE_MUX_LOCK_DFLT_VAL          0x0
+#define CPU_DBG_DIS_LOCK_DFLT_VAL     0x0
+#define RESERVED_REG_4_DFLT_VAL       0x0
+#define RESERVED_REG_5_DFLT_VAL       0x0
+#define RESERVED_REG_6_DFLT_VAL       0x0
+#define RESERVED_REG_7_DFLT_VAL       0x0
+#define RESERVED_REG_8_DFLT_VAL       0x0
+#define RESERVED_REG_9_DFLT_VAL       0x0
+#define RESERVED_REG_10_DFLT_VAL      0x0
+#define RESERVED_REG_11_DFLT_VAL      0x0
+#define RESERVED_REG_12_DFLT_VAL      0x0
+#define RESERVED_REG_13_DFLT_VAL      0x0
+#define RESERVED_REG_14_DFLT_VAL      0x0
+#define RESERVED_REG_15_DFLT_VAL      0x0
+#define RESERVED_REG_16_DFLT_VAL      0x0
+#define RESERVED_REG_17_DFLT_VAL      0x0
+#define RESERVED_REG_18_DFLT_VAL      0x0
+#define RESERVED_REG_19_DFLT_VAL      0x0
+
+
+#endif

board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h

@@ -0,0 +1,90 @@
+//------------------------------------------------------------
+// DONOT MODIFY THIS FILE
+// generated by JISHENGJU automatically
+//------------------------------------------------------------
+
+#ifndef AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
+#define AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
+
+#define AONSYS_RSTGEN_REG_BASE	0xFFFFF44000
+
+#define REG_AON_RST_CNT             (AONSYS_RSTGEN_REG_BASE + 0x0   )
+#define REG_AON_SYS_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x10  )
+#define REG_AON_RTC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x14  )
+#define REG_AON_AOGPIO_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x18  )
+#define REG_AON_AOI2C_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x1c  )
+#define REG_AON_PVTC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x20  )
+#define REG_AON_E902_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x24  )
+#define REG_AON_AOTIMER_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x28  )
+#define REG_AON_AOWDT_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x2c  )
+#define REG_AON_APSYS_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x30  )
+#define REG_AON_NPUSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x34  )
+#define REG_AON_DDRSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x38  )
+#define REG_AON_AUDIO_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x3c  )
+#define REG_AON_BISR_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x50  )
+#define REG_AON_DSP0_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x54  )
+#define REG_AON_DSP1_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x58  )
+#define REG_AON_GPU_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x5c  )
+#define REG_AON_VDEC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x60  )
+#define REG_AON_VENC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x64  )
+#define REG_AON_ADC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x70  )
+#define REG_AON_AUDGPIO_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x74  )
+#define REG_AON_AOUART_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x78  )
+#define REG_AON_RST_CLR_0           (AONSYS_RSTGEN_REG_BASE + 0x100 )
+#define REG_AON_RST_CLR_1           (AONSYS_RSTGEN_REG_BASE + 0x104 )
+#define REG_AON_RST_CLR_2           (AONSYS_RSTGEN_REG_BASE + 0x108 )
+#define REG_AON_RST_CLR_3           (AONSYS_RSTGEN_REG_BASE + 0x10c )
+#define REG_AON_RST_CLR_4           (AONSYS_RSTGEN_REG_BASE + 0x110 )
+#define REG_AON_RST_STS_0           (AONSYS_RSTGEN_REG_BASE + 0x120 )
+#define REG_AON_RST_STS_1           (AONSYS_RSTGEN_REG_BASE + 0x124 )
+#define REG_AON_RST_STS_2           (AONSYS_RSTGEN_REG_BASE + 0x128 )
+#define REG_AON_RST_STS_3           (AONSYS_RSTGEN_REG_BASE + 0x12c )
+#define REG_AON_RST_STS_4           (AONSYS_RSTGEN_REG_BASE + 0x130 )
+#define REG_AON_RST_REQ_EN_0        (AONSYS_RSTGEN_REG_BASE + 0x140 )
+#define REG_AON_RST_REQ_EN_1        (AONSYS_RSTGEN_REG_BASE + 0x144 )
+#define REG_AON_RST_REQ_EN_2        (AONSYS_RSTGEN_REG_BASE + 0x148 )
+#define REG_AON_RST_REQ_EN_3        (AONSYS_RSTGEN_REG_BASE + 0x14c )
+#define REG_AON_SRAM_AXI_RST_CFG    (AONSYS_RSTGEN_REG_BASE + 0x11f4)
+#define REG_AON_SE_RST_CFG          (AONSYS_RSTGEN_REG_BASE + 0x160 )
+
+#define RST_CNT_DFLT_VAL              0xf0f
+#define SYS_RST_CFG_DFLT_VAL          0x0
+#define RTC_RST_CFG_DFLT_VAL          0x3
+#define AOGPIO_RST_CFG_DFLT_VAL       0x3
+#define AOI2C_RST_CFG_DFLT_VAL        0x1
+#define PVTC_RST_CFG_DFLT_VAL         0x1
+#define E902_RST_CFG_DFLT_VAL         0x2
+#define AOTIMER_RST_CFG_DFLT_VAL      0x3
+#define AOWDT_RST_CFG_DFLT_VAL        0x1
+#define APSYS_RST_CFG_DFLT_VAL        0x1
+#define NPUSYS_RST_CFG_DFLT_VAL       0x1
+#define DDRSYS_RST_CFG_DFLT_VAL       0x1
+#define AUDIO_RST_CFG_DFLT_VAL        0x0
+#define BISR_RST_CFG_DFLT_VAL         0x3
+#define DSP0_RST_CFG_DFLT_VAL         0x1
+#define DSP1_RST_CFG_DFLT_VAL         0x1
+#define GPU_RST_CFG_DFLT_VAL          0x1
+#define VDEC_RST_GEN_RST_CFG_DFLT_VAL         0x1
+#define VENC_RST_CFG_DFLT_VAL         0x1
+#define ADC_RST_CFG_DFLT_VAL          0x1
+#define AUDGPIO_RST_CFG_DFLT_VAL      0x3
+#define AOUART_RST_CFG_DFLT_VAL       0x3
+#define RST_CLR_0_DFLT_VAL            0x0
+#define RST_CLR_1_DFLT_VAL            0x0
+#define RST_CLR_2_DFLT_VAL            0x0
+#define RST_CLR_3_DFLT_VAL            0x0
+#define RST_CLR_4_DFLT_VAL            0x0
+#define RST_STS_0_DFLT_VAL            0x0
+#define RST_STS_1_DFLT_VAL            0x0
+#define RST_STS_2_DFLT_VAL            0x0
+#define RST_STS_3_DFLT_VAL            0x0
+#define RST_STS_4_DFLT_VAL            0x0
+#define RST_REQ_EN_0_DFLT_VAL         0x11100
+#define RST_REQ_EN_1_DFLT_VAL         0xbb000000
+#define RST_REQ_EN_2_DFLT_VAL         0x0
+#define RST_REQ_EN_3_DFLT_VAL         0x0
+#define SRAM_AXI_RST_CFG_DFLT_VAL     0x5f
+#define SE_RST_CFG_DFLT_VAL           0x1
+
+
+#endif

board/thead/light-c910/lpddr4/include/common_lib.h

@@ -7,6 +7,8 @@
 #include "ddr_reg_define.h"
 #include "ddr_sysreg_registers_struct.h"
 #include "ddr_sysreg_registers.h"
+#include "aonsys_reg_define.h"
+#include "aonsys_rstget_reg_define.h"
 #include "define_ddr.h"
 #include "DWC_ddr_umctl2_c_struct.h"
 #include "DWC_ddr_umctl2_header.h"

board/thead/light-c910/lpddr4/include/ddr_common_func.h

@@ -15,6 +15,9 @@ enum DDR_BITWIDTH {
 
 unsigned long get_ddr_density(void);
 enum DDR_TYPE get_ddr_type(void);
+int get_ddr_rank_number(void);
+int get_ddr_freq(void);
+enum DDR_BITWIDTH get_ddr_bitwidth(void);
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data);
 unsigned int ddr_sysreg_rd(unsigned long int addr);
 
@@ -48,5 +51,9 @@ void ctrl_init(int rank_num, int speed);
 void addrmap(int rank_num, enum DDR_BITWIDTH bits);
 void ctrl_en(enum DDR_BITWIDTH bits);
 void enable_auto_refresh(void);
-
+void lpddr4_auto_selref(void);
+int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
+                    enum DDR_BITWIDTH bits, unsigned long size);
+int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
+                    enum DDR_BITWIDTH bits, unsigned long size);
 #endif // DDR_COMMON_FUNCE_H

board/thead/light-c910/lpddr4/include/ddr_retention.h

@@ -0,0 +1,35 @@
+#ifndef DDR_RETENTION_H
+#define DDR_RETENTION_H
+
+///data structure to store ddr misc register address, value
+typedef struct Reg_Misc_Addr_Val {
+  uint32_t Address; ///< register address
+  uint32_t Value;   ///< register value
+} Reg_Misc_Addr_Val_t;
+
+///data structure to store register address, value pairs
+typedef struct Reg_Phy_Addr_Val {
+  uint32_t Address; ///< register address
+  uint16_t Value0;   ///< register value phy0
+  uint16_t Value1;   ///< register value phy1
+} Reg_Phy_Addr_Val_t;
+
+/// enumeration of instructions for PhyInit Register Interface
+typedef enum {
+  saveRegs,         ///< save(read) tracked register values
+  restoreRegs,      ///< restore (write) saved register values
+} regInstr;
+
+// typedef struct Reg_Addr_Value {
+//   uint32_t reg_num;
+//   Reg_Addr_Val_t reg[0];
+// } Reg_Addr_Value_t;
+
+typedef struct Ddr_Reg_Config {
+    uint32_t misc_reg_num;
+    uint32_t phy_reg_num;
+} Ddr_Reg_Config_t;
+
+int dwc_ddrphy_phyinit_regInterface(regInstr myRegInstr);
+
+#endif

board/thead/light-c910/lpddr4/src/ddr_common_func.c

@@ -2,9 +2,14 @@
 #include <linux/sizes.h>
 #include "../include/common_lib.h"
 #include "../include/ddr_common_func.h"
+#include "../include/ddr_retention.h"
 
 DDR_SYSREG_REG_SW_REG_S ddr_sysreg;
 
+#ifdef CONFIG_DDR_MSG
+#define DDR_DEBUG(x) printf(x)
+#endif
+
 #ifndef CONFIG_DDR_RANK_SIZE
 #define CONFIG_DDR_RANK_SIZE SZ_4G
 #endif
@@ -14,6 +19,9 @@ unsigned long get_ddr_density() {
 #ifdef CONFIG_DDR_DUAL_RANK
 	mul = 2;
 #endif
+#ifdef CONFIG_DDR_DDP
+	mul *= 2;
+#endif
 #ifdef CONFIG_DDR_H32_MODE
     div = 2;
 #endif
@@ -31,6 +39,44 @@ enum DDR_TYPE get_ddr_type() {
 #endif // #ifdef CONFIG_LPDDR4X
 }
 
+int get_ddr_rank_number() {
+#ifdef CONFIG_DDR_SINGLE_RANK
+	return 1;
+#elif defined CONFIG_DDR_DUAL_RANK
+	return 2;
+#else
+#ifdef CONFIG_DDR_MSG
+	DDR_DEBUG("unsupported ddr rank type!!!\n");
+#endif
+    return NULL;
+#endif
+}
+
+int get_ddr_freq() {
+#ifdef CONFIG_DDR_4266
+    return 4266;
+#elif CONFIG_DDR_3733
+    return 3733;
+#elif CONFIG_DDR_3200
+    return 3200;
+#elif CONFIG_DDR_2133
+	return 2133;
+#else
+    printf("unsupport lpddr4 freq!!!\n");
+    return -1;
+#endif
+}
+
+enum DDR_BITWIDTH get_ddr_bitwidth() {
+#ifdef CONFIG_DDR_H32_MODE
+    return DDR_BITWIDTH_32;
+#elif CONFIG_DDR_H16_MODE
+    return DDR_BITWIDTH_16;
+#else
+    return DDR_BITWIDTH_64;
+#endif
+}
+
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data) {
   wr(addr+DDR_SYSREG_BADDR,wr_data);
 }
@@ -101,75 +147,114 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
 
   void lp4_mrw(int addr, int wdata,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
+  uint32_t val_t0,val_t1;
   if(dch==0) {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        while ((rd(MRSTAT) & 0x1) == 0x1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
-  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        //udelay(10);
+        //delay 5us
+        val_t0=rd(0xFFF4D004);
+        val_t1=rd(0xFFF4D004);
+        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
+
+        while ((rd(MRSTAT) & 0x1) == 0x1);
   }
   else {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
-  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-  }
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        //udelay(10);
+        //delay 5us
+        val_t0=rd(0xFFF4D004);
+        val_t1=rd(0xFFF4D004);
+        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
+        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
   }
+}
 
   int lp4_mrr(int addr,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
   if(dch==0) {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
-  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        udelay(20);
+        while ((rd(MRSTAT) & 0x1) == 0x1);
+        return ddr_sysreg_rd(MRR_STS_CH0);
   }
   else {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
-  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        udelay(20);
+        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
+        return ddr_sysreg_rd(MRR_STS_CH1);
   }
   }
 
@@ -233,15 +318,15 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
     if(port & 0x4) wr(PCTRL_2,0);
     if(port & 0x8) wr(PCTRL_3,0);
     if(port & 0x10) wr(PCTRL_4,0);
-    if(port & 0x1F) { //at least one port is not disabled
-        wr(DBG1,0);
-        wr(DBG1_DCH1,0);
+    while (rd(PSTAT) != 0x0);
+    if ((port & 0x1F) == 0x1F) { //all ports are disabled
+        wr(DBG1, 2);
+        wr(DBG1_DCH1, 2);
     }
-    else { //all ports are disabled
-        wr(DBG1,3);
-        wr(DBG1_DCH1,3);
+    else { //at least one port is not disabled
+        wr(DBG1, 0);
+        wr(DBG1_DCH1, 0);
     }
-
   }
 
   void enable_axi_port(int port) {
@@ -454,7 +539,7 @@ if(bits==64) {
   wr(DFITMG0,0x05a3820e);//[28:24] dft_t_ctrl_delay [22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000c0303);
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0x00400018); //[31:30]=0 use ctrlupd enable
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x00000000);//[31]=0 disable phy ctrlupdate
@@ -554,7 +639,7 @@ if(bits==64) {
   wr(DFITMG0,0x059f820c);//[28:24] dfi_t_ctrl_delay
 #endif
   wr(DFITMG1,0x000c0303);//dfi_t_wrdata_delay=tctrl+6+BL/2+trainedTdqsdly=24, may need take care cmd pipe
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -642,7 +727,7 @@ if(bits==64) {
   wr(DFITMG0,0x059b820a); //[22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -727,7 +812,7 @@ if(bits==64) {
   wr(ZQCTL2,0x00000000);
   wr(DFITMG0,0x048f8206);
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -853,17 +938,28 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 32bit mode\n");
 #endif
-  wr(ADDRMAP0,0x001f001f);  //
   if(rank_num==2) {
-  wr(ADDRMAP0,0x001f0017);//4GB
+#ifdef CONFIG_DDR_DDP
+    wr(ADDRMAP0,0x001f0018);//max 8GB
+#else
+    wr(ADDRMAP0,0x001f0017); //4GB
+#endif
+  }
+  else {
+    wr(ADDRMAP0,0x001f001f); //cs_bit0: NULL
   }
   wr(ADDRMAP1,0x00080808); //bank +2
   wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2  +2
   wr(ADDRMAP3,0x00000000); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x070f0707); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x07070707); //max row 15
-  wr(ADDRMAP7,0x00000f0f);
+  wr(ADDRMAP6,0x07070707); //row 15
+  wr(ADDRMAP7,0x00000f0f); //row16: NULL
+#ifdef CONFIG_DDR_DDP
+  if(rank_num==2) {
+    wr(ADDRMAP7,0x00000f07); //max row16
+  }
+#endif
   wr(ADDRMAP9,0x07070707);
   wr(ADDRMAP10,0x07070707);
   wr(ADDRMAP11,0x00000007);
@@ -871,17 +967,25 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 64bit mode, 256B interleaving\n");
 #endif
-  wr(ADDRMAP0,0x0004001f);  // +2
+  wr(ADDRMAP0,0x0004001f); //cs_bit0: NULL
   if(rank_num==2) {
-  wr(ADDRMAP0,0x00040018);//8GB
+#ifdef CONFIG_DDR_DDP
+    wr(ADDRMAP0,0x00040019);//max 16GB
+#else
+    wr(ADDRMAP0,0x00040018);//8GB
+#endif
   }
   wr(ADDRMAP1,0x00090909); //bank +2
   wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2  +2
   wr(ADDRMAP3,0x01010101); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x08080808);
-  wr(ADDRMAP7,0x00000f0f);
+  wr(ADDRMAP6,0x08080808); //row15
+#ifdef CONFIG_DDR_DDP
+  wr(ADDRMAP7,0x00000f08); //row16
+#else
+  wr(ADDRMAP7,0x00000f0f); //row16: NULL
+#endif
   wr(ADDRMAP9,0x08080808);
   wr(ADDRMAP10,0x08080808);
   wr(ADDRMAP11,0x00000008);
@@ -890,6 +994,130 @@ if(bits==64) {
  }
 }
 
+#define MEMSIZE_MIN_MB (2*1024)
+#define MEMSIZE_MAX_MB (16*1024)
+#define UNIT_MB (1024*1024)
+int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
+					enum DDR_BITWIDTH bits, unsigned long size)
+{
+  if ((size < (unsigned long)MEMSIZE_MIN_MB*UNIT_MB) ||
+    (size > (unsigned long)MEMSIZE_MAX_MB*UNIT_MB))
+    goto err_ret;
+
+  if (bits == DDR_BITWIDTH_32) {// only phy0
+    if (rank_num == 2) {
+      if (size == 0x80000000) //2GB
+        goto err_ret;
+      else if (size == 0x100000000) //4GB
+        goto ret_ok;
+      else if (size == 0x200000000) //8GB
+        goto ret_ok;
+      else if (size == 0x400000000) //16GB
+        goto err_ret;
+      else
+        goto err_ret;
+    }
+    else { // single rank
+      if (size == 0x80000000) //2GB
+        goto ret_ok;
+      else if (size == 0x100000000) //4GB
+        goto err_ret;
+      else if (size == 0x200000000) //8GB
+        goto err_ret;
+      else if (size == 0x400000000) //16GB
+        goto err_ret;
+      else
+        goto err_ret;
+    }
+  }
+  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
+    if (rank_num == 2) {
+      if (size == 0x80000000) //2GB
+        goto err_ret;
+      else if (size == 0x100000000) //4GB
+        goto err_ret;
+      else if (size == 0x200000000) //8GB
+        goto ret_ok;
+      else if (size == 0x400000000) //16GB
+        goto ret_ok;
+      else
+        goto err_ret;
+    }
+    else { // single rank
+      if (size == 0x80000000) //2GB
+        goto err_ret;
+      else if (size == 0x100000000) //4GB
+        goto ret_ok;
+      else if (size == 0x200000000) //8GB
+        goto err_ret;
+      else if (size == 0x400000000) //16GB
+        goto err_ret;
+      else
+        goto err_ret;
+    }
+  }
+  else {
+    goto err_ret;
+  }
+
+ret_ok:
+  return 0;
+
+err_ret:
+  return -1;
+}
+
+int adjust_ddr_addrmap(enum DDR_TYPE type, int rank_num, int speed,
+					enum DDR_BITWIDTH bits, unsigned long size)
+{
+  if (lpddr4_query_boundary(type, rank_num, speed, bits, size) < 0)
+    goto err_ret;
+
+  if (bits == DDR_BITWIDTH_32) {// only phy0
+    if (rank_num == 2) {
+      if (size == 0x100000000) {//4GB
+        wr(ADDRMAP0,0x001f0017); // cs_bit0: HIF[29]
+        wr(ADDRMAP7,0x00000f0f); // row16: NULL
+      }
+      else if (size == 0x200000000) {//8GB
+        wr(ADDRMAP0,0x001f0018); // cs_bit0: HIF[30]
+        wr(ADDRMAP7,0x00000f07); // row16: HIF[29]
+      }
+    }
+	else { // single rank
+      if (size == 0x80000000) //2GB
+        wr(ADDRMAP0,0x001f001f); // cs_bit0: NULL
+    }
+  }
+  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
+    if (rank_num == 2) {
+      if (size == 0x200000000) {//8GB
+        wr(ADDRMAP0,0x00040018); // cs_bit0: HIF[30]
+        wr(ADDRMAP7,0x00000f0f); // row16: NULL
+      }
+      else if (size == 0x400000000) {//16GB
+        wr(ADDRMAP0,0x00040019); // cs_bit0: HIF[31]
+        wr(ADDRMAP7,0x00000f08); // row16: HIF[30]
+      }
+    }
+    else { // single rank
+      if (size == 0x100000000) {//4GB
+        wr(ADDRMAP0,0x0004001f); // cs_bit0: NULL
+        wr(ADDRMAP7,0x00000f0f); // row16: NULL
+      }
+    }
+  }
+  else {
+    // nothing
+  }
+
+  return 0;
+
+err_ret:
+  printf("unsupport memsize %ld\n", size);
+  return -1;
+}
+
   void quasi_reg_write(unsigned long int reg,int wdata) {
     DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
 
@@ -1004,11 +1232,11 @@ void lpddr4_enter_selfrefresh(int pwdn_en,int dis_dram_clk,int mode) {
     umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     if(pwdn_en) {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 2) //wait sdram enter selfrefresh-powerdown state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     }
     else {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 1) //wait sdram enter selfrefresh state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     }
 #ifdef CONFIG_DDR_MSG
     printf("[lpddr4_enter_selfrefresh]: CH1 STAT is :%x after enter selfrefresh state\n",umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32);
@@ -1044,7 +1272,8 @@ void lpddr4_auto_ps_en(int pwdn_en,int selfref_en,int clock_auto_disable ) {
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32 = ddr_sysreg_rd(DDR_CFG0);
-    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
+    //ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
+    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1FA;
     ddr_sysreg_wr(DDR_CFG0,ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32);
   }
 
@@ -1064,7 +1293,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 #ifdef CONFIG_DDR_MSG
   printf("[dfi_freq_change]: start dfi_freq_change, target dfi_freq is %x \n",dfi_freq);
 #endif
-  wr(DBG1,3);
+  //wr(DBG1,3);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
   wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
@@ -1075,7 +1304,6 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_frequency = dfi_freq;
-  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_complete_en = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
 
@@ -1086,15 +1314,28 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   while( umctl2_reg.dwc_ddr_umctl2_c_struct_swstat.sw_done_ack == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWSTAT);
 
+  wr(SWCTL,0x0);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
+  wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
+  wr(SWCTL,0x1);
+  while(rd(SWSTAT)!=0x00000001);
   rdata = rd(DFISTAT);
+  while ((rdata & 0x1) != 0) //wait dfi_init_complete = 0
+    rdata = rd(DFISTAT);
+
+#ifndef CONFIG_DDR_H32_MODE
+  rdata = rd(DCH1_DFISTAT);
   while((rdata & 0x1) != 0) //wait dfi_init_complete = 0
-  rdata = rd(DFISTAT);
+    rdata = rd(DCH1_DFISTAT);
+#endif
+
   //change dfi clk freq here
   //pull down dfi_init_start
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
-  wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
-
+  wr(SWCTL, umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
+ 
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
@@ -1108,9 +1349,17 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
   while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
-  wr(DBG1,0);
+
+  //wait dfi_init_complete = 1
+#ifndef CONFIG_DDR_H32_MODE
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
+  while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
+    umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
+#endif
+
+  //wr(DBG1,0);
 #ifdef CONFIG_DDR_MSG
-  printf("[dfi_freq_change]: dfi_freq_change, end \n",dfi_freq);
+  printf("[dfi_freq_change]: dfi_freq_change, end \n");
 #endif
 }
 
@@ -1121,7 +1370,7 @@ void ddr_soc_pll_disable () {
   printf("DDR SOC PLL PowerDown \n");
 #endif
 }
-void lpddr4_auto_selref()
+void lpddr4_auto_selref(void)
 {
   ddr_sysreg_wr(DDR_CFG1,0xa0000);   //remove core clock after xx
   wr(SWCTL,0);
@@ -1135,3 +1384,168 @@ void lpddr4_auto_selref()
   wr(PWRCTL,0x0000000b); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
   wr(DCH1_PWRCTL,0x0000000b);
 }
+
+void ctrl_en_lp3_exit(enum DDR_BITWIDTH bits) {
+  //skip DRAM init, because this has done 
+  wr(SWCTL,0x00000000);
+  wr(INIT0,0xc0020002);
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+  //dfi frequency change proto ,to PS0
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000000);// [5]dfi_freq=0x0
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000020);// [5]dfi_init_start=0x1
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+
+  while(rd(DFISTAT)!=0x00000001); //polling dfi_init_complete
+if(bits==64) {
+  while(rd(DCH1_DFISTAT)!=0x00000001);
+ }
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000000);
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000001);
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+  //for low power,
+  wr(SWCTL,0x00000000);
+  wr(PWRCTL,0x0000000a); //[3] dfi_dram_clk_disable [1] powerdown_en
+  wr(DCH1_PWRCTL,0x0000000a);
+  wr(SWCTL,0x00000001);
+  while (rd(SWSTAT) != 0x00000001);
+  //detect until umctrl into normal state
+  while (rd(STAT) != 0x00000001);
+  if(bits==64) {
+    while(rd(DCH1_STAT) != 0x00000001);
+  }
+
+  //en phy master proto
+  wr(DFIPHYMSTR,0x14000001);
+
+#ifdef CONFIG_DDR_MSG
+    DDR_DEBUG("DFIPHYMSTR is %0x \n", rd(DFIPHYMSTR));
+    DDR_DEBUG("DFIUPD0    is %0x \n", rd(DFIUPD0));
+    DDR_DEBUG("DFIUPD1    is %0x \n", rd(DFIUPD1));
+    DDR_DEBUG("ZQCTL0     is %0x \n", rd(ZQCTL0));
+    DDR_DEBUG("ADDRMAP0     is %0x \n", rd(ADDRMAP0));
+    DDR_DEBUG("ADDRMAP1     is %0x \n", rd(ADDRMAP1));
+#endif
+}
+
+int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
+					enum DDR_BITWIDTH bits, unsigned long size)
+{
+    int ret;
+    unsigned int rdata;
+
+    //a.
+    ddr_sysreg_wr(DDR_CFG1, 0xa000011f);   //remove core clock after xx
+    wr(PWRCTL, 0x00000000); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
+    wr(DCH1_PWRCTL, 0x00000000);
+
+    // use phy value stored in spl
+    //dwc_ddrphy_phyinit_regInterface(saveRegs);
+
+    //b.dis axi port
+    disable_axi_port(0x1f);
+    while (rd(PSTAT) != 0x0);
+
+#ifdef CONFIG_DDR_MSG
+    DDR_DEBUG("Axi prot idle\n");
+#endif
+    wr(DFIPHYMSTR, 0x14000000);
+    //check status.
+    while ((rd(STAT) & 0x3) == 0x03);
+
+#ifndef CONFIG_DDR_H32_MODE
+    while ((rd(STAT_DCH1) & 0x3) == 0x03);
+#endif
+    //c.poll cam empty flag
+    while ((rd(DBGCAM) & 0x36000000) != 0x36000000);
+    //d.save phy regs
+    //e.SRE
+    lpddr4_enter_selfrefresh(1, 0, 0);
+    //f.LP3 enter
+    dfi_freq_change(0x1f, 0x3);
+    //g.PwrOk disassert
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata &= ~(0x1 << 6);
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
+
+    //p.phy reset
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata &= ~(0x1 << 7);
+    rdata &= 0x0;
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //Phy reset .DDR_CFG0 ALL reset
+
+    //r.ddr core reset
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata &= ~(0x1 << 5);
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //ctrl sw reset
+
+    //s.pwr ok assert
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata |= (0x1 << 6);
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
+
+    //t.ctrl init
+    //dwc_umctl_init_skip_traing(type, rank_num, speed, bits);
+    ddr_sysreg_wr(DDR_CFG0, 0x50);  // release apb presetn
+    ddr_sysreg_wr(DDR_CFG0, 0x50);
+    ddr_sysreg_wr(DDR_CFG0, 0x50);
+    if (bits == 32) {
+        ddr_sysreg_wr(DDR_CFG0, 0x52);
+    }
+    ctrl_init(rank_num, speed);
+    addrmap(rank_num, bits);
+    ret = adjust_ddr_addrmap(type, rank_num, speed, bits, size);
+
+    // msic regu restore for str
+    dwc_ddr_misc_regu_save();
+
+    de_assert_other_reset_ddr(); //after this step, only PwrOk is staill low
+
+    dq_pinmux(bits);
+
+    //u.phy restor
+	  dwc_ddrphy_phyinit_regInterface(restoreRegs);
+
+    //v.ctrl en ,hs
+    ctrl_en_lp3_exit(bits);
+
+    //w.SRE
+    lpddr4_selfrefresh_exit(0);
+
+    //y.en auto refresh
+    enable_auto_refresh();
+ 
+    //x.en axi port
+    enable_axi_port(0x1f);
+    wr(DFIPHYMSTR, 0x14000001);
+    lpddr4_auto_selref();
+
+    if(rd(PSTAT))
+    {
+#ifdef CONFIG_DDR_MSG
+	    DDR_DEBUG("***** DDR busy in LP3 Mode *****\n");
+#endif
+    }else{
+#ifdef CONFIG_DDR_MSG
+	    DDR_DEBUG("***** AXI port idle *****\n");
+#endif
+    }
+    return ret;
+ }
+

board/thead/light-c910/lpddr4/src/lpddr4_init.c

@@ -1,6 +1,7 @@
 #include "../include/common_lib.h"
 #include "../include/pinmux.h"
 #include "../include/ddr_common_func.h"
+#include "../include/ddr_retention.h"
 #include "../include/lpddr4_init.h"
 
 extern void lp4_phy_train1d2d(enum DDR_TYPE type, int speed, enum DDR_BITWIDTH bits);
@@ -26,11 +27,34 @@ void lpddr4_init(enum DDR_TYPE type, int rank_num, int speed, enum DDR_BITWIDTH
 
   lp4_phy_train1d2d(type, speed, bits);
 
+  dwc_ddrphy_phyinit_regInterface(saveRegs);
+
   ctrl_en(bits);
 
   enable_axi_port(0x1f);
-  
+
   enable_auto_refresh();
 
   lpddr4_auto_selref();
 }
+
+int fixup_ddr_addrmap(unsigned long size)
+{
+  enum DDR_TYPE type = get_ddr_type();
+  int rank_num = get_ddr_rank_number();
+  int speed = get_ddr_freq();
+  enum DDR_BITWIDTH bits = get_ddr_bitwidth();
+
+  return lpddr4_reinit_ctrl(type, rank_num, speed, bits, size);
+}
+
+int query_ddr_boundary(unsigned long size)
+{
+  enum DDR_TYPE type = get_ddr_type();
+  int rank_num = get_ddr_rank_number();
+  int speed = get_ddr_freq();
+  enum DDR_BITWIDTH bits = get_ddr_bitwidth();
+
+  return lpddr4_query_boundary(type, rank_num, speed, bits, size);
+}
+

board/thead/light-c910/sbmeta/sbmeta.c

@@ -0,0 +1,436 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited
+ */
+
+#include "sbmeta.h"
+#include "sec_crypto_sha.h"
+
+#define LOGLEVEL_ERROR          1
+#define LOGLEVEL_INFO           2
+#define LOGLEVEL_DEBUG          3
+#define SBMETA_LOGLEVEL         1
+#define trace_printer(level, fmt,...)   printf("%s"fmt, level, ##__VA_ARGS__)
+#if (SBMETA_LOGLEVEL < 1)
+#define EMSG(...)
+#else
+#define EMSG(fmt, args...)      trace_printer("error: ", fmt, ##args)
+#endif
+
+#if (SBMETA_LOGLEVEL < 2)
+#define IMSG(...)
+#else
+#define IMSG(fmt, args...)      trace_printer("info: ", fmt, ##args)
+#endif
+
+#if (SBMETA_LOGLEVEL < 3)
+#define DMSG(...)
+#else
+#define DMSG(fmt, args...)      trace_printer("", fmt, ##args)
+#endif
+
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
+/* digest_size corresponding to digest_scheme specified in sbmeta_info_t */
+static const int digest_size[] = {0, 20, 16, 28, 32, 48, 64, 32};
+static const char* image_name_s[] = {
+    "dtb", "kernel", "tf", "aon", "rootfs", "tee", "uboot", "user"
+};
+/* index to get sc_sha_mode_t value */
+static const int sha_idx2ctl[] = {0, 1, 8, 3, 2, 5, 4, 9};
+
+static const unsigned long image_addrs[] = {
+    LIGHT_DTB_ADDR,
+    LIGHT_KERNEL_ADDR,
+    LIGHT_TF_FW_TMP_ADDR,
+    LIGHT_AON_FW_ADDR,
+    LIGHT_ROOTFS_ADDR,
+    LIGHT_TEE_FW_ADDR,
+    CONFIG_SYS_TEXT_BASE,
+};
+
+typedef struct {
+    int         magiccode;
+    uint8_t     dev;
+    uint8_t     part;
+    uint8_t     image_type;
+    uint8_t     digest_scheme;
+    uint8_t     sign_scheme;
+    uint8_t     isencrypted;
+    uint8_t     medium_type;
+    uint8_t     checksum_scheme;
+    char        filename[MAX_NAME_SIZE];
+    uint8_t     digest[MAX_DIGEST_SIZE];
+    uint32_t    relocated_addr;
+    uint32_t    reserved[4];
+} sbmeta_info_t;
+
+static int is_sbmeta_info(uint32_t entry_src_addr)
+{
+    uint32_t *buffer = (uint32_t *)(uintptr_t)entry_src_addr;
+
+    /* sbmeta_info_t entry should start with magic code 'S''B''M''T' */
+    if (*buffer != SBMETA_MAGIC) {
+        return CMD_RET_FAILURE;
+    }
+
+    return 0;
+}
+
+static int dump_sbmeta_info(sbmeta_info_t *sbmeta_info)
+{
+    if (sbmeta_info == NULL) {
+        return CMD_RET_FAILURE;
+    }
+    /* only support emmc now */
+    if (sbmeta_info->medium_type != 0) {
+        EMSG("medium type %d is not supported now\r\n", sbmeta_info->medium_type);
+        return CMD_RET_FAILURE;
+    }
+    /* only support dtb, krlimg/tf, sbi, aon, rootfs, tee, uboot and user-defined type */
+    if (sbmeta_info->image_type > IMAGE_TYPE_NUM || sbmeta_info->image_type < 0) {
+        EMSG("image type is out of range\r\n");
+        return CMD_RET_FAILURE;
+    }
+    /* only support none, sha1, md5, sha224, sha256, sha384, sha512, sm3 and reserved scheme */
+    if (sbmeta_info->digest_scheme > DIGEST_TYPE_NUM || sbmeta_info->digest_scheme < 0) {
+        EMSG("digest type is out of range\r\n");
+        return CMD_RET_FAILURE;
+    }
+    /* only support none, rsa1024, rsa2048, ecc256, ecc160, sm2 and reserved scheme */
+    if (sbmeta_info->sign_scheme > SIGN_TYPE_NUM || sbmeta_info->sign_scheme < 0) {
+        EMSG("signature type is out of range\r\n");
+        return CMD_RET_FAILURE;
+    }
+    /* DTB, TF, TEE, Kernel will be loaded from default partitions specified in env */
+    if (sbmeta_info->image_type != T_ROOTFS && sbmeta_info->image_type != T_USER) {
+        IMSG("Image has been loaded\r\n");
+    }
+
+    /* dump sbmeta_info_t */
+    DMSG("image medium type: %d\n", sbmeta_info->medium_type);
+    DMSG("image load part: mmc %d:%d\n", sbmeta_info->dev, sbmeta_info->part);
+    DMSG("image type: %d \n", sbmeta_info->image_type);
+    DMSG("image digest scheme: %d\n", sbmeta_info->digest_scheme);
+    DMSG("image sign scheme: %d\n", sbmeta_info->sign_scheme);
+    DMSG("image enable encryption: %s\n", sbmeta_info->isencrypted ? "en" : "dis");
+    DMSG("image file name: %s\n", sbmeta_info->filename);
+    DMSG("image digest:");
+    for (int i = 0; i < digest_size[sbmeta_info->digest_scheme]; i++) {
+        DMSG("%02X", sbmeta_info->digest[i]);
+    }
+    DMSG("\r\n");
+    DMSG("\n\n");
+
+    return 0;
+}
+
+static int sbmeta_field_verify(sbmeta_info_t *sbmeta_info, unsigned long img_src_addr)
+{
+    uint8_t digest_scheme = 0;
+    uint8_t sign_scheme = 0;
+    uint8_t is_encrypted = 0;
+    img_header_t *phead = NULL;
+
+    if (sbmeta_info == NULL) {
+        return CMD_RET_FAILURE;
+    }
+
+    /* if image has secure header, check with sbmeta field */
+    if (image_have_head(img_src_addr)) {
+        phead = (img_header_t *)img_src_addr;
+        digest_scheme = phead->digest_scheme;
+        sign_scheme = phead->signature_scheme;
+        is_encrypted = (phead->option_flag & 0x2) >> 1;
+    }
+
+    if (sbmeta_info->digest_scheme != digest_scheme) {
+        EMSG("digest type %d is not expected: %d\r\n", digest_scheme, sbmeta_info->digest_scheme);
+        return CMD_RET_FAILURE;
+    }
+
+    /* only support none, rsa1024, rsa2048, ecc256, ecc160, sm2 and reserved scheme */
+    if (sbmeta_info->sign_scheme != sign_scheme) {
+        EMSG("signature type %d is not expected: %d\r\n", sign_scheme, sbmeta_info->sign_scheme);
+        return CMD_RET_FAILURE;
+    }
+
+    if (sbmeta_info->isencrypted != is_encrypted) {
+        EMSG("encryption %d is not expected: %d\r\n", is_encrypted, sbmeta_info->isencrypted);
+        return CMD_RET_FAILURE;
+    }
+
+    return 0;
+}
+
+static int check_digest(uint8_t *buffer, uint32_t buffer_size, uint8_t digest_scheme, uint8_t *digest)
+{
+    uint32_t len = 0;
+    uint8_t sum[64];
+    sc_sha_t sha;
+    sc_sha_context_t ctx;
+    int mode = 0;
+
+    if (!buffer || digest_scheme > DIGEST_TYPE_NUM) {
+        EMSG("wrong parameter\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    if (digest_scheme == 0) {
+        return 0;
+    }
+    mode = sha_idx2ctl[digest_scheme];
+
+    if (sc_sha_init(&sha, 0) != 0) {
+        EMSG("sha initialize failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    if (sc_sha_start(&sha, &ctx, mode) != 0) {
+        EMSG("sha start failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    if (sc_sha_update(&sha, &ctx, buffer, buffer_size) != 0) {
+        EMSG("sha update failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    if (sc_sha_finish(&sha, &ctx, sum, &len) != 0) {
+        EMSG("sha finish failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+	sc_sha_uninit(&sha);
+
+    /* check digest value */
+    if (memcmp(digest, sum, len) != 0) {
+        EMSG("check digest failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    return 0;
+}
+
+/* Verify image specified in sbmeta_info_t. The image has been loaded to memory before */
+static int sbmeta_verify_image(uint32_t image_load_addr, sbmeta_info_t *sbmeta_info)
+{
+    uint32_t image_size = 0;
+    const char *image_name;
+    uint8_t image_type = sbmeta_info->image_type;
+    uint8_t checksum_scheme = sbmeta_info->checksum_scheme;
+    uint8_t *digest = sbmeta_info->digest;
+    uint8_t is_encrypted = sbmeta_info->isencrypted;
+    uint32_t security_level = env_get_hex("sbmeta_security_level", 3);
+    uint32_t filesize = 0;
+    char buf[64] = {0};
+
+    /* check image_type to avoid array index out of bounds */
+    if (image_type > IMAGE_TYPE_NUM || image_type < 0) {
+        EMSG("image type is out of range\r\n");
+        return CMD_RET_FAILURE;
+    }
+    image_name = image_name_s[image_type];
+
+    /* check tee/tf version if needed */
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+   if (image_have_head(image_load_addr) == 1) {
+        if (image_type == T_TF) {
+            IMSG("check TF version in boot \n");
+            if (check_tf_version_in_boot(LIGHT_TF_FW_TMP_ADDR) != 0) {
+                return CMD_RET_FAILURE;
+            }
+        }
+
+        if (image_type == T_TEE) {
+            IMSG("check TEE version in boot \n");
+            if (check_tee_version_in_boot(LIGHT_TEE_FW_ADDR) != 0) {
+                return CMD_RET_FAILURE;
+            }
+        }
+   }
+#endif
+
+    /* start verifying images */
+    IMSG("Process %s image verification ...\n", image_name);
+    if (security_level == 3 || is_encrypted != 0) {
+        if (verify_customer_image(image_type, image_load_addr) != 0) {
+            return CMD_RET_FAILURE;
+        }
+    } else if (security_level == 2) {
+        if (memcmp(digest, buf, 64) == 0) {
+            EMSG("sbmeta info doesn't specify digest value in security level 2\r\n");
+            return CMD_RET_FAILURE;
+        }
+
+        snprintf(buf, sizeof(buf), "ext4size mmc %x:%x %s", sbmeta_info->dev, sbmeta_info->part, sbmeta_info->filename);
+        if (run_command(buf, 0) != 0) {
+            EMSG("get file size error\r\n");
+            return CMD_RET_FAILURE;
+        }
+
+        filesize = env_get_hex("filesize", 0);
+        if (check_digest((uint8_t *)(uintptr_t)image_load_addr, filesize, checksum_scheme, digest) != 0) {
+            return CMD_RET_FAILURE;
+        }
+    }
+
+    /* move image headers always */
+    if (image_have_head(image_load_addr) == 1) {
+        image_size = get_image_size(image_load_addr);
+        IMSG("%s image size: %d\n", image_name, image_size);
+        if (image_size < 0) {
+            EMSG("GET %s image size error\n", image_name);
+            return CMD_RET_FAILURE;
+        }
+        if (image_type == T_TF) {
+            memmove((void *)(uintptr_t)LIGHT_TF_FW_ADDR, (const void *)(uintptr_t)(image_load_addr + HEADER_SIZE), image_size);
+        } else {
+            memmove((void *)(uintptr_t)image_load_addr, (const void *)(uintptr_t)(image_load_addr + HEADER_SIZE), image_size);
+        }
+    } else {
+        /* TF should be moved to LIGHT_TF_FW_ADDR all the cases*/
+        if (image_type == T_TF) {
+            /* while image_size is unknown, reload the image */
+            run_command("ext4load mmc 0:3 0x0 trust_firmware.bin", 0);
+        }
+    }
+
+    return 0;
+}
+
+static int light_sbmetaboot(int argc, char *const argv[])
+{
+    int count = 0;
+    uint32_t sbmeta_size = 0;
+    uint32_t info_addr = 0;
+    uint32_t image_load_addr = 0;
+    char cmd[64] = {0};
+    sbmeta_info_t *sbmeta_info = NULL;
+
+    /* Load sbmeta image to memory */
+    snprintf(cmd, sizeof(cmd), "ext4load mmc $mmcdev:%x 0x%p %s", SBMETA_PART, (void *)(uintptr_t)LIGHT_SBMETA_ADDR, SBMETA_FILENAME);
+    if (run_command(cmd, 0) != 0) {
+        /* if sbmeta doesn't exist, do secboot by default */
+        IMSG("SBMETA doesn't exist, go to verify tf/tee\r\n");
+
+        /*
+        * Verify tf and tee by command secboot.
+        * Note that tf and tee has been loaded in "run bootcmd_load"
+        */
+        if (run_command("secboot", 0) != 0) {
+            return CMD_RET_FAILURE;
+        }
+
+        return 0;
+    }
+
+    /* initialize crypto algorithm interfaces */
+    if (csi_sec_init() != 0) {
+        return CMD_RET_FAILURE;
+    }
+
+    /* Check and verify sbmeta image */
+    if (image_have_head(LIGHT_SBMETA_ADDR) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		IMSG("check SBMETA version in boot \n");
+		ret = check_sbmeta_version_in_boot(LIGHT_SBMETA_ADDR);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
+        IMSG("Process SBMETA image verification...\r\n");
+        if (verify_customer_image(T_SBMETA, LIGHT_SBMETA_ADDR) != 0) {
+            return CMD_RET_FAILURE;
+        }
+
+        sbmeta_size = get_image_size(LIGHT_SBMETA_ADDR);
+        IMSG("sbmeta_size:%d\r\n", sbmeta_size);
+        if (sbmeta_size != SBMETA_SIZE) {
+            EMSG("SBMETA header is wrong! Size must equal to %d bytes!\r\n", SBMETA_SIZE);
+            return CMD_RET_FAILURE;
+        }
+        /* move image headers always */
+        memmove((void *)LIGHT_SBMETA_ADDR, (const void *)(LIGHT_SBMETA_ADDR + HEADER_SIZE), sbmeta_size);
+    } else {
+        /* if sbmeta image is not secure, reset */
+        IMSG("SBMETA image must be with signature\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    /* Parse sbmeta_info_t in image sbmeta, then load and verify specified images */
+    info_addr = LIGHT_SBMETA_ADDR;
+    for (count = 0; count < MAX_ENTRY_NUM; count++) {
+        if (is_sbmeta_info(info_addr) == 0) {
+            /* Dump and check sbmeta info */
+            sbmeta_info = (sbmeta_info_t *)(uintptr_t)info_addr;
+            if (dump_sbmeta_info(sbmeta_info) != 0) {
+                return CMD_RET_FAILURE;
+            }
+
+            info_addr += ENTRY_SIZE;
+
+            /*
+             * If image_type != T_USER, load to address specified in light-c910.h;
+             * otherwise, load to user-specified address.
+            */
+            if (sbmeta_info->image_type != T_USER) {
+                image_load_addr = image_addrs[sbmeta_info->image_type];
+            } else {
+                image_load_addr = sbmeta_info->relocated_addr;
+            }
+
+            /*
+            * Load image specified in sbmeta info
+            * Note: only load images don't exist in env "bootcmd_load"
+            */
+            if (sbmeta_info->image_type == T_ROOTFS || sbmeta_info->image_type == T_USER) {
+                snprintf(cmd, sizeof(cmd), "ext4load mmc %x:%x %p %s", sbmeta_info->dev,
+                         sbmeta_info->part, \
+                         (void *)(uintptr_t)image_load_addr, sbmeta_info->filename);
+                if (run_command(cmd, 0) != 0) {
+                    return CMD_RET_FAILURE;
+                }
+            }
+
+            if (sbmeta_field_verify(sbmeta_info, image_load_addr) != 0) {
+                return CMD_RET_FAILURE;
+            }
+
+            /* Check and verify user-specified image */
+            if (sbmeta_verify_image(image_load_addr, sbmeta_info) != 0) {
+                return CMD_RET_FAILURE;
+            }
+        } else {
+            break;
+        }
+    }
+
+    /* if sbmeta didn't specify images, reset */
+    if (count == 0) {
+        EMSG("SBMETA doesn't specify any images!\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    /* Clear sbmeta buffer in memory */
+    memset((void *)LIGHT_SBMETA_ADDR, 0, PLAIN_SBMETA_TEXT);
+    return 0;
+}
+
+static int do_sbmetaboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+    if (light_sbmetaboot(argc, argv) != 0) {
+        EMSG("sbmetaboot failed\r\n");
+        while (1);
+        return CMD_RET_FAILURE;
+    }
+    return 0;
+}
+
+U_BOOT_CMD(
+    sbmetaboot, CONFIG_SYS_MAXARGS, 1, do_sbmetaboot,
+    "load and verify image sbmeta, then verify image files specified in sbmeta",
+    ""
+);
+#endif
+#endif

board/thead/light-c910/sbmeta/sbmeta.h

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited
+ */
+
+#ifndef _LIGHT_SBMETA_H
+#define _LIGHT_SBMETA_H
+
+#include "common.h"
+#include "command.h"
+#include <asm/arch-thead/boot_mode.h>
+
+#define MAX_NAME_SIZE       32
+#define MAX_DIGEST_SIZE     64
+#define SBMETA_MAGIC        0x544D4253  /* = {'S', 'B', 'M', 'T'} */
+
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#define LIGHT_SBMETA_ADDR   0x10000000
+#endif
+#define SBMETA_PART         5
+#define ENTRY_SIZE          128
+#define PLAIN_SBMETA_TEXT   4096
+#define SBMETA_SIZE         4736  /* 4K SMBETA image + 640 footer */
+#define MAX_ENTRY_NUM       PLAIN_SBMETA_TEXT / ENTRY_SIZE  /* 4K/128=32 */
+#define IMAGE_TYPE_NUM      7
+#define DIGEST_TYPE_NUM     8
+#define SIGN_TYPE_NUM       6
+#define SBMETA_FILENAME     "sbmeta.bin"
+
+#define SBMETA_SECURITY_LEVEL_H      3   /* verify signature and hash */
+#define SBMETA_SECURITY_LEVEL_M      2   /* verify checksum */
+#define SBMETA_SECURITY_LEVEL_L      1   /* no verification */
+
+#endif

board/thead/light-c910/sec_check.c

@@ -12,7 +12,7 @@
 #include <asm/arch-thead/boot_mode.h>
 #include "../../../lib/sec_library/include/csi_sec_img_verify.h"
 
-extern int csi_efuse_api_int(void);
+extern int csi_efuse_api_init(void);
 extern int csi_efuse_api_unint(void);
 extern int csi_efuse_read_raw(uint32_t addr, void *data, uint32_t cnt);
 extern int csi_efuse_write_raw(uint32_t addr, const void *data, uint32_t cnt);
@@ -35,7 +35,7 @@ int csi_sec_init(void)
 	char *version;
 
 	/* Initialize eFuse module */
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse init faild[%d]\n", ret);
 		 goto exit;
@@ -62,7 +62,7 @@ void designware_get_mac_from_fuse(unsigned char *mac)
 	int ret;
 
 	/* Initialize eFuse module */
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse init faild[%d]\n", ret);
 		return;
@@ -75,6 +75,89 @@ void designware_get_mac_from_fuse(unsigned char *mac)
 	}
 }
 
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+/* Secure function for image verificaiton here */
+int get_image_version(unsigned long img_src_addr)
+{
+	img_header_t *img = (img_header_t *)img_src_addr;
+	uint8_t magiccode[4] = {0};
+	
+	magiccode[3] = img->magic_num & 0xff;
+	magiccode[2] = (img->magic_num & 0xff00) >> 8;
+	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
+	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
+	if (memcmp(header_magic, magiccode, 4) == 0) {
+		return -1;
+	}
+	
+	return img->image_version;
+}
+
+int get_image_size(unsigned long img_src_addr)
+{
+	img_header_t *img = (img_header_t *)img_src_addr;
+	uint8_t magiccode[4] = {0};
+	
+	magiccode[3] = img->magic_num & 0xff;
+	magiccode[2] = (img->magic_num & 0xff00) >> 8;
+	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
+	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
+	if (memcmp(header_magic, magiccode, 4) == 0) {
+		return -1;
+	}
+	
+	return img->image_size;
+}
+
+void dump_image_header_info(long addr)
+{
+	img_header_t *phead = (img_header_t *)addr;
+
+	printf("\n---------------------------------------------\n");
+	printf("entry point: 0x%x\n", phead->entry_point);
+	printf("image size: %d Bytes\n", phead->image_size);
+	printf("head version: 0x%x\n", phead->head_version);
+	printf("image version: 0x%x\n", phead->image_version);
+	printf("image checksum: 0x%x\n", phead->image_checksum);
+	printf("image run addr: 0x%llx\n", phead->image_run_addr);
+	printf("image offset: 0x%x\n", phead->image_offset);
+	printf("image digest scheme: %d\n", phead->digest_scheme);
+	printf("image sign scheme: %d\n", phead->signature_scheme);
+	printf("image encrypt type: %d\n", phead->encrypt_type);
+	printf("\n---------------------------------------------\n");
+}
+
+int verify_customer_image(img_type_t type, long addr)
+{
+	int ret;
+
+	/* Double check image number */
+	if (image_have_head(addr) == 0) {
+		printf("error: image has no secure header\r\n");
+		return -1;
+	}
+
+	/* Dump image header information here */
+	dump_image_header_info(addr);
+
+	/* Call customer image verification function */
+	if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG) || (type == T_DTB) || (type == T_SBMETA)) {
+		ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
+		if (ret) {
+			printf("Image(%d) is verified fail, Please go to check!\n\n", type);
+			return ret;
+		}
+	} else if (type == T_UBOOT) {
+		ret = csi_sec_uboot_image_verify(addr, addr - PUBKEY_HEADER_SIZE);
+		if (ret) {
+			printf("Image(%s) is verified fail, Please go to check!\n\n", "uboot");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#else
 static int strtou32(const char *str, unsigned int base, u32 *result)
 {
 	char *ep;
@@ -110,7 +193,7 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 	int ret, i;
 
 	/* Initialize eFuse module */
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse init faild[%d]\n", ret);
 		goto err;
@@ -180,88 +263,6 @@ err:
 	return CMD_RET_FAILURE;
 }
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
-/* Secure function for image verificaiton here */
-int get_image_version(unsigned long img_src_addr)
-{
-	img_header_t *img = (img_header_t *)img_src_addr;
-	uint8_t magiccode[4] = {0};
-	
-	magiccode[3] = img->magic_num & 0xff;
-	magiccode[2] = (img->magic_num & 0xff00) >> 8;
-	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
-	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
-	if (memcmp(header_magic, magiccode, 4) == 0) {
-		return -1;
-	}
-	
-	return img->image_version;
-}
-
-int get_image_size(unsigned long img_src_addr)
-{
-	img_header_t *img = (img_header_t *)img_src_addr;
-	uint8_t magiccode[4] = {0};
-	
-	magiccode[3] = img->magic_num & 0xff;
-	magiccode[2] = (img->magic_num & 0xff00) >> 8;
-	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
-	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
-	if (memcmp(header_magic, magiccode, 4) == 0) {
-		return -1;
-	}
-	
-	return img->image_size;
-}
-
-void dump_image_header_info(long addr)
-{
-	img_header_t *phead = (img_header_t *)addr;
-
-	printf("\n---------------------------------------------\n");
-	printf("entry point: 0x%x\n", phead->entry_point);
-	printf("image size: %d Bytes\n", phead->image_size);
-	printf("head version: 0x%x\n", phead->head_version);
-	printf("image version: 0x%x\n", phead->image_version);
-	printf("image checksum: 0x%x\n", phead->image_checksum);
-	printf("image run addr: 0x%llx\n", phead->image_run_addr);
-	printf("image offset: 0x%x\n", phead->image_offset);
-	printf("image digest scheme: %d\n", phead->digest_scheme);
-	printf("image sign scheme: %d\n", phead->signature_scheme);
-	printf("image encrypt type: %d\n", phead->encrypt_type);
-	printf("\n---------------------------------------------\n");
-}
-
-int verify_customer_image(img_type_t type, long addr)
-{
-	int ret;
-    const char *image_name = "";
-    
-	/* Double check image number */
-	if (image_have_head(addr) == 0)
-		return -1;
-
-	/* Dump image header information here */
-	dump_image_header_info(addr);
-
-	/* Call customer image verification function */
-	if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG)) {
-		ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
-		if (ret) {
-			printf("Image(%d) is verified fail, Please go to check!\n\n", type);
-			return ret;
-		}
-	} else if (type == T_UBOOT) {
-		ret = csi_sec_uboot_image_verify(addr, addr - PUBKEY_HEADER_SIZE);
-		if (ret) {
-			printf("Image(%s) is verified fail, Please go to check!\n\n", "uboot");
-			return ret;
-		}
-	}
-
-	return 0;
-}
-#else
 U_BOOT_CMD(
 	efuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
 	"eFuse sub-system",

board/thead/light-c910/secimg_load.c

@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2018, Linaro Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <command.h>
+#include <env.h>
+#include <configs/light-c910.h>
+#include <asm/arch-thead/boot_mode.h>
+#include "sec_library.h"
+
+#define ENV_SECIMG_LOAD     "sec_m_load"
+#define VAL_SECIMG_LOAD     "ext4load mmc ${mmcdev}:${mmcteepart} $tf_addr trust_firmware.bin; ext4load mmc ${mmcdev}:${mmcteepart} $tee_addr tee.bin\0"
+
+#define RPMB_BLOCK_SIZE 256
+#define RPMB_ROLLBACK_BLOCK_START 1
+
+#ifndef LIGHT_KDF_RPMB_KEY
+static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
+												0xbb, 0xaa, 0x99, 0x88, 0xff, 0xee, 0xdd, 0xcc, \
+												0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
+												0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#endif
+
+extern int sprintf(char *buf, const char *fmt, ...);
+extern char * get_slot_name_suffix(void);
+
+static int get_rpmb_key(uint8_t key[32])
+{
+#ifndef LIGHT_KDF_RPMB_KEY
+    memcpy(key, emmc_rpmb_key_sample, sizeof(emmc_rpmb_key_sample));
+
+    return 0;
+#else
+	uint32_t kdf_rpmb_key_length = 0;
+	int ret = 0;
+	ret = csi_kdf_gen_hmac_key(key, &kdf_rpmb_key_length);
+	if (ret != 0) {
+		return -1;
+	}
+
+    return 0;
+#endif
+}
+
+static int get_image_file_size(unsigned long img_src_addr)
+{
+	img_header_t *img = (img_header_t *)img_src_addr;
+	uint8_t magiccode[4] = {0};
+
+	magiccode[3] = img->magic_num & 0xff;
+	magiccode[2] = (img->magic_num & 0xff00) >> 8;
+	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
+	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
+	if (memcmp(header_magic, magiccode, 4) == 0) {
+		return -1;
+	}
+
+	return img->image_size;
+}
+
+static int verify_and_load_image(unsigned long image_addr_src, unsigned long image_addr_dst)
+{
+    int ret = 0;
+	unsigned int image_size = 0;
+
+	if (image_have_head(image_addr_src) == 1) {
+        ret = csi_sec_init();
+        if (ret != 0) {
+			return -1;
+		}
+
+        ret = csi_sec_custom_image_verify(image_addr_src, UBOOT_STAGE_ADDR);
+        if (ret != 0) {
+            printf("image verify error\r\n");
+            return -2;
+        }
+
+		image_size = get_image_file_size(image_addr_src);
+		if (image_size  < 0) {
+            printf("image get size error\r\n");
+			return -3;
+		}
+
+		memmove((void *)image_addr_dst, (const void *)(image_addr_src + HEADER_SIZE), image_size);
+	} else {
+        printf("in secure mode but image has no header\r\n");
+		return -4;
+	}
+
+    return 0;
+}
+
+int verify_and_load_tee_tf_image(void)
+{
+    int ret = 0;
+
+    ret = verify_and_load_image(LIGHT_TF_FW_TMP_ADDR, LIGHT_TF_FW_ADDR);
+    if (ret != 0) {
+        printf("verify tf image failed\r\n");
+        return ret;
+    }
+    printf("verify trust firmware image success\r\n");
+
+    ret = verify_and_load_image(LIGHT_TEE_FW_ADDR, LIGHT_TEE_FW_ADDR);
+    if (ret != 0) {
+        printf("verify tee image failed\r\n");
+        return ret;
+    }
+    printf("verify tee image success\r\n");
+
+    return 0;
+}
+
+/* In order to use common bootloader for both secure boot and non-secure boot,
+   we only know the boot type through reading the sec_boot field in efuse. Due to
+   the efuse is only accessed in lifecycle(DEV/OEM/PRO/RMP), we ensure it must be
+   non-secure boot in lifecycle(INIT) */
+bool get_system_boot_type(void)
+{
+	bool btype = true; /* false: non-secure boot | true: secure boot */
+#if 0
+	int lc = 0;
+	sboot_st_t sb_flag = SECURE_BOOT_DIS;
+	int ret = 0;
+#endif
+	int sb_emulater = 0;
+
+	sb_emulater = env_get_ulong("sb_emulater", 10, 0);
+	if (sb_emulater == 0) {
+		btype = false;
+	}
+# if 0
+	ret = csi_efuse_get_lc(&lc);
+	/* 0: LC_INIT, 1: LC_DEV, 2: LC_OEM, 3: LC_PRO */
+	if ((ret == 0) && (lc != 0)) {
+		csi_efuse_api_init();
+
+		/* Check platform secure boot enable ? */
+		ret = csi_efuse_get_secure_boot_st(&sb_flag);
+		if ((ret == 0) && (sb_flag == SECURE_BOOT_EN))
+			btype = true;
+
+		csi_efuse_api_uninit();
+	}
+#endif
+	return btype;
+}
+
+int sec_read_rollback_index(size_t rollback_index_slot, uint64_t *out_rollback_index)
+{
+	char runcmd[64] = {0};
+	unsigned char blkdata[RPMB_BLOCK_SIZE];
+    size_t rpmb_block = (rollback_index_slot * sizeof(uint64_t)) / RPMB_BLOCK_SIZE + RPMB_ROLLBACK_BLOCK_START;
+    size_t rpmb_offset = (rollback_index_slot * sizeof(uint64_t)) % RPMB_BLOCK_SIZE;
+
+    sprintf(runcmd, "mmc rpmb read 0x%lx %ld 1", (unsigned long)blkdata, rpmb_block);
+	if(run_command(runcmd, 0)) {
+        printf("read_rollback_index failed, mmc read error\r\n");
+        return -1;
+    }
+
+    *out_rollback_index = *(uint64_t*)(blkdata + rpmb_offset);
+	return 0;
+}
+
+int sec_write_rollback_index(size_t rollback_index_slot, uint64_t rollback_index)
+{
+    char runcmd[64] = {0};
+	unsigned char blkdata[RPMB_BLOCK_SIZE];
+    size_t rpmb_block = (rollback_index_slot * sizeof(uint64_t)) / RPMB_BLOCK_SIZE + RPMB_ROLLBACK_BLOCK_START;
+    size_t rpmb_offset = (rollback_index_slot * sizeof(uint64_t)) % RPMB_BLOCK_SIZE;
+    uint8_t rpmb_key[32];
+
+    sprintf(runcmd, "mmc rpmb read 0x%lx %ld 1", (unsigned long)blkdata, rpmb_block);
+	if(run_command(runcmd, 0)) {
+        printf("read_rollback_index failed, mmc read error\r\n");
+        return -1;
+    }
+
+    *(uint64_t*)(blkdata + rpmb_offset) = rollback_index;
+
+    if (get_rpmb_key(rpmb_key) != 0) {
+        return -2;
+    }
+
+	sprintf(runcmd, "mmc rpmb write 0x%lx %ld 1 0x%lx", (unsigned long)blkdata, rpmb_block, (unsigned long)rpmb_key);
+    if(run_command(runcmd, 0)) {
+        printf("read_rollback_index failed, mmc write error\r\n");
+        return -3;
+    }
+
+    return 0;
+}
+
+static int do_secimg_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+    bool sb_enable = false;
+    const char *secimgs_load_str = VAL_SECIMG_LOAD;
+    int ret = -1;
+    int teepart = 0;
+
+#ifdef CONFIG_ANDROID_AB
+	char *slot_suffix = get_slot_name_suffix();
+    teepart = env_get_ulong("mmcteepart", 10, 8);
+	if ((strcmp(slot_suffix, "_a") == 0) && (teepart != 8)) {
+		/* Switch mmcbootpart to "_b" */
+		env_set_ulong("mmcbootpart", 2);
+		/* Switch mmcteepart to "_b" */
+		env_set_ulong("mmcteepart", 8);
+	} else if ((strcmp(slot_suffix, "_b") == 0) && (teepart != 9)){
+		/* Switch mmcbootpart to "_b" */
+		env_set_ulong("mmcbootpart", 3);
+		/* Switch mmcteepart to "_b" */
+		env_set_ulong("mmcteepart", 9);
+	}
+#endif
+
+	sb_enable = get_system_boot_type();
+	if (sb_enable) {
+		/* By default, the value for ENV-SEC-M-LOAD is always to load opensbi image.
+		* if secure boot is enable, we force to change the value to load tee image.
+		* but Never to save it in volatile-RAM
+		*/
+		ret = env_set(ENV_SECIMG_LOAD, secimgs_load_str);
+		if (ret != 0) {
+			printf("Rewrite ENV (%s) fails\n", ENV_SECIMG_LOAD);
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	secimg_load, 1, 1,	do_secimg_load,
+	"Runtime-load secure image if secure system is enable",
+	NULL
+);

board/thead/light-c910/spl.c

@@ -26,6 +26,11 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void init_ddr(void);
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+extern int fixup_ddr_addrmap(unsigned long size);
+extern int query_ddr_boundary(unsigned long size);
+#endif
+extern unsigned long get_ddr_density(void);
 extern void cpu_clk_config(int cpu_freq);
 extern void sys_clk_config(void);
 extern void ddr_clk_config(int ddr_freq);
@@ -48,6 +53,7 @@ static struct light_reset_list light_post_reset_lists[] = {
 	{0x00000002, 0xFFEF528000}, /* VO sys_reg: GPU rst */
 	{0x00000003, 0xFFEF528000}, /* VO sys_reg: GPU rst */
 	{0x00000007, 0xFFFF529004}, /* VO sys_reg: DPU rst */
+	{0x07FFFF18, 0xFFCB000014}, /* Audio sys_reg: DMA rst */
 };
 
 static void light_pre_reset_config(void)
@@ -92,6 +98,25 @@ void setup_ddr_pmp(void)
 	sync_is();
 }
 
+void clear_ddr_pmp(void)
+{
+	/* restore pmp entry0,entry1 setting in bootrom */
+	writel(0x0400000000 >> 12, (void *)(PMP_BASE_ADDR + 0x104));
+	writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x100));
+	writel(0xffe1000000 >> 12, (void *)(PMP_BASE_ADDR + 0x10c));
+	writel(0xffe0180000 >> 12, (void *)(PMP_BASE_ADDR + 0x108));
+
+	writel(0x4040, (void *)(PMP_BASE_ADDR + 0x000));
+
+	sync_is();
+}
+
+static inline void _l2cache_ciall(void)
+{
+	asm volatile (".long 0x0170000b");
+}
+
+
 int get_rng(unsigned int *rng, int cnt)
 {
 	int i;
@@ -296,17 +321,113 @@ void setup_ddr_parity(void)
 	}
 }
 
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+
+#define MAGIC_DATA (0xF4240)
+#define MAGIC_DATA2 (0x5AA5)
+#define MAGIC_DATA3 (0x3C3C)
+#define MAGIC_DATA4 (0xF0F0)
+
+/*
+return: 0: found boundary;
+*/
+int boundary_verify(unsigned long boundary) {
+	phys_addr_t verify_addr = (phys_addr_t)CONFIG_SYS_SDRAM_BASE;
+	phys_addr_t verify_addr2 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/4;
+	phys_addr_t verify_addr3 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/2;
+	phys_addr_t verify_addr4 = (phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE;
+
+	// verify data accessing result firstly
+	writel(MAGIC_DATA2, verify_addr);
+	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl(verify_addr) != MAGIC_DATA2) {
+		printf("ddr rw test failed\n");
+		return -1;
+	}
+	writel(MAGIC_DATA, verify_addr);  // writing at beginning
+	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl(verify_addr) != MAGIC_DATA) {
+		printf("ddr rw test failed\n");
+		return -1;
+	}
+	writel(MAGIC_DATA2, verify_addr2); // writing at one-quarter addr
+	writel(MAGIC_DATA3, verify_addr3); // writing at half addr
+	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
+	invalidate_dcache_range(verify_addr2, verify_addr2 + CONFIG_SYS_CACHELINE_SIZE);
+	invalidate_dcache_range(verify_addr3, verify_addr3 + CONFIG_SYS_CACHELINE_SIZE);
+
+	if (boundary == (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB) { // boundary by design
+		if ((readl(verify_addr) == MAGIC_DATA) &&
+			(readl(verify_addr2) == MAGIC_DATA2) &&
+			(readl(verify_addr3) == MAGIC_DATA3))
+			return 0;
+	}
+	else {
+		writel(MAGIC_DATA4, verify_addr4); // writing out of boundary
+		invalidate_dcache_range(verify_addr4, verify_addr4 + CONFIG_SYS_CACHELINE_SIZE);
+		if ((readl(verify_addr) == MAGIC_DATA4) && // overwrite by verify_addr4
+			(readl(verify_addr2) == MAGIC_DATA2) &&
+			(readl(verify_addr3) == MAGIC_DATA3) &&
+			(readl(verify_addr4) == MAGIC_DATA4))
+			return 0;
+	}
+
+	return -1;
+}
+
+int setup_ddr_addrmap(void)
+{
+	int ret;
+	unsigned long boundary = (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB;
+
+	// verify data accessing result firstly
+	writel(MAGIC_DATA, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
+	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA) {
+		printf("ddr rw test failed\n");
+		goto addrmap_err;
+	}
+	writel(MAGIC_DATA2, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
+	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA2) {
+		printf("ddr rw test failed\n");
+		goto addrmap_err;
+	}
+
+	// try to find memory boundary
+	while (boundary >= (unsigned long)MINIMAL_DDR_DENSITY_MB * UNIT_MB) {
+		if (query_ddr_boundary(boundary) == 0) {
+			clear_ddr_pmp();
+			fixup_ddr_addrmap(boundary);
+			setup_ddr_pmp();
+			if (boundary_verify(boundary) == 0) {
+				gd->ram_size = boundary;
+				printf("found ddr boundary <0x%lx>\n", boundary);
+				return 0;
+			}
+		}
+		boundary = boundary >> 1;
+	}
+
+	gd->ram_size = get_ddr_density();
+addrmap_err:
+	printf("failed to setup ddr addrmap\n");
+	return -1;
+}
+#endif
+
 void cpu_performance_enable(void)
 {
 #define CSR_MHINT2_E	0x7cc
 #define CSR_MHINT4	0x7ce
 	csr_write(CSR_SMPEN, 0x1);
-	csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x20000);
+	// FIXME set mhint2[22] to enable core icg en
+	csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x420000);
 	csr_write(CSR_MHINT4, csr_read(CSR_MHINT4) | 0x410);
 	csr_write(CSR_MCCR2, 0xe2490009);
-	csr_write(CSR_MHCR, 0x117f); // clear bit7 to disable indirect brantch prediction
-	csr_write(CSR_MXSTATUS, 0x638000);
-	csr_write(CSR_MHINT, 0x6e30c | (1<<22)); // set bit22 to close fence broadcast
+	// FIXME: Clear bit[12] to disable L0BTB.
+	csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
+	csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
 }
 
 static int bl1_img_have_head(unsigned long img_src_addr)
@@ -368,9 +489,9 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 
 #ifdef CONFIG_PMIC_VOL_INIT
-	ret = pmic_ddr_regu_init();
+	ret = aon_local_init();
 	if (ret) {
-		printf("%s pmic init failed %d \n",__func__,ret);
+		printf("%s aon local init failed %d \n",__func__,ret);
 		hang();
 	}
 
@@ -385,7 +506,6 @@ void board_init_f(ulong dummy)
 		printf("%s set apcpu voltage failed \n",__func__);
 		hang();
 	}
-
 #endif
 	ddr_clk_config(0);
 	cpu_clk_config(0);
@@ -394,14 +514,31 @@ void board_init_f(ulong dummy)
 	setup_ddr_scramble();
 	setup_ddr_parity();
 	setup_ddr_pmp();
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+	setup_ddr_addrmap();
+#else
+	// update ram_size from board config
+	gd->ram_size = get_ddr_density();
+#endif
 
 	printf("ddr initialized, jump to uboot\n");
 	light_board_init_r(NULL, 0);
 }
 
+static uint32_t get_custom_boot_seq(void)
+{
+	/* boot media definition */
+	/* BOOT_DEVICE_MMC1 - boot from eMMC or SD card */
+	/* BOOT_DEVICE_NAND - boot from nand flash */
+	/* BOOT_DEVICE_SPI - boot from spi flash */
+	/* TODO: user can decide the boot media according their own configuration */
+	return BOOT_DEVICE_MMC1;
+}
+
 void board_boot_order(u32 *spl_boot_list)
 {
 #define SOC_OM_ADDRBASE        0xffef018010
+#if CONFIG_IS_ENABLED(LIGHT_BOOT_FORCE_SEQ)
 	switch (readl((void *)SOC_OM_ADDRBASE) & 0x7) {
 	case 0:
 	case 1:
@@ -428,6 +565,8 @@ void board_boot_order(u32 *spl_boot_list)
 	default:
 		spl_boot_list[0] = BOOT_DEVICE_NONE;
 	}
-
+#else
+	spl_boot_list[0] = get_custom_boot_seq();
+#endif
 	cpu_performance_enable();
 }

board/thead/light-c910/sys_clk.c

@@ -43,9 +43,9 @@ void cpu_clk_config(uint32_t cpu_freq)
 	udelay(11);
 
 	/* config bus: cpu clk ratio to 1:1 */
-	writel((readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
-	writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
-	writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
+	writel((readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
+	writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
+	writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
 
 	/* switch c910_cclk to cpu_pll1_foutpostdiv */
 	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
@@ -290,7 +290,7 @@ void sys_clk_config(void)
 
 	/* The boards other than the LightA board perform the bus down-speed operation */
 
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 	/* axi_sram_clk: 812.8512MHz -> 688.128MHz */
 	tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
 	tmp |= 0x2000;

cmd/Kconfig

@@ -263,6 +263,12 @@ config CMD_BOOTI
 	help
 	  Boot an AArch64 Linux Kernel image from memory.
 
+config CMD_BOOTANDROID
+	bool "bootandroid"
+	default n
+	help
+	Boot an android image from mmc.
+
 config BOOTM_LINUX
 	bool "Support booting Linux OS images"
 	depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI

cmd/Makefile

@@ -175,6 +175,7 @@ obj-$(CONFIG_CMD_REGULATOR) += regulator.o
 obj-$(CONFIG_CMD_BLOB) += blob.o
 
 # Android Verified Boot 2.0
+obj-$(CONFIG_CMD_BOOTANDROID) += bootandroid.o
 obj-$(CONFIG_CMD_AVB) += avb.o
 
 obj-$(CONFIG_DDR_SCAN) += ddrscan.o

cmd/avb.c

@@ -312,6 +312,10 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
 		printf("Unknown error occurred\n");
 	}
 
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+	if (out_data)
+		avb_slot_verify_data_free(out_data);
+#endif
 	return res;
 }
 

cmd/bootandroid.c

@@ -0,0 +1,566 @@
+/*
+ * (C) Copyright 2018, Linaro Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <avb_verify.h>
+#include <command.h>
+#include <env.h>
+#include <image.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <android_image.h>
+#include <android_bootloader_message.h>
+#include <xbc.h>
+
+#define ENV_KERNEL_ADDR  "kernel_addr"
+#define ENV_RAMDISK_ADDR "ramdisk_addr"
+#define ENV_DTB_ADDR     "dtb_addr"
+#define DEFAULT_KERNEL_ADDR  0x00200800
+#define DEFAULT_RAMDISK_ADDR LIGHT_ROOTFS_ADDR
+#define DEFAULT_DTB_ADDR     LIGHT_DTB_ADDR
+#define ENV_RAMDISK_SIZE "ramdisk_size"
+#define MISC_PARTITION "misc"
+#define RECOVERY_PARTITION "recovery"
+#define BOOT_PARTITION "boot"
+#define VENDOR_BOOT_PARTITION "vendor_boot"
+
+#define BOOTDEV_DEFAULT		0
+#define BCB_BOOTONCE	"bootonce-bootloader"
+#define BCB_BOOTRECOVERY	"boot-recovery"
+
+
+/*
+ * Knowing secure boot is enable or disable dependents on
+ * special data field in efuse and efuse control register.
+ */
+extern bool get_system_boot_type(void);
+/*
+ * The suffix for partition name is from the value of ENV_BOOTAB
+ */
+static const char *slot_name_suffix = NULL;
+
+/*
+ * BOOT IMAGE HEADER V3/V4 PAGESIZE
+ * Source code:system/tools/mkbootimg/unpack_bootimg.py
+ */
+#define BOOT_IMAGE_HEADER_V3_PAGESIZE 4096
+
+static struct AvbOps *avb_ops = NULL;
+static struct bootloader_message_ab *s_bcb = NULL;
+static struct bootloader_control *boot_ctl = NULL;
+
+static char *get_boot_partition_name_suffix(void)
+{
+#ifdef CONFIG_ANDROID_AB
+    if (boot_ctl != NULL) {
+		/* index 0 is _a, index 1 is _b*/
+		if(boot_ctl->slot_info[0].priority < boot_ctl->slot_info[1].priority) {
+			strcpy(boot_ctl->slot_suffix, "_b");
+		} else {
+			strcpy(boot_ctl->slot_suffix, "_a");
+		}
+	} else {
+		printf("get_slot_suffix boot_ctl is null return _a");
+		return "_a";
+	}
+	printf("get_slot_suffix boot_ctl->slot_suffix %s\r\n", boot_ctl->slot_suffix);
+	return boot_ctl->slot_suffix;
+#else
+	return "";
+#endif
+}
+
+static void get_partition_name(const char *partion, char *partion_name)
+{
+	strcpy(partion_name, partion);
+	strcat(partion_name, get_boot_partition_name_suffix());
+}
+
+/*
+ *format 4 chars/bytes to a int number
+ */
+static int byteToInt(uint8_t* data,int offset)
+{
+	return data[offset+0] + (data[offset+1] << 8) + (data[offset+2] << 16) + (data[offset+3] << 24);
+}
+
+static int get_number_of_pages(int image_size, int page_size)
+{
+    return (image_size + page_size - 1) / page_size;
+}
+
+/**
+ * header_version >=3,get dtb data from vendor_boot.img ,else boot.img.
+ *
+ * header_version = 4,get bootconfig data from vendor_boot.img ,
+ * and append bootconfig to the end of ramdisk(initrd)
+ * doc:https://www.kernel.org/doc/html/next/translations/zh_CN/admin-guide/bootconfig.html#initrd
+ */
+static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start, uint8_t** buf_bootconfig, int* vendor_bootconfig_size, bool isRecovery)
+{
+	int ret;
+	disk_partition_t part_info;
+	uint8_t* vendor_boot_data = NULL;
+	struct blk_desc *dev_desc  = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	char vb_part_name[32] = {0};
+
+	if (hdr == NULL) {
+		printf("invalid hdr\n");
+		return -1;
+	}
+
+	/* if the vendor boot partition name is beyond 32B, arise error */
+	if ((32 - strlen(VENDOR_BOOT_PARTITION)) < 2)
+		return -1;
+	
+    get_partition_name(VENDOR_BOOT_PARTITION, vb_part_name);
+
+	printf("blk_get_dev %s\n", vb_part_name);
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		printf("MMC err: invalid mmc device\n");
+		return -1;
+	}
+	/* Get boot partition info */
+	ret = part_get_info_by_name(dev_desc, vb_part_name, &part_info);
+	if (ret < 0) {
+		printf("MMC err: cannot find %s partition\n", vb_part_name);
+		return -1;
+	}
+
+    if (part_info.size * part_info.blksz > CONFIG_FASTBOOT_BUF_SIZE) {
+        return -1;
+    }
+    //vendor_boot_data = (uint8_t*)CONFIG_FASTBOOT_BUF_ADDR;
+
+	printf("vendor_boot_data part_info.size = %ld, part_info.blksz = %lu", part_info.size, part_info.blksz);
+	// reuse kernel start address to load vendor boot data
+	// because av_malloc(32M) failed in 2G devices
+	// TODO: why av_malloc failed
+	// ATTATION: If the vendor_boot partition size > boot partition size, it is error.
+	// avb_malloc(part_info.size * part_info.blksz);
+	vendor_boot_data = (uint8_t*)env_get_hex(ENV_KERNEL_ADDR, DEFAULT_KERNEL_ADDR);
+
+	ret = blk_dread(dev_desc, part_info.start, part_info.size, vendor_boot_data);
+	// vendor_boot.img
+	//* +------------------------+
+	//* | vendor boot header     | o pages
+	//* +------------------------+
+	//* | vendor ramdisk section | p pages
+	//* +------------------------+
+	//* | dtb                    | q pages
+	//* +------------------------+
+	//* | vendor ramdisk table   | r pages
+	//* +------------------------+
+	//* | bootconfig             | s pages
+	//* +------------------------+
+	//* o = (2124 + page_size - 1) / page_size
+	//* p = (vendor_ramdisk_size + page_size - 1) / page_size
+	//* q = (dtb_size + page_size - 1) / page_size
+	//* r = (vendor_ramdisk_table_size + page_size - 1) / page_size
+	//* s = (vendor_bootconfig_size + page_size - 1) / page_size
+
+	// see system/tools/mkbootimg/unpack_bootimg.py
+	// info.boot_magic = unpack('8s', args.boot_img.read(8))[0].decode()
+	// info.header_version = unpack('I', args.boot_img.read(4))[0]
+	// info.page_size = unpack('I', args.boot_img.read(4))[0]
+	// info.kernel_load_address = unpack('I', args.boot_img.read(4))[0]
+	// info.ramdisk_load_address = unpack('I', args.boot_img.read(4))[0]
+	// info.vendor_ramdisk_size = unpack('I', args.boot_img.read(4))[0]
+	// info.cmdline = cstr(unpack('2048s', args.boot_img.read(2048))[0].decode())
+	// info.tags_load_address = unpack('I', args.boot_img.read(4))[0]
+	// info.product_name = cstr(unpack('16s', args.boot_img.read(16))[0].decode())
+	// info.header_size = unpack('I', args.boot_img.read(4))[0]
+	// info.dtb_size = unpack('I', args.boot_img.read(4))[0]
+	// info.dtb_load_address = unpack('Q', args.boot_img.read(8))[0]
+	// info.vendor_ramdisk_table_size = unpack('I', args.boot_img.read(4))[0]
+	// vendor_ramdisk_table_entry_num = unpack('I', args.boot_img.read(4))[0]
+	// vendor_ramdisk_table_entry_size = unpack('I', args.boot_img.read(4))[0]
+	// info.vendor_bootconfig_size = unpack('I', args.boot_img.read(4))[0]
+	// num_vendor_ramdisk_table_pages = get_number_of_pages(
+	// 	info.vendor_ramdisk_table_size, page_size)
+	// vendor_ramdisk_table_offset = page_size * (
+	// 	num_boot_header_pages + num_boot_ramdisk_pages + num_boot_dtb_pages)
+	// bootconfig_offset = page_size * (num_boot_header_pages
+	// 	+ num_boot_ramdisk_pages + num_boot_dtb_pages
+	// 	+ num_vendor_ramdisk_table_pages)
+
+	int vendor_boot_pagesize = byteToInt(vendor_boot_data,12);//offset 12
+	int vendor_ramdisk_size = byteToInt(vendor_boot_data,24);//offset 24
+	int dtb_size = byteToInt(vendor_boot_data,2100);//offset 2100
+	int o = (2124 + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	int p = (vendor_ramdisk_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	int dtb_offset = vendor_boot_pagesize * (o + p);
+
+	hdr->dtb_size=  dtb_size;
+	memcpy((void *)(uint64_t)dtb_start, vendor_boot_data + dtb_offset, hdr->dtb_size);
+
+	int q=(hdr->dtb_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	int vendor_ramdisk_table_size=byteToInt(vendor_boot_data,2112);//offset 2112
+	
+	int r=(vendor_ramdisk_table_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	*vendor_bootconfig_size=byteToInt(vendor_boot_data,2124);//offset 2124
+	
+	*buf_bootconfig = avb_malloc(*vendor_bootconfig_size);
+	if (*buf_bootconfig == NULL) {
+		printf("vendor bootconfig malloc fail\n");
+		return -1;
+	}
+	int bootconfig_offset=vendor_boot_pagesize * (o + p + q + r);
+	memcpy(*buf_bootconfig, vendor_boot_data + bootconfig_offset, *vendor_bootconfig_size);
+
+#ifdef CONFIG_ANDROID_AB
+	char *find_str = NULL;
+	char *slot_suffix = get_boot_partition_name_suffix();
+    char *slot_suffx_pre = "androidboot.slot_suffix=";
+	printf("prepare_data_from_vendor_boot slot_suffix:%s\n", slot_suffix);
+    printf("prepare_data_from_vendor_boot slot_suffx_pre:%s\n", slot_suffx_pre);
+
+	find_str = strstr((char *)*buf_bootconfig, slot_suffx_pre);
+    if (find_str != NULL) {
+		memcpy(find_str + strlen(slot_suffx_pre), slot_suffix, strlen(slot_suffix));
+	}
+#endif
+
+	if (isRecovery) {
+		int i = 0;
+		struct vendor_ramdisk_table_entry *ramdisk_entry = NULL;
+		int vendor_ramdisk_table_offset = vendor_boot_pagesize * (o + p + q);
+		int vendor_ramdisk_table_entry_num = byteToInt(vendor_boot_data,2116);//offset 2116
+		printf("vendor_boot vendor_ramdisk_table_entry_num:%d\n",vendor_ramdisk_table_entry_num);
+		int vendor_ramdisk_table_entry_size = byteToInt(vendor_boot_data,2120);//offset 2116
+		printf("vendor_boot vendor_ramdisk_table_entry_size:%d\n",vendor_ramdisk_table_entry_size);
+		for (i = 0; i < vendor_ramdisk_table_entry_num; i++) {
+			ramdisk_entry = (struct vendor_ramdisk_table_entry*)(vendor_boot_data + vendor_ramdisk_table_offset
+											 + ( i * vendor_ramdisk_table_entry_size ));
+			if (ramdisk_entry->ramdisk_type != VENDOR_RAMDISK_TYPE_RECOVERY) {
+				continue;
+			}
+			printf("find recovery from ramdisk table.");
+			int ramdisk_start = env_get_hex(ENV_RAMDISK_ADDR, DEFAULT_RAMDISK_ADDR);
+			int recovery_ramdisk_offset = vendor_boot_pagesize * o + ramdisk_entry->ramdisk_offset;
+			memcpy((void *)(uint64_t)ramdisk_start, vendor_boot_data + recovery_ramdisk_offset,
+													 ramdisk_entry->ramdisk_size);//ramdisk
+			//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
+			char* bootconfig_params = (char*)*buf_bootconfig;
+			int ret = addBootConfigParameters(bootconfig_params, *vendor_bootconfig_size,
+						ramdisk_start + ramdisk_entry->ramdisk_size , 0);
+			if (ret == -1) {
+				printf("\nadd BootConfig Parameters error!!!\n");
+			} else {
+				printf("\nramdisk size is changed,new value is:%d\n",ramdisk_entry->ramdisk_size + ret);
+				//set ramdisk size for bootm
+				env_set_hex(ENV_RAMDISK_SIZE, ramdisk_entry->ramdisk_size + ret);
+			}
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static void prepare_loaded_parttion_data(const uint8_t* data, bool isRecovery)
+{
+	struct andr_img_hdr *hdr = (struct andr_img_hdr *)map_sysmem((phys_addr_t)data, 0);
+
+	if (IMAGE_FORMAT_ANDROID == genimg_get_format(hdr)) {
+		int dtb_start = env_get_hex(ENV_DTB_ADDR, DEFAULT_DTB_ADDR);
+		uint8_t* buf_bootconfig = NULL;
+		int size_bootconfig=0;
+
+		printf("Boot image header_version:%d\n", hdr->header_version);
+		if (hdr->header_version >= 3) {
+			// see system/tools/mkbootimg/unpack_bootimg.py
+			hdr->kernel_size = byteToInt((uint8_t *)data, 8);
+			hdr->ramdisk_size = byteToInt((uint8_t *)data, 12);
+			hdr->page_size = BOOT_IMAGE_HEADER_V3_PAGESIZE;
+			prepare_data_from_vendor_boot(hdr,dtb_start,&buf_bootconfig,&size_bootconfig,isRecovery);
+		}
+
+		int kernel_start = env_get_hex(ENV_KERNEL_ADDR, DEFAULT_KERNEL_ADDR);
+		int ramdisk_start = env_get_hex(ENV_RAMDISK_ADDR, DEFAULT_RAMDISK_ADDR);
+		// see system/tools/mkbootimg/unpack_bootimg.py
+ 		int page_size = hdr->page_size;
+		int num_header_pages = 1;
+		int num_kernel_pages = get_number_of_pages(hdr->kernel_size, page_size);
+		int num_ramdisk_pages = get_number_of_pages(hdr->ramdisk_size, page_size);
+		int kernel_offset = page_size * num_header_pages;
+		int ramdisk_offset = page_size * (num_header_pages + num_kernel_pages);
+		int dtb_offset = page_size * (num_header_pages + num_kernel_pages + num_ramdisk_pages);
+
+		printf("Boot image kernel_start:%x, kernel_offset:%x, kernel_size:%d\n", kernel_start, kernel_offset, hdr->kernel_size);
+		printf("Boot image ramdisk_start:%x, ramdisk_offset:%x, ramdisk_size:%d\n", ramdisk_start, ramdisk_offset, hdr->ramdisk_size);
+		printf("Boot image page_size:%d\n", hdr->page_size);
+		printf("dtb_offset:%x, dtb_size:%d\n", dtb_offset, hdr->dtb_size);
+
+ 		if (kernel_start + hdr->kernel_size > ramdisk_start || kernel_start + hdr->kernel_size > dtb_start) {
+			printf("boot.img kernel space and ramdis space are overlaped !!!\n");
+		} else {
+			memcpy((void *)(uint64_t)kernel_start, data + kernel_offset, hdr->kernel_size);
+			if (!isRecovery) {
+				memcpy((void *)(uint64_t)ramdisk_start, data + ramdisk_offset, hdr->ramdisk_size);
+			}
+
+			if( hdr->header_version < 3) {
+				//set ramdisk size for bootm
+				env_set_hex(ENV_RAMDISK_SIZE, hdr->ramdisk_size);
+				memcpy((void *)(uint64_t)dtb_start, data + dtb_offset, hdr->dtb_size);
+			} else if (!isRecovery) {
+				//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
+				char* bootconfig_params=(char*)buf_bootconfig;
+				int ret = addBootConfigParameters(bootconfig_params, size_bootconfig,
+                            						ramdisk_start + hdr->ramdisk_size , 0);
+				if (ret == -1) {
+					printf("Bootconfig Err: add BootConfig Parameters error!!!\n");
+				} else {
+					printf("ramdisk size is updated to new value is:%d\n",hdr->ramdisk_size + ret);
+					//set ramdisk size for bootm
+					env_set_hex(ENV_RAMDISK_SIZE, hdr->ramdisk_size + ret);
+				}
+			}
+		}
+		if (buf_bootconfig != NULL) {
+			avb_free(buf_bootconfig);
+		}
+	}
+	unmap_sysmem(hdr);
+}
+
+static int prepare_boot_data(const AvbSlotVerifyData *out_data, bool isRecovery)
+{
+	int res = CMD_RET_FAILURE;
+	int i = 0;
+	int num_loaded_partition = out_data->num_loaded_partitions;
+
+	printf("@@@@ prepare loaded partition (%d) data start\n", num_loaded_partition);
+	for (i = 0; i < num_loaded_partition; i++) {
+		const AvbPartitionData *loaded_partition = &out_data->loaded_partitions[i];
+		
+		if (loaded_partition->partition_name != NULL) {
+			printf("partition_name=%s, data_size=%ld\n", \
+					loaded_partition->partition_name, loaded_partition->data_size);
+			prepare_loaded_parttion_data(loaded_partition->data, isRecovery);
+		}
+	}
+	return res;
+}
+
+static void prepare_partition_data(const char *name, bool isRecovery)
+{
+	int ret = 0;
+	disk_partition_t part_info;
+	struct blk_desc *dev_desc  = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	uint8_t *data = NULL;
+
+	printf("prepare_partition_data %s\n", name);
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		printf("MMC err: invalid mmc device\n");
+		return;
+	}
+	/* Get boot partition info */
+	ret = part_get_info_by_name(dev_desc, name, &part_info);
+	if (ret < 0) {
+		printf("MMC err: cannot find %s partition\n", name);
+		return;
+	}
+
+	data = avb_malloc(part_info.size * part_info.blksz);
+	if (data == NULL) {
+		printf("avb malloc(%ldKB) fails\n", part_info.size * part_info.blksz / 1024);
+		return;
+	}
+
+	ret = blk_dread(dev_desc, part_info.start, part_info.size, data);
+	prepare_loaded_parttion_data(data, isRecovery);
+	
+	printf("prepare_partition_data %s, read=%d, start:%lx, size:%ld, blksize:%lx\n", \
+			name, ret, part_info.start, part_info.size, part_info.blksz);
+
+	avb_free(data);
+}
+
+static void clear_bcb(void)
+{
+	int ret;
+	disk_partition_t part_info;
+	struct blk_desc *dev_desc  = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
+	//bcb clear and store
+	memset(s_bcb, 0, sizeof(struct bootloader_message_ab));
+
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		printf("BootAndriod bcb err: invalid mmc device\n");
+		return;
+	}
+	/* Get boot partition info */
+	ret = part_get_info_by_name(dev_desc, MISC_PARTITION, &part_info);
+	if (ret < 0) {
+		printf("BootAndriod bcb err: cannot find misc partition\n");
+		return;
+	}
+
+	ret = blk_dwrite(dev_desc, part_info.start, part_info.size, s_bcb);
+	printf("BootAndriod bcb info :clear_bcb write=%d, %ld,%ld,%ld\n", ret, part_info.start, part_info.size, part_info.blksz);
+}
+
+static int do_andriod_bcb_business(int *boot_recovery)
+{
+	AvbIOResult ret = AVB_IO_RESULT_OK;
+	size_t bytes_read = 0;
+	int res = CMD_RET_FAILURE;
+
+#ifdef CONFIG_ANDROID_AB
+	char *slot_suffix = "_a";
+#else
+	char *slot_suffix = "";
+#endif
+
+    if (avb_ops != NULL) {
+        avb_ops_free(avb_ops);
+        avb_ops = NULL;
+    }
+
+    avb_ops = avb_ops_alloc(BOOTDEV_DEFAULT);
+    if (avb_ops == NULL) {
+        goto _bcb_err;
+    }
+
+    if (s_bcb != NULL) {
+        avb_free(s_bcb);
+        s_bcb = NULL;
+    }
+
+	s_bcb = avb_malloc(sizeof(struct bootloader_message_ab));
+	if (s_bcb == NULL) {
+		goto _bcb_err;
+	}
+
+    if (boot_ctl != NULL) {
+        avb_free(boot_ctl);
+        boot_ctl = NULL;
+    }
+
+    boot_ctl = malloc(sizeof(struct bootloader_control));
+	if (boot_ctl == NULL)
+	{
+        ret = -2;
+		goto _bcb_err;
+	}
+
+	ret = avb_ops->read_from_partition(avb_ops,
+										MISC_PARTITION,
+										0,
+										sizeof(struct bootloader_message_ab),
+										s_bcb,
+										&bytes_read);
+	if (ret != AVB_IO_RESULT_OK) {
+		printf("BootAndriod Err: Bcb read failed\n");
+		goto _bcb_err;
+	}
+
+	/* Enter into fastboot mode if bcb string is bootonce or bootrecovery */
+	if (0 == strncmp(s_bcb->message.command, "bootonce-bootloader", strlen("bootonce-bootloader")))
+		{
+		printf("BootAndriod Info: Bcb read %ld bytes, %s\n", bytes_read, s_bcb->message.command);
+		printf("BootAndriod Info: Enter fastboot mode\n");
+		clear_bcb();
+		run_command("fastboot usb 0", 0);
+	}
+	else if (0 == strncmp(s_bcb->message.command, "boot-recovery", strlen("boot-recovery")))
+	{
+		printf("recovery slot_suffix = %s\n", slot_suffix);
+		*boot_recovery = 1;
+	}
+
+    memset(boot_ctl, 0, sizeof(struct bootloader_control));
+    memcpy(boot_ctl, (struct bootloader_control*)s_bcb->slot_suffix, sizeof(struct bootloader_control));
+
+	res = CMD_RET_SUCCESS;
+
+_bcb_err:
+	if (res != CMD_RET_SUCCESS) {
+        if (avb_ops != NULL) {
+            avb_ops_free(avb_ops);
+            avb_ops = NULL;
+        }
+
+		if (boot_ctl != NULL) {
+            avb_free(boot_ctl);
+            boot_ctl = NULL;
+        }
+
+        if (s_bcb != NULL) {
+            avb_free(s_bcb);
+            s_bcb = NULL;
+        }
+    }
+
+	return res;
+}
+
+static int do_bootandroid(struct cmd_tbl_s *cmdtp, int flag, int argc,
+						char * const argv[]) {
+	
+	const char * const requested_partitions[] = {"vbmeta", "boot", "vbmeta_system", NULL};
+	AvbSlotVerifyResult slot_result = AVB_SLOT_VERIFY_RESULT_OK;
+	AvbSlotVerifyData *slot_data = NULL;
+	AvbIOResult ret = AVB_IO_RESULT_OK;
+	AvbSlotVerifyFlags slotflags = AVB_SLOT_VERIFY_FLAGS_NONE;
+	AvbHashtreeErrorMode htflags = AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE;
+	int res = CMD_RET_FAILURE;
+    char bp_name[32] = {0};
+	int boot_recovery = 0;
+
+    res = do_andriod_bcb_business(&boot_recovery);
+    if (res != CMD_RET_SUCCESS) {
+        goto exit;
+    }
+
+	/* Retieve boot partition 's name suffix */
+	slot_name_suffix = get_boot_partition_name_suffix();
+
+	/* Start with slot verification in secure boot */
+	if (get_system_boot_type()) {
+		/* Verify boot partition requested in vbmeta.img */
+		slot_result = avb_slot_verify(avb_ops,
+									  requested_partitions,
+									  slot_name_suffix,
+									  slotflags,
+									  htflags,
+									&slot_data);
+
+		if (slot_result == AVB_SLOT_VERIFY_RESULT_OK) {
+			printf("BootAndriod Info: Request Partition are verified successfully\n");
+			printf("BootAndriod cmdline: slot_data.cmdline:%s\n", slot_data->cmdline);
+			prepare_boot_data(slot_data, boot_recovery ? true:false);
+			if (ret == 0) {
+				if (slot_data != NULL)
+					avb_slot_verify_data_free(slot_data);
+			}
+		} else {
+			/* In case of avb slot verification failure, Force system reset */
+			run_command("reset", 0);
+		}
+	} else {
+	/* Go to load BOOT partition directly in non-secure boot */
+        get_partition_name(BOOT_PARTITION, bp_name);
+		prepare_partition_data(bp_name, boot_recovery ? true:false);
+	}
+
+exit:
+	return res;
+}
+
+const char * get_slot_name_suffix(void)
+{
+	return slot_name_suffix;
+}
+
+U_BOOT_CMD(
+	bootandroid, 2,	1, do_bootandroid,
+	"bootandroid   - boot android bootimg from device\n",
+	"mmc0 | mmc1 | mmc2 | mmcX]\n    "
+	"- boot application image stored in storage device like mmc\n"
+);
+

cmd/booti.c

@@ -67,7 +67,6 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc,
 int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int ret;
-
 	/* Consume 'booti' */
 	argc--; argv++;
 
@@ -119,20 +118,22 @@ U_BOOT_CMD(
 
 #endif
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 extern int light_secboot(int argc, char * const argv[]);
+#endif
 int do_secboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
     if (light_secboot(argc, argv) != 0) {
-        run_command("reset", 0);
         return -1;
     }
-
+#endif
 	return 0;
 }
 U_BOOT_CMD(
-	secboot, CONFIG_SYS_MAXARGS, 1, do_secboot, 
-	"verify image file with known pubkey which reside in father image or itself!", 
+	secboot, CONFIG_SYS_MAXARGS, 1, do_secboot,
+	"verify image file with known pubkey which reside in father image or itself!",
 	"vimage addr imgname[[tee/tf]	- verify specifed image resides in addr\n"
 );
 

cmd/mmc.c

@@ -574,6 +574,7 @@ static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag,
 }
 
 extern volatile uint32_t DELAY_LANE;
+extern volatile int manual_set_delay ;
 static int do_mmc_set_delay_lane(cmd_tbl_t *cmdtp, int flag,
 	       int argc, char * const argv[])
 {
@@ -587,17 +588,22 @@ static int do_mmc_set_delay_lane(cmd_tbl_t *cmdtp, int flag,
 	mmc = find_mmc_device(curr_device);
 	if (!mmc) {
 		printf("no mmc device at slot %x\n", curr_device);
-		return CMD_RET_FAILURE;
+		goto RET_FAILURE;
 	}
-
+	manual_set_delay = 1;
 	if (0 != snps_mmc_init(mmc))
-		return CMD_RET_FAILURE;
+		goto RET_FAILURE;
 
 	mmc = init_mmc_device(curr_device, true);
 	if (!mmc)
-		return CMD_RET_FAILURE;
-
+		goto RET_FAILURE;
+	
+	manual_set_delay = 0;
 	return CMD_RET_SUCCESS;
+
+RET_FAILURE:
+	manual_set_delay = 0;
+	return CMD_RET_FAILURE;
 }
 
 static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
@@ -605,6 +611,10 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
 {
 	struct mmc *mmc;
 	int i = 0, n;
+	int stop_on_ok = 1;
+	if(argc > 1 && (!strncmp(argv[1],"cont",4))){
+		stop_on_ok = 0;
+	}
 	for(i = 0; i <= 128; i++) {
 		DELAY_LANE = i;
 		printf("set DELAY_LANE = %d\n", DELAY_LANE);
@@ -616,8 +626,10 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
 			return CMD_RET_FAILURE;
 		}
 
+		manual_set_delay = 1;
 		if (0 != snps_mmc_init(mmc)) {
 			printf("Error: mmc init error!\n");
+			manual_set_delay = 0;
 			return CMD_RET_FAILURE;
 		}
 
@@ -628,18 +640,21 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
 
 		if (mmc_getwp(mmc) == 1) {
 			printf("Error: card is write protected!\n");
+			manual_set_delay = 0;
 			return CMD_RET_FAILURE;
 		}
 
 		n = blk_dwrite(mmc_get_blk_desc(mmc), 0, 1, 0);
 		if (n == 1) {
 			printf("blocks written: %s\n", "OK" );
-			return CMD_RET_SUCCESS;
+			manual_set_delay = 0;
+			if(stop_on_ok)
+				return CMD_RET_SUCCESS;
 		} else {
 			printf("written: %s\n", "error");
 		}
 	}
-
+	manual_set_delay = 0;
 	if (i > 128) {
 		return CMD_RET_FAILURE;
 	}
@@ -1239,9 +1254,10 @@ U_BOOT_CMD(
 #endif
 	"mmc erase blk# cnt\n"
 	"mmc rescan\n"
-	"mmc set_delay # val\n"
-	"mmc turning\n"
-	"mmc memset addr # lenght\n"
+	"mmc set_delay # val - set clk out delay mannaul,reinit host and rescan dev\n"
+	"mmc turning [continue] - loop test for clk delay form 0 to 128, reinit host and rescan dev\n"
+	"             - without arg [continue] exit once init and write ok\n"
+	"mmc memset addr # length - set mem addr 0xff with length  '# length' \n"
 	"mmc part - lists available partition on current mmc device\n"
 	"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
 	"mmc list - lists available devices\n"

cmd/net.c

@@ -458,3 +458,22 @@ U_BOOT_CMD(
 );
 
 #endif  /* CONFIG_CMD_LINK_LOCAL */
+
+/* moved from board_init_r sequence here to save normal boot time */
+static int do_eth_init(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+	puts("Net:   ");
+	eth_initialize();
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+	return 0;
+}
+
+U_BOOT_CMD(
+	eth,	6,	1,	do_eth_init,
+	"eth initialize",
+	""
+);

common/Kconfig

@@ -962,6 +962,20 @@ config TPL_HASH
 	  and the algorithms it supports are defined in common/hash.c. See
 	  also CMD_HASH for command-line access.
 
+config BOARD_RNG_SEED
+        bool "Provide /chosen/rng-seed property to the linux kernel"
+        help
+          Selecting this option requires the board to define a
+          board_rng_seed() function, which should return a buffer
+          which will be used to populate the /chosen/rng-seed property
+          in the device tree for the OS being booted.
+
+          It is up to the board code (and more generally the whole
+          BSP) where and how to store (or generate) such a seed, how
+          to ensure a given seed is only used once, how to create a
+          new seed for use on subsequent boots, and whether or not the
+          kernel should account any entropy from the given seed.
+
 endmenu
 
 menu "Update support"

common/avb_verify.c

@@ -14,6 +14,48 @@
 #include <tee.h>
 #include <tee/optee_ta_avb.h>
 
+#ifdef CONFIG_AVB_ROLLBACK_ENABLE
+extern int sec_write_rollback_index(size_t rollback_index_slot, uint64_t rollback_index);
+extern int sec_read_rollback_index(size_t rollback_index_slot, uint64_t *out_rollback_index);
+#endif
+
+#if defined (CONFIG_AVB_USE_OEM_KEY)
+static const unsigned char avb_root_oem_pub[520] = {
+	0x00,0x00,0x08,0x00,0x11,0x70,0xEA,0xC9,0xC2,0xAD,0x66,0x2A,0x57,0x2A,0x89,0x68,
+	0x8B,0x40,0x33,0xF2,0xEA,0x22,0xD7,0x3E,0x31,0x5F,0x9D,0xB8,0xD1,0x16,0x5C,0x22,
+	0xC3,0xFE,0xE6,0x35,0x3F,0x96,0x6D,0xD8,0x1A,0x11,0xE9,0x53,0x90,0x88,0xA9,0xCE,
+	0xA7,0x33,0xB2,0x16,0x60,0x18,0xBE,0x23,0xCC,0x5C,0xAB,0x29,0x0E,0x7B,0x35,0x16,
+	0xB0,0x59,0x3A,0x2F,0x62,0xF1,0x9B,0x39,0x0A,0x21,0x00,0xFE,0x75,0xEB,0x00,0xDF,
+	0x17,0xAF,0x44,0x11,0x42,0x4E,0x4C,0x7C,0xA6,0xDC,0xC5,0xAD,0xB3,0x7C,0xC3,0xB1,
+	0x52,0xAD,0x0C,0xEF,0x73,0x69,0x7E,0xFC,0xF9,0x12,0xA7,0x5C,0x60,0x47,0xEF,0x8F,
+	0xC7,0x9D,0xD9,0x62,0xF5,0x0E,0x62,0xBB,0x3E,0x80,0x23,0xFA,0x19,0x4C,0x0A,0xD6,
+	0xE0,0xA7,0x0E,0x65,0xEA,0xD5,0xB8,0xA9,0xF2,0xA3,0xDA,0x18,0xBE,0x5D,0x4B,0x37,
+	0x91,0xBA,0xDB,0x0D,0x50,0x7E,0xEE,0x52,0xDF,0x90,0xE6,0xFC,0x8F,0xB8,0x24,0x2A,
+	0x2B,0xBE,0xA6,0xC9,0x5B,0x89,0x3E,0xE8,0x24,0xBD,0x6A,0x03,0x31,0x6C,0xFC,0x4A,
+	0xBA,0x6B,0xEE,0x08,0xAE,0x33,0x6E,0xC0,0x64,0x87,0xC1,0x35,0x65,0x42,0x34,0xE5,
+	0xF8,0x3B,0x82,0x36,0xE9,0xFA,0x23,0xD7,0x12,0xC5,0x7B,0x27,0x16,0xB0,0xC7,0x40,
+	0x5A,0xA4,0x8A,0x56,0xA4,0x54,0x0F,0xD9,0xA7,0x25,0x25,0xE3,0x7F,0x72,0x6E,0x4B,
+	0x63,0x1B,0x05,0xFE,0x4E,0x1F,0x1D,0x05,0xDD,0x91,0xA7,0xBF,0xA4,0x90,0xDA,0x7D,
+	0x0F,0xB6,0xFC,0x5D,0x8E,0xFB,0xE2,0xF7,0x5F,0x76,0xFA,0xD5,0x12,0xEC,0x87,0xD6,
+	0x07,0xA0,0xAC,0xB6,0xE6,0xBA,0xB0,0x87,0xBA,0x51,0xD7,0x6C,0x19,0xC0,0x2C,0xA5,
+	0x2C,0x08,0x52,0x2A,0x63,0x18,0x10,0x94,0xEA,0x5C,0x13,0xBF,0x42,0x8E,0x12,0xB6,
+	0x7D,0x34,0xD9,0x1C,0x42,0xBC,0xCE,0x44,0x8A,0x13,0x5B,0x93,0x6F,0x34,0x41,0xA1,
+	0xA3,0xD3,0x2E,0xF4,0xD3,0x28,0xAD,0x8F,0x8B,0x89,0x9D,0x42,0x43,0xD6,0xBF,0xDE,
+	0x9F,0xBD,0x32,0x06,0xE3,0x67,0xD3,0x14,0x2F,0x4C,0xE7,0x6B,0x9A,0xD9,0x04,0xFA,
+	0x4B,0x46,0x88,0xE7,0x04,0xAA,0x56,0xFF,0xBF,0x89,0x1D,0xFD,0x32,0xDF,0x47,0xC0,
+	0x34,0x0D,0x25,0x8C,0xF6,0xE1,0x5E,0xA9,0x3C,0x30,0x3A,0x53,0x0C,0xDB,0xAD,0x8E,
+	0x01,0xCB,0x46,0xE0,0xF5,0x97,0x2D,0xB8,0xF8,0x29,0xC3,0x19,0x4C,0x05,0x8B,0x74,
+	0xE0,0xA6,0x3B,0x3C,0x96,0x4F,0x91,0x74,0x62,0xAA,0x50,0x0F,0x11,0x30,0x59,0xAE,
+	0x7A,0x80,0xD3,0xAC,0xB3,0xDB,0x24,0x3A,0x79,0xD4,0xDB,0x79,0x10,0x63,0x27,0xD0,
+	0x6B,0xF9,0xA3,0xF4,0x27,0x24,0x89,0x0C,0xAC,0x31,0x15,0x08,0x10,0x59,0x08,0x2D,
+	0x00,0x3D,0xD8,0xD6,0x3B,0x91,0xC8,0x55,0xCF,0x28,0x3A,0xFB,0xD7,0xF7,0xF7,0x9D,
+	0x41,0xBD,0x3E,0xD1,0x77,0xA3,0xF6,0xFA,0x33,0x05,0x5A,0x36,0xCE,0xB9,0x02,0x12,
+	0x10,0xEB,0xCA,0xA7,0x3C,0xC8,0x5D,0xCD,0x33,0xD9,0xFA,0x16,0xD4,0x52,0x12,0xB6,
+	0x35,0xD5,0x84,0x53,0xC4,0x21,0xDC,0x72,0x2F,0xF9,0x1E,0x59,0x0A,0xCD,0x7D,0x89,
+	0xD4,0xCF,0x8E,0x2E,0x09,0x36,0xF5,0x12,0x35,0x43,0x64,0x6C,0xD1,0x70,0xBF,0x67,
+	0x3A,0x54,0x72,0x84,0xF3,0xF1,0x4A,0x6A
+};
+#else
 static const unsigned char avb_root_pub[1032] = {
 	0x0, 0x0, 0x10, 0x0, 0x55, 0xd9, 0x4, 0xad, 0xd8, 0x4,
 	0xaf, 0xe3, 0xd3, 0x84, 0x6c, 0x7e, 0xd, 0x89, 0x3d, 0xc2,
@@ -120,7 +162,7 @@ static const unsigned char avb_root_pub[1032] = {
 	0xe1, 0x74, 0xa1, 0xa3, 0x99, 0xa0, 0x85, 0x9e, 0xf1, 0xac,
 	0xd8, 0x7e,
 };
-
+#endif
 /**
  * ============================================================================
  * Boot states support (GREEN, YELLOW, ORANGE, RED) and dm_verity
@@ -590,6 +632,19 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
 					      public_key_metadata_length,
 					      bool *out_key_is_trusted)
 {
+#if defined (CONFIG_AVB_USE_OEM_KEY)
+	if (!public_key_length || !public_key_data || !out_key_is_trusted)
+		return AVB_IO_RESULT_ERROR_IO;
+
+	*out_key_is_trusted = false;
+	if (public_key_length != sizeof(avb_root_oem_pub))
+		return AVB_IO_RESULT_ERROR_IO;
+
+	if (memcmp(avb_root_oem_pub, public_key_data, public_key_length) == 0)
+		*out_key_is_trusted = true;
+	
+	return AVB_IO_RESULT_OK;
+#else
 	if (!public_key_length || !public_key_data || !out_key_is_trusted)
 		return AVB_IO_RESULT_ERROR_IO;
 
@@ -601,6 +656,7 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
 		*out_key_is_trusted = true;
 
 	return AVB_IO_RESULT_OK;
+#endif
 }
 
 #ifdef CONFIG_OPTEE_TA_AVB
@@ -681,8 +737,15 @@ static AvbIOResult read_rollback_index(AvbOps *ops,
 				       size_t rollback_index_slot,
 				       u64 *out_rollback_index)
 {
+#ifdef CONFIG_AVB_ROLLBACK_ENABLE
+    if (sec_read_rollback_index(rollback_index_slot, out_rollback_index) != 0) {
+        return AVB_IO_RESULT_ERROR_IO;
+    }
+
+	return AVB_IO_RESULT_OK;
+#else
 #ifndef CONFIG_OPTEE_TA_AVB
-	/* For now we always return 0 as the stored rollback index. */
+    /* For now we always return 0 as the stored rollback index. */
 	printf("%s not supported yet\n", __func__);
 
 	if (out_rollback_index)
@@ -708,8 +771,10 @@ static AvbIOResult read_rollback_index(AvbOps *ops,
 
 	*out_rollback_index = (u64)param[1].u.value.a << 32 |
 			      (u32)param[1].u.value.b;
+
 	return AVB_IO_RESULT_OK;
 #endif
+#endif
 }
 
 /**
@@ -727,6 +792,13 @@ static AvbIOResult write_rollback_index(AvbOps *ops,
 					size_t rollback_index_slot,
 					u64 rollback_index)
 {
+#ifdef CONFIG_AVB_ROLLBACK_ENABLE
+    if (sec_write_rollback_index(rollback_index_slot, rollback_index) != 0) {
+        return AVB_IO_RESULT_ERROR_IO;
+    }
+    
+	return AVB_IO_RESULT_OK;
+#else
 #ifndef CONFIG_OPTEE_TA_AVB
 	/* For now this is a no-op. */
 	printf("%s not supported yet\n", __func__);
@@ -748,6 +820,7 @@ static AvbIOResult write_rollback_index(AvbOps *ops,
 	return invoke_func(ops->user_data, TA_AVB_CMD_WRITE_ROLLBACK_INDEX,
 			   ARRAY_SIZE(param), param);
 #endif
+#endif
 }
 
 /**

common/fdt_support.c

@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <abuf.h>
 #include <env.h>
 #include <mapmem.h>
 #include <stdio_dev.h>
@@ -274,6 +275,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end)
 
 int fdt_chosen(void *fdt)
 {
+        struct abuf buf = {};
 	int   nodeoffset;
 	int   err;
 	char  *str;		/* used to set string properties */
@@ -289,6 +291,17 @@ int fdt_chosen(void *fdt)
 	if (nodeoffset < 0)
 		return nodeoffset;
 
+        if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) {
+                err = fdt_setprop(fdt, nodeoffset, "rng-seed",
+                                  abuf_data(&buf), abuf_size(&buf));
+                abuf_uninit(&buf);
+                if (err < 0) {
+                        printf("WARNING: could not set rng-seed %s.\n",
+                               fdt_strerror(err));
+                        return err;
+                }
+        }
+
 	str = env_get("bootargs");
 	if (str) {
 		err = fdt_setprop(fdt, nodeoffset, "bootargs", str,

common/image-fdt.c

@@ -416,7 +416,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 				 * FDT blob
 				 */
 				debug("*  fdt: raw FDT blob\n");
-				printf("## Flattened Device Tree blob at %08lx\n",
+				debug("## Flattened Device Tree blob at %08lx\n",
 				       (long)fdt_addr);
 			}
 			break;
@@ -425,7 +425,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 			goto no_fdt;
 		}
 
-		printf("   Booting using the fdt blob at %#08lx\n", fdt_addr);
+		debug("   Booting using the fdt blob at %#08lx\n", fdt_addr);
 		fdt_blob = map_sysmem(fdt_addr, 0);
 	} else if (images->legacy_hdr_valid &&
 			image_check_type(&images->legacy_hdr_os_copy,

common/splash.c

@@ -71,7 +71,7 @@ static int splash_video_logo_load(void)
 		return -EFAULT;
 	}
 
-	memcpy((void *)bmp_load_addr, bmp_logo_bitmap,
+	memcpy((void *)(u64)bmp_load_addr, bmp_logo_bitmap,
 	       ARRAY_SIZE(bmp_logo_bitmap));
 
 	return 0;

configs/light_a_val_android_defconfig

@@ -0,0 +1,118 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
+# CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_a_val_defconfig

@@ -21,17 +21,18 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MTD=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -76,6 +77,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -83,7 +87,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
-# CONFIG_LIGHT_SEC_BOOT is not set
+# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -103,3 +107,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_a_val_sec_defconfig

@@ -18,6 +18,13 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
+# CONFIG_TPM is not set
+# CONFIG_TPM_Z32H330TC_SPI is not set
+# CONFIG_TPM_V2 is not set
+# CONFIG_CMD_TPM_V2 is not set
+# CONFIG_CMD_TPM is not set
+# CONFIG_CMD_TPM_TEST is not set
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -28,7 +35,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -73,6 +79,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -82,6 +91,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
 # CONFIG_EFI_LOADER is not set
 CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
 CONFIG_LIGHT_SEC_UPGRADE=y
+# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -89,6 +99,7 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
@@ -101,3 +112,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_ant_ref_android_defconfig

@@ -0,0 +1,120 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_UPGRADE is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_ant_ref_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -82,7 +83,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
-# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF=y
+CONFIG_LIGHT_SEC_UPGRADE=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y

configs/light_ant_ref_sec_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_b_product_android_defconfig

@@ -0,0 +1,122 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_B=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_TIME=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-b-product"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
+# CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_b_product_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -104,3 +105,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_b_product_sec_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -104,3 +105,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_beagle_android_defconfig

@@ -0,0 +1,118 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_SPL_TEXT_BASE=0xffe0000800

configs/light_lpi4a_android_defconfig

@@ -0,0 +1,118 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_defconfig

@@ -0,0 +1,115 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
+CONFIG_VIDEO_LCD_JD9365DA=y
+CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y
+

configs/light_lpi4a_sec_defconfig

@@ -0,0 +1,115 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A=y
+CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
+CONFIG_VIDEO_LCD_JD9365DA=y
+CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_singlerank_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

drivers/fastboot/Kconfig

@@ -2,7 +2,7 @@ menu "Fastboot support"
 
 config FASTBOOT
 	bool
-	imply ANDROID_BOOT_IMAGE
+	# imply ANDROID_BOOT_IMAGE
 	imply CMD_FASTBOOT
 
 config USB_FUNCTION_FASTBOOT

drivers/fastboot/fb_command.c

@@ -14,6 +14,7 @@
 #include <stdlib.h>
 
 #define BLOCK_SIZE 512
+#define BOARD_ID_OFFSET 0x26
 
 /**
  * image_size - final fastboot image size
@@ -42,6 +43,7 @@ static void reboot_bootloader(char *, char *);
 static void oem_format(char *, char *);
 #endif
 static void oem_command(char *, char *);
+int image_have_head(unsigned long img_src_addr);
 
 static const struct {
 	const char *command;
@@ -263,6 +265,35 @@ void fastboot_data_complete(char *response)
 	fastboot_bytes_received = 0;
 }
 
+/**
+ * check_image_board_id() - check if board id in image matched with board id in env
+ *
+ * @image_data: Image data
+ *
+ * 0 if success otherwise failed
+ */
+int check_image_board_id(uint8_t *image_data)
+{
+	char *env_board_id = NULL;
+	char board_id[3] = {0};
+	env_board_id = env_get("board#");
+	/*if current board id is null or image has no header,skip check*/
+	if (env_board_id == NULL || env_board_id[0] == 0 || image_have_head((unsigned long)image_data) == 0) {
+		return 0;
+	}
+	memcpy(board_id, image_data + BOARD_ID_OFFSET,sizeof(uint16_t));
+	/*if image board id is null,skip check*/
+	if (*(uint16_t*)board_id == 0) {
+		return 0;
+	}
+	/*check if current board id match with board id in image*/
+	if (strncmp(env_board_id, board_id, sizeof(board_id)) != 0) {
+		printf("U-BOOT image download via fastboot is interrupted due to the U-BOOT for board %s does not work in the board %s\r\n",board_id,env_board_id);
+		return -1;
+	}
+	return 0;
+}
+
 #if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
 /**
  * flash() - write the downloaded image to the indicated partition.
@@ -279,8 +310,16 @@ static void flash(char *cmd_parameter, char *response)
 	char cmdbuf[32];
 	u32 block_cnt;
 	struct blk_desc *dev_desc;
+	disk_partition_t info;
+	int ret = 0;
 
 	if (strcmp(cmd_parameter, "uboot") == 0) {
+		ret = check_image_board_id(fastboot_buf_addr);
+		if (ret != 0) {
+			fastboot_fail("U-BOOT image does not match the type of BOARD", response);
+			return;
+		}
+
 		dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
 		if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
 			fastboot_fail("invalid mmc device", response);
@@ -313,8 +352,25 @@ static void flash(char *cmd_parameter, char *response)
 		memcpy((void *)LIGHT_TF_FW_ADDR, fastboot_buf_addr, image_size);
 	} else if ((strcmp(cmd_parameter, TEE_PART_NAME) == 0)) {
 		memcpy((void *)LIGHT_TEE_FW_ADDR, fastboot_buf_addr, image_size);
-	} 
-
+	} else if ((strcmp(cmd_parameter, "boot") == 0)) {
+		dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+		if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+			fastboot_fail("invalid mmc device", response);
+			return;
+        }
+		/* if fastresume partition exists, earse the old image header */
+		if(part_get_info_by_name(dev_desc, "fastresume", &info)) {
+			printf(" find fastresume partition , erase the header:\n");
+			char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096);
+			if(!buf) {
+				printf(" fastresume partition header mem alloc failed\n");
+				return;
+			}
+			memset(buf,0xff,4096);
+			blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf);
+			free(buf);
+		}
+	}
 	if(strcmp(cmd_parameter, "uboot") == 0 || (strcmp(cmd_parameter, "fw") == 0) ||
 	   (strcmp(cmd_parameter, "uImage") == 0) || (strcmp(cmd_parameter, "dtb") == 0) ||
 	   (strcmp(cmd_parameter, "rootfs") == 0) || (strcmp(cmd_parameter, "aon") == 0)) {
@@ -332,7 +388,7 @@ static void flash(char *cmd_parameter, char *response)
 		#endif
 		/* Send ACK to host */
 		fastboot_okay(NULL, response);
-		
+
 		/* set secure upgrade flag to indicate it is TF image upgrade*/
 		sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", TF_SEC_UPGRADE_FLAG);
 		run_command(cmdbuf, 0);
@@ -348,13 +404,29 @@ static void flash(char *cmd_parameter, char *response)
 
 		/* Send ACK to host */
 		fastboot_okay(NULL, response);
-		
+
 		/* set secure upgrade flag to indicate it is TEE image upgrade*/
 		sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", TEE_SEC_UPGRADE_FLAG);
 		run_command(cmdbuf, 0);
 		run_command("saveenv", 0);
 		run_command("reset", 0);
 		return;
+	} else if (strcmp(cmd_parameter, SBMETA_IMG_UPD_NAME) == 0) {
+		#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
+		/* tee/tf/uboot image must be written into stash partition */
+		sprintf(cmdbuf, "%s", STASH_PART_NAME);
+		fastboot_mmc_flash_write(cmdbuf, fastboot_buf_addr, image_size, response);
+		#endif
+
+		/* Send ACK to host */
+		fastboot_okay(NULL, response);
+
+		/* set secure upgrade flag to indicate it is TEE image upgrade*/
+		sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", SBMETA_SEC_UPGRADE_FLAG);
+		run_command(cmdbuf, 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+		return;
 	} else if (strcmp(cmd_parameter, UBOOT_IMG_UPD_NAME) == 0) {
 		#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
 
@@ -366,14 +438,14 @@ static void flash(char *cmd_parameter, char *response)
 
 		/* Send ACK to host */
 		fastboot_okay(NULL, response);
-		
+
 		/* set secure upgrade flag to indicate it is UBOOT image upgrade*/
 		sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", UBOOT_SEC_UPGRADE_FLAG);
 		run_command(cmdbuf, 0);
 		run_command("saveenv", 0);
 		run_command("reset", 0);
 		return;
-	} 
+	}
 #endif
 
 #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)

drivers/fastboot/fb_common.c

@@ -118,7 +118,11 @@ void fastboot_boot(void)
 #ifdef THEAD_LIGHT_FASTBOOT
 	char cmdbuf[32];
 
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+	sprintf(cmdbuf, "run bootcmd");
+#else
 	sprintf(cmdbuf, "bootslave; run set_bootargs; booti %s - %s", LIGHT_KERNEL_ADDR_CMD, LIGHT_DTB_ADDR_CMD);
+#endif
 	printf("fastboot bootcmd %s\n", cmdbuf);
 	run_command(cmdbuf, 0);
 

drivers/fastboot/fb_getvar.c

@@ -13,6 +13,7 @@
 #include <version.h>
 
 static void getvar_version(char *var_parameter, char *response);
+static void getvar_dynamic_partition(char *var_parameter, char *response);
 static void getvar_version_bootloader(char *var_parameter, char *response);
 static void getvar_downloadsize(char *var_parameter, char *response);
 static void getvar_serialno(char *var_parameter, char *response);
@@ -41,6 +42,9 @@ static const struct {
 	}, {
 		.variable = "version-bootloader",
 		.dispatch = getvar_version_bootloader
+	}, {
+		.variable = "dynamic-partition",
+		.dispatch = getvar_dynamic_partition
 	}, {
 		.variable = "downloadsize",
 		.dispatch = getvar_downloadsize
@@ -134,6 +138,17 @@ static void getvar_version_bootloader(char *var_parameter, char *response)
 	fastboot_okay(U_BOOT_VERSION, response);
 }
 
+static void getvar_dynamic_partition(char *var_parameter, char *response)
+{
+	char *part_name="super";
+
+	int r = getvar_get_part_info(part_name, response, NULL);
+	if (r >= 0)
+		fastboot_okay("true", response); /* part exists */
+	else
+		fastboot_okay("false", response);
+}
+
 static void getvar_downloadsize(char *var_parameter, char *response)
 {
 	fastboot_response("OKAY", response, "0x%08x", fastboot_buf_size);
@@ -247,7 +262,11 @@ static void getvar_partition_size(char *part_name, char *response)
 
 static void getvar_is_userspace(char *var_parameter, char *response)
 {
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+	fastboot_okay("yes", response);
+#else
 	fastboot_okay("no", response);
+#endif
 }
 
 /**

drivers/misc/Kconfig

@@ -439,4 +439,10 @@ config K3_AVS0
 	  optimized voltage from the efuse, so that it can be programmed
 	  to the PMIC on board.
 
+config LIGHT_AON_CONF
+	bool "Light aon config support"
+	depends on MISC
+	help
+	  Select this to enable aon config by dts.
+
 endmenu

drivers/misc/Makefile

@@ -68,3 +68,4 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
 obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
 obj-$(CONFIG_K3_AVS0) += k3_avs.o
+obj-$(CONFIG_LIGHT_AON_CONF) += light_regu.o

drivers/misc/light_regu.c

@@ -0,0 +1,975 @@
+#include <common.h>
+#include <asm/gpio.h>
+#include <misc.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <command.h>
+#include "light_regu.h"
+
+#define FDT32_TO_CPU(x) (fdt32_to_cpu(x))
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (szieof(x) / sizeof(x[0]))
+#endif
+
+#ifndef MIN
+#define MIN(x, y) ((x) < (y) ? (x) : (y))
+#endif
+
+#ifdef AON_CONF_DEBUG
+#define AON_CONF_D(fmt, args...)  printf(fmt,##args)
+#else
+#define AON_CONF_D(fmt, args...)
+#endif
+
+#define SOC_VIRTUAL_ID(virtual_id)      \
+	{                                   \
+		.id = virtual_id,               \
+		.virtual_id_name = #virtual_id, \
+	}
+
+soc_virtual_id_t soc_base_virtual_id_list[] = {
+	SOC_VIRTUAL_ID(SOC_DVDD18_AON),		  /*da9063:  ldo-3 */
+	SOC_VIRTUAL_ID(SOC_AVDD33_USB3),	  /*da9063:  ldo-9 */
+	SOC_VIRTUAL_ID(SOC_DVDD08_AON),		  /*da9063:  ldo-2 */
+	SOC_VIRTUAL_ID(SOC_APCPU_DVDD_DVDDM), /*da9063:  vbcore1 & vbcore2*/
+	SOC_VIRTUAL_ID(SOC_DVDD08_DDR),		  /*da9063:  buckperi */
+	SOC_VIRTUAL_ID(SOC_VDD_DDR_1V8),	  /*da9063:  ldo-4  */
+	SOC_VIRTUAL_ID(SOC_VDD_DDR_1V1),	  /*da9063:  buckmem & buckio  */
+	SOC_VIRTUAL_ID(SOC_VDD_DDR_0V6),	  /*da9063:  buckpro */
+	SOC_VIRTUAL_ID(SOC_DVDD18_AP),		  /*da9063:  ldo-11 */
+	SOC_VIRTUAL_ID(SOC_DVDD08_AP),		  /*da9121:  da9121_ex */
+	SOC_VIRTUAL_ID(SOC_AVDD08_MIPI_HDMI), /*da9063:  ldo-1  */
+	SOC_VIRTUAL_ID(SOC_AVDD18_MIPI_HDMI), /*da9063:  ldo-5  */
+	SOC_VIRTUAL_ID(SOC_DVDD33_EMMC),	  /*da9063:  ldo-10 */
+	SOC_VIRTUAL_ID(SOC_DVDD18_EMMC),	  /*slg51000:ldo-3 */
+	SOC_VIRTUAL_ID(SOC_DOVDD18_SCAN),	  /*da9063:  ldo-6 */
+	SOC_VIRTUAL_ID(SOC_VEXT_2V8),		  /*da9063:  ldo-7 */
+	SOC_VIRTUAL_ID(SOC_DVDD12_SCAN),	  /*da9063:  ldo-8 */
+	SOC_VIRTUAL_ID(SOC_AVDD28_SCAN_EN),	  /*da9063:  gpio-4),SGM2019-ADJ */
+	SOC_VIRTUAL_ID(SOC_AVDD28_RGB),		  /*slg51000:ldo-1 */
+	SOC_VIRTUAL_ID(SOC_DOVDD18_RGB),	  /*slg51000:ldo-4 */
+	SOC_VIRTUAL_ID(SOC_DVDD12_RGB),		  /*slg51000:ldo-5 */
+	SOC_VIRTUAL_ID(SOC_AVDD25_IR),		  /*slg51000:ldo-2 */
+	SOC_VIRTUAL_ID(SOC_DOVDD18_IR),		  /*slg51000:ldo-7 */
+	SOC_VIRTUAL_ID(SOC_DVDD12_IR),		  /*slg51000:ldo-6 */
+	SOC_VIRTUAL_ID(SOC_ADC_VREF),
+	SOC_VIRTUAL_ID(SOC_LCD0_EN),
+	SOC_VIRTUAL_ID(SOC_VEXT_1V8),
+};
+
+static int misc_regu_probe(struct udevice *dev)
+{
+	return 0;
+}
+
+static int misc_regu_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+static soc_virtual_id_t *found_base_virtual_id(char *name)
+{
+	for (int i = 0; i < ARRAY_SIZE(soc_base_virtual_id_list); i++)
+	{
+		if (!strcasecmp(soc_base_virtual_id_list[i].virtual_id_name, name))
+		{
+			return &soc_base_virtual_id_list[i];
+		}
+	}
+	return NULL;
+}
+
+static inline char toupper(char str1)
+{
+	if (str1 >= 'a' && str1 <= 'z')
+	{
+		return str1 - 'a' + 'A';
+	}
+	return str1;
+}
+
+void string_to_upper(char *str)
+{
+	if (str == NULL)
+		return;
+
+	while (*str)
+	{
+		*str = toupper((unsigned char)*str);
+		str++;
+	}
+}
+
+static int misc_regu_get_virtual_regu_config(struct udevice *dev, ofnode parent_node, virtual_regu_list_t *regu_list)
+{
+	int regu_num = 0;
+	int ret;
+	ofnode child_node;
+	soc_virtual_id_t *id_list;
+	soc_virtual_id_t *soc_base_id;
+	ofnode_for_each_subnode(child_node, parent_node)
+	{
+		//printf("sub node name: %s\n", ofnode_get_name(child_node));
+		regu_num++;
+	}
+
+	if (!regu_num)
+	{
+		printf("regu list not found in dts\n");
+		return -1;
+	}
+
+	id_list = devm_kcalloc(dev, 1, regu_num * sizeof(soc_virtual_id_t), GFP_KERNEL);
+	if (!id_list)
+	{
+		printf("regu id malloc faild\n");
+		return -ENOMEM;
+	}
+
+	int index = 0;
+	int new_regu_index = ARRAY_SIZE(soc_base_virtual_id_list);
+
+	ofnode_for_each_subnode(child_node, parent_node)
+	{
+		const char *virtual_id_name = ofnode_get_name(child_node);
+		int min_uv;
+		int max_uv;
+		soc_base_id = found_base_virtual_id(virtual_id_name);
+		if (soc_base_id)
+		{
+			id_list[index].id = soc_base_id->id;
+		}
+		else
+		{
+			id_list[index].id = new_regu_index++;
+		}
+
+		int copy_size = MIN(sizeof(id_list[index].virtual_id_name) - 1, strlen(virtual_id_name));
+		memcpy(id_list[index].virtual_id_name, virtual_id_name, copy_size);
+		id_list[index].virtual_id_name[copy_size] = '\0';
+
+		string_to_upper(id_list[index].virtual_id_name);
+
+		ret = ofnode_read_u32(child_node, "regulator-min-microvolt", &min_uv);
+		if (ret)
+		{
+			// printf("%s :regulator-min-microvolt not set, min_uv set to -1", virtual_id_name);
+			id_list[index].min_uv = -1;
+		}
+		else
+		{
+			id_list[index].min_uv = min_uv;
+		}
+
+		ret = ofnode_read_u32(child_node, "regulator-max-microvolt", &max_uv);
+		if (ret)
+		{
+			// printf("%s :regulator-max-microvolt not set, max_uv set to -1", virtual_id_name);
+			id_list[index].max_uv = -1;
+		}
+		else
+		{
+			id_list[index].max_uv = max_uv;
+		}
+#warning "check double"
+		// printf("Get virtual regu_id:[%d]:%s min_uv:%dmv max_uv:%dmv\n", id_list[index].id, id_list[index].virtual_id_name,
+		// 	   id_list[index].min_uv, id_list[index].max_uv);
+		index++;
+	}
+
+	(*regu_list).regu_num = regu_num;
+	(*regu_list).regu_list = id_list;
+
+	return 0;
+}
+
+static int misc_grep_pmic_dev_name_info(char *dev_name, pmic_dev_info_t *dev)
+{
+	int flag_num = 0;
+	int version_flag = 0;
+	int index = 0;
+	char *dev_name_orig = dev_name;
+	while (*dev_name)
+	{
+		if (*dev_name == ',')
+		{
+			flag_num++;
+			if (flag_num == 2)
+			{
+				version_flag = index;
+			}
+		}
+		index++;
+		dev_name++;
+	}
+
+	if (flag_num != 2 || *(dev_name - 1) == ',')
+	{
+		printf("pmic-name should set as pmic-name = \"vendor,type,version");
+		return -1;
+	}
+
+	int len = MIN((version_flag), sizeof(dev->device_name) - 1);
+	memcpy(dev->device_name, dev_name_orig, len);
+	dev->device_name[len] = '\0';
+	len = MIN((index - version_flag - 1), sizeof(dev->device_name) - 1);
+	memcpy(dev->version_name, dev_name_orig + version_flag + 1, len);
+	dev->version_name[len] = '\0';
+	return 0;
+}
+
+static int get_node_index(const char *name)
+{
+	while (*name && *name != '@')
+	{
+		name++;
+	}
+
+	if (strlen(name) == 0)
+	{
+		return -1;
+	}
+	name++;
+	return strtoul(name, NULL, 10);
+}
+
+static int misc_regu_get_pmic_dev_config(ofnode parent_node, pmic_dev_info_t *pmic_dev_info_list)
+{
+	int ret = 0;
+	ofnode child_node, errio_node;
+	fdt_addr_t index;
+	char *pmic_name;
+	int pmic_wdt_flag = 0;
+	int pmic_index = 0;
+	int pmic_addr_len = 0, pmic_addr_size;
+	int gpio_addr_len = 0, gpio_addr_size;
+	char err_io_str[40] = "NOT_SUPPORT";
+	char lpm_io_str[40] = "NOT_SUPPORT";
+	uint32_t port, pin, trigger_mode;
+	uint32_t phandle;
+	const uint32_t *prop_val;
+
+	ofnode_for_each_subnode(child_node, parent_node)
+	{
+		pmic_dev_info_t *dev = &(pmic_dev_info_list[pmic_index]);
+		const char *node_name = ofnode_get_name(child_node);
+		if (!strncmp(node_name, PMIC_DEV_DTS_NAME, strlen(PMIC_DEV_DTS_NAME)))
+		{
+			index = get_node_index(node_name);
+			if (index < 0)
+			{
+				printf("get pmic_dev id faild");
+				return -1;
+			}
+			pmic_name = ofnode_read_string(child_node, "pmic-name");
+			if (!pmic_name)
+			{
+				printf("pmic_name property not set for %s%d", PMIC_DEV_DTS_NAME, index);
+				return -1;
+			}
+
+			if (ofnode_read_bool(child_node, "pmic_wdt_on"))
+			{
+				if (pmic_wdt_flag)
+				{
+					printf("only one pmic dev support wdt\n");
+					return -1;
+				}
+				dev->flag |= PMIC_DEV_ENABLE_WDT;
+				pmic_wdt_flag = 1;
+			}
+
+			prop_val = ofnode_get_property(child_node, "pmic-addr", &pmic_addr_len);
+			if (!prop_val)
+			{
+				printf("pmic-addr property not found\n");
+				return -1;
+			}
+			pmic_addr_size = pmic_addr_len / sizeof(uint32_t);
+
+			if (pmic_addr_size != 2 &&  pmic_addr_size!= 1)
+			{
+				printf("invalid pmic-addr cell size %d\n", pmic_addr_size);
+				return -1;
+			}
+
+			dev->addr1 = FDT32_TO_CPU(prop_val[0]);
+			dev->addr2 = pmic_addr_size == 2 ? FDT32_TO_CPU(prop_val[1]) : dev->addr1;
+
+			prop_val = ofnode_get_property(child_node, "errio_gpio", &gpio_addr_len);
+			if (prop_val)
+			{
+				gpio_addr_size = gpio_addr_len / sizeof(uint32_t);
+				if (gpio_addr_size != 3)
+				{
+					printf("invalid errio_gpio cell size %d\n", gpio_addr_size);
+					return -1;
+				}
+				else
+				{
+					port = FDT32_TO_CPU(prop_val[0]);
+					pin = 1 << FDT32_TO_CPU(prop_val[1]);
+					trigger_mode = FDT32_TO_CPU(prop_val[2]);
+					dev->flag |= PMIC_DEV_ENABLE_ERR_IO;
+					dev->err_io_info.gpio_port = port;
+					dev->err_io_info.pin = pin;
+					dev->err_io_info.trigger_mode = trigger_mode;
+					sprintf(err_io_str, "port:%d pin:%d trigger:%d", port, pin, trigger_mode);
+				}
+			} else {
+                    sprintf(err_io_str, "NOT_SUPPORT");
+			}
+
+			prop_val = ofnode_get_property(child_node, "lpm_gpio", &gpio_addr_len);
+			if (prop_val)
+			{
+				gpio_addr_size = gpio_addr_len / sizeof(uint32_t);
+				if (gpio_addr_size != 3)
+				{
+					printf("invalid lpm_gpio cell size %d\n", gpio_addr_size);
+					return -1;
+				}
+				else
+				{
+					port = FDT32_TO_CPU(prop_val[0]);
+					pin = 1 << FDT32_TO_CPU(prop_val[1]);
+					trigger_mode = FDT32_TO_CPU(prop_val[2]);
+					dev->flag |= PMIC_DEV_ENABLE_LPM_IO;
+					dev->lpm_io_info.gpio_port = port;
+					dev->lpm_io_info.pin = pin;
+					dev->lpm_io_info.trigger_mode = trigger_mode;
+					sprintf(lpm_io_str, "port:%d pin:%d trigger:%d", port, pin, trigger_mode);
+				}
+			} else {
+				sprintf(lpm_io_str,"NOT_SUPPORT");
+			}
+
+			dev->pmic_id = index;
+			ret = misc_grep_pmic_dev_name_info(pmic_name, dev);
+			pmic_index++;
+			AON_CONF_D("Get pmic dev:[%d]:%s|%s addr1:0x%02x addr2:0x%02x wdt:{%s} errio:{%s} lpm_io:{%s}\n", index, dev->device_name, dev->version_name, dev->addr1, dev->addr2, (dev->flag & PMIC_DEV_ENABLE_WDT ? "SUPPORT" : "NOT_SUPPORT"), err_io_str, lpm_io_str);
+		}
+	}
+	return 0;
+}
+
+static int misc_regu_get_pmic_dev_by_name(const char *name, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list)
+{
+	int pmic_id = get_node_index(name);
+	if (pmic_id < 0)
+	{
+		return -1;
+	}
+
+	int pmic_index = 0;
+	for (; pmic_index < pmic_dev_num; pmic_index++)
+	{
+		if (pmic_dev_info_list[pmic_index].pmic_id == pmic_id)
+		{
+			break;
+		}
+	}
+
+	if (pmic_index == pmic_dev_num)
+	{
+		printf("%s not found in pmic list\n", name);
+		return -1;
+	}
+
+	return pmic_index;
+}
+
+static int misc_regu_get_each_regu_hw_id_config(ofnode regu_id_node, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list, soc_virtual_id_t *virtual_id_info, pmic_hw_info_t *id)
+{
+	uint32_t phandle;
+	ofnode pmic_node, pmic_parent_node;
+
+	char *pmic_name;
+
+	int prop_len, prop_size;
+	int on_order, on_delay_ms;
+	int off_order, off_delay_ms;
+	int pmic_index, parent_pmic_index;
+	const uint32_t *prop_val;
+
+	/*get pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>*/
+	prop_val = ofnode_get_property(regu_id_node, "pmic_dev", &prop_len);
+	if (!prop_val)
+	{
+		printf("pmic-addr property not found\n");
+		return -1;
+	}
+
+	prop_size = prop_len / sizeof(uint32_t);
+	if (prop_size != 2)
+	{
+		printf("pmic_dev property should set in format as  pmic_dev = <&pmic_dev_num HW_ID>;\n");
+		return -1;
+	}
+
+	pmic_node = ofnode_get_by_phandle(FDT32_TO_CPU(prop_val[0]));
+	if (!ofnode_valid(pmic_node))
+	{
+		printf("pmic node not found\n");
+		return -1;
+	}
+
+	pmic_index = misc_regu_get_pmic_dev_by_name(ofnode_get_name(pmic_node), pmic_dev_num, pmic_dev_info_list);
+	if (pmic_index < 0)
+	{
+		return -1;
+	}
+
+	(*id).pmic_id = pmic_dev_info_list[pmic_index].pmic_id;
+	(*id).hw_id = FDT32_TO_CPU(prop_val[1]);
+
+	/*get auto_on_info = <0 1 800000>*/
+	prop_val = ofnode_get_property(regu_id_node, "auto_on_info", &prop_len);
+	if (!prop_val)
+	{
+		(*id).soft_power_ctrl_info.on_info.on_order = HW_ID_NO_SOFT_AUTO_ON;
+	}
+	else
+	{
+		prop_size = prop_len / sizeof(uint32_t);
+		if (prop_size != 3 && prop_size != 2)
+		{
+			printf("auto_on_info property should set in format as auto_on_info = <on_order on_delay_ms [on_uv_mv]>\n");
+			return -1;
+		}
+		if (virtual_id_info->min_uv != -1 && FDT32_TO_CPU(prop_val[2]) < virtual_id_info->min_uv)
+		{
+			printf("virtual regu %s voltage shoud larger than %dmv, it is %dmv\n", virtual_id_info->virtual_id_name, virtual_id_info->min_uv, FDT32_TO_CPU(prop_val[2]));
+			return -1;
+		}
+		if (virtual_id_info->max_uv != -1 && FDT32_TO_CPU(prop_val[2]) > virtual_id_info->max_uv)
+		{
+			printf("virtual regu %s voltage shoud less than %dmv, it is %dmv\n", virtual_id_info->virtual_id_name, virtual_id_info->max_uv, FDT32_TO_CPU(prop_val[2]));
+			return -1;
+		}
+		(*id).soft_power_ctrl_info.on_info.on_order = FDT32_TO_CPU(prop_val[0]);
+		(*id).soft_power_ctrl_info.on_info.on_delay_ms = FDT32_TO_CPU(prop_val[1]);
+		if(prop_size == 3) {
+            (*id).soft_power_ctrl_info.on_info.init_target_uv = FDT32_TO_CPU(prop_val[2]);
+		} else {
+			(*id).soft_power_ctrl_info.on_info.init_target_uv = 0;
+		}
+		
+	}
+
+	/*get auto_off_info = <1 1>*/
+	prop_val = ofnode_get_property(regu_id_node, "auto_off_info", &prop_len);
+	if (!prop_val)
+	{
+		(*id).soft_power_ctrl_info.off_info.off_order = HW_ID_NO_SOFT_AUTO_OFF;
+	}
+	else
+	{
+		prop_size = prop_len / sizeof(uint32_t);
+		if (prop_size != 2)
+		{
+			printf("auto_off_info property should set in format as auto_off_info = <off_order off_delay_ms>\n");
+			return -1;
+		}
+		(*id).soft_power_ctrl_info.off_info.off_order = FDT32_TO_CPU(prop_val[0]);
+		(*id).soft_power_ctrl_info.off_info.off_delay_ms = FDT32_TO_CPU(prop_val[1]);
+	}
+
+	/*get parent_pmic_dev = <&pmic_dev_0 2 1>*/
+	prop_val = ofnode_get_property(regu_id_node, "parent_pmic_dev", &prop_len);
+	if (!prop_val)
+	{
+		(*id).parent_hw_info.pmic_id = PMIC_ID_INVALID;
+	}
+	else
+	{
+		prop_size = prop_len / sizeof(uint32_t);
+		if (prop_size != 3)
+		{
+			printf("parent_pmic_dev property should set in format as  parent_pmic_dev = <&pmic_dev_num IO_ID ACTIVATE_STATUS>;\n");
+			return -1;
+		}
+
+		pmic_parent_node = ofnode_get_by_phandle(FDT32_TO_CPU(prop_val[0]));
+		if (!ofnode_valid(pmic_parent_node))
+		{
+			printf("pmic_parent node not found\n");
+			return -1;
+		}
+
+		pmic_index = misc_regu_get_pmic_dev_by_name(ofnode_get_name(pmic_parent_node), pmic_dev_num, pmic_dev_info_list);
+		if (pmic_index < 0)
+		{
+			return -1;
+		}
+
+		(*id).parent_hw_info.pmic_id = pmic_dev_info_list[pmic_index].pmic_id;
+		(*id).parent_hw_info.io_hw_id = FDT32_TO_CPU(prop_val[1]);
+#warning "check status"
+		(*id).parent_hw_info.activate_status = FDT32_TO_CPU(prop_val[2]);
+	}
+
+	return 0;
+}
+
+static int misc_regu_get_each_regu_config(ofnode regu_config_node, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list, soc_virtual_id_t *regu_info, csi_regu_id_t *pmic_regu_id_info)
+{
+	int ret = 0;
+	ofnode hw_id_node;
+	ofnode coupling_node;
+	uint32_t phandle = 0;
+	int index = 0;
+	char *regu_id_name;
+	const uint32_t *prop_val;
+	int prop_len = 0;
+	int prop_size = 0;
+    int coupling_num = 0;
+	uint16_t hw_id_used_flag = 0x0;
+
+	ofnode_for_each_subnode(hw_id_node, regu_config_node)
+	{
+		const char *node_name = ofnode_get_name(hw_id_node);
+		if (!strncmp(node_name, REGU_ID_NAME, strlen(REGU_ID_NAME)))
+		{
+			index = get_node_index(node_name);
+			if (index < 0)
+			{
+				printf("get hw_id faild");
+				return -1;
+			}
+
+			if (index >= PMIC_MAX_HW_ID_NUM || index >= 8 * sizeof(uint16_t))
+			{
+				printf("regu_id index should less than %d\n", MIN(PMIC_MAX_HW_ID_NUM, 8 * sizeof(uint16_t)));
+				return -1;
+			}
+
+			if ((hw_id_used_flag >> index) & 0x01)
+			{
+				printf("%s@%d already exist\n", REGU_ID_NAME, index);
+				return -1;
+			}
+			else
+			{
+				hw_id_used_flag |= 0x01 << index;
+			}
+
+			ret = misc_regu_get_each_regu_hw_id_config(hw_id_node, pmic_dev_num, pmic_dev_info_list, regu_info, &pmic_regu_id_info->sub.id[index]);
+			if (ret)
+			{
+				printf("get hw_id@%d config faild %d\n", ret);
+				return -1;
+			}
+		}
+
+	}
+
+	for (int i = PMIC_MAX_HW_ID_NUM - 1; i >= 0; i--)
+	{
+		if ((hw_id_used_flag & (0x01 << i)) == 0x0)
+		{
+			(*pmic_regu_id_info).sub.id[i].pmic_id = PMIC_ID_INVALID;
+		}
+	}
+    
+	ofnode_for_each_subnode(coupling_node, regu_config_node)
+	{
+		const char *node_name = ofnode_get_name(coupling_node);
+
+		if (!strncmp(node_name, COUPLING_ID_INFO_NAME, strlen(COUPLING_ID_INFO_NAME)))
+		{
+		/*get info = <0 1 -5 30>;*/
+	     prop_val = ofnode_get_property(coupling_node, "info", &prop_len);
+	    if (!prop_val)
+	    {
+		   printf("no info property set for %s", node_name);
+		   return -1;
+	    } else
+	    {
+			prop_size = prop_len / sizeof(uint32_t);
+			if (prop_size != 4)
+			{
+				printf("coupling info property should set in format as info = <id0 id1 max_spread min_spread)>\n");
+				return -1;
+			}
+
+            int id0 = FDT32_TO_CPU(prop_val[0]);
+		    int id1 = FDT32_TO_CPU(prop_val[1]);
+			int8_t max_spread = FDT32_TO_CPU(prop_val[2]);
+			int8_t min_spread = FDT32_TO_CPU(prop_val[3]);
+
+			if(ofnode_read_bool(coupling_node, "negative-min")) {
+                 min_spread = -min_spread; 
+			}
+			if(ofnode_read_bool(coupling_node, "negative-max")) {
+                 max_spread = -max_spread; 
+			}
+			if(id0 == id1) {
+                printf("coupling info: id0 id1 should not be equal");
+				return -1;
+			}
+			if(min_spread > max_spread) {
+                printf("coupling info: min_spread:%d is higher than max_spread:%d", min_spread, max_spread);
+				return -1;
+			}
+			if(id0 >= PMIC_MAX_HW_ID_NUM || id1 >= PMIC_MAX_HW_ID_NUM) {
+                printf("coupling info: id0:%d id1:%d is higher than max_id:%d", id0, id1, PMIC_MAX_HW_ID_NUM -1);
+				return -1;
+			}
+
+			if((*pmic_regu_id_info).sub.id[id0].pmic_id == PMIC_ID_INVALID || (*pmic_regu_id_info).sub.id[id1].pmic_id == PMIC_ID_INVALID) {
+                printf("coupling info:id0:%d id1:%d is invalid", id0, id1);
+				return -1;
+			}
+			(*pmic_regu_id_info).sub.coupling_list[coupling_num].id0 = id0;
+			(*pmic_regu_id_info).sub.coupling_list[coupling_num].id1 = id1;
+			(*pmic_regu_id_info).sub.coupling_list[coupling_num].max_spread = max_spread;
+			(*pmic_regu_id_info).sub.coupling_list[coupling_num].min_spread = min_spread;
+			coupling_num++;
+			if(coupling_num > PMIC_MAX_COUPLING_NUM) {
+                printf("coupling info should no more than %d\n", coupling_num);
+				return -1;
+			}
+	   }
+		}
+
+	}
+
+	for(int i = PMIC_MAX_COUPLING_NUM - 1; i >= coupling_num; i--)
+	{
+       (*pmic_regu_id_info).sub.coupling_list[i].id0 =  REGU_SUB_ID_INVALID;
+	   (*pmic_regu_id_info).sub.coupling_list[i].id1 =  REGU_SUB_ID_INVALID;
+	}
+
+	return 0;
+}
+
+static int misc_regu_get_regu_config(ofnode parent_node, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list, int virtual_id_num, soc_virtual_id_t *regu_list, csi_regu_id_t *pmic_regu_id_list)
+{
+	ofnode child_node;
+	int index = 0;
+	uint32_t phandle = 0;
+	int ret = 0;
+	ofnode regu_virtual_node;
+	char *regu_id_name;
+	int virtual_id_index = 0;
+	uint16_t virtual_id_config_flag = 0;
+	int regu_config_index = 0;
+
+	ofnode_for_each_subnode(child_node, parent_node)
+	{
+		virtual_id_index = 0;
+		char *node_name = ofnode_get_name(child_node);
+		if (!strncmp(node_name, REGU_ID_CONF_NAME, strlen(REGU_ID_CONF_NAME)))
+		{
+
+			if (ofnode_read_u32(child_node, "reg_info", &phandle))
+			{
+				printf("reg_info property not found\n");
+				return -1;
+			}
+
+			regu_virtual_node = ofnode_get_by_phandle(phandle);
+			if (!ofnode_valid(regu_virtual_node))
+			{
+				printf("virtual_regu_node  not found\n");
+				return -1;
+			}
+
+			regu_id_name = ofnode_get_name(regu_virtual_node);
+
+			for (; virtual_id_index < virtual_id_num; virtual_id_index++)
+			{
+				if (!strcasecmp(regu_list[virtual_id_index].virtual_id_name, regu_id_name))
+				{
+					break;
+				}
+			}
+
+			if (virtual_id_index == virtual_id_num)
+			{
+				printf("virtual regu id %s not found\n", regu_id_name);
+				return -1;
+			}
+
+			int virtual_id = regu_list[virtual_id_index].id;
+
+			if ((virtual_id_config_flag >> virtual_id) & 0x01)
+			{
+				printf("%s config for %s already exist\n!", REGU_ID_CONF_NAME, regu_list[virtual_id_index].virtual_id_name);
+				return -1;
+			}
+			else
+			{
+				virtual_id_config_flag |= 0x01 << virtual_id;
+			}
+
+			csi_regu_id_t *regu_conf = &pmic_regu_id_list[regu_config_index];
+
+			regu_conf->regu_ext_id = virtual_id;
+			int copy_size = MIN(sizeof(regu_conf->regu_ext_id_name) - 1, strlen(regu_list[virtual_id_index].virtual_id_name));
+			memcpy(regu_conf->regu_ext_id_name, regu_list[virtual_id_index].virtual_id_name, copy_size);
+
+			ret = misc_regu_get_each_regu_config(child_node, pmic_dev_num, pmic_dev_info_list, &regu_list[virtual_id_index], regu_conf);
+			if (ret)
+			{
+				return -1;
+			}
+
+			AON_CONF_D("Get regu config, virtual_regu_id:[%d]:%s min_uv:%dmv max_uv:%dmv\n", virtual_id, regu_list[virtual_id_index].virtual_id_name, regu_list[virtual_id_index].min_uv,regu_list[virtual_id_index].max_uv);
+			for (int i = 0; i < ARRAY_SIZE(regu_conf->sub.id); i++)
+			{
+				pmic_hw_info_t *sub = &regu_conf->sub.id[i];
+				if (sub->pmic_id != PMIC_ID_INVALID)
+				{
+					char parent_info[50];
+					char auto_on_info[50];
+					char auto_off_info[50];
+
+					if (sub->parent_hw_info.pmic_id == PMIC_ID_INVALID)
+					{
+						sprintf(parent_info, "{NO_PARENT_PMIC}");
+					}
+					else
+					{
+						sprintf(parent_info, "{parent_pmic_dev:%d io_hw_id:%d activate_status:%d}", sub->parent_hw_info.pmic_id, sub->parent_hw_info.io_hw_id, sub->parent_hw_info.activate_status);
+					}
+
+					if (sub->soft_power_ctrl_info.on_info.on_order == HW_ID_NO_SOFT_AUTO_ON)
+					{
+						sprintf(auto_on_info, "{NOT_SUPPORT}");
+					}
+					else
+					{
+						sprintf(auto_on_info, "{on_order:%d on_delay:%d on_uv:%dmv}", sub->soft_power_ctrl_info.on_info.on_order, sub->soft_power_ctrl_info.on_info.on_delay_ms, sub->soft_power_ctrl_info.on_info.init_target_uv);
+					}
+					if (sub->soft_power_ctrl_info.off_info.off_order == HW_ID_NO_SOFT_AUTO_OFF)
+					{
+						sprintf(auto_off_info, "{NOT_SUPPORT}");
+					}
+					else
+					{
+						sprintf(auto_off_info, "{off_order:%d off_delay:%d}", sub->soft_power_ctrl_info.off_info.off_order, sub->soft_power_ctrl_info.off_info.off_delay_ms);
+					}
+
+					AON_CONF_D(">>>>>>%s@%d:{pmic_dev:%d hw_id:%d} parent_info:%s auto_on_info:%s auto_off_info:%s\n", REGU_ID_NAME, i, sub->pmic_id, sub->hw_id, parent_info, auto_on_info, auto_off_info);
+				}
+			}
+			int temp_flag = 0;
+			for(int i = 0; i < ARRAY_SIZE(regu_conf->sub.coupling_list); i++) {
+                coupling_desc_t* coupling_info = &regu_conf->sub.coupling_list[i];
+				if(coupling_info->id0 != REGU_SUB_ID_INVALID) {
+					if(!temp_flag) {
+                        AON_CONF_D(">>>>>>");
+						temp_flag = 1;
+					}
+                    AON_CONF_D("%s@%d:{id0:%d id1:%d max_spreed:%dmv min_spreed:%dmv}   ", COUPLING_ID_INFO_NAME, i,coupling_info->id0, coupling_info->id1, coupling_info->max_spread *10 , coupling_info->min_spread * 10);
+				}
+			}
+			if(temp_flag) {
+				AON_CONF_D("\n");
+			}
+			regu_config_index++;
+		}
+	}
+
+#warning "add no config check"
+	return 0;
+}
+
+static int misc_regu_get_aon_pmic_config(struct udevice *dev, ofnode parent_node, int virtual_id_num, soc_virtual_id_t *regu_list, pmic_dev_list_t *pmic_list, regu_id_list_t *regu_id_list)
+{
+	ofnode child_node;
+	int pmic_dev_num = 0;
+	int regu_id_conf_num = 0;
+	pmic_dev_info_t *pmic_dev_info_list;
+	csi_regu_id_t *pmic_regu_id_list;
+
+	const char *node_name;
+	int ret = 0;
+
+	ofnode_for_each_subnode(child_node, parent_node)
+	{
+		node_name = ofnode_get_name(child_node);
+		if (!strncmp(node_name, PMIC_DEV_DTS_NAME, strlen(PMIC_DEV_DTS_NAME)))
+		{
+			pmic_dev_num++;
+		}
+	}
+
+	if (!pmic_dev_num)
+	{
+		printf("No %s node in dts\n", PMIC_DEV_DTS_NAME);
+		return -1;
+	}
+
+	pmic_dev_info_list = devm_kcalloc(dev, 1, pmic_dev_num * sizeof(pmic_dev_info_t), GFP_KERNEL);
+	if (!pmic_dev_info_list)
+	{
+		printf("pmic dev list malloc faild\n");
+		return -ENOMEM;
+	}
+
+	ret = misc_regu_get_pmic_dev_config(parent_node, pmic_dev_info_list);
+	if (ret)
+	{
+		printf("pmic dev config get faild %d", ret);
+#warning "free"
+		return -1;
+	}
+
+	ofnode_for_each_subnode(child_node, parent_node)
+	{
+		node_name = ofnode_get_name(child_node);
+		if (!strncmp(node_name, REGU_ID_CONF_NAME, strlen(REGU_ID_CONF_NAME)))
+		{
+			regu_id_conf_num++;
+		}
+	}
+
+	if (!regu_id_conf_num)
+	{
+		printf("No %s node in dts\n", REGU_ID_CONF_NAME);
+		return -1;
+	}
+
+	pmic_regu_id_list = devm_kcalloc(dev, 1, regu_id_conf_num * sizeof(csi_regu_id_t), GFP_KERNEL);
+	if (!pmic_regu_id_list)
+	{
+		printf("pmic regu list malloc faild\n");
+		return -ENOMEM;
+	}
+
+	ret = misc_regu_get_regu_config(parent_node, pmic_dev_num, pmic_dev_info_list, virtual_id_num, regu_list, pmic_regu_id_list);
+	if (ret)
+	{
+		printf("get regu config faild %d\n", ret);
+#warning "free"
+		return -1;
+	}
+
+	(*pmic_list).pmic_num = pmic_dev_num;
+	(*pmic_list).pmic_list = pmic_dev_info_list;
+
+	(*regu_id_list).regu_id_num = regu_id_conf_num;
+	(*regu_id_list).regu_id_list = pmic_regu_id_list;
+
+	return 0;
+}
+
+static int misc_regu_bind(struct udevice *dev)
+{
+	struct mic_regu_platdata *plat = dev_get_platdata(dev);
+	ofnode parent_node = dev->node;
+
+	int ret;
+	ofnode child_node, node, regu_node, aon_conf_node;
+	const void *blob = gd->fdt_blob;
+	int subnode;
+	struct udevice *dev_1;
+
+	/* If this is a child device, there is nothing to do here */
+	if (plat)
+	{
+		return 0;
+	}
+
+	if (!ofnode_valid(parent_node))
+	{
+		printf("aon node not ok\n");
+		return -1;
+	}
+
+	int get_regu_dts_flag = 0;
+	int get_aon_conf_dst_flag = 0;
+
+	ofnode_for_each_subnode(child_node, parent_node)
+	{
+		/* Increment base_id for all subnodes, also the disabled ones */
+		//printf("sub node name: %s\n", ofnode_get_name(child_node));
+		if (!strncmp(ofnode_get_name(child_node), REGU_DTS_NAME, strlen(REGU_DTS_NAME)))
+		{
+			regu_node = child_node;
+			get_regu_dts_flag = 1;
+		}
+		if (!strncmp(ofnode_get_name(child_node), AON_CONF_NAME, strlen(AON_CONF_NAME)))
+		{
+			aon_conf_node = child_node;
+			get_aon_conf_dst_flag = 1;
+		}
+	}
+
+
+
+	if (!get_regu_dts_flag)
+	{
+		printf("No %s node in dts\n", REGU_DTS_NAME);
+		return -1;
+	}
+
+	if (!get_aon_conf_dst_flag)
+	{
+		printf("No %s node in dts\n", AON_CONF_NAME);
+		return -1;
+	}
+
+	plat = devm_kcalloc(dev, 1, sizeof(struct mic_regu_platdata), GFP_KERNEL);
+	if (!plat)
+	{
+		return -ENOMEM;
+	}
+
+	plat->wakeup_flag  = 0;
+
+	if (ofnode_read_bool(parent_node, "wakeup-by-gpio-on")) {
+		plat->wakeup_flag |= AON_WAKEUP_BY_GPIO;
+		printf("aon wakeup by gpio enabled\n");
+	}
+
+	if (ofnode_read_bool(parent_node, "wakeup-by-rtc-on")) {
+		plat->wakeup_flag |= AON_WAKEUP_BY_RTC;
+		printf("aon wakeup by rtc enabled\n");
+	}
+
+	ret = misc_regu_get_virtual_regu_config(dev, regu_node, &plat->regu_list);
+	if (ret)
+	{
+		printf("get virtual regu config failed %d\n", ret);
+		return -1;
+	}
+
+	ret = misc_regu_get_aon_pmic_config(dev, aon_conf_node, plat->regu_list.regu_num, plat->regu_list.regu_list, &plat->pmic_list, &plat->regu_id_list);
+	if (ret)
+	{
+		printf("get aon config failed %d\n", ret);
+		return -1;
+	}
+
+	plat->name = ofnode_get_name(parent_node);
+
+	ret = device_bind_ofnode(dev, dev->driver, plat->name, plat, parent_node, &dev_1);
+	if (ret)
+	{
+		printf("bind device faild %d", ret);
+		return ret;
+	}
+	/*fix me err usage*/
+	dev->platdata = plat;
+
+	return 0;
+}
+
+static const struct udevice_id misc_regu_ids[] = {
+	{.compatible = "thead,light-aon"},
+	{}};
+
+U_BOOT_DRIVER(light_regu) = {
+	.name = "light_regu,misc",
+	.id = UCLASS_MISC,
+	.of_match = misc_regu_ids,
+	.probe = misc_regu_probe,
+	.bind = misc_regu_bind,
+	.remove = misc_regu_remove,
+};

drivers/misc/light_regu.h

@@ -0,0 +1,229 @@
+#ifndef __LIGHT_REGU_H__
+#define __LIGHT_REGU_H__
+
+
+typedef enum
+{
+	SOC_DVDD18_AON,		  /*da9063:  ldo-3 */
+	SOC_AVDD33_USB3,	  /*da9063:  ldo-9 */
+	SOC_DVDD08_AON,		  /*da9063:  ldo-2 */
+	SOC_APCPU_DVDD_DVDDM, /*da9063:  vbcore1 & vbcore2*/
+	SOC_DVDD08_DDR,		  /*da9063:  buckperi */
+	SOC_VDD_DDR_1V8,	  /*da9063:  ldo-4  */
+	SOC_VDD_DDR_1V1,	  /*da9063:  buckmem & buckio  */
+	SOC_VDD_DDR_0V6,	  /*da9063:  buckpro */
+	SOC_DVDD18_AP,		  /*da9063:  ldo-11 */
+	SOC_DVDD08_AP,		  /*da9121:  da9121_ex */
+	SOC_AVDD08_MIPI_HDMI, /*da9063:  ldo-1  */
+	SOC_AVDD18_MIPI_HDMI, /*da9063:  ldo-5  */
+	SOC_DVDD33_EMMC,	  /*da9063:  ldo-10 */
+	SOC_DVDD18_EMMC,	  /*slg51000:ldo-3 */
+	SOC_DOVDD18_SCAN,	  /*da9063:  ldo-6 */
+	SOC_VEXT_2V8,		  /*da9063:  ldo-7 */
+	SOC_DVDD12_SCAN,	  /*da9063:  ldo-8 */
+	SOC_AVDD28_SCAN_EN,	  /*da9063:  gpio-4,SGM2019-ADJ */
+	SOC_AVDD28_RGB,		  /*slg51000:ldo-1 */
+	SOC_DOVDD18_RGB,	  /*slg51000:ldo-4 */
+	SOC_DVDD12_RGB,		  /*slg51000:ldo-5 */
+	SOC_AVDD25_IR,		  /*slg51000:ldo-2 */
+	SOC_DOVDD18_IR,		  /*slg51000:ldo-7 */
+	SOC_DVDD12_IR,		  /*slg51000:ldo-6 */
+	SOC_ADC_VREF,
+	SOC_LCD0_EN,
+	SOC_VEXT_1V8,
+
+	SOC_REGU_INVALID = 0xFF
+} soc_virtual_id_en;
+
+
+#define REGU_DTS_NAME "light-regu-reg"
+#define AON_CONF_NAME "aon_pmic_config"
+#define PMIC_DEV_DTS_NAME "pmic-dev"
+#define REGU_ID_CONF_NAME "regu_config"
+#define REGU_ID_NAME      "regu_id"
+#define COUPLING_ID_INFO_NAME  "coupling_info"
+
+
+
+#define PMIC_DEV_ENABLE_WDT                (1U << 0)
+#define PMIC_DEV_ENABLE_ERR_IO             (1U << 1)
+#define PMIC_DEV_ENABLE_LPM_IO             (1U << 2)
+
+#define HW_ID_NO_SOFT_AUTO_ON   (0xff)
+#define HW_ID_NO_SOFT_AUTO_OFF  (0xff)
+#define HW_ID_INVALID           (0xff)
+#define PMIC_ID_INVALID         (0xff)
+#define REGU_SUB_ID_INVALID     (0xff)
+
+#define REGU_EXT_ID_NAME_LEN 30
+#define PMIC_DEV_NAME_LEN 20
+#define PMIC_DEV_VERSION_LEN 20
+
+#define PMIC_MAX_HW_ID_NUM 3
+#define PMIC_MAX_COUPLING_NUM 3
+
+#define AON_WAKEUP_BY_GPIO (1 << 0)
+#define AON_WAKEUP_BY_RTC  (1 << 1)
+
+typedef enum {
+   HW_ID_ACTIVATE_HIGH  = 0U,
+   HW_ID_ACTIVATE_LOW =   1U,
+} hw_activate_status_en;
+
+typedef struct __packed {
+	uint8_t pmic_id;
+    uint8_t io_hw_id;
+    uint8_t activate_status;
+} pmic_parent_hw_io_ctrl_info_t;
+
+typedef struct __packed  {
+    uint8_t   on_order;
+	uint8_t   on_delay_ms;
+    uint32_t  init_target_uv;
+} regu_soft_power_ctrl_on_t;
+
+typedef struct __packed {
+    uint8_t off_order;
+	uint8_t off_delay_ms;
+} regu_soft_power_ctrl_off_t;
+
+typedef struct __packed {
+   regu_soft_power_ctrl_on_t  on_info;
+   regu_soft_power_ctrl_off_t off_info;
+} regu_soft_power_ctrl_t;
+
+
+typedef struct __packed {
+	uint8_t id0;
+	uint8_t id1;
+	int8_t max_spread; // mv/10
+	int8_t min_spread; // mv/10
+}coupling_desc_t;
+
+
+typedef struct __packed {
+   uint8_t pmic_id;
+   uint8_t hw_id;
+   uint8_t benable;
+   pmic_parent_hw_io_ctrl_info_t parent_hw_info;
+   regu_soft_power_ctrl_t soft_power_ctrl_info;
+} pmic_hw_info_t;
+
+
+typedef	struct __packed{
+	coupling_desc_t coupling_list[PMIC_MAX_COUPLING_NUM];
+	pmic_hw_info_t  id[PMIC_MAX_HW_ID_NUM];                             ///<  sub id1 for single-rail or first src of dual-rail
+}pmic_hw_id_t;
+
+typedef struct __packed {
+	uint8_t     regu_ext_id;                   ///< virtual global regulator id
+	char        regu_ext_id_name[REGU_EXT_ID_NAME_LEN];             ///< vitual regu-id name
+	pmic_hw_id_t sub;                           ///<  sub id set for dual-rail/single-rail regulator
+}csi_regu_id_t;
+
+typedef enum {
+   PMIC_CTRL_BY_AON_GPIO =  0U,
+   PMIC_CTRL_BY_PMIC_GPIO = 1U,
+   PMIC_CTRL_BY_NOTHINTG  = 0xFF,
+} pmic_ctrl_info_en;
+
+typedef struct __packed {
+    uint8_t port;
+	uint8_t pin;
+    uint8_t activate_status;
+} pmic_ctrl_by_aon_info_t;
+
+typedef struct __packed {
+	uint8_t pmic_id;
+    uint8_t io_hw_id;
+    uint8_t activate_status;
+} pmic_ctrl_by_pmic_info_t;
+
+typedef struct __packed {
+    uint8_t pmic_ctrl_type;
+	union {
+       pmic_ctrl_by_aon_info_t  aon_io_info;
+	   pmic_ctrl_by_pmic_info_t pmic_io_info;
+	};
+} pmic_parent_ctrl_info_t;
+
+typedef struct  __packed{
+	 uint16_t gpio_port;
+     uint16_t pin;
+	 uint8_t  trigger_mode;
+} pmic_interrupt_io_info_t;
+
+typedef struct __packed  {
+    char device_name[PMIC_DEV_NAME_LEN];
+    char version_name[PMIC_DEV_VERSION_LEN];
+    uint8_t pmic_id;
+    uint8_t addr1;
+    uint8_t addr2;
+	uint8_t flag;          /*support wdt|errio| lpm io*/
+	uint8_t slew_rate;
+	uint32_t    wdt_len;
+	pmic_interrupt_io_info_t err_io_info;
+	pmic_interrupt_io_info_t lpm_io_info;
+    pmic_parent_ctrl_info_t ctrl_info;
+} pmic_dev_info_t;
+
+typedef struct
+{
+	soc_virtual_id_en id;
+	char virtual_id_name[REGU_EXT_ID_NAME_LEN];
+	int min_uv;
+	int max_uv;
+} soc_virtual_id_t;
+
+typedef struct
+{
+	int regu_num;
+	soc_virtual_id_t *regu_list;
+} virtual_regu_list_t;
+
+typedef struct
+{
+	int pmic_num;
+	pmic_dev_info_t *pmic_list;
+} pmic_dev_list_t;
+
+typedef struct
+{
+	int regu_id_num;
+	csi_regu_id_t *regu_id_list;
+} regu_id_list_t;
+
+struct mic_regu_platdata
+{
+	const char *name;
+	uint32_t  wakeup_flag;
+	virtual_regu_list_t regu_list;
+	pmic_dev_list_t pmic_list;
+	regu_id_list_t regu_id_list;
+};
+
+
+#define   AON_CONFIG_MAGIC   "AON_CONFIG"
+#define   AON_CONFIG_VERSION "1.0.0"
+
+typedef  struct __packed{
+	uint8_t iic_id;
+    uint8_t pmic_dev_num;
+    uint8_t regu_num;
+	int pmic_dev_list_offset;
+	int regu_id_list_offset;
+}aon_pmic_config_t;
+
+typedef  struct  __packed{
+   const char  magic[11];
+   const char  version[11];
+   uint8_t   max_hw_id_num;
+   uint64_t  aon_config_partition_size;
+   uint32_t  wakeup_flag;
+   aon_pmic_config_t aon_pmic;
+} aon_config_t;
+
+
+
+
+#endif

drivers/misc/misc-uclass.c

@@ -13,7 +13,6 @@
  * general classes. A set of generic read, write and ioctl methods may
  * be used to access the device.
  */
-
 int misc_read(struct udevice *dev, int offset, void *buf, int size)
 {
 	const struct misc_ops *ops = device_get_ops(dev);

drivers/mmc/sdhci.c

@@ -38,9 +38,7 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
 		timeout--;
 		udelay(1000);
 	}
-#ifdef CONFIG_TARGET_LIGHT_C910
-	mdelay(50);
-#endif
+
 }
 
 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
@@ -136,9 +134,9 @@ static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 	unsigned char ctrl;
 
 	if (data->flags == MMC_DATA_READ)
-		host->start_addr = (dma_addr_t)data->dest;
+		host->start_addr = (dma_addr_t)(u64)data->dest;
 	else
-		host->start_addr = (dma_addr_t)data->src;
+		host->start_addr = (dma_addr_t)(u64)data->src;
 
 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 	ctrl &= ~SDHCI_CTRL_DMA_MASK;

drivers/mmc/snps_sdhci.c

@@ -13,6 +13,7 @@
 #define HS400_DELAY_LANE	24
 
 volatile int DELAY_LANE = 50;
+volatile int manual_set_delay = 0;  //flag for cmd manual setted DELAY_LANE,non-zero is setted. auto clear in cmd
 
 static void sdhci_phy_1_8v_init_no_pull(struct sdhci_host *host)
 {
@@ -154,10 +155,14 @@ void snps_set_uhs_timing(struct sdhci_host *host)
 {
 	struct mmc *mmc = (struct mmc *)host->mmc;
 	u32 reg;
-
+	int restore_delay;
 	reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 	reg &= ~SDHCI_CTRL_UHS_MASK;
-
+    
+	if(manual_set_delay){
+		DELAY_LANE = DELAY_LANE & 0x7f; /*limit bit[0:6]*/
+		printf("%s: manual set delay (%d) active \n",host->name,DELAY_LANE);
+	}
 	switch (mmc->selected_mode) {
 	case UHS_SDR50:
 	case MMC_HS_52:
@@ -175,9 +180,13 @@ void snps_set_uhs_timing(struct sdhci_host *host)
 		reg |= SDHCI_CTRL_UHS_SDR104;
 		break;
 	case MMC_HS_400:
-		DELAY_LANE = HS400_DELAY_LANE;
+		restore_delay = DELAY_LANE;
+		if(!manual_set_delay){  /*default not set manual in cmd,when set in cmd,use DELAY_LANE set in cmd*/
+			 DELAY_LANE = HS400_DELAY_LANE;
+		}
 		sdhci_phy_1_8v_init(host);
 		reg |= SNPS_SDHCI_CTRL_HS400;
+		DELAY_LANE = restore_delay; /*restore for other modes*/
 		break;
 	default:
 		sdhci_phy_3_3v_init(host);
@@ -345,7 +354,10 @@ static int snps_sdhci_probe(struct udevice *dev)
 		ret = max_clk;
 		goto err;
 	}
-
+	//get Maximum Base Clock frequency from dts clock-frequency
+	if(0 == dev_read_u32(dev, "clock-frequency", &max_clk)){
+		host->max_clk = max_clk;
+	}
 	host->mmc = &plat->mmc;
 	host->mmc->dev = dev;
 	host->mmc->priv = host;

drivers/net/designware.c

@@ -508,7 +508,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
 {
 	struct phy_device *phydev;
 	int phy_addr = -1, ret;
-
+	
 #ifdef CONFIG_PHY_ADDR
 	phy_addr = CONFIG_PHY_ADDR;
 #endif
@@ -801,13 +801,16 @@ int designware_eth_probe(struct udevice *dev)
 		err = ret;
 		goto mdio_err;
 	}
-
+#ifdef GMAC_USE_FIRST_MII_BUS
 	if (!g_mii_bus) {
 		priv->bus = miiphy_get_dev_by_name(dev->name);
 		g_mii_bus = priv->bus;
 	} else {
 		priv->bus = g_mii_bus;
 	}
+#else
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+#endif
 	ret = dw_phy_init(priv, dev);
 	debug("%s, ret=%d\n", __func__, ret);
 	if (!ret)
@@ -815,8 +818,18 @@ int designware_eth_probe(struct udevice *dev)
 
 	/* continue here for cleanup if no PHY found */
 	err = ret;
+#ifdef GMAC_USE_FIRST_MII_BUS
+	struct mii_dev *t_mii = NULL;
+	t_mii = miiphy_get_dev_by_name(dev->name);
+	if((g_mii_bus != t_mii) && (t_mii != NULL) ){
+		printf("free mdio bus %s\n",t_mii->name);
+		mdio_unregister(t_mii);
+		mdio_free(t_mii);
+	}
+#else
 	mdio_unregister(priv->bus);
 	mdio_free(priv->bus);
+#endif
 mdio_err:
 
 #ifdef CONFIG_CLK

drivers/tpm/Makefile

@@ -12,3 +12,4 @@ obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o
 
 obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o
 obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_spi.o
+obj-$(CONFIG_TPM_Z32H330TC_SPI) += tpm2_tis_z32h330tc_spi.o

drivers/tpm/tpm2_tis_z32h330tc_spi.c

@@ -0,0 +1,676 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Author:
+ * Miquel Raynal <miquel.raynal@bootlin.com>
+ *
+ * Description:
+ * SPI-level driver for TCG/TIS TPM (trusted platform module).
+ * Specifications at www.trustedcomputinggroup.org
+ *
+ * This device driver implements the TPM interface as defined in
+ * the TCG SPI protocol stack version 2.0.
+ *
+ * It is based on the U-Boot driver tpm_tis_infineon_i2c.c.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <spi.h>
+#include <tpm-v2.h>
+#include <linux/errno.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <asm-generic/gpio.h>
+
+#include "tpm_tis.h"
+#include "tpm_internal.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TPM_ACCESS(l)			(0x0000 | ((l) << 12))
+#define TPM_INT_ENABLE(l)               (0x0008 | ((l) << 12))
+#define TPM_STS(l)			(0x0018 | ((l) << 12))
+#define TPM_DATA_FIFO(l)		(0x0024 | ((l) << 12))
+#define TPM_DID_VID(l)			(0x0F00 | ((l) << 12))
+#define TPM_RID(l)			(0x0F04 | ((l) << 12))
+
+#define MAX_SPI_FRAMESIZE 64
+
+/* Number of wait states to wait for */
+#define TPM_WAIT_STATES 100
+
+/**
+ * struct tpm_tis_chip_data - Non-discoverable TPM information
+ *
+ * @pcr_count:		Number of PCR per bank
+ * @pcr_select_min:	Size in octets of the pcrSelect array
+ */
+struct tpm_tis_chip_data {
+	unsigned int pcr_count;
+	unsigned int pcr_select_min;
+	unsigned int time_before_first_cmd_ms;
+};
+
+
+/**
+ * tpm_tis_spi_read() - Read from TPM register
+ *
+ * @addr: register address to read from
+ * @buffer: provided by caller
+ * @len: number of bytes to read
+ *
+ * Read len bytes from TPM register and put them into
+ * buffer (little-endian format, i.e. first byte is put into buffer[0]).
+ *
+ * NOTE: TPM is big-endian for multi-byte values. Multi-byte
+ * values have to be swapped.
+ *
+ * @return -EIO on error, 0 on success.
+ */
+static int tpm_tis_spi_xfer(struct udevice *dev, u32 addr, const u8 *out,
+			    u8 *in, u16 len)
+{
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+	int transfer_len, ret;
+	u8 tx_buf[MAX_SPI_FRAMESIZE];
+	u8 rx_buf[MAX_SPI_FRAMESIZE];
+
+	if (in && out) {
+		log(LOGC_NONE, LOGL_ERR, "%s: can't do full duplex\n",
+		    __func__);
+		return -EINVAL;
+	}
+
+	ret = spi_claim_bus(slave);
+	if (ret < 0) {
+		log(LOGC_NONE, LOGL_ERR, "%s: could not claim bus\n", __func__);
+		return ret;
+	}
+
+	while (len) {
+		/* Request */
+		transfer_len = min_t(u16, len, MAX_SPI_FRAMESIZE);
+		tx_buf[0] = (in ? BIT(7) : 0) | (transfer_len - 1);
+		tx_buf[1] = 0xD4;
+		tx_buf[2] = addr >> 8;
+		tx_buf[3] = addr;
+		ret = spi_xfer(slave, 4 * 8, tx_buf, rx_buf, SPI_XFER_BEGIN);
+		if (ret < 0) {
+			log(LOGC_NONE, LOGL_ERR,
+			    "%s: spi request transfer failed (err: %d)\n",
+			    __func__, ret);
+			goto release_bus;
+		}
+
+		/* Wait state */
+		if (!(rx_buf[3] & 0x1)) {
+			int i;
+
+			for (i = 0; i < TPM_WAIT_STATES; i++) {
+				ret = spi_xfer(slave, 1 * 8, NULL, rx_buf, 0);
+				if (ret) {
+					log(LOGC_NONE, LOGL_ERR,
+					    "%s: wait state failed: %d\n",
+					    __func__, ret);
+					goto release_bus;
+				}
+
+				if (rx_buf[0] & 0x1)
+					break;
+			}
+
+			if (i == TPM_WAIT_STATES) {
+				log(LOGC_NONE, LOGL_ERR,
+				    "%s: timeout on wait state\n", __func__);
+				ret = -ETIMEDOUT;
+				goto release_bus;
+			}
+		}
+
+		/* Read/Write */
+		if (out) {
+			memcpy(tx_buf, out, transfer_len);
+			out += transfer_len;
+		}
+
+		ret = spi_xfer(slave, transfer_len * 8,
+			       out ? tx_buf : NULL,
+			       in ? rx_buf : NULL,
+			       SPI_XFER_END);
+		if (ret) {
+			log(LOGC_NONE, LOGL_ERR,
+			    "%s: spi read transfer failed (err: %d)\n",
+			    __func__, ret);
+			goto release_bus;
+		}
+
+		if (in) {
+			memcpy(in, rx_buf, transfer_len);
+			in += transfer_len;
+		}
+
+		len -= transfer_len;
+	}
+
+release_bus:
+	/* If an error occurred, release the chip by deasserting the CS */
+	if (ret < 0)
+		spi_xfer(slave, 0, NULL, NULL, SPI_XFER_END);
+
+	spi_release_bus(slave);
+
+	return ret;
+}
+
+static int tpm_tis_spi_read(struct udevice *dev, u16 addr, u8 *in, u16 len)
+{
+	return tpm_tis_spi_xfer(dev, addr, NULL, in, len);
+}
+
+static int tpm_tis_spi_read32(struct udevice *dev, u32 addr, u32 *result)
+{
+	__le32 result_le;
+	int ret;
+
+	ret = tpm_tis_spi_read(dev, addr, (u8 *)&result_le, sizeof(u32));
+	if (!ret)
+		*result = le32_to_cpu(result_le);
+
+	return ret;
+}
+
+static int tpm_tis_spi_write(struct udevice *dev, u16 addr, const u8 *out,
+			     u16 len)
+{
+	return tpm_tis_spi_xfer(dev, addr, out, NULL, len);
+}
+
+static int tpm_tis_spi_check_locality(struct udevice *dev, int loc)
+{
+	const u8 mask = TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID;
+	struct tpm_chip *chip = dev_get_priv(dev);
+	u8 buf;
+	int ret;
+
+	ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1);
+	if (ret)
+		return ret;
+
+	if ((buf & mask) == mask) {
+		chip->locality = loc;
+		return 0;
+	}
+
+	return -ENOENT;
+}
+
+static void tpm_tis_spi_release_locality(struct udevice *dev, int loc,
+					 bool force)
+{
+	const u8 mask = TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID;
+	u8 buf;
+
+	if (tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1) < 0)
+		return;
+
+	if (force || (buf & mask) == mask) {
+		buf = TPM_ACCESS_ACTIVE_LOCALITY;
+		tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1);
+	}
+}
+
+static int tpm_tis_spi_request_locality(struct udevice *dev, int loc)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+	unsigned long start, stop;
+	u8 buf = TPM_ACCESS_REQUEST_USE;
+	int ret;
+
+	ret = tpm_tis_spi_check_locality(dev, loc);
+	if (!ret)
+		return 0;
+
+	if (ret != -ENOENT) {
+		log(LOGC_NONE, LOGL_ERR, "%s: Failed to get locality: %d\n",
+		    __func__, ret);
+		return ret;
+	}
+
+	ret = tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1);
+	if (ret) {
+		log(LOGC_NONE, LOGL_ERR, "%s: Failed to write to TPM: %d\n",
+		    __func__, ret);
+		return ret;
+	}
+
+	start = get_timer(0);
+	stop = chip->timeout_a;
+	do {
+		ret = tpm_tis_spi_check_locality(dev, loc);
+		if (!ret)
+			return 0;
+
+		if (ret != -ENOENT) {
+			log(LOGC_NONE, LOGL_ERR,
+			    "%s: Failed to get locality: %d\n", __func__, ret);
+			return ret;
+		}
+
+		mdelay(TPM_TIMEOUT_MS);
+	} while (get_timer(start) < stop);
+
+	log(LOGC_NONE, LOGL_ERR, "%s: Timeout getting locality: %d\n", __func__,
+	    ret);
+
+	return ret;
+}
+
+static u8 tpm_tis_spi_status(struct udevice *dev, u8 *status)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+
+	return tpm_tis_spi_read(dev, TPM_STS(chip->locality), status, 1);
+}
+
+static int tpm_tis_spi_wait_for_stat(struct udevice *dev, u8 mask,
+				     unsigned long timeout, u8 *status)
+{
+	unsigned long start = get_timer(0);
+	unsigned long stop = timeout;
+	int ret;
+
+	do {
+		mdelay(TPM_TIMEOUT_MS);
+		ret = tpm_tis_spi_status(dev, status);
+		if (ret)
+			return ret;
+
+		if ((*status & mask) == mask)
+			return 0;
+	} while (get_timer(start) < stop);
+
+	return -ETIMEDOUT;
+}
+
+static u8 tpm_tis_spi_valid_status(struct udevice *dev, u8 *status)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+
+	return tpm_tis_spi_wait_for_stat(dev, TPM_STS_VALID,
+		chip->timeout_c, status);
+}
+
+static int tpm_tis_spi_get_burstcount(struct udevice *dev)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+	unsigned long start, stop;
+	u32 burstcount, ret;
+
+	/* wait for burstcount */
+	start = get_timer(0);
+	stop = chip->timeout_d;
+	do {
+		ret = tpm_tis_spi_read32(dev, TPM_STS(chip->locality),
+					 &burstcount);
+		if (ret)
+			return -EBUSY;
+
+		burstcount = (burstcount >> 8) & 0xFFFF;
+		if (burstcount)
+			return burstcount;
+
+		mdelay(TPM_TIMEOUT_MS);
+	} while (get_timer(start) < stop);
+
+	return -EBUSY;
+}
+
+static int tpm_tis_spi_cancel(struct udevice *dev)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+	u8 data = TPM_STS_COMMAND_READY;
+
+	return tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1);
+}
+
+static int tpm_tis_spi_recv_data(struct udevice *dev, u8 *buf, size_t count)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+	int size = 0, burstcnt, len, ret;
+	u8 status;
+
+	while (size < count &&
+	       tpm_tis_spi_wait_for_stat(dev,
+					 TPM_STS_DATA_AVAIL | TPM_STS_VALID,
+					 chip->timeout_c, &status) == 0) {
+		burstcnt = tpm_tis_spi_get_burstcount(dev);
+		if (burstcnt < 0)
+			return burstcnt;
+
+		len = min_t(int, burstcnt, count - size);
+		ret = tpm_tis_spi_read(dev, TPM_DATA_FIFO(chip->locality),
+				       buf + size, len);
+		if (ret < 0)
+			return ret;
+
+		size += len;
+	}
+
+	return size;
+}
+
+static int z32h330tc_spi_recv(struct udevice *dev, u8 *buf, size_t count)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+	int size, expected;
+
+	if (!chip)
+		return -ENODEV;
+
+	if (count < TPM_HEADER_SIZE) {
+		size = -EIO;
+		goto out;
+	}
+
+	size = tpm_tis_spi_recv_data(dev, buf, TPM_HEADER_SIZE);
+	if (size < TPM_HEADER_SIZE) {
+		log(LOGC_NONE, LOGL_ERR, "TPM error, unable to read header\n");
+		goto out;
+	}
+
+	expected = get_unaligned_be32(buf + 2);
+	if (expected > count) {
+		size = -EIO;
+		goto out;
+	}
+
+	size += tpm_tis_spi_recv_data(dev, &buf[TPM_HEADER_SIZE],
+				   expected - TPM_HEADER_SIZE);
+	if (size < expected) {
+		log(LOGC_NONE, LOGL_ERR,
+		    "TPM error, unable to read remaining bytes of result\n");
+		size = -EIO;
+		goto out;
+	}
+
+out:
+	tpm_tis_spi_cancel(dev);
+	tpm_tis_spi_release_locality(dev, chip->locality, false);
+
+	return size;
+}
+
+static int z32h330tc_spi_send(struct udevice *dev, const u8 *buf, size_t len)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+	u32 i, size;
+	u8 status;
+	int burstcnt, ret;
+	u8 data;
+
+	if (!chip)
+		return -ENODEV;
+
+	if (len > TPM_DEV_BUFSIZE)
+		return -E2BIG;  /* Command is too long for our tpm, sorry */
+
+	ret = tpm_tis_spi_request_locality(dev, 0);
+	if (ret < 0)
+		return -EBUSY;
+
+	/*
+	 * Check if the TPM is ready. If not, if not, cancel the pending command
+	 * and poll on the status to be finally ready.
+	 */
+	ret = tpm_tis_spi_status(dev, &status);
+	if (ret)
+		return ret;
+
+	if (!(status & TPM_STS_COMMAND_READY)) {
+		/* Force the transition, usually this will be done at startup */
+		ret = tpm_tis_spi_cancel(dev);
+		if (ret) {
+			log(LOGC_NONE, LOGL_ERR,
+			    "%s: Could not cancel previous operation\n",
+			    __func__);
+			goto out_err;
+		}
+
+		ret = tpm_tis_spi_wait_for_stat(dev, TPM_STS_COMMAND_READY,
+						chip->timeout_b, &status);
+		if (ret < 0 || !(status & TPM_STS_COMMAND_READY)) {
+			log(LOGC_NONE, LOGL_ERR,
+			    "status %d after wait for stat returned %d\n",
+			    status, ret);
+			goto out_err;
+		}
+	}
+
+	for (i = 0; i < len - 1;) {
+		burstcnt = tpm_tis_spi_get_burstcount(dev);
+		if (burstcnt < 0)
+			return burstcnt;
+
+		size = min_t(int, len - i - 1, burstcnt);
+		ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality),
+					buf + i, size);
+		if (ret < 0)
+			goto out_err;
+
+		i += size;
+	}
+
+	ret = tpm_tis_spi_valid_status(dev, &status);
+	if (ret)
+		goto out_err;
+
+	if ((status & TPM_STS_DATA_EXPECT) == 0) {
+		ret = -EIO;
+		goto out_err;
+	}
+
+	ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality),
+				buf + len - 1, 1);
+	if (ret)
+		goto out_err;
+
+	ret = tpm_tis_spi_valid_status(dev, &status);
+	if (ret)
+		goto out_err;
+
+	if ((status & TPM_STS_DATA_EXPECT) != 0) {
+		ret = -EIO;
+		goto out_err;
+	}
+
+	data = TPM_STS_GO;
+	ret = tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1);
+	if (ret)
+		goto out_err;
+
+	return len;
+
+out_err:
+	tpm_tis_spi_cancel(dev);
+	tpm_tis_spi_release_locality(dev, chip->locality, false);
+
+	return ret;
+}
+
+static int z32h330tc_spi_cleanup(struct udevice *dev)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+
+	tpm_tis_spi_cancel(dev);
+	/*
+	 * The TPM needs some time to clean up here,
+	 * so we sleep rather than keeping the bus busy
+	 */
+	mdelay(2);
+	tpm_tis_spi_release_locality(dev, chip->locality, false);
+
+	return 0;
+}
+
+static int z32h330tc_spi_open(struct udevice *dev)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+	struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
+
+	if (chip->is_open)
+		return -EBUSY;
+
+	chip->is_open = 1;
+
+	return 0;
+}
+
+static int z32h330tc_spi_close(struct udevice *dev)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+
+	if (chip->is_open) {
+		tpm_tis_spi_release_locality(dev, chip->locality, true);
+		chip->is_open = 0;
+	}
+
+	return 0;
+}
+
+static int z32h330tc_get_desc(struct udevice *dev, char *buf, int size)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+	if (size < 80)
+		return -ENOSPC;
+
+	return snprintf(buf, size,
+			"%s v2.0: VendorID 0x%04x, DeviceID 0x%04x, RevisionID 0x%02x [%s]",
+			dev->name, chip->vend_dev & 0xFFFF,
+			chip->vend_dev >> 16, chip->rid,
+			(chip->is_open ? "open" : "closed"));
+}
+
+static int tpm_tis_wait_init(struct udevice *dev, int loc)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+	unsigned long start, stop;
+	u8 status;
+	int ret;
+
+	start = get_timer(0);
+	stop = chip->timeout_b;
+	do {
+		mdelay(TPM_TIMEOUT_MS);
+
+		ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &status, 1);
+		if (ret)
+			break;
+
+		if (status & TPM_ACCESS_VALID)
+			return 0;
+	} while (get_timer(start) < stop);
+
+	return -EIO;
+}
+static const struct tpm_tis_chip_data z32h330tc_std_chip_data;
+
+static int z32h330tc_spi_probe(struct udevice *dev)
+{
+	struct tpm_tis_chip_data * drv_data = &z32h330tc_std_chip_data;//(void *)dev_get_driver_data(dev);
+	struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
+	struct tpm_chip *chip = dev_get_priv(dev);
+	struct udevice * bus = NULL;
+	int ret;
+
+	/* Use the TPM v2 stack */
+	priv->version = TPM_V2;
+
+	/* Ensure a minimum amount of time elapsed since reset of the TPM */
+	mdelay(drv_data->time_before_first_cmd_ms);
+	chip->locality = 0;
+	chip->timeout_a = TIS_SHORT_TIMEOUT_MS;
+	chip->timeout_b = TIS_LONG_TIMEOUT_MS;
+	chip->timeout_c = TIS_SHORT_TIMEOUT_MS;
+	chip->timeout_d = TIS_SHORT_TIMEOUT_MS;
+	priv->pcr_count = drv_data->pcr_count;
+	priv->pcr_select_min = drv_data->pcr_select_min;
+
+	ret = tpm_tis_wait_init(dev, chip->locality);
+	if (ret) {
+		log(LOGC_DM, LOGL_ERR, "%s: no device found\n", __func__);
+		return ret;
+	}
+
+	ret = tpm_tis_spi_request_locality(dev, chip->locality);
+	if (ret) {
+		log(LOGC_NONE, LOGL_ERR, "%s: could not request locality %d\n",
+		    __func__, chip->locality);
+		return ret;
+	}
+
+	ret = tpm_tis_spi_read32(dev, TPM_DID_VID(chip->locality),
+				 &chip->vend_dev);
+	if (ret) {
+		log(LOGC_NONE, LOGL_ERR,
+		    "%s: could not retrieve VendorID/DeviceID\n", __func__);
+		return ret;
+	}
+
+	ret = tpm_tis_spi_read(dev, TPM_RID(chip->locality), &chip->rid, 1);
+	if (ret) {
+		log(LOGC_NONE, LOGL_ERR, "%s: could not retrieve RevisionID\n",
+		    __func__);
+		return ret;
+	}
+
+	log(LOGC_NONE, LOGL_ERR,
+	    "SPI TPMv2.0 found (vid:%04x, did:%04x, rid:%02x)\n",
+	    chip->vend_dev & 0xFFFF, chip->vend_dev >> 16, chip->rid);
+
+	return 0;
+}
+
+static int z32h330tc_spi_remove(struct udevice *dev)
+{
+	struct tpm_chip *chip = dev_get_priv(dev);
+
+	tpm_tis_spi_release_locality(dev, chip->locality, true);
+
+	return 0;
+}
+
+static const struct tpm_ops z32h330tc_spi_ops = {
+	.open		= z32h330tc_spi_open,
+	.close		= z32h330tc_spi_close,
+	.get_desc	= z32h330tc_get_desc,
+	.send		= z32h330tc_spi_send,
+	.recv		= z32h330tc_spi_recv,
+	.cleanup	= z32h330tc_spi_cleanup,
+};
+
+static const struct tpm_tis_chip_data z32h330tc_std_chip_data = {
+	.pcr_count = 24,
+	.pcr_select_min = 3,
+	.time_before_first_cmd_ms = 30,
+};
+
+static const struct udevice_id z32h330tc_spi_ids[] = {
+	{
+		.compatible = "z32h330tc,z32h330tc-spi",
+		.data = (ulong)&z32h330tc_std_chip_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(tpm_z32h330tc_spi) = {
+	.name   = "tpm_z32h330tc_spi",
+	.id     = UCLASS_TPM,
+	.of_match = z32h330tc_spi_ids,
+	.ops    = &z32h330tc_spi_ops,
+	.probe	= z32h330tc_spi_probe,
+	.remove	= z32h330tc_spi_remove,
+	.priv_auto_alloc_size = sizeof(struct tpm_chip),
+};

drivers/usb/dwc3/ep0.c

@@ -905,7 +905,10 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 	dep->flags &= ~DWC3_EP_BUSY;
 	dep->resource_index = 0;
 	dwc->setup_packet_pending = false;
-	invalid_dcache_range(dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
+#ifdef CONFIG_TARGET_LIGHT_C910
+	extern void invalid_dcache_range(unsigned long start, unsigned long end);
+	invalid_dcache_range((unsigned long)dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
+#endif
 
 	switch (dwc->ep0state) {
 	case EP0_SETUP_PHASE:

drivers/video/Kconfig

@@ -351,6 +351,19 @@ config VIDEO_LCD_ILITEK_ILI9881C
 	Say Y here if you want to enable support for ILITEK ILI9881C
 	800x1280 DSI video mode panel.
 
+config VIDEO_LCD_JD9365DA
+	bool "JD9365DA DSI LCD panel support"
+	depends on DM_VIDEO
+	select VIDEO_MIPI_DSI
+	help
+	Say Y here if you want to enable support for JD9365DA
+	800x1280 DSI video mode panel.
+
+config VIDEO_LCD_CUSTOM_LOGO
+	bool "LCD CUSTOM logo support"
+	help
+	Say Y here if you want to enable support for custom logo.
+
 config VIDEO_LCD_SSD2828
 	bool "SSD2828 bridge chip"
 	default n

drivers/video/Makefile

@@ -69,6 +69,7 @@ obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
+obj-$(CONFIG_VIDEO_LCD_JD9365DA) += jadard-jd9365da-h3.o
 
 obj-y += bridge/
 obj-y += sunxi/

drivers/video/jadard-jd9365da-h3.c

@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ *
+ * Author:
+ * - Jagan Teki <jagan@amarulasolutions.com>
+ * - Stephen Chen <stephen@radxa.com>
+ */
+
+#include <common.h>
+#include <backlight.h>
+#include <dm.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+
+struct jadard_panel_desc {
+	const struct display_timing *timing;
+	unsigned long mode_flags;
+	enum mipi_dsi_pixel_format format;
+	unsigned int lanes;
+};
+
+struct panel_info {
+	const struct jadard_panel_desc *desc;
+	struct gpio_desc	reset;
+	struct gpio_desc	hsvcc;
+	struct gpio_desc	vspn3v3;
+	bool   prepared;
+	bool   enabled;
+};
+
+static int jd9365_get_display_timing(struct udevice *dev,
+		struct display_timing *timings)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+	struct mipi_dsi_device *device = plat->device;
+	struct panel_info *pinfo = dev_get_priv(dev);
+
+	memcpy(timings, pinfo->desc->timing, sizeof(*timings));
+
+	device->lanes	   = pinfo->desc->lanes;
+	device->format	   = pinfo->desc->format;
+	device->mode_flags = pinfo->desc->mode_flags;
+
+	return 0;
+}
+
+static int jadard_prepare(struct udevice *panel)
+{
+	struct panel_info *pinfo = dev_get_priv(panel);
+	int ret;
+
+	if (pinfo->prepared)
+		return 0;
+	dm_gpio_set_value(&pinfo->reset, false);
+
+	/* Power the panel */
+	ret = dm_gpio_set_value(&pinfo->hsvcc, true);
+	if (ret) {
+		return ret;
+	}
+
+	mdelay(1);
+	ret = dm_gpio_set_value(&pinfo->vspn3v3, true);
+	if (ret) {
+		return ret;
+	}
+	mdelay(1);
+
+	dm_gpio_set_value(&pinfo->reset, true);
+	mdelay(10);
+
+	pinfo->prepared = true;
+
+	return 0;
+}
+
+static int jadard_enable(struct udevice *panel)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(panel);
+	struct mipi_dsi_device *dsi = plat->device;
+	struct panel_info *pinfo = dev_get_priv(panel);
+	u8 power_mode;
+	int ret;
+
+	if (pinfo->enabled)
+		return 0;
+
+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	/* sanity test for connection */
+	ret = mipi_dsi_dcs_get_power_mode(dsi, &power_mode);
+	if (ret) {
+		dev_warn(dsi->dev, "%s: failed to get power mode: %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret)
+		return ret;
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret)
+	{
+		return ret;
+	}
+
+	mdelay(10);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret){
+		return ret;
+	}
+
+	pinfo->enabled = true;
+
+	return 0;
+}
+
+static int jd9365_panel_enable(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat   = dev_get_platdata(dev);
+	struct mipi_dsi_device     *device = plat->device;
+	int ret;
+
+	ret = mipi_dsi_attach(device);
+	if (ret < 0)
+		return ret;
+
+	ret = jadard_enable(dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct display_timing txd_jd9365_timing = {
+	.pixelclock.typ		= 74250000,
+	.hactive.typ		= 800,
+	.hfront_porch.typ	= 60,
+	.hback_porch.typ	= 60,
+	.hsync_len.typ		= 40,
+	.vactive.typ		= 1280,
+	.vfront_porch.typ	= 16,
+	.vback_porch.typ	= 16,
+	.vsync_len.typ		= 8,
+	.flags			=  DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
+};
+
+static const struct jadard_panel_desc jd9365_panel_desc = {
+	.timing = &txd_jd9365_timing,
+	.mode_flags = MIPI_DSI_MODE_VIDEO |  MIPI_DSI_MODE_VIDEO_BURST,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 4,
+};
+
+static int jd9365_panel_ofdata_to_platdata(struct udevice *dev)
+{
+	struct panel_info *pinfo = dev_get_priv(dev);
+	int ret;
+
+	ret = gpio_request_by_name(dev, "reset-gpio", 0,
+			&pinfo->reset, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get reset GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "hsvcc-gpio", 0,
+			&pinfo->hsvcc, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get hsvcc GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "vspn3v3-gpio", 0,
+			&pinfo->vspn3v3, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get vspn3v3 GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int jadard_dsi_probe(struct udevice *panel)
+{
+	int ret;
+	struct panel_info *pinfo = dev_get_priv(panel);
+
+	pinfo->desc = (const struct jadard_panel_desc*)dev_get_driver_data(panel);
+
+	ret = jadard_prepare(panel);
+	if (ret) {
+		dev_err(panel, "failed to prepare panel : %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int jadard_dsi_remove(struct udevice *panel)
+{
+	return 0;
+}
+
+static const struct panel_ops jd9365_panel_ops = {
+	.enable_backlight	= jd9365_panel_enable,
+	.get_display_timing	= jd9365_get_display_timing,
+};
+
+static const struct udevice_id panel_of_match[] = {
+	{
+		.compatible = "jadard,jd9365da-h3",
+		.data = (ulong)&jd9365_panel_desc,
+	},
+	{
+		/* sentinel */
+	}
+};
+
+U_BOOT_DRIVER(jadard_jd9365da) = {
+	.name 			  = "jadard_jd9365da",
+	.id			      = UCLASS_PANEL,
+	.of_match		  = panel_of_match,
+	.ops			  = &jd9365_panel_ops,
+	.ofdata_to_platdata	  = jd9365_panel_ofdata_to_platdata,
+	.probe			  = jadard_dsi_probe,
+	.remove			  = jadard_dsi_remove,
+	.platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto_alloc_size	  = sizeof(struct panel_info),
+};
+

include/abuf.h

@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Handles a buffer that can be allocated and freed
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __ABUF_H
+#define __ABUF_H
+
+#include <linux/types.h>
+
+/**
+ * struct abuf - buffer that can be allocated and freed
+ *
+ * This is useful for a block of data which may be allocated with malloc(), or
+ * not, so that it needs to be freed correctly when finished with.
+ *
+ * For now it has a very simple purpose.
+ *
+ * Using memset() to zero all fields is guaranteed to be equivalent to
+ * abuf_init().
+ *
+ * @data: Pointer to data
+ * @size: Size of data in bytes
+ * @alloced: true if allocated with malloc(), so must be freed after use
+ */
+struct abuf {
+	void *data;
+	size_t size;
+	bool alloced;
+};
+
+static inline void *abuf_data(const struct abuf *abuf)
+{
+	return abuf->data;
+}
+
+static inline size_t abuf_size(const struct abuf *abuf)
+{
+	return abuf->size;
+}
+
+/**
+ * abuf_set() - set the (unallocated) data in a buffer
+ *
+ * This simply makes the abuf point to the supplied data, which must be live
+ * for the lifetime of the abuf. It is not alloced.
+ *
+ * Any existing data in the abuf is freed and the alloced member is set to
+ * false.
+ *
+ * @abuf: abuf to adjust
+ * @data: New contents of abuf
+ * @size: New size of abuf
+ */
+void abuf_set(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_map_sysmem() - calls map_sysmem() to set up an abuf
+ *
+ * This is equivalent to abuf_set(abuf, map_sysmem(addr, size), size)
+ *
+ * Any existing data in the abuf is freed and the alloced member is set to
+ * false.
+ *
+ * @abuf: abuf to adjust
+ * @addr: Address to set the abuf to
+ * @size: New size of abuf
+ */
+void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size);
+
+/**
+ * abuf_realloc() - Change the size of a buffer
+ *
+ * This uses realloc() to change the size of the buffer, with the same semantics
+ * as that function. If the abuf is not currently alloced, then it will alloc
+ * it if the size needs to increase (i.e. set the alloced member to true)
+ *
+ * @abuf: abuf to adjust
+ * @new_size: new size in bytes.
+ *	if 0, the abuf is freed
+ *	if greater than the current size, the abuf is extended and the new
+ *	   space is not inited. The alloced member is set to true
+ *	if less than the current size, the abuf is contracted and the data at
+ *	   the end is lost. If @new_size is 0, this sets the alloced member to
+ *	   false
+ * Return: true if OK, false if out of memory
+ */
+bool abuf_realloc(struct abuf *abuf, size_t new_size);
+
+/**
+ * abuf_uninit_move() - Return the allocated contents and uninit the abuf
+ *
+ * This returns the abuf data to the caller, allocating it if necessary, so that
+ * the caller receives data that it can be sure will hang around. The caller is
+ * responsible for freeing the data.
+ *
+ * If the abuf has allocated data, it is returned. If the abuf has data but it
+ * is not allocated, then it is first allocated, then returned.
+ *
+ * If the abuf size is 0, this returns NULL
+ *
+ * The abuf is uninited as part of this, except if the allocation fails, in
+ * which NULL is returned and the abuf remains untouched.
+ *
+ * The abuf must be inited before this can be called.
+ *
+ * @abuf: abuf to uninit
+ * @sizep: if non-NULL, returns the size of the returned data
+ * Return: data contents, allocated with malloc(), or NULL if the data could not
+ *	be allocated, or the data size is 0
+ */
+void *abuf_uninit_move(struct abuf *abuf, size_t *sizep);
+
+/**
+ * abuf_init_move() - Make abuf take over the management of an allocated region
+ *
+ * After this, @data must not be used. All access must be via the abuf.
+ *
+ * @abuf: abuf to init
+ * @data: Existing allocated buffer to place in the abuf
+ * @size: Size of allocated buffer
+ */
+void abuf_init_move(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_init_set() - Set up a new abuf
+ *
+ * Inits a new abuf and sets up its (unallocated) data
+ *
+ * @abuf: abuf to set up
+ * @data: New contents of abuf
+ * @size: New size of abuf
+ */
+void abuf_init_set(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_uninit() - Free any memory used by an abuf
+ *
+ * The buffer must be inited before this can be called.
+ *
+ * @abuf: abuf to uninit
+ */
+void abuf_uninit(struct abuf *abuf);
+
+/**
+ * abuf_init() - Set up a new abuf
+ *
+ * This initially has no data and alloced is set to false. This is equivalent to
+ * setting all fields to 0, e.g. with memset(), so callers can do that instead
+ * if desired.
+ *
+ * @abuf: abuf to set up
+ */
+void abuf_init(struct abuf *abuf);
+
+#endif

include/android_image.h

@@ -136,4 +136,18 @@ struct andr_img_hdr {
  *    else: jump to kernel_addr
  */
 
+#define VENDOR_RAMDISK_NAME_SIZE 32
+#define VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE 16
+
+#define VENDOR_RAMDISK_TYPE_RECOVERY 2
+struct vendor_ramdisk_table_entry {
+    u32 ramdisk_size; /* size in bytes for the ramdisk image */
+    u32 ramdisk_offset; /* offset to the ramdisk image in vendor ramdisk section */
+    u32 ramdisk_type; /* type of the ramdisk */
+    u8 ramdisk_name[VENDOR_RAMDISK_NAME_SIZE]; /* asciiz ramdisk name */
+
+    // Hardware identifiers describing the board, soc or platform which this
+    // ramdisk is intended to be loaded on.
+    u32 board_id[VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE];
+} __attribute__((packed));
 #endif

include/asm/arch

@@ -0,0 +1 @@
+/home/cxx194832/ssd/u-boot/arch/riscv/include/asm/arch-c9xx

include/configs/light-c910.h

@@ -22,19 +22,30 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR     (CONFIG_SYS_TEXT_BASE + SZ_1M)
 #define CONFIG_SYS_LOAD_ADDR        (CONFIG_SYS_TEXT_BASE + SZ_1M)
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_SYS_MALLOC_LEN       (64*SZ_1M)
+#else
 #define CONFIG_SYS_MALLOC_LEN       SZ_1M
+#endif
 #define CONFIG_SYS_BOOTM_LEN        SZ_64M
 #define CONFIG_SYS_CACHELINE_SIZE   64
 
+#define CONFIG_CMD_READ 1
+
 #define SRAM_BASE_ADDR	 0xffe0000000
 #define PLIC_BASE_ADDR   0xffd8000000
 #define PMP_BASE_ADDR    0xffdc020000
 
+#define MINIMAL_DDR_DENSITY_MB (1*1024)
+#define MAXIMAL_DDR_DENSITY_MB (16*1024)
+#define UNIT_MB (1024*1024)
+
 /* Network Configuration */
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_RGMII            1
 #define CONFIG_PHY_MARVELL      1
 #define CONFIG_NET_RETRY_COUNT  20
+#define GMAC_USE_FIRST_MII_BUS
 
 #define CONFIG_SYS_FLASH_BASE       0x0
 #define CONFIG_SYS_MAX_FLASH_BANKS  1
@@ -57,25 +68,27 @@
 #define THEAD_LIGHT_FASTBOOT	1
 #define LIGHT_FW_ADDR		0x0
 #define LIGHT_KERNEL_ADDR	0x200000
-#define LIGHT_DTB_ADDR		0x1f00000
+#define LIGHT_DTB_ADDR		0x3800000
 #define LIGHT_ROOTFS_ADDR	0x2000000
 #define LIGHT_AON_FW_ADDR	0xffffef8000
 #define LIGHT_TEE_FW_ADDR	0x1c000000
 #define LIGHT_TF_FW_ADDR	LIGHT_FW_ADDR
 #define LIGHT_TF_FW_TMP_ADDR	0x100000
 #define LIGHT_KERNEL_ADDR_CMD	"0x200000"
-#define LIGHT_DTB_ADDR_CMD	"0x1f00000"
+#define LIGHT_DTB_ADDR_CMD	"0x3800000"
 
 
 /* trust image name string */
 #define TF_IMG_UPD_NAME		"stashtf"
 #define TEE_IMG_UPD_NAME	"stashtee"
 #define UBOOT_IMG_UPD_NAME	"stashuboot"
+#define SBMETA_IMG_UPD_NAME	"stashsbmeta"
 #define TF_PART_NAME		"tf"
 #define TEE_PART_NAME		"tee"
 #define UBOOT_PART_NAME		"uboot"
 #define STASH_PART_NAME 	"stash"
 #define KERNEL_PART_NAME	"kernel"
+#define SBMETA_PART_NAME	"sbmeta"
 
 #define UBOOT_STAGE_ADDR	SRAM_BASE_ADDR
 
@@ -90,6 +103,15 @@
 #define TF_SEC_UPGRADE_FLAG	0x5555aaaa
 #define TEE_SEC_UPGRADE_FLAG 0x5a5aa5a5
 #define UBOOT_SEC_UPGRADE_FLAG	0xa5a5aa55
+#define SBMETA_SEC_UPGRADE_FLAG 0xaaaa5555
+
+/* Define secure debug log level */
+#define LOG_LEVEL	1
+#if defined (LOG_LEVEL)
+#define SECLOG_PRINT	printf
+#else
+#define SECLOG_PRINT
+#endif
 
 #define UBOOT_MAX_VER		64
 #define CONFIG_SYS_CBSIZE 	512
@@ -100,96 +122,240 @@
 /* List of different env in debug/release version  */
 #if defined (U_BUILD_DEBUG)
 #define ENV_KERNEL_LOGLEVEL "kernel_loglevel=7\0"
-#define ENV_STR_BOOT_DELAY  
+#define ENV_STR_BOOT_DELAY
+#define CONFIG_ENV_OVERWRITE
+#define ENV_STR_SERIAL 		"serial#=1234567890\0"
+#define ENV_KERNEL_KDUMP	"kdump_buf=180M\0"
 #else
 #define ENV_KERNEL_LOGLEVEL "kernel_loglevel=4\0"
 #define ENV_STR_BOOT_DELAY	"bootdelay=0\0"
+#define ENV_STR_SERIAL 		"serial#=\0"
+#define ENV_KERNEL_KDUMP	"kdump_buf=0M\0"
 #endif
+/*public bootargs in mostly boards, make env 'set_booargs' shorter and clean */
+#define ENV_PUBLIC_BOOTARGS "pub_bootargs=rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused\0"
+
+/* Define board ID in ENV for firmware download protection */
+#if defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A) || \
+    defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || \
+    defined(CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
+#define ENV_STR_BOARD "board#=LA\0"
+#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B) || \
+      defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || \
+      defined(CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+#define ENV_STR_BOARD "board#=LB\0"
+#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A) || \
+      defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || \
+      defined(CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#define ENV_STR_BOARD "board#=LP\0"
+#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE) || \
+      defined(CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+#define ENV_STR_BOARD "board#=LG\0"
+#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF) || \
+      defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || \
+      defined(CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
+#define ENV_STR_BOARD "board#=LD\0"
+#endif
+
 
 #if defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
+    ENV_STR_BOARD \
 	"tf_addr=0x100000\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"tee_addr=0x1c000000\0" \
 	"sec_upgrade_mode=0\0"\
 	"mmcdev=0\0" \
-	"mmcpart=6\0" \
-	"kdump_buf=1M\0" \
+	"mmcpart=8\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"sbmeta_security_level=1\0" \
 	"uboot_version=0x0000000000000000\0"\
-	"fdt_file=light-a-val-sec.dtb\0" \
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
+	"sbmeta_version=0x00000000\0"\
+	"fdt_file=th1520-a-val-sec.dtb\0" \
 	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=sbmeta,size=8MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
-	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio;ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:3 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; run finduuid; run set_bootargs; sbmetaboot;run load_str;booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 
 #elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
+    ENV_STR_BOARD \
 	"tf_addr=0x100000\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"tee_addr=0x1c000000\0" \
 	"sec_upgrade_mode=0\0"\
 	"mmcdev=0\0" \
 	"mmcpart=6\0" \
-	"kdump_buf=1M\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"sbmeta_security_level=1\0" \
 	"uboot_version=0x0000000000000000\0"\
-	"fdt_file=light-b-product-sec.dtb\0" \
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
+	"sbmeta_version=0x00000000\0"\
+	"fdt_file=th1520-b-product-sec.dtb\0" \
 	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=sbmeta,size=8MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
-	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:3 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; sbmetaboot; run load_str;booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 
 #elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
+    ENV_STR_BOARD \
 	"tf_addr=0x100000\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"tee_addr=0x1c000000\0" \
 	"sec_upgrade_mode=0\0"\
 	"mmcdev=0\0" \
 	"mmcpart=6\0" \
-	"kdump_buf=1M\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"uboot_version=0x0000000000000000\0"\
-	"fdt_file=light-ant-ref-sec.dtb\0" \
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
+	"fdt_file=th1520-ant-ref-sec.dtb\0" \
 	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
-	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio;run load_str; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 
+#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+    ENV_STR_BOARD \
+	"tf_addr=0x100000\0" \
+	"dtb_addr=0x03800000\0" \
+	"kernel_addr=0x00200000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
+	"fwaddr=0x10000000\0"\
+	"tee_addr=0x1c000000\0" \
+	"sec_upgrade_mode=0\0"\
+	"mmcdev=0\0" \
+	"mmcpart=8\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"sbmeta_security_level=1\0" \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"uboot_version=0x0000000000000000\0"\
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
+	"sbmeta_version=0x00000000\0"\
+	"fdt_file=th1520-lpi4a-product-sec.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=sbmeta,size=8MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio;ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:3 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; run finduuid; run set_bootargs; sbmetaboot; run load_str;booti $kernel_addr - $dtb_addr;\0" \
+        "\0"
+
+#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A) || defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B) || \
+      defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A) || defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE) || \
+      defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	ENV_STR_SERIAL \
+	ENV_STR_BOARD \
+	"tf_addr=0x0\0" \
+	"tee_addr=0x1c000000\0" \
+	"opensbi_addr=0x0\0" \
+	"dtb_addr=0x03800000\0" \
+	"kernel_addr=0x00200000\0" \
+	"ramdisk_addr=0x02000000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"fwaddr=0x10000000\0"\
+	"boot_ab=_a\0"\
+	"sb_emulater=1\0"\
+	"mmcdev=0\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	"mmcteepart=8\0" \
+	ENV_KERNEL_LOGLEVEL \
+	ENV_KERNEL_KDUMP \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=light-val.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=sparse,size=2031kb;name=bootpart_a,size=16MiB;name=bootpart_b,size=16MiB;name=boot_a,size=32MiB;name=boot_b,size=32MiB;name=vendor_boot_a,size=32MiB;name=vendor_boot_b,size=32MiB;name=tee_a,size=32MiB;name=tee_b,size=32MiB;name=dtbo_a,size=8MiB;name=dtbo_b,size=8MiB;name=super,size=4096MiB;name=vbmeta_a,size=1MiB;name=vbmeta_b,size=1MiB;name=vbmeta_system_a,size=1MiB;name=vbmeta_system_b,size=1MiB;name=misc,size=2MiB;name=metadata,size=16MiB;name=userdata,size=-\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 earlycon clk_ignore_unused loop.max_part=7 loglevel=${kernel_loglevel} crashkernel=${kdump_buf} init=/init bootconfig video=HDMI-A-1:800x600-32@60 firmware_class.path=/vendor/firmware androidboot.serialno=${serial#}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"sec_m_load=ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin\0"\
+	"bootcmd_load=bootandroid;secimg_load;run sec_m_load;run load_aon;run load_c906_audio;fdt addr ${dtb_addr};fdt resize 100;fdt chosen;\0" \
+	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; bootm $kernel_addr $ramdisk_addr:$ramdisk_size $dtb_addr;\0" \
+         "\0"
+
 #else
 #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -197,25 +363,31 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
+    ENV_STR_BOARD \
 	"mmcdev=0\0" \
-	"mmcpart=3\0" \
-	"kdump_buf=1M\0" \
-	"fdt_file=light-a-product.dtb\0" \
+	"mmcpart=5\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=th1520-a-product.dtb\0" \
 	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
+	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
 	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:2 $opensbi_addr fw_dynamic.bin; ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc 0:2 $opensbi_addr fw_dynamic.bin; ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -223,30 +395,30 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
 	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=1M\0" \
+	"kdump_buf=180M\0" \
 	ENV_STR_BOOT_DELAY \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-b-product.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"fdt_file=th1520-b-product.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
-	"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
+	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -254,25 +426,29 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-b-ref.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=th1520-b-ref.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
 	"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
@@ -281,28 +457,30 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=1M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-b-power.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=th1520-b-power.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -310,28 +488,30 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=1M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-ant-ref.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=th1520-ant-ref.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -339,28 +519,30 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=1M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-ant-discrete.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=th1520-ant-discrete.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -368,28 +550,61 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=500M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-beagle.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=th1520-beagle.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+        "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"opensbi_addr=0x0\0" \
+	"dtb_addr=0x03800000\0" \
+	"kernel_addr=0x00200000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
+	"fwaddr=0x10000000\0"\
+	"mmcdev=0\0" \
+	"mmcpart=5\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=th1520-lpi4a-product.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -397,25 +612,29 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-a-ref.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=th1520-a-ref.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 #else
@@ -424,28 +643,30 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x03800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"str_ram_addr=0xffe0000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=500M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-a-val.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"mmcpart=5\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=th1520-a-val.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	ENV_PUBLIC_BOOTARGS \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
+	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 #endif
 #endif

include/dt-bindings/pmic/light_pmic.h

@@ -0,0 +1,55 @@
+#ifndef __LIGHT_PMIC_H_
+#define __LIGHT_PMIC_H_
+
+/*for da9063*/
+#define DA9063_ID_BCORE1   0
+#define DA9063_ID_BCORE2   1
+#define DA9063_ID_BUCKPRO  2
+#define DA9063_ID_BUCKMEM  3
+#define DA9063_ID_BUCKIO   4
+#define DA9063_ID_BUCKPERI 5
+#define DA9063_ID_LDO1     6
+#define DA9063_ID_LDO2     7
+#define DA9063_ID_LDO3     8
+#define DA9063_ID_LDO4     9
+#define DA9063_ID_LDO5     10
+#define DA9063_ID_LDO9     11
+#define DA9063_ID_LDO10    12
+#define DA9063_ID_LDO11    13
+#define DA9063_ID_LDO6     14
+#define DA9063_ID_LDO7     15
+#define DA9063_ID_LDO8     16
+#define DA9063_ID_GPIO4    17
+#define DA9063_ID_GPIO7    18
+
+/*for da9121*/
+#define DA9121_ID_BUCK1  0
+
+
+/* for slg51000*/
+
+#define SLG51000_ID_LDO1   0
+#define SLG51000_ID_LDO2   1
+#define SLG51000_ID_LDO3   2
+#define SLG51000_ID_LDO4   3
+#define SLG51000_ID_LDO5   4
+#define SLG51000_ID_LDO6   5
+#define SLG51000_ID_LDO7   6
+
+
+/* for ricoh567*/
+#define RICOH567_ID_DC1     0
+#define RICOH567_ID_DC2     1
+#define RICOH567_ID_DC3     2
+#define RICOH567_ID_DC4     3
+#define RICOH567_ID_LDO1    4
+#define RICOH567_ID_LDO2    5
+#define RICOH567_ID_LDO3    6
+#define RICOH567_ID_LDO4    7
+#define RICOH567_ID_LDO5    8
+#define RICOH567_ID_LDORTC1 9
+#define RICOH567_ID_LDORTC2 10
+#define RICOH567_ID_GPIO3   11
+
+
+#endif

include/env_flags.h

@@ -70,11 +70,18 @@ enum env_flags_varaccess {
 #define SERIAL_FLAGS ""
 #endif
 
+#ifndef CONFIG_ENV_OVERWRITE
+#define BOARD_FLAGS "board#:so,"
+#else
+#define BOARD_FLAGS ""
+#endif
+
 #define ENV_FLAGS_LIST_STATIC \
 	ETHADDR_FLAGS \
 	NET_FLAGS \
 	SERIAL_FLAGS \
-	CONFIG_ENV_FLAGS_LIST_STATIC
+	CONFIG_ENV_FLAGS_LIST_STATIC \
+	BOARD_FLAGS
 
 #ifdef CONFIG_CMD_ENV_FLAGS
 /*

include/fdt_support.h

@@ -10,6 +10,7 @@
 #ifdef CONFIG_OF_LIBFDT
 
 #include <linux/libfdt.h>
+#include <abuf.h>
 
 u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
 				const char *prop, const u32 dflt);
@@ -170,6 +171,18 @@ int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name);
  */
 int ft_board_setup(void *blob, bd_t *bd);
 
+/**
+ * board_rng_seed() - Provide a seed to be passed via /chosen/rng-seed
+ *
+ * This function is called if CONFIG_BOARD_RNG_SEED is set, and must
+ * be provided by the board. It should return, via @buf, some suitable
+ * seed value to pass to the kernel.
+ *
+ * @param buf         A struct abuf for returning the seed and its size.
+ * @return            0 if ok, negative on error.
+ */
+int board_rng_seed(struct abuf *buf);
+
 /*
  * The keystone2 SOC requires all 32 bit aliased addresses to be converted
  * to their 36 physical format. This has to happen after all fdt nodes

include/xbc.h

@@ -0,0 +1 @@
+#include <../lib/libxbc/libxbc.h>

lib/Kconfig

@@ -316,6 +316,20 @@ config LIBAVB
 
 endmenu
 
+menu "Boot Configuration"
+
+config XBC
+	bool "Boot Configuration support"
+	depends on ANDROID_BOOT_IMAGE
+	default n
+	help
+	  This enables support of Boot Configuration which can be used
+	  to pass boot configuration parameters to user space. These
+	  parameters will show up in /proc/bootconfig similar to the kernel
+	  parameters that show up in /proc/cmdline
+
+endmenu
+
 menu "Hashing Support"
 
 config SHA1

lib/Makefile

@@ -68,6 +68,8 @@ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
 
 obj-$(CONFIG_LIBAVB) += libavb/
 
+obj-$(CONFIG_XBC) += libxbc/
+
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
 ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
 obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o
@@ -119,6 +121,7 @@ else
 obj-y += vsprintf.o strto.o
 endif
 
+obj-y += abuf.o
 obj-y += date.o
 
 #

lib/abuf.c

@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Handles a buffer that can be allocated and freed
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef USE_HOSTCC
+#include <common.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <string.h>
+#endif
+
+#include <abuf.h>
+
+void abuf_set(struct abuf *abuf, void *data, size_t size)
+{
+	abuf_uninit(abuf);
+	abuf->data = data;
+	abuf->size = size;
+}
+
+#ifndef USE_HOSTCC
+void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size)
+{
+	abuf_set(abuf, map_sysmem(addr, size), size);
+}
+
+char *memdup(const void *src, size_t len);
+#else
+/* copied from lib/string.c for convenience */
+static char *memdup(const void *src, size_t len)
+{
+	char *p;
+
+	p = malloc(len);
+	if (!p)
+		return NULL;
+
+	memcpy(p, src, len);
+
+	return p;
+}
+#endif
+
+bool abuf_realloc(struct abuf *abuf, size_t new_size)
+{
+	void *ptr;
+
+	if (!new_size) {
+		/* easy case, just need to uninit, freeing any allocation */
+		abuf_uninit(abuf);
+		return true;
+	} else if (abuf->alloced) {
+		/* currently allocated, so need to reallocate */
+		ptr = realloc(abuf->data, new_size);
+		if (!ptr)
+			return false;
+		abuf->data = ptr;
+		abuf->size = new_size;
+		return true;
+	} else if (new_size <= abuf->size) {
+		/*
+		 * not currently alloced and new size is no larger. Just update
+		 * it. Data is lost off the end if new_size < abuf->size
+		 */
+		abuf->size = new_size;
+		return true;
+	} else {
+		/* not currently allocated and new size is larger. Alloc and
+		 * copy in data. The new space is not inited.
+		 */
+		ptr = malloc(new_size);
+		if (!ptr)
+			return false;
+		if (abuf->size)
+			memcpy(ptr, abuf->data, abuf->size);
+		abuf->data = ptr;
+		abuf->size = new_size;
+		abuf->alloced = true;
+		return true;
+	}
+}
+
+void *abuf_uninit_move(struct abuf *abuf, size_t *sizep)
+{
+	void *ptr;
+
+	if (sizep)
+		*sizep = abuf->size;
+	if (!abuf->size)
+		return NULL;
+	if (abuf->alloced) {
+		ptr = abuf->data;
+	} else {
+		ptr = memdup(abuf->data, abuf->size);
+		if (!ptr)
+			return NULL;
+	}
+	/* Clear everything out so there is no record of the data */
+	abuf_init(abuf);
+
+	return ptr;
+}
+
+void abuf_init_set(struct abuf *abuf, void *data, size_t size)
+{
+	abuf_init(abuf);
+	abuf_set(abuf, data, size);
+}
+
+void abuf_init_move(struct abuf *abuf, void *data, size_t size)
+{
+	abuf_init_set(abuf, data, size);
+	abuf->alloced = true;
+}
+
+void abuf_uninit(struct abuf *abuf)
+{
+	if (abuf->alloced)
+		free(abuf->data);
+	abuf_init(abuf);
+}
+
+void abuf_init(struct abuf *abuf)
+{
+	abuf->data = NULL;
+	abuf->size = 0;
+	abuf->alloced = false;
+}

lib/image-sparse.c

@@ -52,10 +52,10 @@ int write_sparse_image(struct sparse_storage *info,
 	lbaint_t blk;
 	lbaint_t blkcnt;
 	lbaint_t blks;
-	uint32_t bytes_written = 0;
+	uint64_t bytes_written = 0;
 	unsigned int chunk;
 	unsigned int offset;
-	unsigned int chunk_data_sz;
+	uint64_t chunk_data_sz;
 	uint32_t *fill_buf = NULL;
 	uint32_t fill_val;
 	sparse_header_t *sparse_header;
@@ -129,8 +129,8 @@ int write_sparse_image(struct sparse_storage *info,
 				 sizeof(chunk_header_t));
 		}
 
-		chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
-		blkcnt = chunk_data_sz / info->blksz;
+		chunk_data_sz = ((u64)sparse_header->blk_sz) * chunk_header->chunk_sz;
+		blkcnt = DIV_ROUND_UP_ULL(chunk_data_sz, info->blksz);
 		switch (chunk_header->chunk_type) {
 		case CHUNK_TYPE_RAW:
 			if (chunk_header->total_sz !=
@@ -159,7 +159,7 @@ int write_sparse_image(struct sparse_storage *info,
 				return -1;
 			}
 			blk += blks;
-			bytes_written += blkcnt * info->blksz;
+			bytes_written += ((u64)blkcnt) * info->blksz;
 			total_blocks += chunk_header->chunk_sz;
 			data += chunk_data_sz;
 			break;
@@ -219,8 +219,9 @@ int write_sparse_image(struct sparse_storage *info,
 				blk += blks;
 				i += j;
 			}
-			bytes_written += blkcnt * info->blksz;
-			total_blocks += chunk_data_sz / sparse_header->blk_sz;
+			bytes_written += ((u64)blkcnt) * info->blksz;
+			total_blocks += DIV_ROUND_UP_ULL(chunk_data_sz,
+							 sparse_header->blk_sz);
 			free(fill_buf);
 			break;
 
@@ -250,7 +251,7 @@ int write_sparse_image(struct sparse_storage *info,
 
 	debug("Wrote %d blocks, expected to write %d blocks\n",
 	      total_blocks, sparse_header->total_blks);
-	printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name);
+	printf("........ wrote %llu bytes to '%s'\n", bytes_written, part_name);
 
 	if (total_blocks != sparse_header->total_blks) {
 		info->mssg("sparse image write failure", response);

lib/libavb/avb_rsa.c

@@ -13,6 +13,10 @@
 #include "avb_util.h"
 #include "avb_vbmeta_image.h"
 
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+#include "sec_library.h"
+#endif
+
 typedef struct IAvbKey {
   unsigned int len; /* Length of n[] in number of uint32_t */
   uint32_t n0inv;   /* -1 / n[0] mod 2^32 */
@@ -82,7 +86,19 @@ fail:
 static void iavb_free_parsed_key(IAvbKey* key) {
   avb_free(key);
 }
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
 
+static void hw_crypto_accel_init(void)
+{
+	static bool init = false;
+
+	if (!init) {
+		rambus_crypto_init();
+		init = true;
+	}
+}
+
+#else
 /* a[] -= mod */
 static void subM(const IAvbKey* key, uint32_t* a) {
   int64_t A = 0;
@@ -200,7 +216,7 @@ out:
     avb_free(aaR);
   }
 }
-
+#endif
 /* Verify a RSA PKCS1.5 signature against an expected hash.
  * Returns false on failure, true on success.
  */
@@ -212,6 +228,83 @@ bool avb_rsa_verify(const uint8_t* key,
                     size_t hash_num_bytes,
                     const uint8_t* padding,
                     size_t padding_num_bytes) {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  IAvbKey* parsed_key = NULL;
+  uint8_t *nk = NULL;
+  uint8_t *n = NULL;
+  uint8_t *e = NULL;
+  int i;
+  bool success = false;
+  uint32_t key_bytes = 0;
+  sc_rsa_t  rsa;
+  sc_rsa_context_t rsa_ctx;
+
+  if (key == NULL || sig == NULL || hash == NULL || padding == NULL) {
+    avb_error("Invalid input.\n");
+    goto out;
+  }
+
+  parsed_key = iavb_parse_key_data(key, key_num_bytes);
+  if (parsed_key == NULL) {
+    avb_error("Error parsing key.\n");
+    goto out;
+  }
+  
+  if (padding_num_bytes != sig_num_bytes - hash_num_bytes) {
+    avb_error("Padding length does not match hash and signature lengths.\n");
+    goto out;
+  }
+
+  key_bytes = parsed_key->len * sizeof(uint32_t);
+  /* Currently, we only support RSA key 2048bits and SHA256 */
+  if ((key_bytes * 8 != 2048) || (hash_num_bytes * 8 != 256)) {
+    avb_error("Error unsupported keybits length.\n");
+    goto out;
+  }
+
+  nk = (uint8_t *)parsed_key->n;
+  n = avb_malloc(key_bytes);
+  if (n == NULL) {
+    avb_error("Error malloc n.\n");
+    goto out;
+  }
+  /* Reverse modular little endian */
+  for (i = 0; i < key_bytes; i++) {
+    n[i] = nk[key_bytes - i - 1];
+  }
+
+  e = avb_malloc(key_bytes);
+  if (e == NULL) {
+    avb_error("Error malloc e.\n");
+    goto out;
+  }
+  memset(e, 0, key_bytes);
+  /* public exponentiation. (65537} */
+  e[key_bytes-1] = 0x01; e[key_bytes-2] = 0x00; e[key_bytes-3] = 0x01; e[key_bytes-4] = 0x00;
+
+  hw_crypto_accel_init();
+  sc_rsa_init(&rsa, 0, SC_RSA_KEY_BITS_2048);
+
+  rsa_ctx.padding_type = SC_RSA_PADDING_MODE_PKCS1;
+  rsa_ctx.n = n;
+  rsa_ctx.e = e;
+  rsa_ctx.hash_type = SC_RSA_HASH_TYPE_SHA256;
+  rsa_ctx.is_crt = SC_RSA_CRT_DISABLE;
+  rsa_ctx.is_hash = SC_RSA_HASH_DISABLE;
+
+  success = sc_rsa_verify(&rsa, &rsa_ctx, (void *)hash, hash_num_bytes, (void *)sig, sig_num_bytes, SC_RSA_HASH_TYPE_SHA256);
+  sc_rsa_uninit(&rsa);
+
+out:
+  if (parsed_key != NULL) {
+    iavb_free_parsed_key(parsed_key);
+  }
+  if (e != NULL) {
+    avb_free(e);
+  }
+
+  return success;
+#else
   uint8_t* buf = NULL;
   IAvbKey* parsed_key = NULL;
   bool success = false;
@@ -272,4 +365,5 @@ out:
     avb_free(buf);
   }
   return success;
+#endif
 }