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base: t-head:Linux_SDK_V1.0.2
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t-head:th1520 t-head:thead-sdk t-head:huiwei t-head:downclock-sd t-head:develop t-head:master
t-head:20260504 t-head:20251124 t-head:20250930 t-head:20250813 t-head:20250110 t-head:20241223 t-head:Linux_SDK_V2.0.2 t-head:20240720 t-head:20240529 t-head:Linux_SDK_V1.5.4 t-head:20240328 t-head:20240324 t-head:20240131 t-head:20240127 t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5
...
compare: t-head:Linux_SDK_V1.4.2
Branches Tags
t-head:th1520 t-head:thead-sdk t-head:huiwei t-head:downclock-sd t-head:develop t-head:master
t-head:20260504 t-head:20251124 t-head:20250930 t-head:20250813 t-head:20250110 t-head:20241223 t-head:Linux_SDK_V2.0.2 t-head:20240720 t-head:20240529 t-head:Linux_SDK_V1.5.4 t-head:20240328 t-head:20240324 t-head:20240131 t-head:20240127 t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5

7 Commits
Linux_SDK_ ... Linux_SDK_

Author SHA1 Message Date
thead_admin
ba628b63b3 Linux_SDK_V1.4.2 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-12-24 19:20:14 +08:00
thead_admin
60c2e85ba7 Linux_SDK_V1.3.3 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-12-24 19:19:50 +08:00
thead_admin
e14a461444 Linux_SDK_V1.2.1 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-08-19 00:09:12 +08:00
thead_admin
6c027f3c8e fix ftbfs 2023-07-30 03:40:57 +08:00
Han Gao
644f3eb8ff Linux_SDK_V1.2.0 2023-07-30 03:39:06 +08:00
thead_admin
51a2c4f060 Linux_SDK_V1.1.2 2023-03-05 22:36:05 +08:00
thead_admin
02deb8b059 Linux_SDK_V1.0.3 2023-01-04 13:12:02 +08:00
156 changed files with 40808 additions and 750 deletions
Expand all files Collapse all files

2
Kconfig
View File

@@ -302,7 +302,7 @@ menu "Boot images"
config ANDROID_BOOT_IMAGE
bool "Enable support for Android Boot Images"
default y if FASTBOOT
default n if FASTBOOT
help
This enables support for booting images which use the Android
image format header.

5
Makefile
View File

@@ -219,7 +219,7 @@ endif
ifeq ($(KBUILD_SRC),)
# building in the source tree
srctree := .
srctree := $(shell pwd)
else
ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR)))
# building in a subdirectory of the source tree
@@ -726,6 +726,7 @@ UBOOTINCLUDE := \
$(if $(CONFIG_HAS_THUMB2),, \
-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
-I$(srctree)/arch/$(ARCH)/include \
$(if $(CONFIG_TARGET_LIGHT_C910), -I$(srctree)/lib/sec_library/include) \
-include $(srctree)/include/linux/kconfig.h
NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
@@ -811,7 +812,7 @@ PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`
endif
PLATFORM_LIBS += $(PLATFORM_LIBGCC)
ifeq ($(CONFIG_TARGET_LIGHT_C910),y)
PLATFORM_LIBS += -L $(shell pwd)/lib/sec_library -lsec_library
PLATFORM_LIBS += -L $(srctree)/lib/sec_library -lsec_library
endif
ifdef CONFIG_CC_COVERAGE

1
arch/riscv/cpu/c9xx/Makefile
View File

@@ -6,3 +6,4 @@
obj-y += dram.o
obj-y += cpu.o
obj-y += feature.o

5
arch/riscv/cpu/c9xx/cpu.c
View File

@@ -141,8 +141,9 @@ void dcache_enable(void)
#ifdef CONFIG_SPL_RISCV_MMODE
#ifdef CONFIG_TARGET_LIGHT_C910
asm volatile (
"li x29, 0x11ff\n\t"
"csrw mhcr, x29\n\t"
"csrr x29, mhcr\n\t"
"ori x28, x29, 0x2\n\t"
"csrw mhcr, x28\n\t"
);
#endif
#endif

114
arch/riscv/cpu/c9xx/feature.c Normal file
View File

@@ -0,0 +1,114 @@
#include <common.h>
#include <asm/types.h>
#include <asm/asm.h>
#include <asm/csr.h>
void setup_features(void)
{
unsigned int i, cpu_type, cpu_ver;
unsigned long version[8];
for (i = 0; i < 8; i++)
version[i] = csr_read(CSR_MCPUID);
cpu_type = (version[0] >> 18) & 0xf;
cpu_ver = (version[1] >> 12) & 0xffff;
/*
* Warning: CSR_MCCR2 contains an L2 cache latency setting,
* you need to confirm it by your own soc design.
*/
switch (cpu_type) {
case 0x3:
if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) { //1.2.0~1.2.x
csr_write(CSR_MCCR2, 0xe0010009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x6e30c);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver == 0x10ca) { //1.3.10
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x66e30c);
csr_write(CSR_MHCR, 0x17f);
csr_write(CSR_MHINT2, 0x420000);
csr_write(CSR_MHINT4, 0x410);
} else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) { //1.4.0~1.4.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x16e30c);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) { //1.5.0~1.5.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0xe6e30c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) { //1.6.0~1.6.3
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x1ee30c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) { //1.6.4~1.8.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x1ee30c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
} else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) { //2.0.0~
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x31ea32c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
} else {
while(1);
}
break;
case 0x4:
if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) {
csr_write(CSR_MHCR, 0x17f);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x650c);
} else {
while(1);
}
break;
case 0x5:
if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) { //0.0.0~0.0.7
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe0420008);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x2c50c);
csr_write(CSR_MHCR, 0x11ff);
} else if (cpu_ver >= 0x0040 && cpu_ver <= 0xffff) { //0.1.0~
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xa042000a);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x21aa10c);
csr_write(CSR_MHCR, 0x10011ff);
} else {
while(1);
}
break;
case 0x6:
if (cpu_ver >= 0x0) {
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xA042000A);
csr_write(CSR_MXSTATUS, 0x638001);
csr_write(CSR_MHINT, 0x3A1AA10C);
csr_write(CSR_MHCR, 0x10011BF);
} else {
while(1);
}
break;
default:
while(1);
}
}

42
arch/riscv/cpu/mtrap.S
View File

@@ -104,3 +104,45 @@ trap_entry:
LREG x2, 2 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
MODE_PREFIX(ret)
/* trap secondary_entry */
.align 10
.global secondary_entry
secondary_entry:
/*
* Clear L1 cache & BTB & BHT ...
*/
li t0, 0x70013
csrw CSR_MCOR, t0
/*
* Enable cache coherency
*/
li t0, 1
csrw CSR_MSMPR, t0
/*
*Prepare percpu stack
*/
csrr t0, mhartid
li t1, 0x100
mul t1, t1, t0
lla sp, stacks
add sp, sp, t1
/*
* Call C routine
*/
call setup_features
call next_stage
/*
* Never get here, dead loop
*/
j .
.align 10
stacks:
.rept 0x1000
.long
.endr

6
arch/riscv/cpu/start.S
View File

@@ -41,6 +41,12 @@ secondary_harts_relocation_error:
_start:
#if (defined CONFIG_SPL_BUILD) && (defined CONFIG_TARGET_LIGHT_C910)
/* Disable indirect branch prediction once entering into uboot world */
li t0, 0x117f
csrw 0x7c1, t0
/* Disable fence broadcase and HW TLB */
li t0, 0x66e30c
csrw 0x7c5, t0
/* Enable cache ASAP as LIGHT's requirement */
jal icache_enable
jal dcache_enable

2
arch/riscv/dts/Makefile
View File

@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb
dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb
targets += $(dtb-y)

4
arch/riscv/dts/light-a-val.dts
View File

@@ -306,8 +306,8 @@
spi-max-frequency = <100000000>;
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
tpm@0{
compatible = "z32h330tc,z32h330tc-spi";
reg = <0>;
spi-max-frequency = <40000000>;
};

488
arch/riscv/dts/light-lpi4a.dts Normal file
View File

@@ -0,0 +1,488 @@
/dts-v1/;
/ {
model = "T-HEAD c910 light";
compatible = "thead,c910_light";
#address-cells = <2>;
#size-cells = <2>;
memory@0 {
device_type = "memory";
reg = <0x0 0xc0000000 0x0 0x40000000>;
};
aliases {
spi0 = &spi0;
spi1 = &qspi0;
spi2 = &qspi1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <3000000>;
u-boot,dm-pre-reloc;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
u-boot,dm-pre-reloc;
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
u-boot,dm-pre-reloc;
intc: interrupt-controller@ffd8000000 {
compatible = "riscv,plic0";
reg = <0xff 0xd8000000 0x0 0x04000000>;
status = "disabled";
};
dummy_apb: apb-clock {
compatible = "fixed-clock";
clock-frequency = <62500000>;
clock-output-names = "dummy_apb";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_ahb: ahb-clock {
compatible = "fixed-clock";
clock-frequency = <250000000>;
clock-output-names = "core";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_spi: spi-clock {
compatible = "fixed-clock";
clock-frequency = <396000000>;
clock-output-names = "dummy_spi";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_qspi0: qspi0-clock {
compatible = "fixed-clock";
clock-frequency = <792000000>;
clock-output-names = "dummy_qspi0";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_uart_sclk: uart-sclk-clock {
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "dummy_uart_sclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_i2c_icclk: i2c-icclk-clock {
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "dummy_i2c_icclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_dpu_pixclk: dpu-pix-clock {
compatible = "fixed-clock";
clock-frequency = <74250000>;
clock-output-names = "dummy_dpu_pixclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_dphy_refclk: dphy-ref-clock {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "dummy_dpu_refclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
i2c0: i2c@ffe7f20000 {
compatible = "snps,designware-i2c";
reg = <0xff 0xe7f20000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@ffe7f24000{
compatible = "snps,designware-i2c";
reg = <0xff 0xe7f24000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@ffec00c000{
compatible = "snps,designware-i2c";
reg = <0xff 0xec00c000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@ffec014000{
compatible = "snps,designware-i2c";
reg = <0xff 0xec014000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c4: i2c@ffe7f28000{
compatible = "snps,designware-i2c";
reg = <0xff 0xe7f28000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
pcal6408ahk_a: gpio@20 {
compatible = "nxp,pca9554";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c5: i2c@fff7f2c000{
compatible = "snps,designware-i2c";
reg = <0xff 0xf7f2c000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
};
serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x400>;
clocks = <&dummy_uart_sclk>;
clock-frequency = <100000000>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
u-boot,dm-pre-reloc;
};
gmac0: ethernet@ffe7070000 {
compatible = "snps,dwmac";
reg = <0xff 0xe7070000 0x0 0x2000>;
clocks = <&dummy_apb>;
clock-names = "stmmaceth";
snps,pbl = <32>;
snps,fixed-burst;
phy-mode = "rgmii-id";
phy-handle = <&phy_88E1111_a>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_a: ethernet-phy@1 {
reg = <0x1>;
};
phy_88E1111_b: ethernet-phy@2 {
reg = <0x2>;
};
};
};
gmac1: ethernet@ffe7060000 {
compatible = "snps,dwmac";
reg = <0xff 0xe7060000 0x0 0x2000>;
clocks = <&dummy_apb>;
clock-names = "stmmaceth";
snps,pbl = <32>;
snps,fixed-burst;
phy-mode = "rgmii-id";
phy-handle = <&phy_88E1111_b>;
status = "okay";
};
emmc: sdhci@ffe7080000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7080000 0x0 0x10000>;
index = <0x0>;
clocks = <&dummy_ahb>;
clock-frequency = <198000000>;
clock-names = "core";
max-frequency = <198000000>;
sdhci-caps-mask = <0x0 0x1000000>;
mmc-hs400-1_8v;
non-removable;
no-sdio;
no-sd;
bus-width = <8>;
voltage= "1.8v";
pull_up;
io_fixed_1v8;
fifo-mode;
u-boot,dm-pre-reloc;
};
sdhci0: sd@ffe7090000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7090000 0x0 0x10000>;
index = <0x1>;
clocks = <&dummy_ahb>;
clock-frequency = <198000000>;
max-frequency = <198000000>;
sd-uhs-sdr104;
pull_up;
clock-names = "core";
bus-width = <4>;
voltage= "3.3v";
};
qspi0: spi@ffea000000 {
compatible = "snps,dw-apb-ssi-quad";
reg = <0xff 0xea000000 0x0 0x1000>;
clocks = <&dummy_qspi0>;
num-cs = <1>;
cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
spi-max-frequency = <100000000>;
#address-cells = <1>;
#size-cells =<0>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
};
qspi1: spi@fff8000000 {
compatible = "snps,dw-apb-ssi-quad";
reg = <0xff 0xf8000000 0x0 0x1000>;
clocks = <&dummy_spi>;
num-cs = <1>;
cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
spi-max-frequency = <66000000>;
#address-cells = <1>;
#size-cells =<0>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
};
spi0: spi@ffe700c000 {
compatible = "snps,dw-apb-ssi";
reg = <0xff 0xe700c000 0x0 0x1000>;
clocks = <&dummy_spi>;
cs-gpio = <&gpio2_porta 15 0>;
spi-max-frequency = <100000000>;
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
gpio2: gpio@ffe7f34000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f34000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio2_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio0: gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio0_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio1: gpio@ffec006000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec006000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio1_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
pwm: pwm@ffec01c000 {
compatible = "thead,pwm-light";
reg = <0xff 0xec01c000 0x0 0x4000>;
#pwm-cells = <2>;
};
dsi_regs: dsi-controller@ffef500000 {
compatible = "thead,light-dsi-regs", "syscon";
reg = <0xff 0xef500000 0x0 0x10000>;
status = "okay";
};
vosys_regs: vosys@ffef528000 {
compatible = "thead,light-vo-subsys", "syscon";
reg = <0xff 0xef528000 0x0 0x1000>;
status = "okay";
};
dpu: dc8200@ffef600000 {
compatible = "verisilicon,dc8200";
reg = <0xff 0xef600000 0x0 0x100>;
};
axiscr {
compatible = "thead,axiscr";
reg = <0xff 0xff004000 0x0 0x1000>;
lock-read = "okay";
lock-write = "okay";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
axiscr0: axisrc@0 {
device_type = "axiscr";
region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
axiscr1: axisrc@1 {
device_type = "axiscr";
region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
axiscr2: axisrc@2 {
device_type = "axiscr";
region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
};
axiparity {
compatible = "thead,axiparity";
reg = <0xff 0xff00c000 0x0 0x1000>;
lock = "okay";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
axiparity0: axiparity@0 {
device_type = "axiparity";
region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
axiparity1: axiparity@1 {
device_type = "axiparity";
region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
};
dsi_bridge: dsi-bridge {
compatible = "thead,light-dsi-bridge";
clocks = <&dummy_dpu_pixclk>;
clock-names = "pix-clk";
phys = <&dsi_dphy>;
phy-names = "dphy";
};
dsi_host: dsi-host {
compatible = "synopsys,dw-mipi-dsi";
regmap = <&dsi_regs>;
status = "okay";
};
dsi_dphy: dsi-dphy {
compatible = "synopsys,dw-dphy";
regmap = <&dsi_regs>;
vosys-regmap = <&vosys_regs>;
clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
clock-names = "pix-clk", "ref-clk";
#phy-cells = <0>;
status = "okay";
};
lcd_backlight: pwm-backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
ili9881c_panel {
compatible = "ilitek,ili9881c";
backlight = <&lcd_backlight>;
reset-gpios = <&gpio1_porta 5 1>; /* active low */
lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
};
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "/soc/serial@ffe7014000:115200";
};
};

4
arch/riscv/include/asm/arch-thead/boot_mode.h
View File

@@ -34,7 +34,9 @@ typedef enum image_type {
T_ROOTFS = 4,
T_TF = 2,
T_TEE = 5,
T_UBOOT = 6
T_UBOOT = 6,
T_USER = 7,
T_SBMETA = 8,
} img_type_t;
static const char header_magic[4] = {'T', 'H', 'E', 'D'};

17
arch/riscv/include/asm/arch-thead/light-reset.h Normal file
View File

@@ -0,0 +1,17 @@
#ifndef __LIGHT_RESET_H__
#define __LIGHT_RESET_H__
#define APSYS_RSTGEN_BASE 0xFFEF014000
#define REG_C910_SWRST (APSYS_RSTGEN_BASE + 0x4)
#define APSYS_REG_BASE 0xFFEF018000
#define REG_C910_CORE0_RVBA_L (APSYS_REG_BASE + 0x50)
#define REG_C910_CORE0_RVBA_H (APSYS_REG_BASE + 0x54)
#define REG_C910_CORE1_RVBA_L (APSYS_REG_BASE + 0x58)
#define REG_C910_CORE1_RVBA_H (APSYS_REG_BASE + 0x5C)
#define REG_C910_CORE2_RVBA_L (APSYS_REG_BASE + 0x60)
#define REG_C910_CORE2_RVBA_H (APSYS_REG_BASE + 0x64)
#define REG_C910_CORE3_RVBA_L (APSYS_REG_BASE + 0x68)
#define REG_C910_CORE3_RVBA_H (APSYS_REG_BASE + 0x6C)
#define REG_PLIC_DELEGATE 0xffd81ffffc
#endif /* __LIGHT_RESET_H__ */

53
arch/riscv/include/asm/atomic.h Normal file
View File

@@ -0,0 +1,53 @@
#ifndef _ASM_RISCV_ATOMIC_H
#define _ASM_RISCV_ATOMIC_H
#include <linux/types.h>
#include <asm/barrier.h>
typedef struct {
volatile long counter;
} atomic_t;
#define ATOMIC_INIT(_lptr, val) (_lptr)->counter = (val)
#define ATOMIC_INITIALIZER(val) \
{ \
.counter = (val), \
}
long atomic_read(atomic_t *atom)
{
long ret = atom->counter;
rmb();
return ret;
}
void atomic_write(atomic_t *atom, long value)
{
atom->counter = value;
wmb();
}
long atomic_add_return(atomic_t *atom, long value)
{
long ret;
#if __SIZEOF_LONG__ == 4
__asm__ __volatile__(" amoadd.w.aqrl %1, %2, %0"
: "+A"(atom->counter), "=r"(ret)
: "r"(value)
: "memory");
#elif __SIZEOF_LONG__ == 8
__asm__ __volatile__(" amoadd.d.aqrl %1, %2, %0"
: "+A"(atom->counter), "=r"(ret)
: "r"(value)
: "memory");
#endif
return ret + value;
}
long atomic_sub_return(atomic_t *atom, long value)
{
return atomic_add_return(atom, -value);
}
#endif /* _ASM_RISCV_ATOMIC_H */

12
arch/riscv/include/asm/csr.h
View File

@@ -104,15 +104,23 @@
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
#define CSR_MVENDORID 0xf11
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
#define CSR_MCPUID 0xfc0
#define CSR_SMPEN 0x7f3
#define CSR_MTEE 0x7f4
#define CSR_SMPEN 0x7f3
#define CSR_MTEE 0x7f4
#define CSR_MCOR 0x7c2
#define CSR_MHCR 0x7c1
#define CSR_MCCR2 0x7c3
#define CSR_MHINT 0x7c5
#define CSR_MHINT2 0x7cc
#define CSR_MHINT3 0x7cd
#define CSR_MHINT4 0x7ce
#define CSR_MXSTATUS 0x7c0
#define CSR_MSMPR 0x7f3
#define CSR_PLIC_BASE 0xfc1
#define sync_is() asm volatile (".long 0x01b0000b")

1
arch/riscv/include/asm/dma-mapping.h
View File

@@ -10,6 +10,7 @@
#define __ASM_RISCV_DMA_MAPPING_H
#include <linux/dma-direction.h>
#include "common.h"
#define dma_mapping_error(x, y) 0

87
arch/riscv/lib/bootm.c
View File

@@ -14,7 +14,11 @@
#include <opensbi.h>
#include <asm/byteorder.h>
#include <asm/csr.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/barrier.h>
#include <asm/atomic.h>
#include <asm/arch-thead/light-reset.h>
#include <dm/device.h>
#include <dm/root.h>
#include <u-boot/zlib.h>
@@ -22,6 +26,12 @@
DECLARE_GLOBAL_DATA_PTR;
static struct fw_dynamic_info opensbi_info;
static atomic_t _harts_count = ATOMIC_INITIALIZER(3);
static ulong _load_start;
static ulong _dtb_addr;
static ulong _dyn_info_addr;
extern void secondary_entry();
__weak void board_quiesce_devices(void)
{
@@ -81,6 +91,58 @@ static void boot_prep_linux(bootm_headers_t *images)
}
}
void next_stage(void)
{
void (*next_entry)(unsigned long arg0,unsigned long arg1,unsigned long arg2);
next_entry = (void (*))(_load_start);
ulong hartid = csr_read(CSR_MHARTID);
atomic_sub_return(&_harts_count, 1);
/*
* set $a0 = hartid
* set $a1 = $dtb_addr
* set $a2 = $dyn_info_addr
*/
next_entry(hartid, _dtb_addr , _dyn_info_addr);
}
bool has_reset_sample(ulong dtb_addr)
{
int node_offset;
node_offset = fdt_path_offset(dtb_addr, "/soc/reset-sample");
if (node_offset < 0) {
printf("## fdt has no reset_sample\n");
return false;
} else {
printf("## fdt has reset_sample\n");
return true;
}
}
static void reset_sample(void)
{
ulong addr;
uint addr_l, addr_h;
// RESET ADDR
addr = (unsigned long)(void *)secondary_entry;
addr_h = (uint)(addr >> 32);
addr_l = (uint)(addr & 0xFFFFFFFF);
// writel(addr_h, (volatile void *)REG_C910_CORE0_RVBA_H);
// writel(addr_l, (volatile void *)REG_C910_CORE0_RVBA_L);
writel(addr_h, (volatile void *)REG_C910_CORE1_RVBA_H);
writel(addr_l, (volatile void *)REG_C910_CORE1_RVBA_L);
writel(addr_h, (volatile void *)REG_C910_CORE2_RVBA_H);
writel(addr_l, (volatile void *)REG_C910_CORE2_RVBA_L);
writel(addr_h, (volatile void *)REG_C910_CORE3_RVBA_H);
writel(addr_l, (volatile void *)REG_C910_CORE3_RVBA_L);
// RESET
writel(0x1F, (volatile void *)REG_C910_SWRST);
writel(0x1, (volatile void *)REG_PLIC_DELEGATE);
}
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
void (*kernel)(ulong hart, void *dtb, struct fw_dynamic_info *p);
@@ -98,12 +160,25 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
announce_and_cleanup(fake);
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = 0x1;
opensbi_info.next_addr = images->os.start;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = 0;
opensbi_info.boot_hart = 0;
_load_start = kernel;
_dtb_addr = images->ft_addr;
_dyn_info_addr = (ulong)&opensbi_info;
if (!has_reset_sample(_dtb_addr)) {
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = 0x2;
opensbi_info.next_addr = images->os.start;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = 0;
opensbi_info.boot_hart = 0;
reset_sample();
} else {
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = 0x1;
opensbi_info.next_addr = images->os.start;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = 0;
opensbi_info.boot_hart = 0;
}
if (!fake) {
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {

14
arch/riscv/lib/reset.c
View File

@@ -5,9 +5,21 @@
#include <common.h>
#include <command.h>
#include <asm/io.h>
#define AONSYS_RSTGEN_BASE ((void __iomem *)0xFFFFF44000UL)
#define REG_RST_REQ_EN_0 (AONSYS_RSTGEN_BASE + 0x140)
#define WDT0_SYS_RST_REQ (1 << 8)
static __attribute__((naked))void sys_wdt_reset(void)
{
uint32_t data;
/* wdt0 reset enable */
data = readl(REG_RST_REQ_EN_0);
data |= WDT0_SYS_RST_REQ;
writel(data, REG_RST_REQ_EN_0);
asm volatile (
"1: \n\r"
"li a0, 0xFFEFC30000 \n\r"
@@ -21,7 +33,7 @@ static __attribute__((naked))void sys_wdt_reset(void)
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf("resetting ...\n");
printf("resetting ...\n");
sys_wdt_reset();
hang();

56
board/thead/light-c910/Kconfig
View File

@@ -34,19 +34,57 @@ config SYS_BOARD
config SYS_CONFIG_NAME
default "light-c910"
config LIGHT_BOOT_FORCE_SEQ
bool "light boot force sequence"
default n
config LIGHT_SEC_UPGRADE
bool "light secure upgrade"
default n
config LIGHT_ANDROID_BOOT_IMAGE_VAL_A
bool "light board-a android image"
default n
config AVB_USE_OEM_KEY
bool "AVB signature with OEM key"
default n
config AVB_ROLLBACK_ENABLE
bool "AVB rollback index in RPMB"
default n
config AVB_HW_ENGINE_ENABLE
bool "AVB Hardware cryptographic engine enable"
default n
config LIGHT_ANDROID_BOOT_IMAGE_VAL_B
bool "light board-b android image"
default n
config LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A
bool "light board-lpi4a android image"
default n
config LIGHT_ANDROID_BOOT_IMAGE_ANT_REF
bool "light board ant ref android image"
default n
config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A
bool "light board-a security boot with verification"
default n
config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B
bool "light board-b security boot with verification"
bool "light board-b security boot with verification"
default n
config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
bool "light ant ref security boot with verification"
bool "light ant ref security boot with verification"
default n
config LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
bool "light lpi4a security boot with verification"
default n
config TARGET_LIGHT_FPGA_FM_C910
bool "light fullmask FPGA board"
@@ -84,6 +122,10 @@ config TARGET_LIGHT_FM_C910_BEAGLE
bool "light fullmask for beagle board "
default n
config TARGET_LIGHT_FM_C910_LPI4A
bool "light fullmask for Lichee Pi 4A board "
default n
config TARGET_LIGHT_FM_C910_B_POWER
bool "light fullmask for light-b-power board "
default n
@@ -94,8 +136,8 @@ config SYS_TEXT_BASE
config SPL_TEXT_BASE
hex
default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
config SPL_MAX_SIZE
hex
@@ -206,6 +248,12 @@ config DDR_LP4_2133_SINGLERANK
help
Enabling this will support lpddr4 2133 singlerank configuration.
config DDR_DDP
bool "LPDDR4/4X Dual Die Package support"
help
Enabling this will support ddr Dual Die Package configuration.
e.g. to support 8GB ddr device with 17-bit row address (16:0)
config DDR_H32_MODE
bool "LPDDR4/4X 32bit mode configuration"
help

2
board/thead/light-c910/Makefile
View File

@@ -60,6 +60,7 @@ obj-$(CONFIG_THEAD_LIGHT_DIGITAL_SENSOR) += digital_sensor.o digital_sensor_test
obj-y += clock_config.o
obj-y += sec_check.o
obj-y += boot.o
obj-y += sbmeta/sbmeta.o
ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
@@ -68,4 +69,5 @@ endif
obj-y += light-sv/pll_io_test.o
obj-y += light-sv/adc_test.o
obj-y += version_rollback.o
obj-$(CONFIG_AVB_VERIFY) += secimg_load.o
endif

56
board/thead/light-c910/board.c
View File

@@ -9,10 +9,12 @@
#include <dwc3-uboot.h>
#include <usb.h>
#include <cpu_func.h>
#include <abuf.h>
#include "sec_library.h"
#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_HIGH,
.maximum_speed = USB_SPEED_SUPER,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
};
@@ -50,9 +52,11 @@ int g_dnl_board_usb_cable_connected(void)
#define C906_RST_ADDR_L 0xfffff48048
#define C906_RST_ADDR_H 0xfffff4804C
#define C906_START_ADDRESS_L 0xc0000000
#define C906_START_ADDRESS_H 0xff
#define C910_C906_START_ADDRESS 0xffc0000000
#define C906_START_ADDRESS_L 0x32000000
#define C906_START_ADDRESS_H 0x00
#define C910_C906_START_ADDRESS 0x0032000000
#define C906_CPR_IPCG_ADDRESS 0xFFCB000010
#define C906_IOCTL_GPIO_SEL_ADDRESS 0xFFCB01D000
#define C906_IOCTL_AF_SELH_ADDRESS 0xFFCB01D008
@@ -111,3 +115,47 @@ int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
return 0;
}
#endif
#ifdef CONFIG_BOARD_RNG_SEED
const char pre_gen_seed[128] = {211, 134, 226, 116, 1, 13, 224, 196, 88, 213, 188, 219, 128, 41, 231, 228, 129, 123, 173, 234, 219, 79, 152, 154, 169, 27, 183, 166, 52, 21, 118, 7, 155, 89, 124, 156, 102, 92, 96, 190, 49, 28, 154, 177, 69, 129, 149, 199, 253, 66, 177, 216, 146, 73, 114, 59, 100, 41, 225, 152, 62, 88, 160, 217, 177, 28, 117, 23, 120, 213, 213, 169, 242, 111, 90, 55, 241, 239, 254, 238, 50, 175, 198, 196, 248, 56, 255, 92, 97, 224, 245, 160, 56, 149, 121, 233, 177, 239, 0, 41, 196, 214, 210, 182, 69, 44, 238, 54, 27, 236, 36, 77, 156, 234, 17, 148, 34, 16, 241, 132, 241, 230, 36, 41, 123, 157, 19, 44};
/* Use hardware rng to seed Linux random. */
int board_rng_seed(struct abuf *buf)
{
size_t len = 128;
uint8_t *data = NULL;
int sc_err = SC_FAIL;
/* abuf is working up in asynchronization mode, so the memory usage for random data storage must
be allocated first. */
data = malloc(len);
if (!data) {
printf("Fail to allocate memory, using pre-defined entropy\n");
return -1;
}
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
/* We still use pre-define entropy data in case hardware random engine does not work */
sc_err = csi_sec_library_init();
if (sc_err != SC_OK) {
printf("Fail to initialize sec library, using pre-defined entropy\n");
goto _err;
}
sc_err = sc_rng_get_random_bytes(data, len);
if (sc_err != SC_OK) {
printf("Fail to retrieve random data, using pre-defined entropy\n");
goto _err;
}
abuf_init_set(buf, data, len);
return 0;
_err:
#endif
/* use pre-defined random data in case of the random engine is disable */
memcpy(data, pre_gen_seed, len);
abuf_init_set(buf, data, len);
return 0;
}
#endif

456
board/thead/light-c910/boot.c
View File

@@ -7,26 +7,31 @@
#include <dm.h>
#include <fdt_support.h>
#include <fdtdec.h>
#include <mmc.h>
#include <opensbi.h>
#include <asm/csr.h>
#include <asm/arch-thead/boot_mode.h>
#include "../../../lib/sec_library/include/csi_efuse_api.h"
#include "../../../lib/sec_library/include/sec_crypto_sha.h"
#include "../../../lib/sec_library/include/kdf.h"
#include "../../../lib/sec_library/include/sec_crypto_mac.h"
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
/* The micro is used to enable NON-COT boot with non-signed image */
/* The macro is used to enable NON-COT boot with non-signed image */
#define LIGHT_NON_COT_BOOT 1
/* The micro is used to enable uboot version in efuse */
/* The macro is used to enable uboot version in efuse */
#define LIGHT_UBOOT_VERSION_IN_ENV 1
/* The micro is used to enble RPMB ACCESS KEY from KDF */
/* The macro is used to enble RPMB ACCESS KEY from KDF */
//#define LIGHT_KDF_RPMB_KEY 1
/* The macro is used to enable secure image version check in boot */
//#define LIGHT_IMG_VERSION_CHECK_IN_BOOT 1
/* the sample rpmb key is only used for testing */
#ifndef LIGHT_KDF_RPMB_KEY
#ifndef LIGHT_KDF_RPMB_KEY
static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
0xbb, 0xaa, 0x99, 0x88, 0xff, 0xee, 0xdd, 0xcc, \
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
@@ -34,18 +39,88 @@ static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0
#endif
static unsigned int upgrade_image_version = 0;
int csi_rpmb_write_access_key(void)
#define RPMB_EMMC_CID_SIZE 16
#define RPMB_CID_PRV_OFFSET 9
#define RPMB_CID_CRC_OFFSET 15
#ifdef LIGHT_KDF_RPMB_KEY
static int tee_rpmb_key_gen(uint8_t* key, uint32_t * length)
{
uint32_t data[RPMB_EMMC_CID_SIZE / 4];
uint8_t huk[32];
uint32_t huk_len;
struct mmc *mmc = find_mmc_device(0);
int i;
sc_mac_t mac_handle;
int ret = 0;
if (!mmc)
return -1;
if (!mmc->ext_csd)
return -1;
for (i = 0; i < ARRAY_SIZE(mmc->cid); i++)
data[i] = cpu_to_be32(mmc->cid[i]);
/*
* PRV/CRC would be changed when doing eMMC FFU
* The following fields should be masked off when deriving RPMB key
*
* CID [55: 48]: PRV (Product revision)
* CID [07: 01]: CRC (CRC7 checksum)
* CID [00]: not used
*/
memset((void *)((uint64_t)data + RPMB_CID_PRV_OFFSET), 0, 1);
memset((void *)((uint64_t)data + RPMB_CID_CRC_OFFSET), 0, 1);
/* Step1: Derive HUK from KDF function */
ret = csi_kdf_gen_hmac_key(huk, &huk_len);
if (ret) {
printf("kdf gen hmac key faild[%d]\r\n", ret);
return -1;
}
/* Step2: Using HUK and data to generate RPMB key */
ret = sc_mac_init(&mac_handle, 0);
if (ret) {
printf("mac init faild[%d]\r\n", ret);
ret = -1;
return -1;
}
/* LSB 16 bytes are used as key */
ret = sc_mac_set_key(&mac_handle, huk, 16);
if (ret) {
printf("mac set key faild[%d]\r\n", ret);
ret = -1;
goto func_exit;
}
ret = sc_mac_calc(&mac_handle, SC_SHA_MODE_256, (uint8_t *)&data, sizeof(data), key, length);
if (ret) {
printf("mac calc faild[%d]\r\n", ret);
ret = -1;
goto func_exit;
}
func_exit:
sc_mac_uninit(&mac_handle);
return ret;
}
#endif
int csi_rpmb_write_access_key(void)
{
#ifdef LIGHT_KDF_RPMB_KEY
unsigned long *temp_rpmb_key_addr = NULL;
char runcmd[64] = {0};
uint8_t blkdata[256] = {0};
uint8_t kdf_rpmb_key[32];
uint32_t kdf_rpmb_key_length = 0;
__attribute__((__aligned__(8))) uint8_t kdf_rpmb_key[32];
uint32_t kdf_rpmb_key_length = 0;
int ret = 0;
#ifdef LIGHT_KDF_RPMB_KEY
/* Step1: retrive RPMB key from KDF function */
ret = csi_kdf_gen_hmac_key(kdf_rpmb_key, &kdf_rpmb_key_length);
ret = tee_rpmb_key_gen(kdf_rpmb_key, &kdf_rpmb_key_length);
if (ret != 0) {
return -1;
}
@@ -79,13 +154,16 @@ int csi_tf_get_image_version(unsigned int *ver)
{
char runcmd[64] = {0};
unsigned char blkdata[256];
int ret = 0;
/* tf version reside in RPMB block#0, offset#16*/
sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
run_command(runcmd, 0);
*ver = (blkdata[16] << 8) + blkdata[17];
ret = run_command(runcmd, 0);
if (ret == 0) {
*ver = (blkdata[16] << 8) + blkdata[17];
}
return 0;
return ret;
}
int csi_tf_set_image_version(unsigned int ver)
@@ -101,9 +179,9 @@ int csi_tf_set_image_version(unsigned int ver)
blkdata[17] = ver & 0xFF;
/* tf version reside in RPMB block#0, offset#16*/
#ifndef LIGHT_KDF_RPMB_KEY
#ifndef LIGHT_KDF_RPMB_KEY
temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
#else
#else
uint8_t kdf_rpmb_key[32];
uint32_t kdf_rpmb_key_length = 0;
int ret = 0;
@@ -129,13 +207,16 @@ int csi_tee_get_image_version(unsigned int *ver)
{
char runcmd[64] = {0};
unsigned char blkdata[256];
int ret = 0;
/* tf version reside in RPMB block#0, offset#0*/
sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
run_command(runcmd, 0);
*ver = (blkdata[0] << 8) + blkdata[1];
ret = run_command(runcmd, 0);
if (ret == 0) {
*ver = (blkdata[0] << 8) + blkdata[1];
}
return 0;
return ret;
}
int csi_kernel_get_image_version(unsigned int *ver)
@@ -164,9 +245,9 @@ int csi_tee_set_image_version(unsigned int ver)
blkdata[1] = ver & 0xFF;
/* tf version reside in RPMB block#0, offset#16*/
#ifndef LIGHT_KDF_RPMB_KEY
#ifndef LIGHT_KDF_RPMB_KEY
temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
#else
#else
uint8_t kdf_rpmb_key[32];
uint32_t kdf_rpmb_key_length = 0;
int ret = 0;
@@ -187,6 +268,57 @@ int csi_tee_set_upgrade_version(void)
return csi_tee_set_image_version(upgrade_image_version);
}
int csi_sbmeta_get_image_version(unsigned int *ver)
{
char runcmd[64] = {0};
unsigned char blkdata[256];
int ret = 0;
/* sbmeta version reside in RPMB block#0, offset#48*/
sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
ret = run_command(runcmd, 0);
if (ret == 0) {
*ver = (blkdata[48] << 8) + blkdata[49];
}
return ret;
}
int csi_sbmeta_set_image_version(unsigned int ver)
{
char runcmd[64] = {0};
unsigned char blkdata[256];
unsigned long *temp_rpmb_key_addr = NULL;
/* sbmeta version reside in RPMB block#0, offset#48*/
sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
run_command(runcmd, 0);
blkdata[48] = (ver & 0xFF00) >> 8;
blkdata[49] = ver & 0xFF;
/* sbmeta version reside in RPMB block#0, offset#48*/
#ifndef LIGHT_KDF_RPMB_KEY
temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
#else
uint8_t kdf_rpmb_key[32];
uint32_t kdf_rpmb_key_length = 0;
int ret = 0;
ret = csi_kdf_gen_hmac_key(kdf_rpmb_key, &kdf_rpmb_key_length);
if (ret != 0) {
return -1;
}
temp_rpmb_key_addr = (unsigned long *)kdf_rpmb_key;
#endif
sprintf(runcmd, "mmc rpmb write 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
run_command(runcmd, 0);
return 0;
}
int csi_sbmeta_set_upgrade_version(void)
{
return csi_sbmeta_set_image_version(upgrade_image_version);
}
int csi_uboot_get_image_version(unsigned int *ver)
{
#ifdef LIGHT_UBOOT_VERSION_IN_ENV
@@ -214,7 +346,7 @@ int csi_uboot_get_image_version(unsigned int *ver)
unsigned int ver_x = 0;
int ret = 0;
ret = csi_efuse_api_int();
ret = csi_efuse_api_init();
if (ret) {
printf("efuse api init fail \n");
return -1;
@@ -240,7 +372,6 @@ int csi_uboot_set_image_version(unsigned int ver)
//TODO
unsigned long long uboot_ver = 0;
unsigned char ver_x = (ver & 0xff00) >> 8;
char ver_str[32] = {0};
uboot_ver = env_get_hex("uboot_version", 0xffffffffffffffff);
@@ -263,7 +394,7 @@ int csi_uboot_set_image_version(unsigned int ver)
return 0;
}
ret = csi_efuse_api_int();
ret = csi_efuse_api_init();
if (ret) {
printf("efuse api init fail \n");
return -1;
@@ -320,6 +451,109 @@ int verify_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
return 0;
}
int check_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
{
unsigned char new_ver_x = 0, new_ver_y = 0;
unsigned char cur_ver_x = 0, cur_ver_y = 0;
/* Get secure version X from image version X.Y */
new_ver_x = (new_ver & 0xFF00) >> 8;
new_ver_y = new_ver & 0xFF;
cur_ver_x = (cur_ver & 0xFF00) >> 8;
cur_ver_y = cur_ver & 0xFF;
(void)new_ver_y;
(void)cur_ver_y;
/* Ensure image version must be less than expected version */
if (new_ver_x < cur_ver_x) {
return -1;
}
return 0;
}
int check_tf_version_in_boot(unsigned long tf_addr)
{
int ret = 0;
unsigned int img_version = 0;
unsigned int expected_img_version = 0;
img_version = get_image_version(tf_addr);
if (img_version == 0) {
printf("get tf image version fail\n");
return -1;
}
ret = csi_tf_get_image_version(&expected_img_version);
if (ret != 0) {
printf("Get tf expected img version fail\n");
return -1;
}
ret = check_image_version_rule(img_version, expected_img_version);
if (ret != 0) {
printf("Image version breaks the rule\n");
return -1;
}
return 0;
}
int check_tee_version_in_boot(unsigned long tee_addr)
{
int ret = 0;
unsigned int img_version = 0;
unsigned int expected_img_version = 0;
img_version = get_image_version(tee_addr);
if (img_version == 0) {
printf("get tee image version fail\n");
return -1;
}
ret = csi_tee_get_image_version(&expected_img_version);
if (ret != 0) {
printf("Get tee expected img version fail\n");
return -1;
}
ret = check_image_version_rule(img_version, expected_img_version);
if (ret != 0) {
printf("Image version breaks the rule\n");
return -1;
}
return 0;
}
int check_sbmeta_version_in_boot(unsigned long sbmeta_addr)
{
int ret = 0;
unsigned int img_version = 0;
unsigned int expected_img_version = 0;
img_version = get_image_version(sbmeta_addr);
if (img_version == 0) {
printf("get sbmeta image version fail\n");
return -1;
}
ret = csi_sbmeta_get_image_version(&expected_img_version);
if (ret != 0) {
printf("Get sbmeta expected img version fail\n");
return -1;
}
ret = check_image_version_rule(img_version, expected_img_version);
if (ret != 0) {
printf("Image version breaks the rule\n");
return -1;
}
return 0;
}
int light_vimage(int argc, char *const argv[])
{
int ret = 0;
@@ -327,14 +561,14 @@ int light_vimage(int argc, char *const argv[])
unsigned int new_img_version = 0;
unsigned int cur_img_version = 0;
char imgname[32] = {0};
if (argc < 3)
if (argc < 3)
return CMD_RET_USAGE;
/* Parse input parameters */
vimage_addr = simple_strtoul(argv[1], NULL, 16);
strcpy(imgname, argv[2]);
/* Retrieve desired information from image header */
new_img_version = get_image_version(vimage_addr);
if (new_img_version == 0) {
@@ -368,13 +602,20 @@ int light_vimage(int argc, char *const argv[])
printf("Get kernel img version fail\n");
return CMD_RET_FAILURE;
}
} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
} else if (strcmp(imgname, SBMETA_PART_NAME) == 0){
ret = csi_sbmeta_get_image_version(&cur_img_version);
if (ret != 0) {
printf("Get sbmeta img version fail\n");
return CMD_RET_FAILURE;
}
} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
ret = csi_uboot_get_image_version(&cur_img_version);
if (ret != 0) {
printf("Get uboot img version fail\n");
return CMD_RET_FAILURE;
}
}
// Check uboot maximization version > 64
if (((new_img_version & 0xFF00) >> 8) > UBOOT_MAX_VER) {
printf("UBOOT Image version has reached to max-version\n");
@@ -422,6 +663,11 @@ int light_vimage(int argc, char *const argv[])
if (ret != 0) {
return CMD_RET_FAILURE;
}
} else if (strcmp(imgname, SBMETA_PART_NAME) == 0) {
ret = verify_customer_image(T_SBMETA, vimage_addr);
if (ret != 0) {
return CMD_RET_FAILURE;
}
} else {
printf("Error: unknow image name\n");
return CMD_RET_FAILURE;
@@ -435,10 +681,8 @@ int light_secboot(int argc, char * const argv[])
int ret = 0;
unsigned long tf_addr = LIGHT_TF_FW_ADDR;
unsigned long tee_addr = LIGHT_TEE_FW_ADDR;
unsigned long kernel_addr = LIGHT_KERNEL_ADDR;
unsigned int tf_image_size = 0;
unsigned int tee_image_size = 0;
unsigned int kernel_image_size = 0;
printf("\n\n");
printf("Now, we start to verify all trust firmware before boot kernel !\n");
@@ -454,6 +698,13 @@ int light_secboot(int argc, char * const argv[])
/* Step1. Check and verify TF image */
if (image_have_head(LIGHT_TF_FW_TMP_ADDR) == 1) {
#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
printf("check TF version in boot \n");
ret = check_tf_version_in_boot(LIGHT_TF_FW_TMP_ADDR);
if (ret != 0) {
return CMD_RET_FAILURE;
}
#endif
printf("Process TF image verification ...\n");
ret = verify_customer_image(T_TF, LIGHT_TF_FW_TMP_ADDR);
@@ -479,6 +730,14 @@ int light_secboot(int argc, char * const argv[])
/* Step2. Check and verify TEE image */
if (image_have_head(tee_addr) == 1) {
#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
printf("check TEE version in boot \n");
ret = check_tee_version_in_boot(tee_addr);
if (ret != 0) {
return CMD_RET_FAILURE;
}
#endif
printf("Process TEE image verification ...\n");
ret = verify_customer_image(T_TEE, tee_addr);
if (ret != 0) {
@@ -529,16 +788,40 @@ void sec_firmware_version_dump(void)
unsigned int tf_ver = 0;
unsigned int tee_ver = 0;
unsigned int uboot_ver = 0;
unsigned int sbmeta_ver = 0;
unsigned int tf_ver_env = 0;
unsigned int tee_ver_env = 0;
unsigned int sbmeta_ver_env = 0;
csi_uboot_get_image_version(&uboot_ver);
csi_tf_get_image_version(&tf_ver);
csi_tee_get_image_version(&tee_ver);
csi_sbmeta_get_image_version(&sbmeta_ver);
/* Keep sync with version in RPMB, the Following version could be leveraged by OTA client */
tee_ver_env = env_get_hex("tee_version", 0);
tf_ver_env = env_get_hex("tf_version", 0);
sbmeta_ver_env = env_get_hex("sbmeta_version", 0);
if ((tee_ver_env != tee_ver) && (tee_ver != 0)) {
env_set_hex("tee_version", tee_ver);
run_command("saveenv", 0);
}
if ((tf_ver_env != tf_ver) && (tf_ver != 0)) {
env_set_hex("tf_version", tf_ver);
run_command("saveenv", 0);
}
if ((sbmeta_ver_env != sbmeta_ver) && (sbmeta_ver != 0)) {
env_set_hex("sbmeta_version", sbmeta_ver);
run_command("saveenv", 0);
}
printf("\n\n");
printf("Secure Firmware image version info: \n");
printf("uboot Firmware v%d.0\n", (uboot_ver & 0xff00) >> 8);
printf("Trust Firmware v%d.%d\n", (tf_ver & 0xff00) >> 8, tf_ver & 0xff);
printf("TEE OS v%d.%d\n", (tee_ver & 0xff00) >> 8, tee_ver & 0xff);
printf("SBMETA v%d.%d\n", (sbmeta_ver & 0xff00) >> 8, sbmeta_ver & 0xff);
printf("\n\n");
}
@@ -546,6 +829,8 @@ void sec_upgrade_thread(void)
{
const unsigned long temp_addr=0x200000;
char runcmd[80];
uint8_t * image_buffer = NULL;
uint8_t * image_malloc_buffer = NULL;
int ret = 0;
unsigned int sec_upgrade_flag = 0;
unsigned int upgrade_file_size = 0;
@@ -553,13 +838,11 @@ void sec_upgrade_thread(void)
sec_upgrade_flag = env_get_hex("sec_upgrade_mode", 0);
if (sec_upgrade_flag == 0)
return;
printf("bootstrap: sec_upgrade_flag: %x\n", sec_upgrade_flag);
if (sec_upgrade_flag == TF_SEC_UPGRADE_FLAG) {
/* STEP 1: read upgrade image (trust_firmware.bin) from stash partition */
printf("read upgrade image (trust_firmware.bin) from stash partition \n");
sprintf(runcmd, "ext4load mmc 0:5 0x%p trust_firmware.bin", (void *)temp_addr);
sprintf(runcmd, "ext4load mmc 0:4 0x%p trust_firmware.bin", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
@@ -570,6 +853,15 @@ void sec_upgrade_thread(void)
upgrade_file_size = env_get_hex("filesize", 0);
printf("upgrade file size: %d\n", upgrade_file_size);
/*store image to temp buffer as temp_addr may be decrypted*/
image_malloc_buffer = malloc(upgrade_file_size);
if ( image_malloc_buffer == NULL ) {
image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
} else {
image_buffer = image_malloc_buffer;
}
memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
/* STEP 2: verify its authentiticy here */
sprintf(runcmd, "vimage 0x%p tf", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
@@ -581,7 +873,7 @@ void sec_upgrade_thread(void)
/* STEP 3: update tf partition */
printf("read upgrade image (trust_firmware.bin) into tf partition \n");
sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)temp_addr, upgrade_file_size);
sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)image_buffer, upgrade_file_size);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
@@ -603,11 +895,15 @@ _upgrade_tf_exit:
run_command("saveenv", 0);
run_command("reset", 0);
if ( image_malloc_buffer != NULL ) {
free(image_malloc_buffer);
image_malloc_buffer = NULL;
}
} else if (sec_upgrade_flag == TEE_SEC_UPGRADE_FLAG) {
/* STEP 1: read upgrade image (tee.bin) from stash partition */
printf("read upgrade image (tee.bin) from stash partition \n");
sprintf(runcmd, "ext4load mmc 0:5 0x%p tee.bin", (void *)temp_addr);
sprintf(runcmd, "ext4load mmc 0:4 0x%p tee.bin", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
@@ -618,6 +914,15 @@ _upgrade_tf_exit:
upgrade_file_size = env_get_hex("filesize", 0);
printf("TEE upgrade file size: %d\n", upgrade_file_size);
/*store image to temp buffer as temp_addr may be decrypted*/
image_malloc_buffer = malloc(upgrade_file_size);
if ( image_malloc_buffer == NULL ) {
image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
} else {
image_buffer = image_malloc_buffer;
}
memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
/* STEP 2: verify its authentiticy here */
sprintf(runcmd, "vimage 0x%p tee", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
@@ -628,8 +933,8 @@ _upgrade_tf_exit:
}
/* STEP 3: update tee partition */
printf("read upgrade image (tee.bin) into tf partition \n");
sprintf(runcmd, "ext4write mmc 0:4 0x%p /tee.bin 0x%x", (void *)temp_addr, upgrade_file_size);
printf("read upgrade image (tee.bin) into sbmeta partition \n");
sprintf(runcmd, "ext4write mmc 0:3 0x%p /tee.bin 0x%x", (void *)image_buffer, upgrade_file_size);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
@@ -651,7 +956,72 @@ _upgrade_tee_exit:
run_command("saveenv", 0);
run_command("reset", 0);
} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) {
if ( image_malloc_buffer != NULL ) {
free(image_malloc_buffer);
image_malloc_buffer = NULL;
}
} else if (sec_upgrade_flag == SBMETA_SEC_UPGRADE_FLAG) {
/* STEP 1: read upgrade image (sbmeta.bin) from stash partition */
printf("read upgrade image (sbmeta.bin) from stash partition \n");
sprintf(runcmd, "ext4load mmc 0:4 0x%p sbmeta.bin", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("SBMETA Upgrade process is terminated due to some reason\n");
goto _upgrade_sbmeta_exit;
}
/* Fetch the total file size after read out operation end */
upgrade_file_size = env_get_hex("filesize", 0);
printf("SBMETA upgrade file size: %d\n", upgrade_file_size);
/*store image to temp buffer as temp_addr may be decrypted*/
image_malloc_buffer = malloc(upgrade_file_size);
if ( image_malloc_buffer == NULL ) {
image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
} else {
image_buffer = image_malloc_buffer;
}
memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
/* STEP 2: verify its authentiticy here */
sprintf(runcmd, "vimage 0x%p sbmeta", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("SBMETA Image verification fail and upgrade process terminates\n");
goto _upgrade_sbmeta_exit;
}
/* STEP 3: update sbmeta partition */
printf("read upgrade image (SBMETA.bin) into sbmeta partition \n");
sprintf(runcmd, "ext4write mmc 0:3 0x%p /sbmeta.bin 0x%x", (void *)image_buffer, upgrade_file_size);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("SBMETA upgrade process is terminated due to some reason\n");
goto _upgrade_sbmeta_exit;
}
/* STEP 4: update sbmeta version */
ret = csi_sbmeta_set_upgrade_version();
if (ret != 0) {
printf("Set sbmeta upgrade version fail\n");
goto _upgrade_sbmeta_exit;
}
printf("\n\nSBMETA image ugprade process is successful\n\n");
_upgrade_sbmeta_exit:
/* set secure upgrade flag to 0 that indicate upgrade over */
run_command("env set sec_upgrade_mode 0", 0);
run_command("saveenv", 0);
run_command("reset", 0);
if ( image_malloc_buffer != NULL ) {
free(image_malloc_buffer);
image_malloc_buffer = NULL;
}
} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) {
unsigned int block_cnt;
struct blk_desc *dev_desc;
const unsigned long uboot_temp_addr=0x80000000;
@@ -660,7 +1030,7 @@ _upgrade_tee_exit:
/* STEP 1: read upgrade image (u-boot-with-spl.bin) from stash partition */
printf("read upgrade image (u-boot-with-spl.bin) from stash partition \n");
sprintf(runcmd, "ext4load mmc 0:5 0x%p u-boot-with-spl.bin", (void *)temp_addr);
sprintf(runcmd, "ext4load mmc 0:4 0x%p u-boot-with-spl.bin", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {

6
board/thead/light-c910/clock_config.c
View File

@@ -1146,6 +1146,7 @@ void ap_mipi_dsi1_clk_endisable(bool en)
writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
}
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
{
unsigned long div_reg;
@@ -1209,6 +1210,7 @@ static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned in
div_cfg |= div_en;
writel(div_cfg, (void __iomem *)div_reg);
}
#endif
int clk_config(void)
{
@@ -1302,9 +1304,9 @@ int clk_config(void)
/* The boards other than the LightA board perform the bus down-speed operation */
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 15); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP_RY_CORE_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VO_DPU_CORE_DIV, 4); /* Input frquency: 2376MHZ */

291
board/thead/light-c910/light.c
View File

@@ -31,6 +31,7 @@
#define GMAC0_APB3S_BADDR 0xffec003000
#define GMAC1_APB3S_BADDR 0xffec004000
static uint64_t apb3s_baddr;
extern int check_image_board_id(uint8_t *image_data);
typedef enum {
UART0_TXD = PAD_GRP_BASE_SET(SOC_PIN_AP_RIGHT_TOP),
@@ -555,12 +556,14 @@ static void gmac_phy_rst(void)
(void *)LIGHT_GPIO3_BADDR);
writel(readl((void *)LIGHT_GPIO1_BADDR) & ~LIGHT_GPIO1_13,
(void *)LIGHT_GPIO1_BADDR);
wmb();
/* At least 10ms */
mdelay(12);
mdelay(50);
writel(readl((void *)LIGHT_GPIO3_BADDR) | LIGHT_GPIO3_21,
(void *)LIGHT_GPIO3_BADDR);
writel(readl((void *)LIGHT_GPIO1_BADDR) | LIGHT_GPIO1_13,
(void *)LIGHT_GPIO1_BADDR);
wmb();
}
static void gmac_glue_init(uint64_t apb3s_baddr)
@@ -910,14 +913,14 @@ static void light_iopin_init(void)
light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
#if ! defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2); //soc_vdd18_lcd0_en_reg --backup regulator
#else
light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PU,2); //soc_vdd18_lcd0_en_reg
#endif
light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2);//soc_lcd0_bias_en_reg
light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
#if ! defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);//reg_tp_pwr_en --touch pannel
#else
light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PU,2);//reg_tp_pwr_en --touch pannel
@@ -1406,6 +1409,280 @@ static void light_iopin_init(void)
light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
}
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
static void light_iopin_init(void)
{
/* aon-padmux config */
light_pin_cfg(I2C_AON_SCL, PIN_SPEED_NORMAL, PIN_PN, 8);
light_pin_cfg(I2C_AON_SDA, PIN_SPEED_NORMAL, PIN_PN, 8);
light_pin_mux(CPU_JTG_TCLK, 3);
light_pin_cfg(CPU_JTG_TCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(CPU_JTG_TMS, 3);
light_pin_cfg(CPU_JTG_TMS, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(CPU_JTG_TDI, 3);
light_pin_cfg(CPU_JTG_TDI, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AOGPIO_7, 1);
light_pin_mux(AOGPIO_8, 1);
// light_pin_mux(AOGPIO_9, 0);
light_pin_mux(AOGPIO_10, 1);
light_pin_mux(AOGPIO_11, 1);
light_pin_mux(AOGPIO_12, 1);
light_pin_mux(AOGPIO_13, 1);
light_pin_mux(AOGPIO_14, 0);
// light_pin_mux(AOGPIO_15,0);
light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2); ///NC
light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2); ///NC
// light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(AOGPIO_13, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
// light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AUDIO_PA0, 0);
light_pin_cfg(AUDIO_PA0, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA1, 0);
light_pin_cfg(AUDIO_PA1, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA3, 0);
light_pin_cfg(AUDIO_PA3, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA4, 0);
light_pin_cfg(AUDIO_PA4, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA5, 0);
light_pin_cfg(AUDIO_PA5, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA6, 0);
light_pin_cfg(AUDIO_PA6, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA7, 0);
light_pin_cfg(AUDIO_PA7, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA14, 0);
light_pin_cfg(AUDIO_PA14, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA15, 0);
light_pin_cfg(AUDIO_PA15, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA16, 0);
light_pin_cfg(AUDIO_PA16, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA17, 0);
light_pin_cfg(AUDIO_PA17, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA29, 0);
light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA30, 0);
light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2);
// light_pin_mux(AUDIO_PA9,3); ///AUDIO-PA-RESET
// light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
// light_pin_mux(AUDIO_PA10,3); /// AUD-3V3-EN
// light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
// light_pin_mux(AUDIO_PA12,3); /// AUD-1V8-EN
// light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
// light_pin_mux(AUDIO_PA13,0);
/*ap-padmux on left/top */
light_pin_mux(QSPI1_SCLK, 4);
light_pin_cfg(QSPI1_SCLK, PIN_SPEED_NORMAL,PIN_PN, 8); ///se-spi
light_pin_mux(QSPI1_CSN0, 4);
light_pin_cfg(QSPI1_CSN0, PIN_SPEED_NORMAL, PIN_PN, 8); ///se-spi
light_pin_mux(QSPI1_D0_MOSI, 4);
light_pin_cfg(QSPI1_D0_MOSI, PIN_SPEED_NORMAL, PIN_PU, 8); ///se-spi
light_pin_mux(QSPI1_D1_MISO, 4);
light_pin_cfg(QSPI1_D1_MISO, PIN_SPEED_NORMAL, PIN_PU, 8); ///se-spi
light_pin_mux(QSPI1_D2_WP, 4);
light_pin_cfg(QSPI1_D2_WP, PIN_SPEED_NORMAL, PIN_PN, 8); ///NC
// light_pin_mux(QSPI1_D3_HOLD, 4);
// light_pin_cfg(QSPI1_D3_HOLD, PIN_SPEED_NORMAL, PIN_PN, 8); ///NC
light_pin_cfg(I2C0_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
light_pin_cfg(I2C0_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
light_pin_cfg(I2C1_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
light_pin_cfg(I2C1_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
light_pin_cfg(UART1_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART1_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART4_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART4_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART4_CTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART4_RTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(UART3_TXD, 1);
light_pin_cfg(UART3_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(UART3_RXD, 1);
light_pin_cfg(UART3_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
// light_pin_mux(GPIO0_18,1);
// light_pin_mux(GPIO0_19,1);
// light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
// light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
// light_pin_mux(GPIO0_20,0);
// light_pin_mux(GPIO0_21,0);
// light_pin_mux(GPIO0_22,1);
// light_pin_mux(GPIO0_23,1);
// light_pin_mux(GPIO0_24,1);
// light_pin_mux(GPIO0_25,1);
// light_pin_mux(GPIO0_26,1);
// light_pin_mux(GPIO0_27,0);
// light_pin_mux(GPIO0_28,0);
// light_pin_mux(GPIO0_29,0);
// light_pin_mux(GPIO0_30,0);
// light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
// light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO0_24, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(GPIO0_25, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(GPIO0_27, PIN_SPEED_NORMAL, PIN_PN, 2); ///< NC(not used)
light_pin_cfg(GPIO0_28, PIN_SPEED_NORMAL, PIN_PN, 2); ///< AVDD25_IR_EN
// light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2); ///< DVDD12_IR_EN
light_pin_cfg(GPIO0_30, PIN_SPEED_NORMAL, PIN_PU, 2); ///< gmac,uart,led
light_pin_cfg(GPIO0_31, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(GPIO1_0, 0);
// light_pin_mux(GPIO1_1,1);
// light_pin_mux(GPIO1_2,1);
light_pin_mux(GPIO1_3, 0);
light_pin_mux(GPIO1_4, 0);
light_pin_mux(GPIO1_5, 0);
light_pin_mux(GPIO1_6, 0);
light_pin_mux(GPIO1_9, 0);
light_pin_mux(GPIO1_10, 0);
// light_pin_mux(GPIO1_11,0);
// light_pin_mux(GPIO1_12,0);
light_pin_mux(GPIO1_13, 0);
light_pin_mux(GPIO1_14, 0);
// light_pin_mux(GPIO1_15,0);
// light_pin_mux(GPIO1_16,0);
light_pin_cfg(GPIO1_0, PIN_SPEED_NORMAL, PIN_PN, 2);
// light_pin_cfg(GPIO1_1,PIN_SPEED_NORMAL,PIN_PN,2);
// light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_3, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(GPIO1_4, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(GPIO1_5, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(GPIO1_6, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(GPIO1_9, PIN_SPEED_NORMAL, PIN_PN, 2); ///<VDD18_LCD0_EN
light_pin_cfg(GPIO1_10, PIN_SPEED_NORMAL, PIN_PN, 2); ///<LCD0_BIAS_EN
// light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
// light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2); ///<TOUCH-PANNEL VDD28_TP0_EN
light_pin_cfg(GPIO1_13, PIN_SPEED_NORMAL, PIN_PN, 2); ///<DOVDD18_RGB_EN
light_pin_cfg(GPIO1_14, PIN_SPEED_NORMAL, PIN_PN, 2); ///<DVDD12_RGB_EN
// light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2); ///<AVDD28_RGB_EN
// light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(CLK_OUT_0, 1);
light_pin_cfg(CLK_OUT_0, PIN_SPEED_NORMAL, PIN_PU, 2);
light_pin_mux(CLK_OUT_1, 1);
light_pin_cfg(CLK_OUT_1, PIN_SPEED_NORMAL, PIN_PU, 2);
light_pin_mux(CLK_OUT_2, 0);
light_pin_cfg(CLK_OUT_2, PIN_SPEED_NORMAL, PIN_PU, 2);
light_pin_mux(CLK_OUT_3, 0);
light_pin_cfg(CLK_OUT_3, PIN_SPEED_NORMAL, PIN_PU, 2);
// light_pin_mux(GPIO1_21,3);
light_pin_mux(GPIO1_22, 3);
// light_pin_mux(GPIO1_23,3);
light_pin_mux(GPIO1_24, 3);
// light_pin_mux(GPIO1_25,3);
// light_pin_mux(GPIO1_26,3);
// light_pin_mux(GPIO1_27,3);
light_pin_mux(GPIO1_28, 0);
// light_pin_mux(GPIO1_29,3);
light_pin_mux(GPIO1_30, 0);
// light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_22, PIN_SPEED_NORMAL, PIN_PN,2);
// light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2); ///<LED_PDN
light_pin_cfg(GPIO1_24, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(GPIO1_28, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(GPIO1_30, PIN_SPEED_NORMAL, PIN_PN, 2); ///<DBB2LEDDRIVER_EN
light_pin_cfg(UART0_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART0_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
/*ap-pdmux on righ/top*/
// light_pin_mux(QSPI0_SCLK,3); ///NC
// light_pin_mux(QSPI0_CSN0,3); ///NC
// light_pin_mux(QSPI0_CSN1,3); ///NC
// light_pin_mux(QSPI0_D0_MOSI,3); ///NC
// light_pin_mux(QSPI0_D1_MISO,3); ///NC
// light_pin_mux(QSPI0_D2_WP,3); ///NC
// light_pin_mux(QSPI0_D3_HOLD,3); ///NC
light_pin_cfg(I2C2_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
light_pin_cfg(I2C2_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
light_pin_cfg(I2C3_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
light_pin_cfg(I2C3_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
// light_pin_mux(SPI_CSN,3); /// W_DISABLE_CATE1
// light_pin_mux(SPI_MOSI,3); /// NC
// light_pin_mux(SPI_MISO,3); /// RERST1_N_CAT1
// light_pin_mux(SPI_SCLK,3);
light_pin_cfg(SPI_CSN, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(SPI_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(SPI_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(SPI_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(GPIO2_13, 0);
light_pin_mux(GPIO2_18, 1);
light_pin_mux(GPIO2_19, 1);
light_pin_mux(GPIO2_20, 1);
light_pin_mux(GPIO2_21, 1);
light_pin_mux(GPIO2_22, 1);
light_pin_mux(GPIO2_23, 1);
light_pin_mux(GPIO2_24, 1);
light_pin_mux(GPIO2_25, 1);
light_pin_cfg(GPIO2_13, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(GPIO2_18, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GPIO2_19, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GPIO2_20, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GPIO2_21, PIN_SPEED_NORMAL, PIN_PN, 0xF); ///<NC
light_pin_cfg(GPIO2_22, PIN_SPEED_NORMAL, PIN_PN, 0xF); ///<WIFI_BT_GPIO2
light_pin_cfg(GPIO2_23, PIN_SPEED_NORMAL, PIN_PN, 0xF); ///<WIFI_BT_GPIO3
light_pin_cfg(GPIO2_24, PIN_SPEED_NORMAL, PIN_PN, 0xF); ///<WIFI_BT_RST_N
light_pin_cfg(GPIO2_25, PIN_SPEED_NORMAL, PIN_PU, 0xF); ///KEY1
light_pin_mux(SDIO0_DETN, 0);
light_pin_cfg(SDIO0_DETN, PIN_SPEED_NORMAL, PIN_PN, 2);
// light_pin_mux(SDIO0_WPRTN,3);
// light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2); ///< NC
// light_pin_mux(SDIO1_WPRTN,3);
// light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2); ///VBUS_EN
// light_pin_mux(SDIO1_DETN,3);
// light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2); ///WCN_33_EN
light_pin_mux(GPIO2_30, 1);
light_pin_mux(GPIO2_31, 1);
light_pin_mux(GPIO3_0, 1);
light_pin_mux(GPIO3_1, 1);
light_pin_mux(GPIO3_2, 1);
light_pin_mux(GPIO3_3, 1);
light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0xF); ///NC
light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0xF); ///NC
light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0xF); ///NC
light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(HDMI_SCL, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(HDMI_SDA, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(HDMI_CEC, PIN_SPEED_NORMAL, PIN_PN, 0x2);
/* GMAC0 pad drive strength configurate to 0xF */
light_pin_cfg(GMAC0_TX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXEN, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXDV, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
// light_pin_cfg(GMAC0_MDC, PIN_SPEED_NORMAL, PIN_PN, 0xF);
// light_pin_cfg(GMAC0_MDIO, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_mux(GMAC0_COL, 3);
light_pin_mux(GMAC0_CRS, 3);
light_pin_cfg(GMAC0_COL, PIN_SPEED_NORMAL, PIN_PU, 2);
light_pin_cfg(GMAC0_CRS, PIN_SPEED_NORMAL, PIN_PU, 2);
}
#else
static void light_iopin_init(void)
{
@@ -1586,10 +1863,18 @@ static void light_usb_boot_check(void)
uchar env_enetaddr[6]={0};
uchar env_enet1addr[6]={0};
int env_ethaddr_flag,env_eth1addr_flag;
int ret = 0;
boot_mode = readl((void *)SOC_OM_ADDRBASE) & 0x7;
if (boot_mode & BIT(2))
return;
/*check board id of uboot image*/
ret = check_image_board_id((uint8_t*)SRAM_BASE_ADDR);
if (ret != 0) {
while(1);
}
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("usb_fastboot", "yes");
#endif

19
board/thead/light-c910/lpddr-regu/ddr_regu.c
View File

@@ -136,7 +136,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
},
};
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
/**
* board for ant-ref
*
@@ -165,6 +165,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
}
};
#else
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
/**
* board for EB064A10/EB064A11
*
@@ -183,6 +184,7 @@ static const struct regulator_t g_regu_id_list[] = {
REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_1V1,0x5A,0xA7,0,1,CONFIG_DDR_REGU_1V1,800000,1500000,20000,0),
}
};
#endif
static const struct regulator_t g_apcpu_regu_id_list[] = {
{
@@ -236,7 +238,7 @@ static int wait_iic_receive(dw_iic_regs_t *iic_base, uint32_t wait_data_num, uin
}
unsigned long soc_get_iic_freq(uint32_t idx)
static unsigned long soc_get_iic_freq(uint32_t idx)
{
if (idx == IIC_IDX_AONIIC){
return 49152000U;
@@ -651,6 +653,7 @@ int32_t csi_iic_mem_receive_sr(csi_iic_t *iic, uint32_t devaddr, uint16_t memadd
return read_count;
}
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A) ||defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
static int pmic_read_reg_sr(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
{
int32_t num;
@@ -662,6 +665,7 @@ static int pmic_read_reg_sr(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t off
*val = temp[0];
return 0;
}
#endif
static int pmic_write_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t val)
{
@@ -688,6 +692,7 @@ static int pmic_write_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offse
return 0;
}
#if !defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A) && !defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
static int pmic_read_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
{
int32_t num;
@@ -716,6 +721,7 @@ static int pmic_read_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset
*val = temp[0];
return 0;
}
#endif
static int _pmic_ddr_regu_init(uint32_t idx)
{
@@ -818,13 +824,14 @@ int pmic_ddr_regu_init(void)
int pmic_ddr_set_voltage(void)
{
int ret = 0;
#if 0 //currently,no need to modify ddr regulator voltage
uint32_t val = 0;
uint32_t regu_num = ARRAY_SIZE(g_regu_id_list);
uint32_t i;
struct regulator_t *pregu;
csi_iic_t *dev_handle;
#if 0 //currently,no need to modify ddr regulator voltage
pregu = (struct regulator_t*)g_regu_id_list;
for (i = 0; i < regu_num; i++, pregu++) {
if (pregu->regu_vol_target < pregu->regu_vol_min || pregu->regu_vol_target > pregu->regu_vol_max)
@@ -838,6 +845,10 @@ int pmic_ddr_set_voltage(void)
#endif
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
uint32_t val = 0;
struct regulator_t *pregu;
csi_iic_t *dev_handle;
/*enable lcd0_en ldo*/
pregu = (struct regulator_t*)&g_regu_id_list[LCD0_EN];
dev_handle = pmic_get_iic_handle(pregu->iic_id);
@@ -944,7 +955,7 @@ int pmic_reset_apcpu_voltage(void)
return ret;
return 0;
}
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
int pmic_reset_apcpu_voltage(void)
{
int ret = -1;

2
board/thead/light-c910/lpddr4/include/ddr_common_func.h
View File

@@ -48,5 +48,5 @@ void ctrl_init(int rank_num, int speed);
void addrmap(int rank_num, enum DDR_BITWIDTH bits);
void ctrl_en(enum DDR_BITWIDTH bits);
void enable_auto_refresh(void);
void lpddr4_auto_selref(void);
#endif // DDR_COMMON_FUNCE_H

13
board/thead/light-c910/lpddr4/src/ddr_common_func.c
View File

@@ -14,6 +14,9 @@ unsigned long get_ddr_density() {
#ifdef CONFIG_DDR_DUAL_RANK
mul = 2;
#endif
#ifdef CONFIG_DDR_DDP
mul *= 2;
#endif
#ifdef CONFIG_DDR_H32_MODE
div = 2;
#endif
@@ -873,7 +876,11 @@ if(bits==64) {
#endif
wr(ADDRMAP0,0x0004001f); // +2
if(rank_num==2) {
#ifdef CONFIG_DDR_DDP
wr(ADDRMAP0,0x00040019);//16GB
#else
wr(ADDRMAP0,0x00040018);//8GB
#endif
}
wr(ADDRMAP1,0x00090909); //bank +2
wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2 +2
@@ -881,7 +888,11 @@ if(bits==64) {
wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0 +6
wr(ADDRMAP6,0x08080808);
#ifdef CONFIG_DDR_DDP
wr(ADDRMAP7,0x00000f08);
#else
wr(ADDRMAP7,0x00000f0f);
#endif
wr(ADDRMAP9,0x08080808);
wr(ADDRMAP10,0x08080808);
wr(ADDRMAP11,0x00000008);
@@ -1121,7 +1132,7 @@ void ddr_soc_pll_disable () {
printf("DDR SOC PLL PowerDown \n");
#endif
}
void lpddr4_auto_selref()
void lpddr4_auto_selref(void)
{
ddr_sysreg_wr(DDR_CFG1,0xa0000); //remove core clock after xx
wr(SWCTL,0);

984
board/thead/light-c910/lpddr4/src/lpddr4_init.c
View File

@@ -26,11 +26,993 @@ void lpddr4_init(enum DDR_TYPE type, int rank_num, int speed, enum DDR_BITWIDTH
lp4_phy_train1d2d(type, speed, bits);
dwc_ddrphy_phyinit_regInterface();
ctrl_en(bits);
enable_axi_port(0x1f);
enable_auto_refresh();
lpddr4_auto_selref();
}
static const uint32_t RetRegList_addr[934] =
{
0x1005f,
0x1015f,
0x1105f,
0x1115f,
0x1205f,
0x1215f,
0x1305f,
0x1315f,
0x55,
0x1055,
0x2055,
0x3055,
0x4055,
0x5055,
0x200c5,
0x2002e,
0x90204,
0x20024,
0x2003a,
0x2007d,
0x2007c,
0x20056,
0x1004d,
0x1014d,
0x1104d,
0x1114d,
0x1204d,
0x1214d,
0x1304d,
0x1314d,
0x10049,
0x10149,
0x11049,
0x11149,
0x12049,
0x12149,
0x13049,
0x13149,
0x43,
0x1043,
0x2043,
0x3043,
0x4043,
0x5043,
0x20018,
0x20075,
0x20050,
0x2009b,
0x20008,
0x20088,
0x200b2,
0x10043,
0x10143,
0x11043,
0x11143,
0x12043,
0x12143,
0x13043,
0x13143,
0x200fa,
0x20019,
0x200f0,
0x200f1,
0x200f2,
0x200f3,
0x200f4,
0x200f5,
0x200f6,
0x200f7,
0x20025,
0x2002d,
0x20021,
0x2002c,
0xd0000,
0x90000,
0x90001,
0x90002,
0x90003,
0x90004,
0x90005,
0x90029,
0x9002a,
0x9002b,
0x9002c,
0x9002d,
0x9002e,
0x9002f,
0x90030,
0x90031,
0x90032,
0x90033,
0x90034,
0x90035,
0x90036,
0x90037,
0x90038,
0x90039,
0x9003a,
0x9003b,
0x9003c,
0x9003d,
0x9003e,
0x9003f,
0x90040,
0x90041,
0x90042,
0x90043,
0x90044,
0x90045,
0x90046,
0x90047,
0x90048,
0x90049,
0x9004a,
0x9004b,
0x9004c,
0x9004d,
0x9004e,
0x9004f,
0x90050,
0x90051,
0x90052,
0x90053,
0x90054,
0x90055,
0x90056,
0x90057,
0x90058,
0x90059,
0x9005a,
0x9005b,
0x9005c,
0x9005d,
0x9005e,
0x9005f,
0x90060,
0x90061,
0x90062,
0x90063,
0x90064,
0x90065,
0x90066,
0x90067,
0x90068,
0x90069,
0x9006a,
0x9006b,
0x9006c,
0x9006d,
0x9006e,
0x9006f,
0x90070,
0x90071,
0x90072,
0x90073,
0x90074,
0x90075,
0x90076,
0x90077,
0x90078,
0x90079,
0x9007a,
0x9007b,
0x9007c,
0x9007d,
0x9007e,
0x9007f,
0x90080,
0x90081,
0x90082,
0x90083,
0x90084,
0x90085,
0x90086,
0x90087,
0x90088,
0x90089,
0x9008a,
0x9008b,
0x9008c,
0x9008d,
0x9008e,
0x9008f,
0x90090,
0x90091,
0x90092,
0x90093,
0x90094,
0x90095,
0x90096,
0x90097,
0x90098,
0x90099,
0x9009a,
0x9009b,
0x9009c,
0x9009d,
0x9009e,
0x9009f,
0x900a0,
0x900a1,
0x900a2,
0x900a3,
0x40000,
0x40020,
0x40040,
0x40060,
0x40001,
0x40021,
0x40041,
0x40061,
0x40002,
0x40022,
0x40042,
0x40062,
0x40003,
0x40023,
0x40043,
0x40063,
0x40004,
0x40024,
0x40044,
0x40064,
0x40005,
0x40025,
0x40045,
0x40065,
0x40006,
0x40026,
0x40046,
0x40066,
0x40007,
0x40027,
0x40047,
0x40067,
0x40008,
0x40028,
0x40048,
0x40068,
0x40009,
0x40029,
0x40049,
0x40069,
0x4000a,
0x4002a,
0x4004a,
0x4006a,
0x4000b,
0x4002b,
0x4004b,
0x4006b,
0x4000c,
0x4002c,
0x4004c,
0x4006c,
0x4000d,
0x4002d,
0x4004d,
0x4006d,
0x4000e,
0x4002e,
0x4004e,
0x4006e,
0x4000f,
0x4002f,
0x4004f,
0x4006f,
0x40010,
0x40030,
0x40050,
0x40070,
0x40011,
0x40031,
0x40051,
0x40071,
0x40012,
0x40032,
0x40052,
0x40072,
0x40013,
0x40033,
0x40053,
0x40073,
0x40014,
0x40034,
0x40054,
0x40074,
0x40015,
0x40035,
0x40055,
0x40075,
0x40016,
0x40036,
0x40056,
0x40076,
0x40017,
0x40037,
0x40057,
0x40077,
0x40018,
0x40038,
0x40058,
0x40078,
0x40019,
0x40039,
0x40059,
0x40079,
0x4001a,
0x4003a,
0x4005a,
0x4007a,
0x900a4,
0x900a5,
0x900a6,
0x900a7,
0x900a8,
0x900a9,
0x900aa,
0x900ab,
0x900ac,
0x900ad,
0x900ae,
0x900af,
0x900b0,
0x900b1,
0x900b2,
0x900b3,
0x900b4,
0x900b5,
0x900b6,
0x900b7,
0x900b8,
0x900b9,
0x900ba,
0x900bb,
0x900bc,
0x900bd,
0x900be,
0x900bf,
0x900c0,
0x900c1,
0x900c2,
0x900c3,
0x900c4,
0x900c5,
0x900c6,
0x900c7,
0x900c8,
0x900c9,
0x900ca,
0x900cb,
0x900cc,
0x900cd,
0x900ce,
0x900cf,
0x900d0,
0x900d1,
0x900d2,
0x900d3,
0x900d4,
0x900d5,
0x900d6,
0x900d7,
0x900d8,
0x900d9,
0x900da,
0x900db,
0x900dc,
0x900dd,
0x900de,
0x900df,
0x900e0,
0x900e1,
0x900e2,
0x900e3,
0x900e4,
0x900e5,
0x900e6,
0x900e7,
0x900e8,
0x900e9,
0x900ea,
0x900eb,
0x900ec,
0x900ed,
0x900ee,
0x900ef,
0x900f0,
0x900f1,
0x900f2,
0x900f3,
0x900f4,
0x900f5,
0x900f6,
0x900f7,
0x900f8,
0x900f9,
0x900fa,
0x900fb,
0x900fc,
0x900fd,
0x900fe,
0x900ff,
0x90100,
0x90101,
0x90102,
0x90103,
0x90104,
0x90105,
0x90106,
0x90107,
0x90108,
0x90109,
0x9010a,
0x9010b,
0x9010c,
0x9010d,
0x9010e,
0x9010f,
0x90110,
0x90111,
0x90112,
0x90113,
0x90114,
0x90115,
0x90116,
0x90117,
0x90118,
0x90119,
0x9011a,
0x9011b,
0x9011c,
0x9011d,
0x9011e,
0x9011f,
0x90120,
0x90121,
0x90122,
0x90123,
0x90124,
0x90125,
0x90126,
0x90127,
0x90128,
0x90129,
0x9012a,
0x9012b,
0x9012c,
0x9012d,
0x9012e,
0x9012f,
0x90130,
0x90131,
0x90132,
0x90133,
0x90134,
0x90135,
0x90136,
0x90137,
0x90138,
0x90139,
0x9013a,
0x9013b,
0x9013c,
0x9013d,
0x9013e,
0x9013f,
0x90140,
0x90141,
0x90142,
0x90143,
0x90144,
0x90145,
0x90146,
0x90147,
0x90148,
0x90149,
0x9014a,
0x9014b,
0x9014c,
0x9014d,
0x9014e,
0x9014f,
0x90150,
0x90151,
0x90152,
0x90153,
0x90154,
0x90155,
0x90156,
0x90157,
0x90158,
0x90159,
0x9015a,
0x9015b,
0x9015c,
0x9015d,
0x9015e,
0x9015f,
0x90160,
0x90161,
0x90162,
0x90163,
0x90164,
0x90165,
0x90166,
0x90167,
0x90168,
0x90169,
0x9016a,
0x9016b,
0x9016c,
0x9016d,
0x9016e,
0x9016f,
0x90170,
0x90171,
0x90172,
0x90173,
0x90174,
0x90175,
0x90176,
0x90177,
0x90178,
0x90179,
0x9017a,
0x9017b,
0x9017c,
0x9017d,
0x9017e,
0x9017f,
0x90180,
0x90181,
0x90006,
0x90007,
0x90008,
0x90009,
0x9000a,
0x9000b,
0xd00e7,
0x90017,
0x9001f,
0x90026,
0x400d0,
0x400d1,
0x400d2,
0x400d3,
0x400d4,
0x400d5,
0x400d6,
0x400d7,
0x200be,
0x2000b,
0x2000c,
0x2000d,
0x2000e,
0x9000c,
0x9000d,
0x9000e,
0x9000f,
0x90010,
0x90011,
0x90012,
0x90013,
0x20010,
0x20011,
0x40080,
0x40081,
0x40082,
0x40083,
0x40084,
0x40085,
0x400fd,
0x10011,
0x10012,
0x10013,
0x10018,
0x10002,
0x100b2,
0x101b4,
0x102b4,
0x103b4,
0x104b4,
0x105b4,
0x106b4,
0x107b4,
0x108b4,
0x11011,
0x11012,
0x11013,
0x11018,
0x11002,
0x110b2,
0x111b4,
0x112b4,
0x113b4,
0x114b4,
0x115b4,
0x116b4,
0x117b4,
0x118b4,
0x12011,
0x12012,
0x12013,
0x12018,
0x12002,
0x120b2,
0x121b4,
0x122b4,
0x123b4,
0x124b4,
0x125b4,
0x126b4,
0x127b4,
0x128b4,
0x13011,
0x13012,
0x13013,
0x13018,
0x13002,
0x130b2,
0x131b4,
0x132b4,
0x133b4,
0x134b4,
0x135b4,
0x136b4,
0x137b4,
0x138b4,
0x20089,
0xc0080,
0x200cb,
0x10068,
0x10069,
0x10168,
0x10169,
0x10268,
0x10269,
0x10368,
0x10369,
0x10468,
0x10469,
0x10568,
0x10569,
0x10668,
0x10669,
0x10768,
0x10769,
0x10868,
0x10869,
0x100aa,
0x10062,
0x10001,
0x100a0,
0x100a1,
0x100a2,
0x100a3,
0x100a4,
0x100a5,
0x100a6,
0x100a7,
0x11068,
0x11069,
0x11168,
0x11169,
0x11268,
0x11269,
0x11368,
0x11369,
0x11468,
0x11469,
0x11568,
0x11569,
0x11668,
0x11669,
0x11768,
0x11769,
0x11868,
0x11869,
0x110aa,
0x11062,
0x11001,
0x110a0,
0x110a1,
0x110a2,
0x110a3,
0x110a4,
0x110a5,
0x110a6,
0x110a7,
0x12068,
0x12069,
0x12168,
0x12169,
0x12268,
0x12269,
0x12368,
0x12369,
0x12468,
0x12469,
0x12568,
0x12569,
0x12668,
0x12669,
0x12768,
0x12769,
0x12868,
0x12869,
0x120aa,
0x12062,
0x12001,
0x120a0,
0x120a1,
0x120a2,
0x120a3,
0x120a4,
0x120a5,
0x120a6,
0x120a7,
0x13068,
0x13069,
0x13168,
0x13169,
0x13268,
0x13269,
0x13368,
0x13369,
0x13468,
0x13469,
0x13568,
0x13569,
0x13668,
0x13669,
0x13768,
0x13769,
0x13868,
0x13869,
0x130aa,
0x13062,
0x13001,
0x130a0,
0x130a1,
0x130a2,
0x130a3,
0x130a4,
0x130a5,
0x130a6,
0x130a7,
0x80,
0x1080,
0x2080,
0x3080,
0x4080,
0x5080,
0x10020,
0x10080,
0x10081,
0x100d0,
0x100d1,
0x1008c,
0x1008d,
0x10180,
0x10181,
0x101d0,
0x101d1,
0x1018c,
0x1018d,
0x100c0,
0x100c1,
0x101c0,
0x101c1,
0x102c0,
0x102c1,
0x103c0,
0x103c1,
0x104c0,
0x104c1,
0x105c0,
0x105c1,
0x106c0,
0x106c1,
0x107c0,
0x107c1,
0x108c0,
0x108c1,
0x100ae,
0x100af,
0x11020,
0x11080,
0x11081,
0x110d0,
0x110d1,
0x1108c,
0x1108d,
0x11180,
0x11181,
0x111d0,
0x111d1,
0x1118c,
0x1118d,
0x110c0,
0x110c1,
0x111c0,
0x111c1,
0x112c0,
0x112c1,
0x113c0,
0x113c1,
0x114c0,
0x114c1,
0x115c0,
0x115c1,
0x116c0,
0x116c1,
0x117c0,
0x117c1,
0x118c0,
0x118c1,
0x110ae,
0x110af,
0x12020,
0x12080,
0x12081,
0x120d0,
0x120d1,
0x1208c,
0x1208d,
0x12180,
0x12181,
0x121d0,
0x121d1,
0x1218c,
0x1218d,
0x120c0,
0x120c1,
0x121c0,
0x121c1,
0x122c0,
0x122c1,
0x123c0,
0x123c1,
0x124c0,
0x124c1,
0x125c0,
0x125c1,
0x126c0,
0x126c1,
0x127c0,
0x127c1,
0x128c0,
0x128c1,
0x120ae,
0x120af,
0x13020,
0x13080,
0x13081,
0x130d0,
0x130d1,
0x1308c,
0x1308d,
0x13180,
0x13181,
0x131d0,
0x131d1,
0x1318c,
0x1318d,
0x130c0,
0x130c1,
0x131c0,
0x131c1,
0x132c0,
0x132c1,
0x133c0,
0x133c1,
0x134c0,
0x134c1,
0x135c0,
0x135c1,
0x136c0,
0x136c1,
0x137c0,
0x137c1,
0x138c0,
0x138c1,
0x130ae,
0x130af,
0x90201,
0x90202,
0x90203,
0x90205,
0x90206,
0x90207,
0x90208,
0x20020,
0x20077,
0x20072,
0x20073,
0x400c0,
0x10040,
0x10140,
0x10240,
0x10340,
0x10440,
0x10540,
0x10640,
0x10740,
0x10840,
0x11040,
0x11140,
0x11240,
0x11340,
0x11440,
0x11540,
0x11640,
0x11740,
0x11840,
0x12040,
0x12140,
0x12240,
0x12340,
0x12440,
0x12540,
0x12640,
0x12740,
0x12840,
0x13040,
0x13140,
0x13240,
0x13340,
0x13440,
0x13540,
0x13640,
0x13740,
0x13840,
};
typedef struct Reg_Addr_Val {
uint32_t Address; ///< register address
uint16_t Value0; ///< register value phy0
uint16_t Value1; ///< register value phy1
} Reg_Addr_Val_t;
typedef struct Reg_Addr_Value {
uint32_t reg_num;
Reg_Addr_Val_t reg[0];
} Reg_Addr_Value_t;
int NumRegSaved = 934; ///< Current Number of registers saved.
#define SRAM_E902_BASEADDR 0xFFFFEF8000
#define DDR_PHY_REG_SAVEADDR (SRAM_E902_BASEADDR + 0xDF00)
Reg_Addr_Value_t *pRetRegList = (Reg_Addr_Value_t *)DDR_PHY_REG_SAVEADDR;
int dwc_ddrphy_phyinit_regInterface() {
ddr_phy_reg_wr(0xd0000, 0x0);
ddr_phy_reg_wr(0xc0080, 0x3);
pRetRegList->reg_num = NumRegSaved;
// go through all the tracked registers, issue a register read and place
// the result in the data structure for future recovery.
int regIndx = 0;
uint16_t data;
for (regIndx = 0; regIndx < NumRegSaved; regIndx++)
{
data = ddr_phy0_reg_rd(RetRegList_addr[regIndx]);
pRetRegList->reg[regIndx].Value0 = data;
pRetRegList->reg[regIndx].Address = RetRegList_addr[regIndx];
}
#ifndef CONFIG_DDR_H32_MODE
for (regIndx = 0; regIndx < NumRegSaved; regIndx++)
{
data = ddr_phy1_reg_rd(RetRegList_addr[regIndx]);
pRetRegList->reg[regIndx].Value1 = data;
}
#endif
ddr_phy_reg_wr(0xc0080, 0x2);
ddr_phy_reg_wr(0xd0000, 0x1);
return 1;
}

436
board/thead/light-c910/sbmeta/sbmeta.c Normal file
View File

@@ -0,0 +1,436 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited
*/
#include "sbmeta.h"
#include "sec_crypto_sha.h"
#define LOGLEVEL_ERROR 1
#define LOGLEVEL_INFO 2
#define LOGLEVEL_DEBUG 3
#define SBMETA_LOGLEVEL 1
#define trace_printer(level, fmt,...) printf("%s"fmt, level, ##__VA_ARGS__)
#if (SBMETA_LOGLEVEL < 1)
#define EMSG(...)
#else
#define EMSG(fmt, args...) trace_printer("error: ", fmt, ##args)
#endif
#if (SBMETA_LOGLEVEL < 2)
#define IMSG(...)
#else
#define IMSG(fmt, args...) trace_printer("info: ", fmt, ##args)
#endif
#if (SBMETA_LOGLEVEL < 3)
#define DMSG(...)
#else
#define DMSG(fmt, args...) trace_printer("", fmt, ##args)
#endif
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
/* digest_size corresponding to digest_scheme specified in sbmeta_info_t */
static const int digest_size[] = {0, 20, 16, 28, 32, 48, 64, 32};
static const char* image_name_s[] = {
"dtb", "kernel", "tf", "aon", "rootfs", "tee", "uboot", "user"
};
/* index to get sc_sha_mode_t value */
static const int sha_idx2ctl[] = {0, 1, 8, 3, 2, 5, 4, 9};
static const unsigned long image_addrs[] = {
LIGHT_DTB_ADDR,
LIGHT_KERNEL_ADDR,
LIGHT_TF_FW_TMP_ADDR,
LIGHT_AON_FW_ADDR,
LIGHT_ROOTFS_ADDR,
LIGHT_TEE_FW_ADDR,
CONFIG_SYS_TEXT_BASE,
};
typedef struct {
int magiccode;
uint8_t dev;
uint8_t part;
uint8_t image_type;
uint8_t digest_scheme;
uint8_t sign_scheme;
uint8_t isencrypted;
uint8_t medium_type;
uint8_t checksum_scheme;
char filename[MAX_NAME_SIZE];
uint8_t digest[MAX_DIGEST_SIZE];
uint32_t relocated_addr;
uint32_t reserved[4];
} sbmeta_info_t;
static int is_sbmeta_info(uint32_t entry_src_addr)
{
uint32_t *buffer = (uint32_t *)(uintptr_t)entry_src_addr;
/* sbmeta_info_t entry should start with magic code 'S''B''M''T' */
if (*buffer != SBMETA_MAGIC) {
return CMD_RET_FAILURE;
}
return 0;
}
static int dump_sbmeta_info(sbmeta_info_t *sbmeta_info)
{
if (sbmeta_info == NULL) {
return CMD_RET_FAILURE;
}
/* only support emmc now */
if (sbmeta_info->medium_type != 0) {
EMSG("medium type %d is not supported now\r\n", sbmeta_info->medium_type);
return CMD_RET_FAILURE;
}
/* only support dtb, krlimg/tf, sbi, aon, rootfs, tee, uboot and user-defined type */
if (sbmeta_info->image_type > IMAGE_TYPE_NUM || sbmeta_info->image_type < 0) {
EMSG("image type is out of range\r\n");
return CMD_RET_FAILURE;
}
/* only support none, sha1, md5, sha224, sha256, sha384, sha512, sm3 and reserved scheme */
if (sbmeta_info->digest_scheme > DIGEST_TYPE_NUM || sbmeta_info->digest_scheme < 0) {
EMSG("digest type is out of range\r\n");
return CMD_RET_FAILURE;
}
/* only support none, rsa1024, rsa2048, ecc256, ecc160, sm2 and reserved scheme */
if (sbmeta_info->sign_scheme > SIGN_TYPE_NUM || sbmeta_info->sign_scheme < 0) {
EMSG("signature type is out of range\r\n");
return CMD_RET_FAILURE;
}
/* DTB, TF, TEE, Kernel will be loaded from default partitions specified in env */
if (sbmeta_info->image_type != T_ROOTFS && sbmeta_info->image_type != T_USER) {
IMSG("Image has been loaded\r\n");
}
/* dump sbmeta_info_t */
DMSG("image medium type: %d\n", sbmeta_info->medium_type);
DMSG("image load part: mmc %d:%d\n", sbmeta_info->dev, sbmeta_info->part);
DMSG("image type: %d \n", sbmeta_info->image_type);
DMSG("image digest scheme: %d\n", sbmeta_info->digest_scheme);
DMSG("image sign scheme: %d\n", sbmeta_info->sign_scheme);
DMSG("image enable encryption: %s\n", sbmeta_info->isencrypted ? "en" : "dis");
DMSG("image file name: %s\n", sbmeta_info->filename);
DMSG("image digest:");
for (int i = 0; i < digest_size[sbmeta_info->digest_scheme]; i++) {
DMSG("%02X", sbmeta_info->digest[i]);
}
DMSG("\r\n");
DMSG("\n\n");
return 0;
}
static int sbmeta_field_verify(sbmeta_info_t *sbmeta_info, unsigned long img_src_addr)
{
uint8_t digest_scheme = 0;
uint8_t sign_scheme = 0;
uint8_t is_encrypted = 0;
img_header_t *phead = NULL;
if (sbmeta_info == NULL) {
return CMD_RET_FAILURE;
}
/* if image has secure header, check with sbmeta field */
if (image_have_head(img_src_addr)) {
phead = (img_header_t *)img_src_addr;
digest_scheme = phead->digest_scheme;
sign_scheme = phead->signature_scheme;
is_encrypted = (phead->option_flag & 0x2) >> 1;
}
if (sbmeta_info->digest_scheme != digest_scheme) {
EMSG("digest type %d is not expected: %d\r\n", digest_scheme, sbmeta_info->digest_scheme);
return CMD_RET_FAILURE;
}
/* only support none, rsa1024, rsa2048, ecc256, ecc160, sm2 and reserved scheme */
if (sbmeta_info->sign_scheme != sign_scheme) {
EMSG("signature type %d is not expected: %d\r\n", sign_scheme, sbmeta_info->sign_scheme);
return CMD_RET_FAILURE;
}
if (sbmeta_info->isencrypted != is_encrypted) {
EMSG("encryption %d is not expected: %d\r\n", is_encrypted, sbmeta_info->isencrypted);
return CMD_RET_FAILURE;
}
return 0;
}
static int check_digest(uint8_t *buffer, uint32_t buffer_size, uint8_t digest_scheme, uint8_t *digest)
{
uint32_t len = 0;
uint8_t sum[64];
sc_sha_t sha;
sc_sha_context_t ctx;
int mode = 0;
if (!buffer || digest_scheme > DIGEST_TYPE_NUM) {
EMSG("wrong parameter\r\n");
return CMD_RET_FAILURE;
}
if (digest_scheme == 0) {
return 0;
}
mode = sha_idx2ctl[digest_scheme];
if (sc_sha_init(&sha, 0) != 0) {
EMSG("sha initialize failed\r\n");
return CMD_RET_FAILURE;
}
if (sc_sha_start(&sha, &ctx, mode) != 0) {
EMSG("sha start failed\r\n");
return CMD_RET_FAILURE;
}
if (sc_sha_update(&sha, &ctx, buffer, buffer_size) != 0) {
EMSG("sha update failed\r\n");
return CMD_RET_FAILURE;
}
if (sc_sha_finish(&sha, &ctx, sum, &len) != 0) {
EMSG("sha finish failed\r\n");
return CMD_RET_FAILURE;
}
sc_sha_uninit(&sha);
/* check digest value */
if (memcmp(digest, sum, len) != 0) {
EMSG("check digest failed\r\n");
return CMD_RET_FAILURE;
}
return 0;
}
/* Verify image specified in sbmeta_info_t. The image has been loaded to memory before */
static int sbmeta_verify_image(uint32_t image_load_addr, sbmeta_info_t *sbmeta_info)
{
uint32_t image_size = 0;
const char *image_name;
uint8_t image_type = sbmeta_info->image_type;
uint8_t checksum_scheme = sbmeta_info->checksum_scheme;
uint8_t *digest = sbmeta_info->digest;
uint8_t is_encrypted = sbmeta_info->isencrypted;
uint32_t security_level = env_get_hex("sbmeta_security_level", 3);
uint32_t filesize = 0;
char buf[64] = {0};
/* check image_type to avoid array index out of bounds */
if (image_type > IMAGE_TYPE_NUM || image_type < 0) {
EMSG("image type is out of range\r\n");
return CMD_RET_FAILURE;
}
image_name = image_name_s[image_type];
/* check tee/tf version if needed */
#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
if (image_have_head(image_load_addr) == 1) {
if (image_type == T_TF) {
IMSG("check TF version in boot \n");
if (check_tf_version_in_boot(LIGHT_TF_FW_TMP_ADDR) != 0) {
return CMD_RET_FAILURE;
}
}
if (image_type == T_TEE) {
IMSG("check TEE version in boot \n");
if (check_tee_version_in_boot(LIGHT_TEE_FW_ADDR) != 0) {
return CMD_RET_FAILURE;
}
}
}
#endif
/* start verifying images */
IMSG("Process %s image verification ...\n", image_name);
if (security_level == 3 || is_encrypted != 0) {
if (verify_customer_image(image_type, image_load_addr) != 0) {
return CMD_RET_FAILURE;
}
} else if (security_level == 2) {
if (memcmp(digest, buf, 64) == 0) {
EMSG("sbmeta info doesn't specify digest value in security level 2\r\n");
return CMD_RET_FAILURE;
}
snprintf(buf, sizeof(buf), "ext4size mmc %x:%x %s", sbmeta_info->dev, sbmeta_info->part, sbmeta_info->filename);
if (run_command(buf, 0) != 0) {
EMSG("get file size error\r\n");
return CMD_RET_FAILURE;
}
filesize = env_get_hex("filesize", 0);
if (check_digest((uint8_t *)(uintptr_t)image_load_addr, filesize, checksum_scheme, digest) != 0) {
return CMD_RET_FAILURE;
}
}
/* move image headers always */
if (image_have_head(image_load_addr) == 1) {
image_size = get_image_size(image_load_addr);
IMSG("%s image size: %d\n", image_name, image_size);
if (image_size < 0) {
EMSG("GET %s image size error\n", image_name);
return CMD_RET_FAILURE;
}
if (image_type == T_TF) {
memmove((void *)(uintptr_t)LIGHT_TF_FW_ADDR, (const void *)(uintptr_t)(image_load_addr + HEADER_SIZE), image_size);
} else {
memmove((void *)(uintptr_t)image_load_addr, (const void *)(uintptr_t)(image_load_addr + HEADER_SIZE), image_size);
}
} else {
/* TF should be moved to LIGHT_TF_FW_ADDR all the cases*/
if (image_type == T_TF) {
/* while image_size is unknown, reload the image */
run_command("ext4load mmc 0:3 0x0 trust_firmware.bin", 0);
}
}
return 0;
}
static int light_sbmetaboot(int argc, char *const argv[])
{
int count = 0;
uint32_t sbmeta_size = 0;
uint32_t info_addr = 0;
uint32_t image_load_addr = 0;
char cmd[64] = {0};
sbmeta_info_t *sbmeta_info = NULL;
/* Load sbmeta image to memory */
snprintf(cmd, sizeof(cmd), "ext4load mmc $mmcdev:%x 0x%p %s", SBMETA_PART, (void *)(uintptr_t)LIGHT_SBMETA_ADDR, SBMETA_FILENAME);
if (run_command(cmd, 0) != 0) {
/* if sbmeta doesn't exist, do secboot by default */
IMSG("SBMETA doesn't exist, go to verify tf/tee\r\n");
/*
* Verify tf and tee by command secboot.
* Note that tf and tee has been loaded in "run bootcmd_load"
*/
if (run_command("secboot", 0) != 0) {
return CMD_RET_FAILURE;
}
return 0;
}
/* initialize crypto algorithm interfaces */
if (csi_sec_init() != 0) {
return CMD_RET_FAILURE;
}
/* Check and verify sbmeta image */
if (image_have_head(LIGHT_SBMETA_ADDR) == 1) {
#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
IMSG("check SBMETA version in boot \n");
ret = check_sbmeta_version_in_boot(LIGHT_SBMETA_ADDR);
if (ret != 0) {
return CMD_RET_FAILURE;
}
#endif
IMSG("Process SBMETA image verification...\r\n");
if (verify_customer_image(T_SBMETA, LIGHT_SBMETA_ADDR) != 0) {
return CMD_RET_FAILURE;
}
sbmeta_size = get_image_size(LIGHT_SBMETA_ADDR);
IMSG("sbmeta_size:%d\r\n", sbmeta_size);
if (sbmeta_size != SBMETA_SIZE) {
EMSG("SBMETA header is wrong! Size must equal to %d bytes!\r\n", SBMETA_SIZE);
return CMD_RET_FAILURE;
}
/* move image headers always */
memmove((void *)LIGHT_SBMETA_ADDR, (const void *)(LIGHT_SBMETA_ADDR + HEADER_SIZE), sbmeta_size);
} else {
/* if sbmeta image is not secure, reset */
IMSG("SBMETA image must be with signature\r\n");
return CMD_RET_FAILURE;
}
/* Parse sbmeta_info_t in image sbmeta, then load and verify specified images */
info_addr = LIGHT_SBMETA_ADDR;
for (count = 0; count < MAX_ENTRY_NUM; count++) {
if (is_sbmeta_info(info_addr) == 0) {
/* Dump and check sbmeta info */
sbmeta_info = (sbmeta_info_t *)(uintptr_t)info_addr;
if (dump_sbmeta_info(sbmeta_info) != 0) {
return CMD_RET_FAILURE;
}
info_addr += ENTRY_SIZE;
/*
* If image_type != T_USER, load to address specified in light-c910.h;
* otherwise, load to user-specified address.
*/
if (sbmeta_info->image_type != T_USER) {
image_load_addr = image_addrs[sbmeta_info->image_type];
} else {
image_load_addr = sbmeta_info->relocated_addr;
}
/*
* Load image specified in sbmeta info
* Note: only load images don't exist in env "bootcmd_load"
*/
if (sbmeta_info->image_type == T_ROOTFS || sbmeta_info->image_type == T_USER) {
snprintf(cmd, sizeof(cmd), "ext4load mmc %x:%x %p %s", sbmeta_info->dev,
sbmeta_info->part, \
(void *)(uintptr_t)image_load_addr, sbmeta_info->filename);
if (run_command(cmd, 0) != 0) {
return CMD_RET_FAILURE;
}
}
if (sbmeta_field_verify(sbmeta_info, image_load_addr) != 0) {
return CMD_RET_FAILURE;
}
/* Check and verify user-specified image */
if (sbmeta_verify_image(image_load_addr, sbmeta_info) != 0) {
return CMD_RET_FAILURE;
}
} else {
break;
}
}
/* if sbmeta didn't specify images, reset */
if (count == 0) {
EMSG("SBMETA doesn't specify any images!\r\n");
return CMD_RET_FAILURE;
}
/* Clear sbmeta buffer in memory */
memset((void *)LIGHT_SBMETA_ADDR, 0, PLAIN_SBMETA_TEXT);
return 0;
}
static int do_sbmetaboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
if (light_sbmetaboot(argc, argv) != 0) {
EMSG("sbmetaboot failed\r\n");
while (1);
return CMD_RET_FAILURE;
}
return 0;
}
U_BOOT_CMD(
sbmetaboot, CONFIG_SYS_MAXARGS, 1, do_sbmetaboot,
"load and verify image sbmeta, then verify image files specified in sbmeta",
""
);
#endif
#endif

34
board/thead/light-c910/sbmeta/sbmeta.h Normal file
View File

@@ -0,0 +1,34 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited
*/
#ifndef _LIGHT_SBMETA_H
#define _LIGHT_SBMETA_H
#include "common.h"
#include "command.h"
#include <asm/arch-thead/boot_mode.h>
#define MAX_NAME_SIZE 32
#define MAX_DIGEST_SIZE 64
#define SBMETA_MAGIC 0x544D4253 /* = {'S', 'B', 'M', 'T'} */
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
#define LIGHT_SBMETA_ADDR 0x10000000
#endif
#define SBMETA_PART 5
#define ENTRY_SIZE 128
#define PLAIN_SBMETA_TEXT 4096
#define SBMETA_SIZE 4736 /* 4K SMBETA image + 640 footer */
#define MAX_ENTRY_NUM PLAIN_SBMETA_TEXT / ENTRY_SIZE /* 4K/128=32 */
#define IMAGE_TYPE_NUM 7
#define DIGEST_TYPE_NUM 8
#define SIGN_TYPE_NUM 6
#define SBMETA_FILENAME "sbmeta.bin"
#define SBMETA_SECURITY_LEVEL_H 3 /* verify signature and hash */
#define SBMETA_SECURITY_LEVEL_M 2 /* verify checksum */
#define SBMETA_SECURITY_LEVEL_L 1 /* no verification */
#endif

173
board/thead/light-c910/sec_check.c
View File

@@ -12,7 +12,7 @@
#include <asm/arch-thead/boot_mode.h>
#include "../../../lib/sec_library/include/csi_sec_img_verify.h"
extern int csi_efuse_api_int(void);
extern int csi_efuse_api_init(void);
extern int csi_efuse_api_unint(void);
extern int csi_efuse_read_raw(uint32_t addr, void *data, uint32_t cnt);
extern int csi_efuse_write_raw(uint32_t addr, const void *data, uint32_t cnt);
@@ -35,7 +35,7 @@ int csi_sec_init(void)
char *version;
/* Initialize eFuse module */
ret = csi_efuse_api_int();
ret = csi_efuse_api_init();
if (ret) {
printf("efuse init faild[%d]\n", ret);
goto exit;
@@ -62,7 +62,7 @@ void designware_get_mac_from_fuse(unsigned char *mac)
int ret;
/* Initialize eFuse module */
ret = csi_efuse_api_int();
ret = csi_efuse_api_init();
if (ret) {
printf("efuse init faild[%d]\n", ret);
return;
@@ -75,6 +75,89 @@ void designware_get_mac_from_fuse(unsigned char *mac)
}
}
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
/* Secure function for image verificaiton here */
int get_image_version(unsigned long img_src_addr)
{
img_header_t *img = (img_header_t *)img_src_addr;
uint8_t magiccode[4] = {0};
magiccode[3] = img->magic_num & 0xff;
magiccode[2] = (img->magic_num & 0xff00) >> 8;
magiccode[1] = (img->magic_num & 0xff0000) >> 16;
magiccode[0] = (img->magic_num & 0xff000000) >> 24;
if (memcmp(header_magic, magiccode, 4) == 0) {
return -1;
}
return img->image_version;
}
int get_image_size(unsigned long img_src_addr)
{
img_header_t *img = (img_header_t *)img_src_addr;
uint8_t magiccode[4] = {0};
magiccode[3] = img->magic_num & 0xff;
magiccode[2] = (img->magic_num & 0xff00) >> 8;
magiccode[1] = (img->magic_num & 0xff0000) >> 16;
magiccode[0] = (img->magic_num & 0xff000000) >> 24;
if (memcmp(header_magic, magiccode, 4) == 0) {
return -1;
}
return img->image_size;
}
void dump_image_header_info(long addr)
{
img_header_t *phead = (img_header_t *)addr;
printf("\n---------------------------------------------\n");
printf("entry point: 0x%x\n", phead->entry_point);
printf("image size: %d Bytes\n", phead->image_size);
printf("head version: 0x%x\n", phead->head_version);
printf("image version: 0x%x\n", phead->image_version);
printf("image checksum: 0x%x\n", phead->image_checksum);
printf("image run addr: 0x%llx\n", phead->image_run_addr);
printf("image offset: 0x%x\n", phead->image_offset);
printf("image digest scheme: %d\n", phead->digest_scheme);
printf("image sign scheme: %d\n", phead->signature_scheme);
printf("image encrypt type: %d\n", phead->encrypt_type);
printf("\n---------------------------------------------\n");
}
int verify_customer_image(img_type_t type, long addr)
{
int ret;
/* Double check image number */
if (image_have_head(addr) == 0) {
printf("error: image has no secure header\r\n");
return -1;
}
/* Dump image header information here */
dump_image_header_info(addr);
/* Call customer image verification function */
if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG) || (type == T_DTB) || (type == T_SBMETA)) {
ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
if (ret) {
printf("Image(%d) is verified fail, Please go to check!\n\n", type);
return ret;
}
} else if (type == T_UBOOT) {
ret = csi_sec_uboot_image_verify(addr, addr - PUBKEY_HEADER_SIZE);
if (ret) {
printf("Image(%s) is verified fail, Please go to check!\n\n", "uboot");
return ret;
}
}
return 0;
}
#else
static int strtou32(const char *str, unsigned int base, u32 *result)
{
char *ep;
@@ -110,7 +193,7 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
int ret, i;
/* Initialize eFuse module */
ret = csi_efuse_api_int();
ret = csi_efuse_api_init();
if (ret) {
printf("efuse init faild[%d]\n", ret);
goto err;
@@ -180,88 +263,6 @@ err:
return CMD_RET_FAILURE;
}
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
/* Secure function for image verificaiton here */
int get_image_version(unsigned long img_src_addr)
{
img_header_t *img = (img_header_t *)img_src_addr;
uint8_t magiccode[4] = {0};
magiccode[3] = img->magic_num & 0xff;
magiccode[2] = (img->magic_num & 0xff00) >> 8;
magiccode[1] = (img->magic_num & 0xff0000) >> 16;
magiccode[0] = (img->magic_num & 0xff000000) >> 24;
if (memcmp(header_magic, magiccode, 4) == 0) {
return -1;
}
return img->image_version;
}
int get_image_size(unsigned long img_src_addr)
{
img_header_t *img = (img_header_t *)img_src_addr;
uint8_t magiccode[4] = {0};
magiccode[3] = img->magic_num & 0xff;
magiccode[2] = (img->magic_num & 0xff00) >> 8;
magiccode[1] = (img->magic_num & 0xff0000) >> 16;
magiccode[0] = (img->magic_num & 0xff000000) >> 24;
if (memcmp(header_magic, magiccode, 4) == 0) {
return -1;
}
return img->image_size;
}
void dump_image_header_info(long addr)
{
img_header_t *phead = (img_header_t *)addr;
printf("\n---------------------------------------------\n");
printf("entry point: 0x%x\n", phead->entry_point);
printf("image size: %d Bytes\n", phead->image_size);
printf("head version: 0x%x\n", phead->head_version);
printf("image version: 0x%x\n", phead->image_version);
printf("image checksum: 0x%x\n", phead->image_checksum);
printf("image run addr: 0x%llx\n", phead->image_run_addr);
printf("image offset: 0x%x\n", phead->image_offset);
printf("image digest scheme: %d\n", phead->digest_scheme);
printf("image sign scheme: %d\n", phead->signature_scheme);
printf("image encrypt type: %d\n", phead->encrypt_type);
printf("\n---------------------------------------------\n");
}
int verify_customer_image(img_type_t type, long addr)
{
int ret;
const char *image_name = "";
/* Double check image number */
if (image_have_head(addr) == 0)
return -1;
/* Dump image header information here */
dump_image_header_info(addr);
/* Call customer image verification function */
if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG)) {
ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
if (ret) {
printf("Image(%d) is verified fail, Please go to check!\n\n", type);
return ret;
}
} else if (type == T_UBOOT) {
ret = csi_sec_uboot_image_verify(addr, addr - PUBKEY_HEADER_SIZE);
if (ret) {
printf("Image(%s) is verified fail, Please go to check!\n\n", "uboot");
return ret;
}
}
return 0;
}
#else
U_BOOT_CMD(
efuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
"eFuse sub-system",

239
board/thead/light-c910/secimg_load.c Normal file
View File

@@ -0,0 +1,239 @@
/*
* (C) Copyright 2018, Linaro Limited
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <command.h>
#include <env.h>
#include <configs/light-c910.h>
#include <asm/arch-thead/boot_mode.h>
#include "sec_library.h"
#define ENV_SECIMG_LOAD "sec_m_load"
#define VAL_SECIMG_LOAD "ext4load mmc ${mmcdev}:${mmcteepart} $tf_addr trust_firmware.bin; ext4load mmc ${mmcdev}:${mmcteepart} $tee_addr tee.bin\0"
#define RPMB_BLOCK_SIZE 256
#define RPMB_ROLLBACK_BLOCK_START 1
#ifndef LIGHT_KDF_RPMB_KEY
static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
0xbb, 0xaa, 0x99, 0x88, 0xff, 0xee, 0xdd, 0xcc, \
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
#endif
extern int sprintf(char *buf, const char *fmt, ...);
extern char * get_slot_name_suffix(void);
static int get_rpmb_key(uint8_t key[32])
{
#ifndef LIGHT_KDF_RPMB_KEY
memcpy(key, emmc_rpmb_key_sample, sizeof(emmc_rpmb_key_sample));
return 0;
#else
uint32_t kdf_rpmb_key_length = 0;
int ret = 0;
ret = csi_kdf_gen_hmac_key(key, &kdf_rpmb_key_length);
if (ret != 0) {
return -1;
}
return 0;
#endif
}
static int get_image_file_size(unsigned long img_src_addr)
{
img_header_t *img = (img_header_t *)img_src_addr;
uint8_t magiccode[4] = {0};
magiccode[3] = img->magic_num & 0xff;
magiccode[2] = (img->magic_num & 0xff00) >> 8;
magiccode[1] = (img->magic_num & 0xff0000) >> 16;
magiccode[0] = (img->magic_num & 0xff000000) >> 24;
if (memcmp(header_magic, magiccode, 4) == 0) {
return -1;
}
return img->image_size;
}
static int verify_and_load_image(unsigned long image_addr_src, unsigned long image_addr_dst)
{
int ret = 0;
unsigned int image_size = 0;
if (image_have_head(image_addr_src) == 1) {
ret = csi_sec_init();
if (ret != 0) {
return -1;
}
ret = csi_sec_custom_image_verify(image_addr_src, UBOOT_STAGE_ADDR);
if (ret != 0) {
printf("image verify error\r\n");
return -2;
}
image_size = get_image_file_size(image_addr_src);
if (image_size < 0) {
printf("image get size error\r\n");
return -3;
}
memmove((void *)image_addr_dst, (const void *)(image_addr_src + HEADER_SIZE), image_size);
} else {
printf("in secure mode but image has no header\r\n");
return -4;
}
return 0;
}
int verify_and_load_tee_tf_image(void)
{
int ret = 0;
ret = verify_and_load_image(LIGHT_TF_FW_TMP_ADDR, LIGHT_TF_FW_ADDR);
if (ret != 0) {
printf("verify tf image failed\r\n");
return ret;
}
printf("verify trust firmware image success\r\n");
ret = verify_and_load_image(LIGHT_TEE_FW_ADDR, LIGHT_TEE_FW_ADDR);
if (ret != 0) {
printf("verify tee image failed\r\n");
return ret;
}
printf("verify tee image success\r\n");
return 0;
}
/* In order to use common bootloader for both secure boot and non-secure boot,
we only know the boot type through reading the sec_boot field in efuse. Due to
the efuse is only accessed in lifecycle(DEV/OEM/PRO/RMP), we ensure it must be
non-secure boot in lifecycle(INIT) */
bool get_system_boot_type(void)
{
bool btype = true; /* false: non-secure boot | true: secure boot */
#if 0
int lc = 0;
sboot_st_t sb_flag = SECURE_BOOT_DIS;
int ret = 0;
#endif
int sb_emulater = 0;
sb_emulater = env_get_ulong("sb_emulater", 10, 0);
if (sb_emulater == 0) {
btype = false;
}
# if 0
ret = csi_efuse_get_lc(&lc);
/* 0: LC_INIT, 1: LC_DEV, 2: LC_OEM, 3: LC_PRO */
if ((ret == 0) && (lc != 0)) {
csi_efuse_api_init();
/* Check platform secure boot enable ? */
ret = csi_efuse_get_secure_boot_st(&sb_flag);
if ((ret == 0) && (sb_flag == SECURE_BOOT_EN))
btype = true;
csi_efuse_api_uninit();
}
#endif
return btype;
}
int sec_read_rollback_index(size_t rollback_index_slot, uint64_t *out_rollback_index)
{
char runcmd[64] = {0};
unsigned char blkdata[RPMB_BLOCK_SIZE];
size_t rpmb_block = (rollback_index_slot * sizeof(uint64_t)) / RPMB_BLOCK_SIZE + RPMB_ROLLBACK_BLOCK_START;
size_t rpmb_offset = (rollback_index_slot * sizeof(uint64_t)) % RPMB_BLOCK_SIZE;
sprintf(runcmd, "mmc rpmb read 0x%lx %ld 1", (unsigned long)blkdata, rpmb_block);
if(run_command(runcmd, 0)) {
printf("read_rollback_index failed, mmc read error\r\n");
return -1;
}
*out_rollback_index = *(uint64_t*)(blkdata + rpmb_offset);
return 0;
}
int sec_write_rollback_index(size_t rollback_index_slot, uint64_t rollback_index)
{
char runcmd[64] = {0};
unsigned char blkdata[RPMB_BLOCK_SIZE];
size_t rpmb_block = (rollback_index_slot * sizeof(uint64_t)) / RPMB_BLOCK_SIZE + RPMB_ROLLBACK_BLOCK_START;
size_t rpmb_offset = (rollback_index_slot * sizeof(uint64_t)) % RPMB_BLOCK_SIZE;
uint8_t rpmb_key[32];
sprintf(runcmd, "mmc rpmb read 0x%lx %ld 1", (unsigned long)blkdata, rpmb_block);
if(run_command(runcmd, 0)) {
printf("read_rollback_index failed, mmc read error\r\n");
return -1;
}
*(uint64_t*)(blkdata + rpmb_offset) = rollback_index;
if (get_rpmb_key(rpmb_key) != 0) {
return -2;
}
sprintf(runcmd, "mmc rpmb write 0x%lx %ld 1 0x%lx", (unsigned long)blkdata, rpmb_block, (unsigned long)rpmb_key);
if(run_command(runcmd, 0)) {
printf("read_rollback_index failed, mmc write error\r\n");
return -3;
}
return 0;
}
static int do_secimg_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bool sb_enable = false;
const char *secimgs_load_str = VAL_SECIMG_LOAD;
int ret = -1;
int teepart = 0;
#ifdef CONFIG_ANDROID_AB
char *slot_suffix = get_slot_name_suffix();
teepart = env_get_ulong("mmcteepart", 10, 8);
if ((strcmp(slot_suffix, "_a") == 0) && (teepart != 8)) {
/* Switch mmcbootpart to "_b" */
env_set_ulong("mmcbootpart", 2);
/* Switch mmcteepart to "_b" */
env_set_ulong("mmcteepart", 8);
} else if ((strcmp(slot_suffix, "_b") == 0) && (teepart != 9)){
/* Switch mmcbootpart to "_b" */
env_set_ulong("mmcbootpart", 3);
/* Switch mmcteepart to "_b" */
env_set_ulong("mmcteepart", 9);
}
#endif
sb_enable = get_system_boot_type();
if (sb_enable) {
/* By default, the value for ENV-SEC-M-LOAD is always to load opensbi image.
* if secure boot is enable, we force to change the value to load tee image.
* but Never to save it in volatile-RAM
*/
ret = env_set(ENV_SECIMG_LOAD, secimgs_load_str);
if (ret != 0) {
printf("Rewrite ENV (%s) fails\n", ENV_SECIMG_LOAD);
return CMD_RET_FAILURE;
}
}
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
secimg_load, 1, 1, do_secimg_load,
"Runtime-load secure image if secure system is enable",
NULL
);

24
board/thead/light-c910/spl.c
View File

@@ -48,6 +48,7 @@ static struct light_reset_list light_post_reset_lists[] = {
{0x00000002, 0xFFEF528000}, /* VO sys_reg: GPU rst */
{0x00000003, 0xFFEF528000}, /* VO sys_reg: GPU rst */
{0x00000007, 0xFFFF529004}, /* VO sys_reg: DPU rst */
{0x07FFFF18, 0xFFCB000014}, /* Audio sys_reg: DMA rst */
};
static void light_pre_reset_config(void)
@@ -301,12 +302,14 @@ void cpu_performance_enable(void)
#define CSR_MHINT2_E 0x7cc
#define CSR_MHINT4 0x7ce
csr_write(CSR_SMPEN, 0x1);
csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x20000);
// FIXME set mhint2[22] to enable core icg en
csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x420000);
csr_write(CSR_MHINT4, csr_read(CSR_MHINT4) | 0x410);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MHCR, 0x117f); // clear bit7 to disable indirect brantch prediction
// FIXME: Clear bit[12] to disable L0BTB.
csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x6e30c | (1<<22)); // set bit22 to close fence broadcast
csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
}
static int bl1_img_have_head(unsigned long img_src_addr)
@@ -399,9 +402,20 @@ void board_init_f(ulong dummy)
light_board_init_r(NULL, 0);
}
static uint32_t get_custom_boot_seq(void)
{
/* boot media definition */
/* BOOT_DEVICE_MMC1 - boot from eMMC or SD card */
/* BOOT_DEVICE_NAND - boot from nand flash */
/* BOOT_DEVICE_SPI - boot from spi flash */
/* TODO: user can decide the boot media according their own configuration */
return BOOT_DEVICE_MMC1;
}
void board_boot_order(u32 *spl_boot_list)
{
#define SOC_OM_ADDRBASE 0xffef018010
#if CONFIG_IS_ENABLED(LIGHT_BOOT_FORCE_SEQ)
switch (readl((void *)SOC_OM_ADDRBASE) & 0x7) {
case 0:
case 1:
@@ -428,6 +442,8 @@ void board_boot_order(u32 *spl_boot_list)
default:
spl_boot_list[0] = BOOT_DEVICE_NONE;
}
#else
spl_boot_list[0] = get_custom_boot_seq();
#endif
cpu_performance_enable();
}

8
board/thead/light-c910/sys_clk.c
View File

@@ -43,9 +43,9 @@ void cpu_clk_config(uint32_t cpu_freq)
udelay(11);
/* config bus: cpu clk ratio to 1:1 */
writel((readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
writel((readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
/* switch c910_cclk to cpu_pll1_foutpostdiv */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
@@ -290,7 +290,7 @@ void sys_clk_config(void)
/* The boards other than the LightA board perform the bus down-speed operation */
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
/* axi_sram_clk: 812.8512MHz -> 688.128MHz */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
tmp |= 0x2000;

6
cmd/Kconfig
View File

@@ -263,6 +263,12 @@ config CMD_BOOTI
help
Boot an AArch64 Linux Kernel image from memory.
config CMD_BOOTANDROID
bool "bootandroid"
default n
help
Boot an android image from mmc.
config BOOTM_LINUX
bool "Support booting Linux OS images"
depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI

1
cmd/Makefile
View File

@@ -175,6 +175,7 @@ obj-$(CONFIG_CMD_REGULATOR) += regulator.o
obj-$(CONFIG_CMD_BLOB) += blob.o
# Android Verified Boot 2.0
obj-$(CONFIG_CMD_BOOTANDROID) += bootandroid.o
obj-$(CONFIG_CMD_AVB) += avb.o
obj-$(CONFIG_DDR_SCAN) += ddrscan.o

4
cmd/avb.c
View File

@@ -312,6 +312,10 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
printf("Unknown error occurred\n");
}
#ifdef CONFIG_ANDROID_BOOT_IMAGE
if (out_data)
avb_slot_verify_data_free(out_data);
#endif
return res;
}

566
cmd/bootandroid.c Normal file
View File

@@ -0,0 +1,566 @@
/*
* (C) Copyright 2018, Linaro Limited
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <avb_verify.h>
#include <command.h>
#include <env.h>
#include <image.h>
#include <malloc.h>
#include <mmc.h>
#include <android_image.h>
#include <android_bootloader_message.h>
#include <xbc.h>
#define ENV_KERNEL_ADDR "kernel_addr"
#define ENV_RAMDISK_ADDR "ramdisk_addr"
#define ENV_DTB_ADDR "dtb_addr"
#define DEFAULT_KERNEL_ADDR 0x00200800
#define DEFAULT_RAMDISK_ADDR LIGHT_ROOTFS_ADDR
#define DEFAULT_DTB_ADDR LIGHT_DTB_ADDR
#define ENV_RAMDISK_SIZE "ramdisk_size"
#define MISC_PARTITION "misc"
#define RECOVERY_PARTITION "recovery"
#define BOOT_PARTITION "boot"
#define VENDOR_BOOT_PARTITION "vendor_boot"
#define BOOTDEV_DEFAULT 0
#define BCB_BOOTONCE "bootonce-bootloader"
#define BCB_BOOTRECOVERY "boot-recovery"
/*
* Knowing secure boot is enable or disable dependents on
* special data field in efuse and efuse control register.
*/
extern bool get_system_boot_type(void);
/*
* The suffix for partition name is from the value of ENV_BOOTAB
*/
static const char *slot_name_suffix = NULL;
/*
* BOOT IMAGE HEADER V3/V4 PAGESIZE
* Source code:system/tools/mkbootimg/unpack_bootimg.py
*/
#define BOOT_IMAGE_HEADER_V3_PAGESIZE 4096
static struct AvbOps *avb_ops = NULL;
static struct bootloader_message_ab *s_bcb = NULL;
static struct bootloader_control *boot_ctl = NULL;
static char *get_boot_partition_name_suffix(void)
{
#ifdef CONFIG_ANDROID_AB
if (boot_ctl != NULL) {
/* index 0 is _a, index 1 is _b*/
if(boot_ctl->slot_info[0].priority < boot_ctl->slot_info[1].priority) {
strcpy(boot_ctl->slot_suffix, "_b");
} else {
strcpy(boot_ctl->slot_suffix, "_a");
}
} else {
printf("get_slot_suffix boot_ctl is null return _a");
return "_a";
}
printf("get_slot_suffix boot_ctl->slot_suffix %s\r\n", boot_ctl->slot_suffix);
return boot_ctl->slot_suffix;
#else
return "";
#endif
}
static void get_partition_name(const char *partion, char *partion_name)
{
strcpy(partion_name, partion);
strcat(partion_name, get_boot_partition_name_suffix());
}
/*
*format 4 chars/bytes to a int number
*/
static int byteToInt(uint8_t* data,int offset)
{
return data[offset+0] + (data[offset+1] << 8) + (data[offset+2] << 16) + (data[offset+3] << 24);
}
static int get_number_of_pages(int image_size, int page_size)
{
return (image_size + page_size - 1) / page_size;
}
/**
* header_version >=3,get dtb data from vendor_boot.img ,else boot.img.
*
* header_version = 4,get bootconfig data from vendor_boot.img ,
* and append bootconfig to the end of ramdisk(initrd)
* doc:https://www.kernel.org/doc/html/next/translations/zh_CN/admin-guide/bootconfig.html#initrd
*/
static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start, uint8_t** buf_bootconfig, int* vendor_bootconfig_size, bool isRecovery)
{
int ret;
disk_partition_t part_info;
uint8_t* vendor_boot_data = NULL;
struct blk_desc *dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
char vb_part_name[32] = {0};
if (hdr == NULL) {
printf("invalid hdr\n");
return -1;
}
/* if the vendor boot partition name is beyond 32B, arise error */
if ((32 - strlen(VENDOR_BOOT_PARTITION)) < 2)
return -1;
get_partition_name(VENDOR_BOOT_PARTITION, vb_part_name);
printf("blk_get_dev %s\n", vb_part_name);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
printf("MMC err: invalid mmc device\n");
return -1;
}
/* Get boot partition info */
ret = part_get_info_by_name(dev_desc, vb_part_name, &part_info);
if (ret < 0) {
printf("MMC err: cannot find %s partition\n", vb_part_name);
return -1;
}
if (part_info.size * part_info.blksz > CONFIG_FASTBOOT_BUF_SIZE) {
return -1;
}
//vendor_boot_data = (uint8_t*)CONFIG_FASTBOOT_BUF_ADDR;
printf("vendor_boot_data part_info.size = %ld, part_info.blksz = %lu", part_info.size, part_info.blksz);
// reuse kernel start address to load vendor boot data
// because av_malloc(32M) failed in 2G devices
// TODO: why av_malloc failed
// ATTATION: If the vendor_boot partition size > boot partition size, it is error.
// avb_malloc(part_info.size * part_info.blksz);
vendor_boot_data = (uint8_t*)env_get_hex(ENV_KERNEL_ADDR, DEFAULT_KERNEL_ADDR);
ret = blk_dread(dev_desc, part_info.start, part_info.size, vendor_boot_data);
// vendor_boot.img
//* +------------------------+
//* | vendor boot header | o pages
//* +------------------------+
//* | vendor ramdisk section | p pages
//* +------------------------+
//* | dtb | q pages
//* +------------------------+
//* | vendor ramdisk table | r pages
//* +------------------------+
//* | bootconfig | s pages
//* +------------------------+
//* o = (2124 + page_size - 1) / page_size
//* p = (vendor_ramdisk_size + page_size - 1) / page_size
//* q = (dtb_size + page_size - 1) / page_size
//* r = (vendor_ramdisk_table_size + page_size - 1) / page_size
//* s = (vendor_bootconfig_size + page_size - 1) / page_size
// see system/tools/mkbootimg/unpack_bootimg.py
// info.boot_magic = unpack('8s', args.boot_img.read(8))[0].decode()
// info.header_version = unpack('I', args.boot_img.read(4))[0]
// info.page_size = unpack('I', args.boot_img.read(4))[0]
// info.kernel_load_address = unpack('I', args.boot_img.read(4))[0]
// info.ramdisk_load_address = unpack('I', args.boot_img.read(4))[0]
// info.vendor_ramdisk_size = unpack('I', args.boot_img.read(4))[0]
// info.cmdline = cstr(unpack('2048s', args.boot_img.read(2048))[0].decode())
// info.tags_load_address = unpack('I', args.boot_img.read(4))[0]
// info.product_name = cstr(unpack('16s', args.boot_img.read(16))[0].decode())
// info.header_size = unpack('I', args.boot_img.read(4))[0]
// info.dtb_size = unpack('I', args.boot_img.read(4))[0]
// info.dtb_load_address = unpack('Q', args.boot_img.read(8))[0]
// info.vendor_ramdisk_table_size = unpack('I', args.boot_img.read(4))[0]
// vendor_ramdisk_table_entry_num = unpack('I', args.boot_img.read(4))[0]
// vendor_ramdisk_table_entry_size = unpack('I', args.boot_img.read(4))[0]
// info.vendor_bootconfig_size = unpack('I', args.boot_img.read(4))[0]
// num_vendor_ramdisk_table_pages = get_number_of_pages(
// info.vendor_ramdisk_table_size, page_size)
// vendor_ramdisk_table_offset = page_size * (
// num_boot_header_pages + num_boot_ramdisk_pages + num_boot_dtb_pages)
// bootconfig_offset = page_size * (num_boot_header_pages
// + num_boot_ramdisk_pages + num_boot_dtb_pages
// + num_vendor_ramdisk_table_pages)
int vendor_boot_pagesize = byteToInt(vendor_boot_data,12);//offset 12
int vendor_ramdisk_size = byteToInt(vendor_boot_data,24);//offset 24
int dtb_size = byteToInt(vendor_boot_data,2100);//offset 2100
int o = (2124 + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
int p = (vendor_ramdisk_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
int dtb_offset = vendor_boot_pagesize * (o + p);
hdr->dtb_size= dtb_size;
memcpy((void *)(uint64_t)dtb_start, vendor_boot_data + dtb_offset, hdr->dtb_size);
int q=(hdr->dtb_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
int vendor_ramdisk_table_size=byteToInt(vendor_boot_data,2112);//offset 2112
int r=(vendor_ramdisk_table_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
*vendor_bootconfig_size=byteToInt(vendor_boot_data,2124);//offset 2124
*buf_bootconfig = avb_malloc(*vendor_bootconfig_size);
if (*buf_bootconfig == NULL) {
printf("vendor bootconfig malloc fail\n");
return -1;
}
int bootconfig_offset=vendor_boot_pagesize * (o + p + q + r);
memcpy(*buf_bootconfig, vendor_boot_data + bootconfig_offset, *vendor_bootconfig_size);
#ifdef CONFIG_ANDROID_AB
char *find_str = NULL;
char *slot_suffix = get_boot_partition_name_suffix();
char *slot_suffx_pre = "androidboot.slot_suffix=";
printf("prepare_data_from_vendor_boot slot_suffix:%s\n", slot_suffix);
printf("prepare_data_from_vendor_boot slot_suffx_pre:%s\n", slot_suffx_pre);
find_str = strstr((char *)*buf_bootconfig, slot_suffx_pre);
if (find_str != NULL) {
memcpy(find_str + strlen(slot_suffx_pre), slot_suffix, strlen(slot_suffix));
}
#endif
if (isRecovery) {
int i = 0;
struct vendor_ramdisk_table_entry *ramdisk_entry = NULL;
int vendor_ramdisk_table_offset = vendor_boot_pagesize * (o + p + q);
int vendor_ramdisk_table_entry_num = byteToInt(vendor_boot_data,2116);//offset 2116
printf("vendor_boot vendor_ramdisk_table_entry_num:%d\n",vendor_ramdisk_table_entry_num);
int vendor_ramdisk_table_entry_size = byteToInt(vendor_boot_data,2120);//offset 2116
printf("vendor_boot vendor_ramdisk_table_entry_size:%d\n",vendor_ramdisk_table_entry_size);
for (i = 0; i < vendor_ramdisk_table_entry_num; i++) {
ramdisk_entry = (struct vendor_ramdisk_table_entry*)(vendor_boot_data + vendor_ramdisk_table_offset
+ ( i * vendor_ramdisk_table_entry_size ));
if (ramdisk_entry->ramdisk_type != VENDOR_RAMDISK_TYPE_RECOVERY) {
continue;
}
printf("find recovery from ramdisk table.");
int ramdisk_start = env_get_hex(ENV_RAMDISK_ADDR, DEFAULT_RAMDISK_ADDR);
int recovery_ramdisk_offset = vendor_boot_pagesize * o + ramdisk_entry->ramdisk_offset;
memcpy((void *)(uint64_t)ramdisk_start, vendor_boot_data + recovery_ramdisk_offset,
ramdisk_entry->ramdisk_size);//ramdisk
//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
char* bootconfig_params = (char*)*buf_bootconfig;
int ret = addBootConfigParameters(bootconfig_params, *vendor_bootconfig_size,
ramdisk_start + ramdisk_entry->ramdisk_size , 0);
if (ret == -1) {
printf("\nadd BootConfig Parameters error!!!\n");
} else {
printf("\nramdisk size is changed,new value is:%d\n",ramdisk_entry->ramdisk_size + ret);
//set ramdisk size for bootm
env_set_hex(ENV_RAMDISK_SIZE, ramdisk_entry->ramdisk_size + ret);
}
break;
}
}
return 0;
}
static void prepare_loaded_parttion_data(const uint8_t* data, bool isRecovery)
{
struct andr_img_hdr *hdr = (struct andr_img_hdr *)map_sysmem((phys_addr_t)data, 0);
if (IMAGE_FORMAT_ANDROID == genimg_get_format(hdr)) {
int dtb_start = env_get_hex(ENV_DTB_ADDR, DEFAULT_DTB_ADDR);
uint8_t* buf_bootconfig = NULL;
int size_bootconfig=0;
printf("Boot image header_version:%d\n", hdr->header_version);
if (hdr->header_version >= 3) {
// see system/tools/mkbootimg/unpack_bootimg.py
hdr->kernel_size = byteToInt((uint8_t *)data, 8);
hdr->ramdisk_size = byteToInt((uint8_t *)data, 12);
hdr->page_size = BOOT_IMAGE_HEADER_V3_PAGESIZE;
prepare_data_from_vendor_boot(hdr,dtb_start,&buf_bootconfig,&size_bootconfig,isRecovery);
}
int kernel_start = env_get_hex(ENV_KERNEL_ADDR, DEFAULT_KERNEL_ADDR);
int ramdisk_start = env_get_hex(ENV_RAMDISK_ADDR, DEFAULT_RAMDISK_ADDR);
// see system/tools/mkbootimg/unpack_bootimg.py
int page_size = hdr->page_size;
int num_header_pages = 1;
int num_kernel_pages = get_number_of_pages(hdr->kernel_size, page_size);
int num_ramdisk_pages = get_number_of_pages(hdr->ramdisk_size, page_size);
int kernel_offset = page_size * num_header_pages;
int ramdisk_offset = page_size * (num_header_pages + num_kernel_pages);
int dtb_offset = page_size * (num_header_pages + num_kernel_pages + num_ramdisk_pages);
printf("Boot image kernel_start:%x, kernel_offset:%x, kernel_size:%d\n", kernel_start, kernel_offset, hdr->kernel_size);
printf("Boot image ramdisk_start:%x, ramdisk_offset:%x, ramdisk_size:%d\n", ramdisk_start, ramdisk_offset, hdr->ramdisk_size);
printf("Boot image page_size:%d\n", hdr->page_size);
printf("dtb_offset:%x, dtb_size:%d\n", dtb_offset, hdr->dtb_size);
if (kernel_start + hdr->kernel_size > ramdisk_start || kernel_start + hdr->kernel_size > dtb_start) {
printf("boot.img kernel space and ramdis space are overlaped !!!\n");
} else {
memcpy((void *)(uint64_t)kernel_start, data + kernel_offset, hdr->kernel_size);
if (!isRecovery) {
memcpy((void *)(uint64_t)ramdisk_start, data + ramdisk_offset, hdr->ramdisk_size);
}
if( hdr->header_version < 3) {
//set ramdisk size for bootm
env_set_hex(ENV_RAMDISK_SIZE, hdr->ramdisk_size);
memcpy((void *)(uint64_t)dtb_start, data + dtb_offset, hdr->dtb_size);
} else if (!isRecovery) {
//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
char* bootconfig_params=(char*)buf_bootconfig;
int ret = addBootConfigParameters(bootconfig_params, size_bootconfig,
ramdisk_start + hdr->ramdisk_size , 0);
if (ret == -1) {
printf("Bootconfig Err: add BootConfig Parameters error!!!\n");
} else {
printf("ramdisk size is updated to new value is:%d\n",hdr->ramdisk_size + ret);
//set ramdisk size for bootm
env_set_hex(ENV_RAMDISK_SIZE, hdr->ramdisk_size + ret);
}
}
}
if (buf_bootconfig != NULL) {
avb_free(buf_bootconfig);
}
}
unmap_sysmem(hdr);
}
static int prepare_boot_data(const AvbSlotVerifyData *out_data, bool isRecovery)
{
int res = CMD_RET_FAILURE;
int i = 0;
int num_loaded_partition = out_data->num_loaded_partitions;
printf("@@@@ prepare loaded partition (%d) data start\n", num_loaded_partition);
for (i = 0; i < num_loaded_partition; i++) {
const AvbPartitionData *loaded_partition = &out_data->loaded_partitions[i];
if (loaded_partition->partition_name != NULL) {
printf("partition_name=%s, data_size=%ld\n", \
loaded_partition->partition_name, loaded_partition->data_size);
prepare_loaded_parttion_data(loaded_partition->data, isRecovery);
}
}
return res;
}
static void prepare_partition_data(const char *name, bool isRecovery)
{
int ret = 0;
disk_partition_t part_info;
struct blk_desc *dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
uint8_t *data = NULL;
printf("prepare_partition_data %s\n", name);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
printf("MMC err: invalid mmc device\n");
return;
}
/* Get boot partition info */
ret = part_get_info_by_name(dev_desc, name, &part_info);
if (ret < 0) {
printf("MMC err: cannot find %s partition\n", name);
return;
}
data = avb_malloc(part_info.size * part_info.blksz);
if (data == NULL) {
printf("avb malloc(%ldKB) fails\n", part_info.size * part_info.blksz / 1024);
return;
}
ret = blk_dread(dev_desc, part_info.start, part_info.size, data);
prepare_loaded_parttion_data(data, isRecovery);
printf("prepare_partition_data %s, read=%d, start:%lx, size:%ld, blksize:%lx\n", \
name, ret, part_info.start, part_info.size, part_info.blksz);
avb_free(data);
}
static void clear_bcb(void)
{
int ret;
disk_partition_t part_info;
struct blk_desc *dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
//bcb clear and store
memset(s_bcb, 0, sizeof(struct bootloader_message_ab));
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
printf("BootAndriod bcb err: invalid mmc device\n");
return;
}
/* Get boot partition info */
ret = part_get_info_by_name(dev_desc, MISC_PARTITION, &part_info);
if (ret < 0) {
printf("BootAndriod bcb err: cannot find misc partition\n");
return;
}
ret = blk_dwrite(dev_desc, part_info.start, part_info.size, s_bcb);
printf("BootAndriod bcb info :clear_bcb write=%d, %ld,%ld,%ld\n", ret, part_info.start, part_info.size, part_info.blksz);
}
static int do_andriod_bcb_business(int *boot_recovery)
{
AvbIOResult ret = AVB_IO_RESULT_OK;
size_t bytes_read = 0;
int res = CMD_RET_FAILURE;
#ifdef CONFIG_ANDROID_AB
char *slot_suffix = "_a";
#else
char *slot_suffix = "";
#endif
if (avb_ops != NULL) {
avb_ops_free(avb_ops);
avb_ops = NULL;
}
avb_ops = avb_ops_alloc(BOOTDEV_DEFAULT);
if (avb_ops == NULL) {
goto _bcb_err;
}
if (s_bcb != NULL) {
avb_free(s_bcb);
s_bcb = NULL;
}
s_bcb = avb_malloc(sizeof(struct bootloader_message_ab));
if (s_bcb == NULL) {
goto _bcb_err;
}
if (boot_ctl != NULL) {
avb_free(boot_ctl);
boot_ctl = NULL;
}
boot_ctl = malloc(sizeof(struct bootloader_control));
if (boot_ctl == NULL)
{
ret = -2;
goto _bcb_err;
}
ret = avb_ops->read_from_partition(avb_ops,
MISC_PARTITION,
0,
sizeof(struct bootloader_message_ab),
s_bcb,
&bytes_read);
if (ret != AVB_IO_RESULT_OK) {
printf("BootAndriod Err: Bcb read failed\n");
goto _bcb_err;
}
/* Enter into fastboot mode if bcb string is bootonce or bootrecovery */
if (0 == strncmp(s_bcb->message.command, "bootonce-bootloader", strlen("bootonce-bootloader")))
{
printf("BootAndriod Info: Bcb read %ld bytes, %s\n", bytes_read, s_bcb->message.command);
printf("BootAndriod Info: Enter fastboot mode\n");
clear_bcb();
run_command("fastboot usb 0", 0);
}
else if (0 == strncmp(s_bcb->message.command, "boot-recovery", strlen("boot-recovery")))
{
printf("recovery slot_suffix = %s\n", slot_suffix);
*boot_recovery = 1;
}
memset(boot_ctl, 0, sizeof(struct bootloader_control));
memcpy(boot_ctl, (struct bootloader_control*)s_bcb->slot_suffix, sizeof(struct bootloader_control));
res = CMD_RET_SUCCESS;
_bcb_err:
if (res != CMD_RET_SUCCESS) {
if (avb_ops != NULL) {
avb_ops_free(avb_ops);
avb_ops = NULL;
}
if (boot_ctl != NULL) {
avb_free(boot_ctl);
boot_ctl = NULL;
}
if (s_bcb != NULL) {
avb_free(s_bcb);
s_bcb = NULL;
}
}
return res;
}
static int do_bootandroid(struct cmd_tbl_s *cmdtp, int flag, int argc,
char * const argv[]) {
const char * const requested_partitions[] = {"vbmeta", "boot", "vbmeta_system", NULL};
AvbSlotVerifyResult slot_result = AVB_SLOT_VERIFY_RESULT_OK;
AvbSlotVerifyData *slot_data = NULL;
AvbIOResult ret = AVB_IO_RESULT_OK;
AvbSlotVerifyFlags slotflags = AVB_SLOT_VERIFY_FLAGS_NONE;
AvbHashtreeErrorMode htflags = AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE;
int res = CMD_RET_FAILURE;
char bp_name[32] = {0};
int boot_recovery = 0;
res = do_andriod_bcb_business(&boot_recovery);
if (res != CMD_RET_SUCCESS) {
goto exit;
}
/* Retieve boot partition 's name suffix */
slot_name_suffix = get_boot_partition_name_suffix();
/* Start with slot verification in secure boot */
if (get_system_boot_type()) {
/* Verify boot partition requested in vbmeta.img */
slot_result = avb_slot_verify(avb_ops,
requested_partitions,
slot_name_suffix,
slotflags,
htflags,
&slot_data);
if (slot_result == AVB_SLOT_VERIFY_RESULT_OK) {
printf("BootAndriod Info: Request Partition are verified successfully\n");
printf("BootAndriod cmdline: slot_data.cmdline:%s\n", slot_data->cmdline);
prepare_boot_data(slot_data, boot_recovery ? true:false);
if (ret == 0) {
if (slot_data != NULL)
avb_slot_verify_data_free(slot_data);
}
} else {
/* In case of avb slot verification failure, Force system reset */
run_command("reset", 0);
}
} else {
/* Go to load BOOT partition directly in non-secure boot */
get_partition_name(BOOT_PARTITION, bp_name);
prepare_partition_data(bp_name, boot_recovery ? true:false);
}
exit:
return res;
}
const char * get_slot_name_suffix(void)
{
return slot_name_suffix;
}
U_BOOT_CMD(
bootandroid, 2, 1, do_bootandroid,
"bootandroid - boot android bootimg from device\n",
"mmc0 | mmc1 | mmc2 | mmcX]\n "
"- boot application image stored in storage device like mmc\n"
);

13
cmd/booti.c
View File

@@ -67,7 +67,6 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc,
int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int ret;
/* Consume 'booti' */
argc--; argv++;
@@ -119,20 +118,22 @@ U_BOOT_CMD(
#endif
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
extern int light_secboot(int argc, char * const argv[]);
#endif
int do_secboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
if (light_secboot(argc, argv) != 0) {
run_command("reset", 0);
return -1;
}
#endif
return 0;
}
U_BOOT_CMD(
secboot, CONFIG_SYS_MAXARGS, 1, do_secboot,
"verify image file with known pubkey which reside in father image or itself!",
secboot, CONFIG_SYS_MAXARGS, 1, do_secboot,
"verify image file with known pubkey which reside in father image or itself!",
"vimage addr imgname[[tee/tf] - verify specifed image resides in addr\n"
);

36
cmd/mmc.c
View File

@@ -574,6 +574,7 @@ static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag,
}
extern volatile uint32_t DELAY_LANE;
extern volatile int manual_set_delay ;
static int do_mmc_set_delay_lane(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
@@ -587,17 +588,22 @@ static int do_mmc_set_delay_lane(cmd_tbl_t *cmdtp, int flag,
mmc = find_mmc_device(curr_device);
if (!mmc) {
printf("no mmc device at slot %x\n", curr_device);
return CMD_RET_FAILURE;
goto RET_FAILURE;
}
manual_set_delay = 1;
if (0 != snps_mmc_init(mmc))
return CMD_RET_FAILURE;
goto RET_FAILURE;
mmc = init_mmc_device(curr_device, true);
if (!mmc)
return CMD_RET_FAILURE;
goto RET_FAILURE;
manual_set_delay = 0;
return CMD_RET_SUCCESS;
RET_FAILURE:
manual_set_delay = 0;
return CMD_RET_FAILURE;
}
static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
@@ -605,6 +611,10 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
{
struct mmc *mmc;
int i = 0, n;
int stop_on_ok = 1;
if(argc > 1 && (!strncmp(argv[1],"cont",4))){
stop_on_ok = 0;
}
for(i = 0; i <= 128; i++) {
DELAY_LANE = i;
printf("set DELAY_LANE = %d\n", DELAY_LANE);
@@ -616,8 +626,10 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
return CMD_RET_FAILURE;
}
manual_set_delay = 1;
if (0 != snps_mmc_init(mmc)) {
printf("Error: mmc init error!\n");
manual_set_delay = 0;
return CMD_RET_FAILURE;
}
@@ -628,18 +640,21 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
if (mmc_getwp(mmc) == 1) {
printf("Error: card is write protected!\n");
manual_set_delay = 0;
return CMD_RET_FAILURE;
}
n = blk_dwrite(mmc_get_blk_desc(mmc), 0, 1, 0);
if (n == 1) {
printf("blocks written: %s\n", "OK" );
return CMD_RET_SUCCESS;
manual_set_delay = 0;
if(stop_on_ok)
return CMD_RET_SUCCESS;
} else {
printf("written: %s\n", "error");
}
}
manual_set_delay = 0;
if (i > 128) {
return CMD_RET_FAILURE;
}
@@ -1239,9 +1254,10 @@ U_BOOT_CMD(
#endif
"mmc erase blk# cnt\n"
"mmc rescan\n"
"mmc set_delay # val\n"
"mmc turning\n"
"mmc memset addr # lenght\n"
"mmc set_delay # val - set clk out delay mannaul,reinit host and rescan dev\n"
"mmc turning [continue] - loop test for clk delay form 0 to 128, reinit host and rescan dev\n"
" - without arg [continue] exit once init and write ok\n"
"mmc memset addr # length - set mem addr 0xff with length '# length' \n"
"mmc part - lists available partition on current mmc device\n"
"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
"mmc list - lists available devices\n"

14
common/Kconfig
View File

@@ -962,6 +962,20 @@ config TPL_HASH
and the algorithms it supports are defined in common/hash.c. See
also CMD_HASH for command-line access.
config BOARD_RNG_SEED
bool "Provide /chosen/rng-seed property to the linux kernel"
help
Selecting this option requires the board to define a
board_rng_seed() function, which should return a buffer
which will be used to populate the /chosen/rng-seed property
in the device tree for the OS being booted.
It is up to the board code (and more generally the whole
BSP) where and how to store (or generate) such a seed, how
to ensure a given seed is only used once, how to create a
new seed for use on subsequent boots, and whether or not the
kernel should account any entropy from the given seed.
endmenu
menu "Update support"

77
common/avb_verify.c
View File

@@ -14,6 +14,48 @@
#include <tee.h>
#include <tee/optee_ta_avb.h>
#ifdef CONFIG_AVB_ROLLBACK_ENABLE
extern int sec_write_rollback_index(size_t rollback_index_slot, uint64_t rollback_index);
extern int sec_read_rollback_index(size_t rollback_index_slot, uint64_t *out_rollback_index);
#endif
#if defined (CONFIG_AVB_USE_OEM_KEY)
static const unsigned char avb_root_oem_pub[520] = {
0x00,0x00,0x08,0x00,0x11,0x70,0xEA,0xC9,0xC2,0xAD,0x66,0x2A,0x57,0x2A,0x89,0x68,
0x8B,0x40,0x33,0xF2,0xEA,0x22,0xD7,0x3E,0x31,0x5F,0x9D,0xB8,0xD1,0x16,0x5C,0x22,
0xC3,0xFE,0xE6,0x35,0x3F,0x96,0x6D,0xD8,0x1A,0x11,0xE9,0x53,0x90,0x88,0xA9,0xCE,
0xA7,0x33,0xB2,0x16,0x60,0x18,0xBE,0x23,0xCC,0x5C,0xAB,0x29,0x0E,0x7B,0x35,0x16,
0xB0,0x59,0x3A,0x2F,0x62,0xF1,0x9B,0x39,0x0A,0x21,0x00,0xFE,0x75,0xEB,0x00,0xDF,
0x17,0xAF,0x44,0x11,0x42,0x4E,0x4C,0x7C,0xA6,0xDC,0xC5,0xAD,0xB3,0x7C,0xC3,0xB1,
0x52,0xAD,0x0C,0xEF,0x73,0x69,0x7E,0xFC,0xF9,0x12,0xA7,0x5C,0x60,0x47,0xEF,0x8F,
0xC7,0x9D,0xD9,0x62,0xF5,0x0E,0x62,0xBB,0x3E,0x80,0x23,0xFA,0x19,0x4C,0x0A,0xD6,
0xE0,0xA7,0x0E,0x65,0xEA,0xD5,0xB8,0xA9,0xF2,0xA3,0xDA,0x18,0xBE,0x5D,0x4B,0x37,
0x91,0xBA,0xDB,0x0D,0x50,0x7E,0xEE,0x52,0xDF,0x90,0xE6,0xFC,0x8F,0xB8,0x24,0x2A,
0x2B,0xBE,0xA6,0xC9,0x5B,0x89,0x3E,0xE8,0x24,0xBD,0x6A,0x03,0x31,0x6C,0xFC,0x4A,
0xBA,0x6B,0xEE,0x08,0xAE,0x33,0x6E,0xC0,0x64,0x87,0xC1,0x35,0x65,0x42,0x34,0xE5,
0xF8,0x3B,0x82,0x36,0xE9,0xFA,0x23,0xD7,0x12,0xC5,0x7B,0x27,0x16,0xB0,0xC7,0x40,
0x5A,0xA4,0x8A,0x56,0xA4,0x54,0x0F,0xD9,0xA7,0x25,0x25,0xE3,0x7F,0x72,0x6E,0x4B,
0x63,0x1B,0x05,0xFE,0x4E,0x1F,0x1D,0x05,0xDD,0x91,0xA7,0xBF,0xA4,0x90,0xDA,0x7D,
0x0F,0xB6,0xFC,0x5D,0x8E,0xFB,0xE2,0xF7,0x5F,0x76,0xFA,0xD5,0x12,0xEC,0x87,0xD6,
0x07,0xA0,0xAC,0xB6,0xE6,0xBA,0xB0,0x87,0xBA,0x51,0xD7,0x6C,0x19,0xC0,0x2C,0xA5,
0x2C,0x08,0x52,0x2A,0x63,0x18,0x10,0x94,0xEA,0x5C,0x13,0xBF,0x42,0x8E,0x12,0xB6,
0x7D,0x34,0xD9,0x1C,0x42,0xBC,0xCE,0x44,0x8A,0x13,0x5B,0x93,0x6F,0x34,0x41,0xA1,
0xA3,0xD3,0x2E,0xF4,0xD3,0x28,0xAD,0x8F,0x8B,0x89,0x9D,0x42,0x43,0xD6,0xBF,0xDE,
0x9F,0xBD,0x32,0x06,0xE3,0x67,0xD3,0x14,0x2F,0x4C,0xE7,0x6B,0x9A,0xD9,0x04,0xFA,
0x4B,0x46,0x88,0xE7,0x04,0xAA,0x56,0xFF,0xBF,0x89,0x1D,0xFD,0x32,0xDF,0x47,0xC0,
0x34,0x0D,0x25,0x8C,0xF6,0xE1,0x5E,0xA9,0x3C,0x30,0x3A,0x53,0x0C,0xDB,0xAD,0x8E,
0x01,0xCB,0x46,0xE0,0xF5,0x97,0x2D,0xB8,0xF8,0x29,0xC3,0x19,0x4C,0x05,0x8B,0x74,
0xE0,0xA6,0x3B,0x3C,0x96,0x4F,0x91,0x74,0x62,0xAA,0x50,0x0F,0x11,0x30,0x59,0xAE,
0x7A,0x80,0xD3,0xAC,0xB3,0xDB,0x24,0x3A,0x79,0xD4,0xDB,0x79,0x10,0x63,0x27,0xD0,
0x6B,0xF9,0xA3,0xF4,0x27,0x24,0x89,0x0C,0xAC,0x31,0x15,0x08,0x10,0x59,0x08,0x2D,
0x00,0x3D,0xD8,0xD6,0x3B,0x91,0xC8,0x55,0xCF,0x28,0x3A,0xFB,0xD7,0xF7,0xF7,0x9D,
0x41,0xBD,0x3E,0xD1,0x77,0xA3,0xF6,0xFA,0x33,0x05,0x5A,0x36,0xCE,0xB9,0x02,0x12,
0x10,0xEB,0xCA,0xA7,0x3C,0xC8,0x5D,0xCD,0x33,0xD9,0xFA,0x16,0xD4,0x52,0x12,0xB6,
0x35,0xD5,0x84,0x53,0xC4,0x21,0xDC,0x72,0x2F,0xF9,0x1E,0x59,0x0A,0xCD,0x7D,0x89,
0xD4,0xCF,0x8E,0x2E,0x09,0x36,0xF5,0x12,0x35,0x43,0x64,0x6C,0xD1,0x70,0xBF,0x67,
0x3A,0x54,0x72,0x84,0xF3,0xF1,0x4A,0x6A
};
#else
static const unsigned char avb_root_pub[1032] = {
0x0, 0x0, 0x10, 0x0, 0x55, 0xd9, 0x4, 0xad, 0xd8, 0x4,
0xaf, 0xe3, 0xd3, 0x84, 0x6c, 0x7e, 0xd, 0x89, 0x3d, 0xc2,
@@ -120,7 +162,7 @@ static const unsigned char avb_root_pub[1032] = {
0xe1, 0x74, 0xa1, 0xa3, 0x99, 0xa0, 0x85, 0x9e, 0xf1, 0xac,
0xd8, 0x7e,
};
#endif
/**
* ============================================================================
* Boot states support (GREEN, YELLOW, ORANGE, RED) and dm_verity
@@ -590,6 +632,19 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
public_key_metadata_length,
bool *out_key_is_trusted)
{
#if defined (CONFIG_AVB_USE_OEM_KEY)
if (!public_key_length || !public_key_data || !out_key_is_trusted)
return AVB_IO_RESULT_ERROR_IO;
*out_key_is_trusted = false;
if (public_key_length != sizeof(avb_root_oem_pub))
return AVB_IO_RESULT_ERROR_IO;
if (memcmp(avb_root_oem_pub, public_key_data, public_key_length) == 0)
*out_key_is_trusted = true;
return AVB_IO_RESULT_OK;
#else
if (!public_key_length || !public_key_data || !out_key_is_trusted)
return AVB_IO_RESULT_ERROR_IO;
@@ -601,6 +656,7 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
*out_key_is_trusted = true;
return AVB_IO_RESULT_OK;
#endif
}
#ifdef CONFIG_OPTEE_TA_AVB
@@ -681,8 +737,15 @@ static AvbIOResult read_rollback_index(AvbOps *ops,
size_t rollback_index_slot,
u64 *out_rollback_index)
{
#ifdef CONFIG_AVB_ROLLBACK_ENABLE
if (sec_read_rollback_index(rollback_index_slot, out_rollback_index) != 0) {
return AVB_IO_RESULT_ERROR_IO;
}
return AVB_IO_RESULT_OK;
#else
#ifndef CONFIG_OPTEE_TA_AVB
/* For now we always return 0 as the stored rollback index. */
/* For now we always return 0 as the stored rollback index. */
printf("%s not supported yet\n", __func__);
if (out_rollback_index)
@@ -708,8 +771,10 @@ static AvbIOResult read_rollback_index(AvbOps *ops,
*out_rollback_index = (u64)param[1].u.value.a << 32 |
(u32)param[1].u.value.b;
return AVB_IO_RESULT_OK;
#endif
#endif
}
/**
@@ -727,6 +792,13 @@ static AvbIOResult write_rollback_index(AvbOps *ops,
size_t rollback_index_slot,
u64 rollback_index)
{
#ifdef CONFIG_AVB_ROLLBACK_ENABLE
if (sec_write_rollback_index(rollback_index_slot, rollback_index) != 0) {
return AVB_IO_RESULT_ERROR_IO;
}
return AVB_IO_RESULT_OK;
#else
#ifndef CONFIG_OPTEE_TA_AVB
/* For now this is a no-op. */
printf("%s not supported yet\n", __func__);
@@ -748,6 +820,7 @@ static AvbIOResult write_rollback_index(AvbOps *ops,
return invoke_func(ops->user_data, TA_AVB_CMD_WRITE_ROLLBACK_INDEX,
ARRAY_SIZE(param), param);
#endif
#endif
}
/**

13
common/fdt_support.c
View File

@@ -7,6 +7,7 @@
*/
#include <common.h>
#include <abuf.h>
#include <env.h>
#include <mapmem.h>
#include <stdio_dev.h>
@@ -274,6 +275,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end)
int fdt_chosen(void *fdt)
{
struct abuf buf = {};
int nodeoffset;
int err;
char *str; /* used to set string properties */
@@ -289,6 +291,17 @@ int fdt_chosen(void *fdt)
if (nodeoffset < 0)
return nodeoffset;
if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) {
err = fdt_setprop(fdt, nodeoffset, "rng-seed",
abuf_data(&buf), abuf_size(&buf));
abuf_uninit(&buf);
if (err < 0) {
printf("WARNING: could not set rng-seed %s.\n",
fdt_strerror(err));
return err;
}
}
str = env_get("bootargs");
if (str) {
err = fdt_setprop(fdt, nodeoffset, "bootargs", str,

2
common/splash.c
View File

@@ -71,7 +71,7 @@ static int splash_video_logo_load(void)
return -EFAULT;
}
memcpy((void *)bmp_load_addr, bmp_logo_bitmap,
memcpy((void *)(u64)bmp_load_addr, bmp_logo_bitmap,
ARRAY_SIZE(bmp_logo_bitmap));
return 0;

117
configs/light_a_val_android_defconfig Normal file
View File

@@ -0,0 +1,117 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
# CONFIG_LIGHT_SEC_UPGRADE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_SPL_TEXT_BASE=0xffe0000800
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A=y
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
CONFIG_CMD_AVB=y
CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y

2
configs/light_a_val_defconfig
View File

@@ -83,7 +83,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y

7
configs/light_a_val_sec_defconfig
View File

@@ -18,6 +18,12 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
# CONFIG_TPM is not set
# CONFIG_TPM_Z32H330TC_SPI is not set
# CONFIG_TPM_V2 is not set
# CONFIG_CMD_TPM_V2 is not set
# CONFIG_CMD_TPM is not set
# CONFIG_CMD_TPM_TEST is not set
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -82,6 +88,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_EFI_LOADER is not set
CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
CONFIG_LIGHT_SEC_UPGRADE=y
# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y

119
configs/light_ant_ref_android_defconfig Normal file
View File

@@ -0,0 +1,119 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_UPGRADE is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SYS_TEXT_BASE=0x7b000000
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_SPL_TEXT_BASE=0xffe0000800
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF=y
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
CONFIG_CMD_AVB=y
CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y

3
configs/light_ant_ref_defconfig
View File

@@ -82,7 +82,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF=y
CONFIG_LIGHT_SEC_UPGRADE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y

121
configs/light_b_product_android_defconfig Normal file
View File

@@ -0,0 +1,121 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_VAL_B=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_TIME=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-b-product"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
# CONFIG_LIGHT_SEC_UPGRADE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SYS_TEXT_BASE=0x7b000000
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_SPL_TEXT_BASE=0xffe0000800
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B=y
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
CONFIG_CMD_AVB=y
CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y

117
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CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE=y
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
CONFIG_CMD_AVB=y
CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_TEXT_BASE=0xffe0000800

117
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CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_SPL_TEXT_BASE=0xffe0000800
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A=y
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
CONFIG_CMD_AVB=y
CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y

107
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CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000

108
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CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A=y
CONFIG_LIGHT_SEC_UPGRADE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000

106
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CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000

2
drivers/fastboot/Kconfig
View File

@@ -2,7 +2,7 @@ menu "Fastboot support"
config FASTBOOT
bool
imply ANDROID_BOOT_IMAGE
# imply ANDROID_BOOT_IMAGE
imply CMD_FASTBOOT
config USB_FUNCTION_FASTBOOT

64
drivers/fastboot/fb_command.c
View File

@@ -14,6 +14,7 @@
#include <stdlib.h>
#define BLOCK_SIZE 512
#define BOARD_ID_OFFSET 0x26
/**
* image_size - final fastboot image size
@@ -42,6 +43,7 @@ static void reboot_bootloader(char *, char *);
static void oem_format(char *, char *);
#endif
static void oem_command(char *, char *);
int image_have_head(unsigned long img_src_addr);
static const struct {
const char *command;
@@ -263,6 +265,35 @@ void fastboot_data_complete(char *response)
fastboot_bytes_received = 0;
}
/**
* check_image_board_id() - check if board id in image matched with board id in env
*
* @image_data: Image data
*
* 0 if success otherwise failed
*/
int check_image_board_id(uint8_t *image_data)
{
char *env_board_id = NULL;
char board_id[3] = {0};
env_board_id = env_get("board#");
/*if current board id is null or image has no header,skip check*/
if (env_board_id == NULL || env_board_id[0] == 0 || image_have_head((unsigned long)image_data) == 0) {
return 0;
}
memcpy(board_id, image_data + BOARD_ID_OFFSET,sizeof(uint16_t));
/*if image board id is null,skip check*/
if (*(uint16_t*)board_id == 0) {
return 0;
}
/*check if current board id match with board id in image*/
if (strncmp(env_board_id, board_id, sizeof(board_id)) != 0) {
printf("U-BOOT image download via fastboot is interrupted due to the U-BOOT for board %s does not work in the board %s\r\n",board_id,env_board_id);
return -1;
}
return 0;
}
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
/**
* flash() - write the downloaded image to the indicated partition.
@@ -279,8 +310,15 @@ static void flash(char *cmd_parameter, char *response)
char cmdbuf[32];
u32 block_cnt;
struct blk_desc *dev_desc;
int ret = 0;
if (strcmp(cmd_parameter, "uboot") == 0) {
ret = check_image_board_id(fastboot_buf_addr);
if (ret != 0) {
fastboot_fail("U-BOOT image does not match the type of BOARD", response);
return;
}
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
fastboot_fail("invalid mmc device", response);
@@ -313,7 +351,7 @@ static void flash(char *cmd_parameter, char *response)
memcpy((void *)LIGHT_TF_FW_ADDR, fastboot_buf_addr, image_size);
} else if ((strcmp(cmd_parameter, TEE_PART_NAME) == 0)) {
memcpy((void *)LIGHT_TEE_FW_ADDR, fastboot_buf_addr, image_size);
}
}
if(strcmp(cmd_parameter, "uboot") == 0 || (strcmp(cmd_parameter, "fw") == 0) ||
(strcmp(cmd_parameter, "uImage") == 0) || (strcmp(cmd_parameter, "dtb") == 0) ||
@@ -332,7 +370,7 @@ static void flash(char *cmd_parameter, char *response)
#endif
/* Send ACK to host */
fastboot_okay(NULL, response);
/* set secure upgrade flag to indicate it is TF image upgrade*/
sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", TF_SEC_UPGRADE_FLAG);
run_command(cmdbuf, 0);
@@ -348,13 +386,29 @@ static void flash(char *cmd_parameter, char *response)
/* Send ACK to host */
fastboot_okay(NULL, response);
/* set secure upgrade flag to indicate it is TEE image upgrade*/
sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", TEE_SEC_UPGRADE_FLAG);
run_command(cmdbuf, 0);
run_command("saveenv", 0);
run_command("reset", 0);
return;
} else if (strcmp(cmd_parameter, SBMETA_IMG_UPD_NAME) == 0) {
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
/* tee/tf/uboot image must be written into stash partition */
sprintf(cmdbuf, "%s", STASH_PART_NAME);
fastboot_mmc_flash_write(cmdbuf, fastboot_buf_addr, image_size, response);
#endif
/* Send ACK to host */
fastboot_okay(NULL, response);
/* set secure upgrade flag to indicate it is TEE image upgrade*/
sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", SBMETA_SEC_UPGRADE_FLAG);
run_command(cmdbuf, 0);
run_command("saveenv", 0);
run_command("reset", 0);
return;
} else if (strcmp(cmd_parameter, UBOOT_IMG_UPD_NAME) == 0) {
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
@@ -366,14 +420,14 @@ static void flash(char *cmd_parameter, char *response)
/* Send ACK to host */
fastboot_okay(NULL, response);
/* set secure upgrade flag to indicate it is UBOOT image upgrade*/
sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", UBOOT_SEC_UPGRADE_FLAG);
run_command(cmdbuf, 0);
run_command("saveenv", 0);
run_command("reset", 0);
return;
}
}
#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)

4
drivers/fastboot/fb_common.c
View File

@@ -118,7 +118,11 @@ void fastboot_boot(void)
#ifdef THEAD_LIGHT_FASTBOOT
char cmdbuf[32];
#ifdef CONFIG_ANDROID_BOOT_IMAGE
sprintf(cmdbuf, "run bootcmd");
#else
sprintf(cmdbuf, "bootslave; run set_bootargs; booti %s - %s", LIGHT_KERNEL_ADDR_CMD, LIGHT_DTB_ADDR_CMD);
#endif
printf("fastboot bootcmd %s\n", cmdbuf);
run_command(cmdbuf, 0);

19
drivers/fastboot/fb_getvar.c
View File

@@ -13,6 +13,7 @@
#include <version.h>
static void getvar_version(char *var_parameter, char *response);
static void getvar_dynamic_partition(char *var_parameter, char *response);
static void getvar_version_bootloader(char *var_parameter, char *response);
static void getvar_downloadsize(char *var_parameter, char *response);
static void getvar_serialno(char *var_parameter, char *response);
@@ -41,6 +42,9 @@ static const struct {
}, {
.variable = "version-bootloader",
.dispatch = getvar_version_bootloader
}, {
.variable = "dynamic-partition",
.dispatch = getvar_dynamic_partition
}, {
.variable = "downloadsize",
.dispatch = getvar_downloadsize
@@ -134,6 +138,17 @@ static void getvar_version_bootloader(char *var_parameter, char *response)
fastboot_okay(U_BOOT_VERSION, response);
}
static void getvar_dynamic_partition(char *var_parameter, char *response)
{
char *part_name="super";
int r = getvar_get_part_info(part_name, response, NULL);
if (r >= 0)
fastboot_okay("true", response); /* part exists */
else
fastboot_okay("false", response);
}
static void getvar_downloadsize(char *var_parameter, char *response)
{
fastboot_response("OKAY", response, "0x%08x", fastboot_buf_size);
@@ -247,7 +262,11 @@ static void getvar_partition_size(char *part_name, char *response)
static void getvar_is_userspace(char *var_parameter, char *response)
{
#ifdef CONFIG_ANDROID_BOOT_IMAGE
fastboot_okay("yes", response);
#else
fastboot_okay("no", response);
#endif
}
/**

4
drivers/mmc/sdhci.c
View File

@@ -136,9 +136,9 @@ static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
unsigned char ctrl;
if (data->flags == MMC_DATA_READ)
host->start_addr = (dma_addr_t)data->dest;
host->start_addr = (dma_addr_t)(u64)data->dest;
else
host->start_addr = (dma_addr_t)data->src;
host->start_addr = (dma_addr_t)(u64)data->src;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;

20
drivers/mmc/snps_sdhci.c
View File

@@ -13,6 +13,7 @@
#define HS400_DELAY_LANE 24
volatile int DELAY_LANE = 50;
volatile int manual_set_delay = 0; //flag for cmd manual setted DELAY_LANE,non-zero is setted. auto clear in cmd
static void sdhci_phy_1_8v_init_no_pull(struct sdhci_host *host)
{
@@ -154,10 +155,14 @@ void snps_set_uhs_timing(struct sdhci_host *host)
{
struct mmc *mmc = (struct mmc *)host->mmc;
u32 reg;
int restore_delay;
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg &= ~SDHCI_CTRL_UHS_MASK;
if(manual_set_delay){
DELAY_LANE = DELAY_LANE & 0x7f; /*limit bit[0:6]*/
printf("%s: manual set delay (%d) active \n",host->name,DELAY_LANE);
}
switch (mmc->selected_mode) {
case UHS_SDR50:
case MMC_HS_52:
@@ -175,9 +180,13 @@ void snps_set_uhs_timing(struct sdhci_host *host)
reg |= SDHCI_CTRL_UHS_SDR104;
break;
case MMC_HS_400:
DELAY_LANE = HS400_DELAY_LANE;
restore_delay = DELAY_LANE;
if(!manual_set_delay){ /*default not set manual in cmd,when set in cmd,use DELAY_LANE set in cmd*/
DELAY_LANE = HS400_DELAY_LANE;
}
sdhci_phy_1_8v_init(host);
reg |= SNPS_SDHCI_CTRL_HS400;
DELAY_LANE = restore_delay; /*restore for other modes*/
break;
default:
sdhci_phy_3_3v_init(host);
@@ -345,7 +354,10 @@ static int snps_sdhci_probe(struct udevice *dev)
ret = max_clk;
goto err;
}
//get Maximum Base Clock frequency from dts clock-frequency
if(0 == dev_read_u32(dev, "clock-frequency", &max_clk)){
host->max_clk = max_clk;
}
host->mmc = &plat->mmc;
host->mmc->dev = dev;
host->mmc->priv = host;

17
drivers/net/designware.c
View File

@@ -508,7 +508,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
struct phy_device *phydev;
int phy_addr = -1, ret;
#ifdef CONFIG_PHY_ADDR
phy_addr = CONFIG_PHY_ADDR;
#endif
@@ -801,13 +801,16 @@ int designware_eth_probe(struct udevice *dev)
err = ret;
goto mdio_err;
}
#ifdef GMAC_USE_FIRST_MII_BUS
if (!g_mii_bus) {
priv->bus = miiphy_get_dev_by_name(dev->name);
g_mii_bus = priv->bus;
} else {
priv->bus = g_mii_bus;
}
#else
priv->bus = miiphy_get_dev_by_name(dev->name);
#endif
ret = dw_phy_init(priv, dev);
debug("%s, ret=%d\n", __func__, ret);
if (!ret)
@@ -815,8 +818,18 @@ int designware_eth_probe(struct udevice *dev)
/* continue here for cleanup if no PHY found */
err = ret;
#ifdef GMAC_USE_FIRST_MII_BUS
struct mii_dev *t_mii = NULL;
t_mii = miiphy_get_dev_by_name(dev->name);
if((g_mii_bus != t_mii) && (t_mii != NULL) ){
printf("free mdio bus %s\n",t_mii->name);
mdio_unregister(t_mii);
mdio_free(t_mii);
}
#else
mdio_unregister(priv->bus);
mdio_free(priv->bus);
#endif
mdio_err:
#ifdef CONFIG_CLK

1
drivers/tpm/Makefile
View File

@@ -12,3 +12,4 @@ obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o
obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o
obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_spi.o
obj-$(CONFIG_TPM_Z32H330TC_SPI) += tpm2_tis_z32h330tc_spi.o

676
drivers/tpm/tpm2_tis_z32h330tc_spi.c Normal file
View File

@@ -0,0 +1,676 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Author:
* Miquel Raynal <miquel.raynal@bootlin.com>
*
* Description:
* SPI-level driver for TCG/TIS TPM (trusted platform module).
* Specifications at www.trustedcomputinggroup.org
*
* This device driver implements the TPM interface as defined in
* the TCG SPI protocol stack version 2.0.
*
* It is based on the U-Boot driver tpm_tis_infineon_i2c.c.
*/
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
#include <spi.h>
#include <tpm-v2.h>
#include <linux/errno.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/unaligned/be_byteshift.h>
#include <asm-generic/gpio.h>
#include "tpm_tis.h"
#include "tpm_internal.h"
DECLARE_GLOBAL_DATA_PTR;
#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
#define TPM_STS(l) (0x0018 | ((l) << 12))
#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
#define TPM_RID(l) (0x0F04 | ((l) << 12))
#define MAX_SPI_FRAMESIZE 64
/* Number of wait states to wait for */
#define TPM_WAIT_STATES 100
/**
* struct tpm_tis_chip_data - Non-discoverable TPM information
*
* @pcr_count: Number of PCR per bank
* @pcr_select_min: Size in octets of the pcrSelect array
*/
struct tpm_tis_chip_data {
unsigned int pcr_count;
unsigned int pcr_select_min;
unsigned int time_before_first_cmd_ms;
};
/**
* tpm_tis_spi_read() - Read from TPM register
*
* @addr: register address to read from
* @buffer: provided by caller
* @len: number of bytes to read
*
* Read len bytes from TPM register and put them into
* buffer (little-endian format, i.e. first byte is put into buffer[0]).
*
* NOTE: TPM is big-endian for multi-byte values. Multi-byte
* values have to be swapped.
*
* @return -EIO on error, 0 on success.
*/
static int tpm_tis_spi_xfer(struct udevice *dev, u32 addr, const u8 *out,
u8 *in, u16 len)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
int transfer_len, ret;
u8 tx_buf[MAX_SPI_FRAMESIZE];
u8 rx_buf[MAX_SPI_FRAMESIZE];
if (in && out) {
log(LOGC_NONE, LOGL_ERR, "%s: can't do full duplex\n",
__func__);
return -EINVAL;
}
ret = spi_claim_bus(slave);
if (ret < 0) {
log(LOGC_NONE, LOGL_ERR, "%s: could not claim bus\n", __func__);
return ret;
}
while (len) {
/* Request */
transfer_len = min_t(u16, len, MAX_SPI_FRAMESIZE);
tx_buf[0] = (in ? BIT(7) : 0) | (transfer_len - 1);
tx_buf[1] = 0xD4;
tx_buf[2] = addr >> 8;
tx_buf[3] = addr;
ret = spi_xfer(slave, 4 * 8, tx_buf, rx_buf, SPI_XFER_BEGIN);
if (ret < 0) {
log(LOGC_NONE, LOGL_ERR,
"%s: spi request transfer failed (err: %d)\n",
__func__, ret);
goto release_bus;
}
/* Wait state */
if (!(rx_buf[3] & 0x1)) {
int i;
for (i = 0; i < TPM_WAIT_STATES; i++) {
ret = spi_xfer(slave, 1 * 8, NULL, rx_buf, 0);
if (ret) {
log(LOGC_NONE, LOGL_ERR,
"%s: wait state failed: %d\n",
__func__, ret);
goto release_bus;
}
if (rx_buf[0] & 0x1)
break;
}
if (i == TPM_WAIT_STATES) {
log(LOGC_NONE, LOGL_ERR,
"%s: timeout on wait state\n", __func__);
ret = -ETIMEDOUT;
goto release_bus;
}
}
/* Read/Write */
if (out) {
memcpy(tx_buf, out, transfer_len);
out += transfer_len;
}
ret = spi_xfer(slave, transfer_len * 8,
out ? tx_buf : NULL,
in ? rx_buf : NULL,
SPI_XFER_END);
if (ret) {
log(LOGC_NONE, LOGL_ERR,
"%s: spi read transfer failed (err: %d)\n",
__func__, ret);
goto release_bus;
}
if (in) {
memcpy(in, rx_buf, transfer_len);
in += transfer_len;
}
len -= transfer_len;
}
release_bus:
/* If an error occurred, release the chip by deasserting the CS */
if (ret < 0)
spi_xfer(slave, 0, NULL, NULL, SPI_XFER_END);
spi_release_bus(slave);
return ret;
}
static int tpm_tis_spi_read(struct udevice *dev, u16 addr, u8 *in, u16 len)
{
return tpm_tis_spi_xfer(dev, addr, NULL, in, len);
}
static int tpm_tis_spi_read32(struct udevice *dev, u32 addr, u32 *result)
{
__le32 result_le;
int ret;
ret = tpm_tis_spi_read(dev, addr, (u8 *)&result_le, sizeof(u32));
if (!ret)
*result = le32_to_cpu(result_le);
return ret;
}
static int tpm_tis_spi_write(struct udevice *dev, u16 addr, const u8 *out,
u16 len)
{
return tpm_tis_spi_xfer(dev, addr, out, NULL, len);
}
static int tpm_tis_spi_check_locality(struct udevice *dev, int loc)
{
const u8 mask = TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID;
struct tpm_chip *chip = dev_get_priv(dev);
u8 buf;
int ret;
ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1);
if (ret)
return ret;
if ((buf & mask) == mask) {
chip->locality = loc;
return 0;
}
return -ENOENT;
}
static void tpm_tis_spi_release_locality(struct udevice *dev, int loc,
bool force)
{
const u8 mask = TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID;
u8 buf;
if (tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1) < 0)
return;
if (force || (buf & mask) == mask) {
buf = TPM_ACCESS_ACTIVE_LOCALITY;
tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1);
}
}
static int tpm_tis_spi_request_locality(struct udevice *dev, int loc)
{
struct tpm_chip *chip = dev_get_priv(dev);
unsigned long start, stop;
u8 buf = TPM_ACCESS_REQUEST_USE;
int ret;
ret = tpm_tis_spi_check_locality(dev, loc);
if (!ret)
return 0;
if (ret != -ENOENT) {
log(LOGC_NONE, LOGL_ERR, "%s: Failed to get locality: %d\n",
__func__, ret);
return ret;
}
ret = tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1);
if (ret) {
log(LOGC_NONE, LOGL_ERR, "%s: Failed to write to TPM: %d\n",
__func__, ret);
return ret;
}
start = get_timer(0);
stop = chip->timeout_a;
do {
ret = tpm_tis_spi_check_locality(dev, loc);
if (!ret)
return 0;
if (ret != -ENOENT) {
log(LOGC_NONE, LOGL_ERR,
"%s: Failed to get locality: %d\n", __func__, ret);
return ret;
}
mdelay(TPM_TIMEOUT_MS);
} while (get_timer(start) < stop);
log(LOGC_NONE, LOGL_ERR, "%s: Timeout getting locality: %d\n", __func__,
ret);
return ret;
}
static u8 tpm_tis_spi_status(struct udevice *dev, u8 *status)
{
struct tpm_chip *chip = dev_get_priv(dev);
return tpm_tis_spi_read(dev, TPM_STS(chip->locality), status, 1);
}
static int tpm_tis_spi_wait_for_stat(struct udevice *dev, u8 mask,
unsigned long timeout, u8 *status)
{
unsigned long start = get_timer(0);
unsigned long stop = timeout;
int ret;
do {
mdelay(TPM_TIMEOUT_MS);
ret = tpm_tis_spi_status(dev, status);
if (ret)
return ret;
if ((*status & mask) == mask)
return 0;
} while (get_timer(start) < stop);
return -ETIMEDOUT;
}
static u8 tpm_tis_spi_valid_status(struct udevice *dev, u8 *status)
{
struct tpm_chip *chip = dev_get_priv(dev);
return tpm_tis_spi_wait_for_stat(dev, TPM_STS_VALID,
chip->timeout_c, status);
}
static int tpm_tis_spi_get_burstcount(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
unsigned long start, stop;
u32 burstcount, ret;
/* wait for burstcount */
start = get_timer(0);
stop = chip->timeout_d;
do {
ret = tpm_tis_spi_read32(dev, TPM_STS(chip->locality),
&burstcount);
if (ret)
return -EBUSY;
burstcount = (burstcount >> 8) & 0xFFFF;
if (burstcount)
return burstcount;
mdelay(TPM_TIMEOUT_MS);
} while (get_timer(start) < stop);
return -EBUSY;
}
static int tpm_tis_spi_cancel(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
u8 data = TPM_STS_COMMAND_READY;
return tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1);
}
static int tpm_tis_spi_recv_data(struct udevice *dev, u8 *buf, size_t count)
{
struct tpm_chip *chip = dev_get_priv(dev);
int size = 0, burstcnt, len, ret;
u8 status;
while (size < count &&
tpm_tis_spi_wait_for_stat(dev,
TPM_STS_DATA_AVAIL | TPM_STS_VALID,
chip->timeout_c, &status) == 0) {
burstcnt = tpm_tis_spi_get_burstcount(dev);
if (burstcnt < 0)
return burstcnt;
len = min_t(int, burstcnt, count - size);
ret = tpm_tis_spi_read(dev, TPM_DATA_FIFO(chip->locality),
buf + size, len);
if (ret < 0)
return ret;
size += len;
}
return size;
}
static int z32h330tc_spi_recv(struct udevice *dev, u8 *buf, size_t count)
{
struct tpm_chip *chip = dev_get_priv(dev);
int size, expected;
if (!chip)
return -ENODEV;
if (count < TPM_HEADER_SIZE) {
size = -EIO;
goto out;
}
size = tpm_tis_spi_recv_data(dev, buf, TPM_HEADER_SIZE);
if (size < TPM_HEADER_SIZE) {
log(LOGC_NONE, LOGL_ERR, "TPM error, unable to read header\n");
goto out;
}
expected = get_unaligned_be32(buf + 2);
if (expected > count) {
size = -EIO;
goto out;
}
size += tpm_tis_spi_recv_data(dev, &buf[TPM_HEADER_SIZE],
expected - TPM_HEADER_SIZE);
if (size < expected) {
log(LOGC_NONE, LOGL_ERR,
"TPM error, unable to read remaining bytes of result\n");
size = -EIO;
goto out;
}
out:
tpm_tis_spi_cancel(dev);
tpm_tis_spi_release_locality(dev, chip->locality, false);
return size;
}
static int z32h330tc_spi_send(struct udevice *dev, const u8 *buf, size_t len)
{
struct tpm_chip *chip = dev_get_priv(dev);
u32 i, size;
u8 status;
int burstcnt, ret;
u8 data;
if (!chip)
return -ENODEV;
if (len > TPM_DEV_BUFSIZE)
return -E2BIG; /* Command is too long for our tpm, sorry */
ret = tpm_tis_spi_request_locality(dev, 0);
if (ret < 0)
return -EBUSY;
/*
* Check if the TPM is ready. If not, if not, cancel the pending command
* and poll on the status to be finally ready.
*/
ret = tpm_tis_spi_status(dev, &status);
if (ret)
return ret;
if (!(status & TPM_STS_COMMAND_READY)) {
/* Force the transition, usually this will be done at startup */
ret = tpm_tis_spi_cancel(dev);
if (ret) {
log(LOGC_NONE, LOGL_ERR,
"%s: Could not cancel previous operation\n",
__func__);
goto out_err;
}
ret = tpm_tis_spi_wait_for_stat(dev, TPM_STS_COMMAND_READY,
chip->timeout_b, &status);
if (ret < 0 || !(status & TPM_STS_COMMAND_READY)) {
log(LOGC_NONE, LOGL_ERR,
"status %d after wait for stat returned %d\n",
status, ret);
goto out_err;
}
}
for (i = 0; i < len - 1;) {
burstcnt = tpm_tis_spi_get_burstcount(dev);
if (burstcnt < 0)
return burstcnt;
size = min_t(int, len - i - 1, burstcnt);
ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality),
buf + i, size);
if (ret < 0)
goto out_err;
i += size;
}
ret = tpm_tis_spi_valid_status(dev, &status);
if (ret)
goto out_err;
if ((status & TPM_STS_DATA_EXPECT) == 0) {
ret = -EIO;
goto out_err;
}
ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality),
buf + len - 1, 1);
if (ret)
goto out_err;
ret = tpm_tis_spi_valid_status(dev, &status);
if (ret)
goto out_err;
if ((status & TPM_STS_DATA_EXPECT) != 0) {
ret = -EIO;
goto out_err;
}
data = TPM_STS_GO;
ret = tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1);
if (ret)
goto out_err;
return len;
out_err:
tpm_tis_spi_cancel(dev);
tpm_tis_spi_release_locality(dev, chip->locality, false);
return ret;
}
static int z32h330tc_spi_cleanup(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
tpm_tis_spi_cancel(dev);
/*
* The TPM needs some time to clean up here,
* so we sleep rather than keeping the bus busy
*/
mdelay(2);
tpm_tis_spi_release_locality(dev, chip->locality, false);
return 0;
}
static int z32h330tc_spi_open(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
if (chip->is_open)
return -EBUSY;
chip->is_open = 1;
return 0;
}
static int z32h330tc_spi_close(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
if (chip->is_open) {
tpm_tis_spi_release_locality(dev, chip->locality, true);
chip->is_open = 0;
}
return 0;
}
static int z32h330tc_get_desc(struct udevice *dev, char *buf, int size)
{
struct tpm_chip *chip = dev_get_priv(dev);
if (size < 80)
return -ENOSPC;
return snprintf(buf, size,
"%s v2.0: VendorID 0x%04x, DeviceID 0x%04x, RevisionID 0x%02x [%s]",
dev->name, chip->vend_dev & 0xFFFF,
chip->vend_dev >> 16, chip->rid,
(chip->is_open ? "open" : "closed"));
}
static int tpm_tis_wait_init(struct udevice *dev, int loc)
{
struct tpm_chip *chip = dev_get_priv(dev);
unsigned long start, stop;
u8 status;
int ret;
start = get_timer(0);
stop = chip->timeout_b;
do {
mdelay(TPM_TIMEOUT_MS);
ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &status, 1);
if (ret)
break;
if (status & TPM_ACCESS_VALID)
return 0;
} while (get_timer(start) < stop);
return -EIO;
}
static const struct tpm_tis_chip_data z32h330tc_std_chip_data;
static int z32h330tc_spi_probe(struct udevice *dev)
{
struct tpm_tis_chip_data * drv_data = &z32h330tc_std_chip_data;//(void *)dev_get_driver_data(dev);
struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
struct tpm_chip *chip = dev_get_priv(dev);
struct udevice * bus = NULL;
int ret;
/* Use the TPM v2 stack */
priv->version = TPM_V2;
/* Ensure a minimum amount of time elapsed since reset of the TPM */
mdelay(drv_data->time_before_first_cmd_ms);
chip->locality = 0;
chip->timeout_a = TIS_SHORT_TIMEOUT_MS;
chip->timeout_b = TIS_LONG_TIMEOUT_MS;
chip->timeout_c = TIS_SHORT_TIMEOUT_MS;
chip->timeout_d = TIS_SHORT_TIMEOUT_MS;
priv->pcr_count = drv_data->pcr_count;
priv->pcr_select_min = drv_data->pcr_select_min;
ret = tpm_tis_wait_init(dev, chip->locality);
if (ret) {
log(LOGC_DM, LOGL_ERR, "%s: no device found\n", __func__);
return ret;
}
ret = tpm_tis_spi_request_locality(dev, chip->locality);
if (ret) {
log(LOGC_NONE, LOGL_ERR, "%s: could not request locality %d\n",
__func__, chip->locality);
return ret;
}
ret = tpm_tis_spi_read32(dev, TPM_DID_VID(chip->locality),
&chip->vend_dev);
if (ret) {
log(LOGC_NONE, LOGL_ERR,
"%s: could not retrieve VendorID/DeviceID\n", __func__);
return ret;
}
ret = tpm_tis_spi_read(dev, TPM_RID(chip->locality), &chip->rid, 1);
if (ret) {
log(LOGC_NONE, LOGL_ERR, "%s: could not retrieve RevisionID\n",
__func__);
return ret;
}
log(LOGC_NONE, LOGL_ERR,
"SPI TPMv2.0 found (vid:%04x, did:%04x, rid:%02x)\n",
chip->vend_dev & 0xFFFF, chip->vend_dev >> 16, chip->rid);
return 0;
}
static int z32h330tc_spi_remove(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
tpm_tis_spi_release_locality(dev, chip->locality, true);
return 0;
}
static const struct tpm_ops z32h330tc_spi_ops = {
.open = z32h330tc_spi_open,
.close = z32h330tc_spi_close,
.get_desc = z32h330tc_get_desc,
.send = z32h330tc_spi_send,
.recv = z32h330tc_spi_recv,
.cleanup = z32h330tc_spi_cleanup,
};
static const struct tpm_tis_chip_data z32h330tc_std_chip_data = {
.pcr_count = 24,
.pcr_select_min = 3,
.time_before_first_cmd_ms = 30,
};
static const struct udevice_id z32h330tc_spi_ids[] = {
{
.compatible = "z32h330tc,z32h330tc-spi",
.data = (ulong)&z32h330tc_std_chip_data,
},
{ }
};
U_BOOT_DRIVER(tpm_z32h330tc_spi) = {
.name = "tpm_z32h330tc_spi",
.id = UCLASS_TPM,
.of_match = z32h330tc_spi_ids,
.ops = &z32h330tc_spi_ops,
.probe = z32h330tc_spi_probe,
.remove = z32h330tc_spi_remove,
.priv_auto_alloc_size = sizeof(struct tpm_chip),
};

5
drivers/usb/dwc3/ep0.c
View File

@@ -905,7 +905,10 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
dep->flags &= ~DWC3_EP_BUSY;
dep->resource_index = 0;
dwc->setup_packet_pending = false;
invalid_dcache_range(dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
#ifdef CONFIG_TARGET_LIGHT_C910
extern void invalid_dcache_range(unsigned long start, unsigned long end);
invalid_dcache_range((unsigned long)dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
#endif
switch (dwc->ep0state) {
case EP0_SETUP_PHASE:

5
drivers/video/Kconfig
View File

@@ -351,6 +351,11 @@ config VIDEO_LCD_ILITEK_ILI9881C
Say Y here if you want to enable support for ILITEK ILI9881C
800x1280 DSI video mode panel.
config VIDEO_LCD_CUSTOM_LOGO
bool "LCD CUSTOM logo support"
help
Say Y here if you want to enable support for custom logo.
config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n

159
include/abuf.h Normal file
View File

@@ -0,0 +1,159 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Handles a buffer that can be allocated and freed
*
* Copyright 2021 Google LLC
* Written by Simon Glass <sjg@chromium.org>
*/
#ifndef __ABUF_H
#define __ABUF_H
#include <linux/types.h>
/**
* struct abuf - buffer that can be allocated and freed
*
* This is useful for a block of data which may be allocated with malloc(), or
* not, so that it needs to be freed correctly when finished with.
*
* For now it has a very simple purpose.
*
* Using memset() to zero all fields is guaranteed to be equivalent to
* abuf_init().
*
* @data: Pointer to data
* @size: Size of data in bytes
* @alloced: true if allocated with malloc(), so must be freed after use
*/
struct abuf {
void *data;
size_t size;
bool alloced;
};
static inline void *abuf_data(const struct abuf *abuf)
{
return abuf->data;
}
static inline size_t abuf_size(const struct abuf *abuf)
{
return abuf->size;
}
/**
* abuf_set() - set the (unallocated) data in a buffer
*
* This simply makes the abuf point to the supplied data, which must be live
* for the lifetime of the abuf. It is not alloced.
*
* Any existing data in the abuf is freed and the alloced member is set to
* false.
*
* @abuf: abuf to adjust
* @data: New contents of abuf
* @size: New size of abuf
*/
void abuf_set(struct abuf *abuf, void *data, size_t size);
/**
* abuf_map_sysmem() - calls map_sysmem() to set up an abuf
*
* This is equivalent to abuf_set(abuf, map_sysmem(addr, size), size)
*
* Any existing data in the abuf is freed and the alloced member is set to
* false.
*
* @abuf: abuf to adjust
* @addr: Address to set the abuf to
* @size: New size of abuf
*/
void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size);
/**
* abuf_realloc() - Change the size of a buffer
*
* This uses realloc() to change the size of the buffer, with the same semantics
* as that function. If the abuf is not currently alloced, then it will alloc
* it if the size needs to increase (i.e. set the alloced member to true)
*
* @abuf: abuf to adjust
* @new_size: new size in bytes.
* if 0, the abuf is freed
* if greater than the current size, the abuf is extended and the new
* space is not inited. The alloced member is set to true
* if less than the current size, the abuf is contracted and the data at
* the end is lost. If @new_size is 0, this sets the alloced member to
* false
* Return: true if OK, false if out of memory
*/
bool abuf_realloc(struct abuf *abuf, size_t new_size);
/**
* abuf_uninit_move() - Return the allocated contents and uninit the abuf
*
* This returns the abuf data to the caller, allocating it if necessary, so that
* the caller receives data that it can be sure will hang around. The caller is
* responsible for freeing the data.
*
* If the abuf has allocated data, it is returned. If the abuf has data but it
* is not allocated, then it is first allocated, then returned.
*
* If the abuf size is 0, this returns NULL
*
* The abuf is uninited as part of this, except if the allocation fails, in
* which NULL is returned and the abuf remains untouched.
*
* The abuf must be inited before this can be called.
*
* @abuf: abuf to uninit
* @sizep: if non-NULL, returns the size of the returned data
* Return: data contents, allocated with malloc(), or NULL if the data could not
* be allocated, or the data size is 0
*/
void *abuf_uninit_move(struct abuf *abuf, size_t *sizep);
/**
* abuf_init_move() - Make abuf take over the management of an allocated region
*
* After this, @data must not be used. All access must be via the abuf.
*
* @abuf: abuf to init
* @data: Existing allocated buffer to place in the abuf
* @size: Size of allocated buffer
*/
void abuf_init_move(struct abuf *abuf, void *data, size_t size);
/**
* abuf_init_set() - Set up a new abuf
*
* Inits a new abuf and sets up its (unallocated) data
*
* @abuf: abuf to set up
* @data: New contents of abuf
* @size: New size of abuf
*/
void abuf_init_set(struct abuf *abuf, void *data, size_t size);
/**
* abuf_uninit() - Free any memory used by an abuf
*
* The buffer must be inited before this can be called.
*
* @abuf: abuf to uninit
*/
void abuf_uninit(struct abuf *abuf);
/**
* abuf_init() - Set up a new abuf
*
* This initially has no data and alloced is set to false. This is equivalent to
* setting all fields to 0, e.g. with memset(), so callers can do that instead
* if desired.
*
* @abuf: abuf to set up
*/
void abuf_init(struct abuf *abuf);
#endif

14
include/android_image.h
View File

@@ -136,4 +136,18 @@ struct andr_img_hdr {
* else: jump to kernel_addr
*/
#define VENDOR_RAMDISK_NAME_SIZE 32
#define VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE 16
#define VENDOR_RAMDISK_TYPE_RECOVERY 2
struct vendor_ramdisk_table_entry {
u32 ramdisk_size; /* size in bytes for the ramdisk image */
u32 ramdisk_offset; /* offset to the ramdisk image in vendor ramdisk section */
u32 ramdisk_type; /* type of the ramdisk */
u8 ramdisk_name[VENDOR_RAMDISK_NAME_SIZE]; /* asciiz ramdisk name */
// Hardware identifiers describing the board, soc or platform which this
// ramdisk is intended to be loaded on.
u32 board_id[VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE];
} __attribute__((packed));
#endif

1
include/asm/arch Symbolic link
View File

@@ -0,0 +1 @@
/home/cxx194832/ssd/u-boot/arch/riscv/include/asm/arch-c9xx

489
include/configs/light-c910.h
View File

@@ -22,7 +22,11 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_1M)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_TEXT_BASE + SZ_1M)
#ifdef CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_SYS_MALLOC_LEN (64*SZ_1M)
#else
#define CONFIG_SYS_MALLOC_LEN SZ_1M
#endif
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_SYS_CACHELINE_SIZE 64
@@ -35,6 +39,7 @@
#define CONFIG_RGMII 1
#define CONFIG_PHY_MARVELL 1
#define CONFIG_NET_RETRY_COUNT 20
#define GMAC_USE_FIRST_MII_BUS
#define CONFIG_SYS_FLASH_BASE 0x0
#define CONFIG_SYS_MAX_FLASH_BANKS 1
@@ -57,25 +62,27 @@
#define THEAD_LIGHT_FASTBOOT 1
#define LIGHT_FW_ADDR 0x0
#define LIGHT_KERNEL_ADDR 0x200000
#define LIGHT_DTB_ADDR 0x1f00000
#define LIGHT_DTB_ADDR 0x3800000
#define LIGHT_ROOTFS_ADDR 0x2000000
#define LIGHT_AON_FW_ADDR 0xffffef8000
#define LIGHT_TEE_FW_ADDR 0x1c000000
#define LIGHT_TF_FW_ADDR LIGHT_FW_ADDR
#define LIGHT_TF_FW_TMP_ADDR 0x100000
#define LIGHT_KERNEL_ADDR_CMD "0x200000"
#define LIGHT_DTB_ADDR_CMD "0x1f00000"
#define LIGHT_DTB_ADDR_CMD "0x3800000"
/* trust image name string */
#define TF_IMG_UPD_NAME "stashtf"
#define TEE_IMG_UPD_NAME "stashtee"
#define UBOOT_IMG_UPD_NAME "stashuboot"
#define SBMETA_IMG_UPD_NAME "stashsbmeta"
#define TF_PART_NAME "tf"
#define TEE_PART_NAME "tee"
#define UBOOT_PART_NAME "uboot"
#define STASH_PART_NAME "stash"
#define KERNEL_PART_NAME "kernel"
#define SBMETA_PART_NAME "sbmeta"
#define UBOOT_STAGE_ADDR SRAM_BASE_ADDR
@@ -90,6 +97,15 @@
#define TF_SEC_UPGRADE_FLAG 0x5555aaaa
#define TEE_SEC_UPGRADE_FLAG 0x5a5aa5a5
#define UBOOT_SEC_UPGRADE_FLAG 0xa5a5aa55
#define SBMETA_SEC_UPGRADE_FLAG 0xaaaa5555
/* Define secure debug log level */
#define LOG_LEVEL 1
#if defined (LOG_LEVEL)
#define SECLOG_PRINT printf
#else
#define SECLOG_PRINT
#endif
#define UBOOT_MAX_VER 64
#define CONFIG_SYS_CBSIZE 512
@@ -100,96 +116,234 @@
/* List of different env in debug/release version */
#if defined (U_BUILD_DEBUG)
#define ENV_KERNEL_LOGLEVEL "kernel_loglevel=7\0"
#define ENV_STR_BOOT_DELAY
#define ENV_STR_BOOT_DELAY
#define CONFIG_ENV_OVERWRITE
#define ENV_STR_SERIAL "serial#=1234567890\0"
#define ENV_KERNEL_KDUMP "kdump_buf=180M\0"
#else
#define ENV_KERNEL_LOGLEVEL "kernel_loglevel=4\0"
#define ENV_STR_BOOT_DELAY "bootdelay=0\0"
#define ENV_STR_SERIAL "serial#=\0"
#define ENV_KERNEL_KDUMP "kdump_buf=0M\0"
#endif
/* Define board ID in ENV for firmware download protection */
#if defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A) || \
defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || \
defined(CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
#define ENV_STR_BOARD "board#=LA\0"
#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B) || \
defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || \
defined(CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
#define ENV_STR_BOARD "board#=LB\0"
#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A) || \
defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || \
defined(CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
#define ENV_STR_BOARD "board#=LP\0"
#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE) || \
defined(CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
#define ENV_STR_BOARD "board#=LG\0"
#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF) || \
defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || \
defined(CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
#define ENV_STR_BOARD "board#=LD\0"
#endif
#if defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A)
#define CONFIG_EXTRA_ENV_SETTINGS \
"splashimage=0x30000000\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
ENV_STR_BOARD \
"tf_addr=0x100000\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"tee_addr=0x1c000000\0" \
"sec_upgrade_mode=0\0"\
"mmcdev=0\0" \
"mmcpart=6\0" \
"kdump_buf=1M\0" \
"mmcpart=7\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"sbmeta_security_level=1\0" \
"uboot_version=0x0000000000000000\0"\
"fdt_file=light-a-val-sec.dtb\0" \
"tee_version=0x00000000\0"\
"tf_version=0x00000000\0"\
"sbmeta_version=0x00000000\0"\
"fdt_file=th1520-a-val-sec.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=sbmeta,size=8MiB,type=boot;name=swap,size=2048MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} resume=/dev/mmcblk0p6\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio;ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:3 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; sbmetaboot;run load_str;booti $kernel_addr - $dtb_addr;\0" \
"\0"
#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B)
#define CONFIG_EXTRA_ENV_SETTINGS \
"splashimage=0x30000000\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
ENV_STR_BOARD \
"tf_addr=0x100000\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"tee_addr=0x1c000000\0" \
"sec_upgrade_mode=0\0"\
"mmcdev=0\0" \
"mmcpart=6\0" \
"kdump_buf=1M\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"sbmeta_security_level=1\0" \
"uboot_version=0x0000000000000000\0"\
"fdt_file=light-b-product-sec.dtb\0" \
"tee_version=0x00000000\0"\
"tf_version=0x00000000\0"\
"sbmeta_version=0x00000000\0"\
"fdt_file=th1520-b-product-sec.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=sbmeta,size=8MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:3 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; sbmetaboot; run load_str;booti $kernel_addr - $dtb_addr;\0" \
"\0"
#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
#define CONFIG_EXTRA_ENV_SETTINGS \
"splashimage=0x30000000\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
ENV_STR_BOARD \
"tf_addr=0x100000\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"tee_addr=0x1c000000\0" \
"sec_upgrade_mode=0\0"\
"mmcdev=0\0" \
"mmcpart=6\0" \
"kdump_buf=1M\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"uboot_version=0x0000000000000000\0"\
"fdt_file=light-ant-ref-sec.dtb\0" \
"tee_version=0x00000000\0"\
"tf_version=0x00000000\0"\
"fdt_file=th1520-ant-ref-sec.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio;run load_str; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
#define CONFIG_EXTRA_ENV_SETTINGS \
"splashimage=0x30000000\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
ENV_STR_BOARD \
"tf_addr=0x100000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"tee_addr=0x1c000000\0" \
"sec_upgrade_mode=0\0"\
"mmcdev=0\0" \
"mmcpart=7\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"sbmeta_security_level=1\0" \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"uboot_version=0x0000000000000000\0"\
"tee_version=0x00000000\0"\
"tf_version=0x00000000\0"\
"sbmeta_version=0x00000000\0"\
"fdt_file=th1520-lpi4a-product-sec.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=sbmeta,size=8MiB,type=boot;name=swap,size=2048MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} resume=/dev/mmcblk0p6\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio;ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:3 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; sbmetaboot; run load_str;booti $kernel_addr - $dtb_addr;\0" \
"\0"
#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A) || defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B) || \
defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A) || defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE) || \
defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF)
#define CONFIG_EXTRA_ENV_SETTINGS \
"splashimage=0x30000000\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
ENV_STR_SERIAL \
ENV_STR_BOARD \
"tf_addr=0x0\0" \
"tee_addr=0x1c000000\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"ramdisk_addr=0x02000000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0x32000000\0" \
"fwaddr=0x10000000\0"\
"boot_ab=_a\0"\
"sb_emulater=1\0"\
"mmcdev=0\0" \
"mmcpart=3\0" \
"mmcbootpart=2\0" \
"mmcteepart=8\0" \
ENV_KERNEL_LOGLEVEL \
ENV_KERNEL_KDUMP \
ENV_STR_BOOT_DELAY \
"fdt_file=light-val.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=sparse,size=2031kb;name=bootpart_a,size=16MiB;name=bootpart_b,size=16MiB;name=boot_a,size=32MiB;name=boot_b,size=32MiB;name=vendor_boot_a,size=32MiB;name=vendor_boot_b,size=32MiB;name=tee_a,size=32MiB;name=tee_b,size=32MiB;name=dtbo_a,size=8MiB;name=dtbo_b,size=8MiB;name=super,size=4096MiB;name=vbmeta_a,size=1MiB;name=vbmeta_b,size=1MiB;name=vbmeta_system_a,size=1MiB;name=vbmeta_system_b,size=1MiB;name=misc,size=2MiB;name=metadata,size=16MiB;name=userdata,size=-\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 earlycon clk_ignore_unused loop.max_part=7 loglevel=${kernel_loglevel} crashkernel=${kdump_buf} init=/init bootconfig video=HDMI-A-1:800x600-32@60 firmware_class.path=/vendor/firmware androidboot.serialno=${serial#}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"sec_m_load=ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin\0"\
"bootcmd_load=bootandroid;secimg_load;run sec_m_load;run load_aon;run load_c906_audio;fdt addr ${dtb_addr};fdt resize 100;fdt chosen;\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; bootm $kernel_addr $ramdisk_addr:$ramdisk_size $dtb_addr;\0" \
"\0"
#else
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -197,25 +351,30 @@
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
ENV_STR_BOARD \
"mmcdev=0\0" \
"mmcpart=3\0" \
"kdump_buf=1M\0" \
"fdt_file=light-a-product.dtb\0" \
"mmcpart=4\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"fdt_file=th1520-a-product.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=swap,size=2048MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} resume=/dev/mmcblk0p3\0" \
"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:2 $opensbi_addr fw_dynamic.bin; ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc 0:2 $opensbi_addr fw_dynamic.bin; ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -223,30 +382,29 @@
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
"mmcpart=3\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=1M\0" \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-b-product.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"fdt_file=th1520-b-product.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -254,25 +412,28 @@
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-b-ref.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"mmcpart=3\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"fdt_file=th1520-b-ref.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
@@ -281,28 +442,29 @@
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
"kdump_buf=1M\0" \
"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-b-power.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"mmcpart=3\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"fdt_file=th1520-b-power.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -310,28 +472,29 @@
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
"kdump_buf=1M\0" \
"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-ant-ref.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"mmcpart=3\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"fdt_file=th1520-ant-ref.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE)
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -339,28 +502,29 @@
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
"kdump_buf=1M\0" \
"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-ant-discrete.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"mmcpart=3\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"fdt_file=th1520-ant-discrete.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -368,28 +532,59 @@
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
"kdump_buf=500M\0" \
"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-beagle.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"mmcpart=3\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"fdt_file=th1520-beagle.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
#define CONFIG_EXTRA_ENV_SETTINGS \
"splashimage=0x30000000\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"mmcpart=4\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"fdt_file=th1520-lpi4a-product.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=swap,size=2048MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} resume=/dev/mmcblk0p3\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF)
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -397,25 +592,28 @@
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-a-ref.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"mmcpart=3\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"fdt_file=th1520-a-ref.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"\0"
#else
@@ -424,28 +622,29 @@
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"opensbi_addr=0x0\0" \
"dtb_addr=0x01f00000\0" \
"dtb_addr=0x03800000\0" \
"kernel_addr=0x00200000\0" \
"aon_ram_addr=0xffffef8000\0" \
"audio_ram_addr=0xffc0000000\0" \
"audio_ram_addr=0x32000000\0" \
"str_ram_addr=0xffe0000000\0" \
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
"kdump_buf=500M\0" \
"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-a-val.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"mmcpart=4\0" \
"mmcbootpart=2\0" \
ENV_KERNEL_LOGLEVEL \
"kdump_buf=180M\0" \
ENV_STR_BOOT_DELAY \
"fdt_file=th1520-a-val.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=swap,size=2048MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} resume=/dev/mmcblk0p3\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
"factory_reset=yes\0"\
"\0"
#endif
#endif

9
include/env_flags.h
View File

@@ -70,11 +70,18 @@ enum env_flags_varaccess {
#define SERIAL_FLAGS ""
#endif
#ifndef CONFIG_ENV_OVERWRITE
#define BOARD_FLAGS "board#:so,"
#else
#define BOARD_FLAGS ""
#endif
#define ENV_FLAGS_LIST_STATIC \
ETHADDR_FLAGS \
NET_FLAGS \
SERIAL_FLAGS \
CONFIG_ENV_FLAGS_LIST_STATIC
CONFIG_ENV_FLAGS_LIST_STATIC \
BOARD_FLAGS
#ifdef CONFIG_CMD_ENV_FLAGS
/*

13
include/fdt_support.h
View File

@@ -10,6 +10,7 @@
#ifdef CONFIG_OF_LIBFDT
#include <linux/libfdt.h>
#include <abuf.h>
u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
const char *prop, const u32 dflt);
@@ -170,6 +171,18 @@ int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name);
*/
int ft_board_setup(void *blob, bd_t *bd);
/**
* board_rng_seed() - Provide a seed to be passed via /chosen/rng-seed
*
* This function is called if CONFIG_BOARD_RNG_SEED is set, and must
* be provided by the board. It should return, via @buf, some suitable
* seed value to pass to the kernel.
*
* @param buf A struct abuf for returning the seed and its size.
* @return 0 if ok, negative on error.
*/
int board_rng_seed(struct abuf *buf);
/*
* The keystone2 SOC requires all 32 bit aliased addresses to be converted
* to their 36 physical format. This has to happen after all fdt nodes

1
include/xbc.h Normal file
View File

@@ -0,0 +1 @@
#include <../lib/libxbc/libxbc.h>

14
lib/Kconfig
View File

@@ -316,6 +316,20 @@ config LIBAVB
endmenu
menu "Boot Configuration"
config XBC
bool "Boot Configuration support"
depends on ANDROID_BOOT_IMAGE
default n
help
This enables support of Boot Configuration which can be used
to pass boot configuration parameters to user space. These
parameters will show up in /proc/bootconfig similar to the kernel
parameters that show up in /proc/cmdline
endmenu
menu "Hashing Support"
config SHA1

3
lib/Makefile
View File

@@ -68,6 +68,8 @@ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
obj-$(CONFIG_LIBAVB) += libavb/
obj-$(CONFIG_XBC) += libxbc/
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o
@@ -119,6 +121,7 @@ else
obj-y += vsprintf.o strto.o
endif
obj-y += abuf.o
obj-y += date.o
#

132
lib/abuf.c Normal file
View File

@@ -0,0 +1,132 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Handles a buffer that can be allocated and freed
*
* Copyright 2021 Google LLC
* Written by Simon Glass <sjg@chromium.org>
*/
#ifndef USE_HOSTCC
#include <common.h>
#include <malloc.h>
#include <mapmem.h>
#include <string.h>
#endif
#include <abuf.h>
void abuf_set(struct abuf *abuf, void *data, size_t size)
{
abuf_uninit(abuf);
abuf->data = data;
abuf->size = size;
}
#ifndef USE_HOSTCC
void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size)
{
abuf_set(abuf, map_sysmem(addr, size), size);
}
char *memdup(const void *src, size_t len);
#else
/* copied from lib/string.c for convenience */
static char *memdup(const void *src, size_t len)
{
char *p;
p = malloc(len);
if (!p)
return NULL;
memcpy(p, src, len);
return p;
}
#endif
bool abuf_realloc(struct abuf *abuf, size_t new_size)
{
void *ptr;
if (!new_size) {
/* easy case, just need to uninit, freeing any allocation */
abuf_uninit(abuf);
return true;
} else if (abuf->alloced) {
/* currently allocated, so need to reallocate */
ptr = realloc(abuf->data, new_size);
if (!ptr)
return false;
abuf->data = ptr;
abuf->size = new_size;
return true;
} else if (new_size <= abuf->size) {
/*
* not currently alloced and new size is no larger. Just update
* it. Data is lost off the end if new_size < abuf->size
*/
abuf->size = new_size;
return true;
} else {
/* not currently allocated and new size is larger. Alloc and
* copy in data. The new space is not inited.
*/
ptr = malloc(new_size);
if (!ptr)
return false;
if (abuf->size)
memcpy(ptr, abuf->data, abuf->size);
abuf->data = ptr;
abuf->size = new_size;
abuf->alloced = true;
return true;
}
}
void *abuf_uninit_move(struct abuf *abuf, size_t *sizep)
{
void *ptr;
if (sizep)
*sizep = abuf->size;
if (!abuf->size)
return NULL;
if (abuf->alloced) {
ptr = abuf->data;
} else {
ptr = memdup(abuf->data, abuf->size);
if (!ptr)
return NULL;
}
/* Clear everything out so there is no record of the data */
abuf_init(abuf);
return ptr;
}
void abuf_init_set(struct abuf *abuf, void *data, size_t size)
{
abuf_init(abuf);
abuf_set(abuf, data, size);
}
void abuf_init_move(struct abuf *abuf, void *data, size_t size)
{
abuf_init_set(abuf, data, size);
abuf->alloced = true;
}
void abuf_uninit(struct abuf *abuf)
{
if (abuf->alloced)
free(abuf->data);
abuf_init(abuf);
}
void abuf_init(struct abuf *abuf)
{
abuf->data = NULL;
abuf->size = 0;
abuf->alloced = false;
}

17
lib/image-sparse.c
View File

@@ -52,10 +52,10 @@ int write_sparse_image(struct sparse_storage *info,
lbaint_t blk;
lbaint_t blkcnt;
lbaint_t blks;
uint32_t bytes_written = 0;
uint64_t bytes_written = 0;
unsigned int chunk;
unsigned int offset;
unsigned int chunk_data_sz;
uint64_t chunk_data_sz;
uint32_t *fill_buf = NULL;
uint32_t fill_val;
sparse_header_t *sparse_header;
@@ -129,8 +129,8 @@ int write_sparse_image(struct sparse_storage *info,
sizeof(chunk_header_t));
}
chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
blkcnt = chunk_data_sz / info->blksz;
chunk_data_sz = ((u64)sparse_header->blk_sz) * chunk_header->chunk_sz;
blkcnt = DIV_ROUND_UP_ULL(chunk_data_sz, info->blksz);
switch (chunk_header->chunk_type) {
case CHUNK_TYPE_RAW:
if (chunk_header->total_sz !=
@@ -159,7 +159,7 @@ int write_sparse_image(struct sparse_storage *info,
return -1;
}
blk += blks;
bytes_written += blkcnt * info->blksz;
bytes_written += ((u64)blkcnt) * info->blksz;
total_blocks += chunk_header->chunk_sz;
data += chunk_data_sz;
break;
@@ -219,8 +219,9 @@ int write_sparse_image(struct sparse_storage *info,
blk += blks;
i += j;
}
bytes_written += blkcnt * info->blksz;
total_blocks += chunk_data_sz / sparse_header->blk_sz;
bytes_written += ((u64)blkcnt) * info->blksz;
total_blocks += DIV_ROUND_UP_ULL(chunk_data_sz,
sparse_header->blk_sz);
free(fill_buf);
break;
@@ -250,7 +251,7 @@ int write_sparse_image(struct sparse_storage *info,
debug("Wrote %d blocks, expected to write %d blocks\n",
total_blocks, sparse_header->total_blks);
printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name);
printf("........ wrote %llu bytes to '%s'\n", bytes_written, part_name);
if (total_blocks != sparse_header->total_blks) {
info->mssg("sparse image write failure", response);

96
lib/libavb/avb_rsa.c
View File

@@ -13,6 +13,10 @@
#include "avb_util.h"
#include "avb_vbmeta_image.h"
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
#include "sec_library.h"
#endif
typedef struct IAvbKey {
unsigned int len; /* Length of n[] in number of uint32_t */
uint32_t n0inv; /* -1 / n[0] mod 2^32 */
@@ -82,7 +86,19 @@ fail:
static void iavb_free_parsed_key(IAvbKey* key) {
avb_free(key);
}
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
static void hw_crypto_accel_init(void)
{
static bool init = false;
if (!init) {
rambus_crypto_init();
init = true;
}
}
#else
/* a[] -= mod */
static void subM(const IAvbKey* key, uint32_t* a) {
int64_t A = 0;
@@ -200,7 +216,7 @@ out:
avb_free(aaR);
}
}
#endif
/* Verify a RSA PKCS1.5 signature against an expected hash.
* Returns false on failure, true on success.
*/
@@ -212,6 +228,83 @@ bool avb_rsa_verify(const uint8_t* key,
size_t hash_num_bytes,
const uint8_t* padding,
size_t padding_num_bytes) {
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
IAvbKey* parsed_key = NULL;
uint8_t *nk = NULL;
uint8_t *n = NULL;
uint8_t *e = NULL;
int i;
bool success = false;
uint32_t key_bytes = 0;
sc_rsa_t rsa;
sc_rsa_context_t rsa_ctx;
if (key == NULL || sig == NULL || hash == NULL || padding == NULL) {
avb_error("Invalid input.\n");
goto out;
}
parsed_key = iavb_parse_key_data(key, key_num_bytes);
if (parsed_key == NULL) {
avb_error("Error parsing key.\n");
goto out;
}
if (padding_num_bytes != sig_num_bytes - hash_num_bytes) {
avb_error("Padding length does not match hash and signature lengths.\n");
goto out;
}
key_bytes = parsed_key->len * sizeof(uint32_t);
/* Currently, we only support RSA key 2048bits and SHA256 */
if ((key_bytes * 8 != 2048) || (hash_num_bytes * 8 != 256)) {
avb_error("Error unsupported keybits length.\n");
goto out;
}
nk = (uint8_t *)parsed_key->n;
n = avb_malloc(key_bytes);
if (n == NULL) {
avb_error("Error malloc n.\n");
goto out;
}
/* Reverse modular little endian */
for (i = 0; i < key_bytes; i++) {
n[i] = nk[key_bytes - i - 1];
}
e = avb_malloc(key_bytes);
if (e == NULL) {
avb_error("Error malloc e.\n");
goto out;
}
memset(e, 0, key_bytes);
/* public exponentiation. (65537} */
e[key_bytes-1] = 0x01; e[key_bytes-2] = 0x00; e[key_bytes-3] = 0x01; e[key_bytes-4] = 0x00;
hw_crypto_accel_init();
sc_rsa_init(&rsa, 0, SC_RSA_KEY_BITS_2048);
rsa_ctx.padding_type = SC_RSA_PADDING_MODE_PKCS1;
rsa_ctx.n = n;
rsa_ctx.e = e;
rsa_ctx.hash_type = SC_RSA_HASH_TYPE_SHA256;
rsa_ctx.is_crt = SC_RSA_CRT_DISABLE;
rsa_ctx.is_hash = SC_RSA_HASH_DISABLE;
success = sc_rsa_verify(&rsa, &rsa_ctx, (void *)hash, hash_num_bytes, (void *)sig, sig_num_bytes, SC_RSA_HASH_TYPE_SHA256);
sc_rsa_uninit(&rsa);
out:
if (parsed_key != NULL) {
iavb_free_parsed_key(parsed_key);
}
if (e != NULL) {
avb_free(e);
}
return success;
#else
uint8_t* buf = NULL;
IAvbKey* parsed_key = NULL;
bool success = false;
@@ -272,4 +365,5 @@ out:
avb_free(buf);
}
return success;
#endif
}

13
lib/libavb/avb_sha.h
View File

@@ -20,6 +20,9 @@ extern "C" {
#include "avb_crypto.h"
#include "avb_sysdeps.h"
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
#include "sec_library.h"
#endif
/* Block size in bytes of a SHA-256 digest. */
#define AVB_SHA256_BLOCK_SIZE 64
@@ -30,19 +33,29 @@ extern "C" {
/* Data structure used for SHA-256. */
typedef struct {
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
sc_sha_t sha_t;
sc_sha_context_t sha_context;
#else
uint32_t h[8];
uint64_t tot_len;
size_t len;
uint8_t block[2 * AVB_SHA256_BLOCK_SIZE];
#endif
uint8_t buf[AVB_SHA256_DIGEST_SIZE]; /* Used for storing the final digest. */
} AvbSHA256Ctx;
/* Data structure used for SHA-512. */
typedef struct {
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
sc_sha_t sha_t;
sc_sha_context_t sha_context;
#else
uint64_t h[8];
uint64_t tot_len;
size_t len;
uint8_t block[2 * AVB_SHA512_BLOCK_SIZE];
#endif
uint8_t buf[AVB_SHA512_DIGEST_SIZE]; /* Used for storing the final digest. */
} AvbSHA512Ctx;

38
lib/libavb/avb_sha256.c
View File

@@ -10,6 +10,7 @@
#include "avb_sha.h"
#if !defined(CONFIG_AVB_HW_ENGINE_ENABLE)
#define SHFR(x, n) (x >> n)
#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
@@ -83,9 +84,19 @@ static const uint32_t sha256_k[64] = {
0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a,
0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2};
#endif
/* SHA-256 implementation */
void avb_sha256_init(AvbSHA256Ctx* ctx) {
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
if (ctx == NULL) {
return;
}
sc_sha_init(&ctx->sha_t, 0);
sc_sha_start(&ctx->sha_t, &ctx->sha_context, SC_SHA_MODE_256);
sc_sha_trans_config(&ctx->sha_t, &ctx->sha_context, 1);
#else
#ifndef UNROLL_LOOPS
int i;
for (i = 0; i < 8; i++) {
@@ -104,8 +115,10 @@ void avb_sha256_init(AvbSHA256Ctx* ctx) {
ctx->len = 0;
ctx->tot_len = 0;
#endif
}
#if !defined(CONFIG_AVB_HW_ENGINE_ENABLE)
static void SHA256_transform(AvbSHA256Ctx* ctx,
const uint8_t* message,
size_t block_nb) {
@@ -304,8 +317,16 @@ static void SHA256_transform(AvbSHA256Ctx* ctx,
#endif /* !UNROLL_LOOPS */
}
}
#endif
void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, size_t len) {
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
if (ctx == NULL || data == NULL) {
return;
}
sc_sha_update(&ctx->sha_t, &ctx->sha_context, data, len);
#else
size_t block_nb;
size_t new_len, rem_len, tmp_len;
const uint8_t* shifted_data;
@@ -334,9 +355,25 @@ void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, size_t len) {
ctx->len = rem_len;
ctx->tot_len += (block_nb + 1) << 6;
#endif
}
uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) {
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
uint32_t len = 0;
uint32_t ret = 0;
if (ctx == NULL) {
return NULL;
}
ret = sc_sha_finish(&ctx->sha_t, &ctx->sha_context, ctx->buf, &len);
if (ret != 0) {
return NULL;
}
return ctx->buf;
#else
size_t block_nb;
size_t pm_len;
uint64_t len_b;
@@ -372,4 +409,5 @@ uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) {
#endif /* !UNROLL_LOOPS */
return ctx->buf;
#endif
}

38
lib/libavb/avb_sha512.c
View File

@@ -10,6 +10,7 @@
#include "avb_sha.h"
#if !defined(CONFIG_AVB_HW_ENGINE_ENABLE)
#define SHFR(x, n) (x >> n)
#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
@@ -101,10 +102,20 @@ static const uint64_t sha512_k[80] = {
0x28db77f523047d84ULL, 0x32caab7b40c72493ULL, 0x3c9ebe0a15c9bebcULL,
0x431d67c49c100d4cULL, 0x4cc5d4becb3e42b6ULL, 0x597f299cfc657e2aULL,
0x5fcb6fab3ad6faecULL, 0x6c44198c4a475817ULL};
#endif
/* SHA-512 implementation */
void avb_sha512_init(AvbSHA512Ctx* ctx) {
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
if (ctx == NULL) {
return;
}
sc_sha_init(&ctx->sha_t, 0);
sc_sha_start(&ctx->sha_t, &ctx->sha_context, SC_SHA_MODE_512);
sc_sha_trans_config(&ctx->sha_t, &ctx->sha_context, 1);
#else
#ifdef UNROLL_LOOPS_SHA512
ctx->h[0] = sha512_h0[0];
ctx->h[1] = sha512_h0[1];
@@ -123,8 +134,10 @@ void avb_sha512_init(AvbSHA512Ctx* ctx) {
ctx->len = 0;
ctx->tot_len = 0;
#endif
}
#if !defined(CONFIG_AVB_HW_ENGINE_ENABLE)
static void SHA512_transform(AvbSHA512Ctx* ctx,
const uint8_t* message,
size_t block_nb) {
@@ -290,8 +303,16 @@ static void SHA512_transform(AvbSHA512Ctx* ctx,
#endif /* UNROLL_LOOPS_SHA512 */
}
}
#endif
void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len) {
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
if (ctx == NULL || data == NULL) {
return;
}
sc_sha_update(&ctx->sha_t, &ctx->sha_context, data, len);
#else
size_t block_nb;
size_t new_len, rem_len, tmp_len;
const uint8_t* shifted_data;
@@ -320,9 +341,25 @@ void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len) {
ctx->len = rem_len;
ctx->tot_len += (block_nb + 1) << 7;
#endif
}
uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) {
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
uint32_t len = 0;
uint32_t ret = 0;
if (ctx == NULL) {
return NULL;
}
ret = sc_sha_finish(&ctx->sha_t, &ctx->sha_context, ctx->buf, &len);
if (ret != 0) {
return NULL;
}
return ctx->buf;
#else
size_t block_nb;
size_t pm_len;
uint64_t len_b;
@@ -358,4 +395,5 @@ uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) {
#endif /* UNROLL_LOOPS_SHA512 */
return ctx->buf;
#endif
}

170
lib/libxbc/COPYING Normal file
View File

@@ -0,0 +1,170 @@
Apache License
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http://www.apache.org/licenses/
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14
lib/libxbc/Makefile Normal file
View File

@@ -0,0 +1,14 @@
# Copyright (C) 2021 The Android Open Source Project
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
obj-$(CONFIG_XBC) += libxbc.o

104
lib/libxbc/libxbc.c Normal file
View File

@@ -0,0 +1,104 @@
/*
* Copyright (C) 2021 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "libxbc.h"
#define BOOTCONFIG_MAGIC "#BOOTCONFIG\n"
#define BOOTCONFIG_MAGIC_SIZE 12
#define BOOTCONFIG_SIZE_SIZE 4
#define BOOTCONFIG_CHECKSUM_SIZE 4
#define BOOTCONFIG_TRAILER_SIZE BOOTCONFIG_MAGIC_SIZE + \
BOOTCONFIG_SIZE_SIZE + \
BOOTCONFIG_CHECKSUM_SIZE
/*
* Simple checksum for a buffer.
*
* @param addr pointer to the start of the buffer.
* @param size size of the buffer in bytes.
* @return check sum result.
*/
static uint32_t checksum(const unsigned char* const buffer, uint32_t size) {
uint32_t sum = 0;
for (uint32_t i = 0; i < size; i++) {
sum += buffer[i];
}
return sum;
}
/*
* Check if the bootconfig trailer is present within the bootconfig section.
*
* @param bootconfig_end_addr address of the end of the bootconfig section. If
* the trailer is present, it will be directly preceding this address.
* @return true if the trailer is present, false if not.
*/
static bool isTrailerPresent(uint64_t bootconfig_end_addr) {
return !strncmp((char*)(bootconfig_end_addr - BOOTCONFIG_MAGIC_SIZE),
BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE);
}
/*
* Add a string of boot config parameters to memory appended by the trailer.
*/
int32_t addBootConfigParameters(char* params, uint32_t params_size,
uint64_t bootconfig_start_addr, uint32_t bootconfig_size) {
if (!params || !bootconfig_start_addr) {
return -1;
}
if (params_size == 0) {
return 0;
}
int32_t applied_bytes = 0;
int32_t new_size = 0;
uint64_t end = bootconfig_start_addr + bootconfig_size;
if (isTrailerPresent(end)) {
end -= BOOTCONFIG_TRAILER_SIZE;
applied_bytes -= BOOTCONFIG_TRAILER_SIZE;
memcpy(&new_size, (void *)end, BOOTCONFIG_SIZE_SIZE);
} else {
new_size = bootconfig_size;
}
// params
memcpy((void*)end, params, params_size);
applied_bytes += params_size;
applied_bytes += addBootConfigTrailer(bootconfig_start_addr,
bootconfig_size + applied_bytes);
return applied_bytes;
}
/*
* Add boot config trailer.
*/
int32_t addBootConfigTrailer(uint64_t bootconfig_start_addr,
uint32_t bootconfig_size) {
if (!bootconfig_start_addr) {
return -1;
}
if (bootconfig_size == 0) {
return 0;
}
uint64_t end = bootconfig_start_addr + bootconfig_size;
if (isTrailerPresent(end)) {
// no need to overwrite the current trailers
return 0;
}
// size
memcpy((void *)(end), &bootconfig_size, BOOTCONFIG_SIZE_SIZE);
// checksum
uint32_t sum =
checksum((unsigned char*)bootconfig_start_addr, bootconfig_size);
memcpy((void *)(end + BOOTCONFIG_SIZE_SIZE), &sum,
BOOTCONFIG_CHECKSUM_SIZE);
// magic
memcpy((void *)(end + BOOTCONFIG_SIZE_SIZE + BOOTCONFIG_CHECKSUM_SIZE),
BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE);
return BOOTCONFIG_TRAILER_SIZE;
}

54
lib/libxbc/libxbc.h Normal file
View File

@@ -0,0 +1,54 @@
/*
* Copyright (C) 2021 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef LIBXBC_H_
#define LIBXBC_H_
// memcpy and strncmp
#include <common.h>
/*
* Add a string of boot config parameters to memory appended by the trailer.
* This memory needs to be immediately following the end of the ramdisks.
* The new boot config trailer will be written to the end of the entire
* parameter section(previous + new). The trailer contains a 4 byte size of the
* parameters, followed by a 4 byte checksum of the parameters, followed by a 12
* byte magic string.
*
* @param params pointer to string of boot config parameters
* @param params_size size of params string in bytes
* @param bootconfig_start_addr address that the boot config section is starting
* at in memory.
* @param bootconfig_size size of the current bootconfig section in bytes.
* @return number of bytes added to the boot config section. -1 for error.
*/
int addBootConfigParameters(char *params, uint32_t params_size,
uint64_t bootconfig_start_addr,
uint32_t bootconfig_size);
/*
* Add the boot config trailer to the end of the boot config parameter section.
* This can be used after the vendor bootconfig section has been placed into
* memory if there are no additional parameters that need to be added.
* The new boot config trailer will be written to the end of the entire
* parameter section at (bootconfig_start_addr + bootconfig_size).
* The trailer contains a 4 byte size of the parameters, followed by a 4 byte
* checksum of the parameters, followed by a 12 byte magic string.
*
* @param bootconfig_start_addr address that the boot config section is starting
* at in memory.
* @param bootconfig_size size of the current bootconfig section in bytes.
* @return number of bytes added to the boot config section. -1 for error.
*/
int addBootConfigTrailer(uint64_t bootconfig_start_addr,
uint32_t bootconfig_size);
#endif /* LIBXBC_H_ */

180
lib/sec_library/include/aes.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
@@ -14,23 +14,86 @@
#define _DRV_AES_H_
#include <stdint.h>
#include <drv/common.h>
#include "common.h"
#ifdef __cplusplus
extern "C" {
#endif
/*----- Encrypt & Decrypt: Config key length -----*/
#define AES_KEY_LEN_BYTES_32 (32)
#define AES_KEY_LEN_BYTES_24 (24)
#define AES_KEY_LEN_BYTES_16 (16)
#define AES_BLOCK_IV_SIZE (16)
#define AES_BLOCK_TAG_SIZE (16)
#define AES_BLOCK_CRYPTO_SIZE (16)
#define AES_DIR_ENCRYPT (1)
#define AES_DIR_DECRYPT (0)
#define KEY_128_BITS (0x08)
#define KEY_192_BITS (0x10)
#define KEY_256_BITS (0x18)
#define AES_DMA_ENABLE (1)
#define AES_DMA_DISABLE (0)
/**
\brief AES data transfer mode config
*/
typedef enum {
AES_KEY_LEN_BITS_128 = 0, ///< 128 Data bits
AES_KEY_LEN_BITS_192, ///< 192 Data bits
AES_KEY_LEN_BITS_256 ///< 256 Data bits
AES_SLAVE_MODE = 0U, /*slave mode*/
AES_DMA_MODE, /*dma mode*/
} csi_aes_trans_mode_t;
/**
\brief AES Keylen type
*/
typedef enum {
AES_KEY_LEN_BITS_128 = 0, /*128 Data bits*/
AES_KEY_LEN_BITS_192, /*192 Data bits*/
AES_KEY_LEN_BITS_256 /*256 Data bits*/
} csi_aes_key_bits_t;
/**
\brief AES mode config
*/
typedef enum{
AES_MODE_ECB = 0,
AES_MODE_CBC = 0x20000020,
AES_MODE_CTR = 0x200001c0,
AES_MODE_CFB = 0x20000400,
AES_MODE_GCM = 0x20030040,
AES_MODE_CCM = 0x21D40040,
AES_MODE_OFB = 0x24000000,
} csi_aes_mode_t;
/**
\brief AES state
*/
typedef struct {
uint32_t busy : 1; /*Calculate busy flag*/
uint32_t error : 1; /*Calculate error flag*/
} csi_aes_state_t;
/**
\brief AES Context
*/
typedef struct {
uint32_t key_len_byte;
uint8_t key[32]; /*Data block being processed*/
uint32_t sca;
uint32_t is_kdf;
uint32_t is_dma;
} csi_aes_context_t;
/**
\brief AES Ctrl Block
*/
typedef struct {
csi_aes_state_t state;
csi_aes_context_t context;
csi_dev_t dev;
void *priv;
} csi_aes_t;
@@ -97,7 +160,7 @@ csi_error_t csi_aes_ecb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t si
\param[in] iv Init vector
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv) ;
/**
\brief AES cbc decrypt
@@ -161,10 +224,9 @@ csi_error_t csi_aes_cfb8_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t s
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES cfb128 encrypt
@@ -173,10 +235,9 @@ csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES ofb encrypt
@@ -185,22 +246,22 @@ csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\param[in] key_len key bits
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES ofb decrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
\brief Aes ofb decrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\param[in] key_len key bits
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, void *iv);
/**
\brief AES ctr encrypt
@@ -208,20 +269,10 @@ csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t si
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] nonce_counter Pointer to the 128-bit nonce and counter
\param[in] stream_block Pointer to the saved stream-block for resuming
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,
void *in,
void *out,
uint32_t size,
uint8_t nonce_counter[16],
uint8_t stream_block[16],
void *iv,
uint32_t *num);
csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,void *in,void *out,uint32_t size,void *iv);
/**
\brief AES ctr decrypt
@@ -229,20 +280,56 @@ csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] nonce_counter Pointer to the 128-bit nonce and counter
\param[in] stream_block Pointer to the saved stream-block for resuming
\param[in] iv Init vecotr
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes,
void *in,
void *out,
uint32_t size,
uint8_t nonce_counter[16],
uint8_t stream_block[16],
void *iv,
uint32_t *num);
csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes,void *in,void *out,uint32_t size,void *iv);
/**
\brief Aes gcm encrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_gcm_encrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
/**
\brief Aes gcm decrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data.
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vecotr
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_gcm_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
/**
\brief Aes ccm encrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\param[in] tag_out tag output
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_ccm_encrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t *tag_out);
/**
\brief Aes ccm decrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vecotr
\param[in] tag_out tag output
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_ccm_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t *tag_out);
/**
\brief Enable AES power manage
@@ -258,6 +345,13 @@ csi_error_t csi_aes_enable_pm(csi_aes_t *aes);
*/
void csi_aes_disable_pm(csi_aes_t *aes);
/**
\brief Config AES data transfer mode
\param[in] mode \ref csi_des_trans_mode_t
\return None
*/
csi_error_t csi_aes_trans_config(csi_aes_t *aes, csi_aes_trans_mode_t mode);
#ifdef __cplusplus
}
#endif

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/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/common.h
* @brief Header File for Common Driver
* @version V1.0
* @date 31. March 2020
* @model common
******************************************************************************/
#ifndef _DRV_COMMON_H_
#define _DRV_COMMON_H_
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include "list.h"
#include "dev_tag.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_DEBUG_MODE
#define CSI_ASSERT(expr) \
do { \
if ((unsigned long)expr == (unsigned long)NULL) { \
printf("PROGRAM ASSERT\n"); \
while(1); \
} \
} while(0);
#else
#define CSI_ASSERT(expr) ((void)0U)
#endif
#ifdef CONFIG_PARAM_NOT_CHECK
#define CSI_PARAM_CHK(para, err) \
do { \
if ((unsigned long)para == (unsigned long)NULL) { \
return (err); \
} \
} while (0)
#define CSI_PARAM_CHK_NORETVAL(para) \
do { \
if ((unsigned long)para == (unsigned long)NULL) { \
return; \
} \
} while (0)
#else
#define CSI_PARAM_CHK(para, err)
#define CSI_PARAM_CHK_NORETVAL(para)
#endif
#define CSI_EXAMPLE_RESULT(val) \
do { \
if(val>=0) \
{ \
printf("-*success*-\n"); \
} \
else \
{ \
printf("-*fail*-\n"); \
} \
} while (0);
typedef enum {
CSI_OK = 0,
CSI_ERROR = -1,
CSI_BUSY = -2,
CSI_TIMEOUT = -3,
CSI_UNSUPPORTED = -4,
CSI_INVALID_PARAM = -5,
CSI_CRYPT_FAIL = -6,
} csi_error_t;
typedef struct {
uint8_t readable;
uint8_t writeable;
uint8_t error;
} csi_state_t;
typedef struct csi_dev csi_dev_t;
#ifdef CONFIG_PM
typedef enum {
PM_DEV_SUSPEND,
PM_DEV_RESUME,
} csi_pm_dev_action_t;
typedef enum {
PM_MODE_RUN = 0, ///< Running mode
PM_MODE_SLEEP_1, ///< Sleep LV1 mode
PM_MODE_SLEEP_2, ///< Sleep LV2 mode
PM_MODE_DEEP_SLEEP_1, ///< Deep sleep LV1 mode
PM_MODE_DEEP_SLEEP_2, ///< Deep sleep LV2 mode
PM_MODE_DEEP_SLEEP_3, ///< Deep sleep LV3 mode
} csi_pm_mode_t;
typedef struct {
slist_t next;
csi_error_t (*pm_action)(csi_dev_t *dev, csi_pm_dev_action_t action);
uint32_t *reten_mem;
uint32_t size;
} csi_pm_dev_t;
#include <drv/pm.h>
#endif
struct csi_dev {
unsigned long reg_base;
uint8_t irq_num;
uint8_t idx;
uint16_t dev_tag;
void (*irq_handler)(void *);
#ifdef CONFIG_PM
csi_pm_dev_t pm_dev;
#endif
};
#define HANDLE_REG_BASE(handle) (handle->dev.reg_base)
#define HANDLE_IRQ_NUM(handle) (handle->dev.irq_num)
#define HANDLE_DEV_IDX(handle) (handle->dev.idx)
#define HANDLE_IRQ_HANDLER(handle) (handle->dev.irq_handler)
typedef struct {
unsigned long reg_base;
uint8_t irq_num;
uint8_t idx;
uint16_t dev_tag;
} csi_perip_info_t;
csi_error_t target_get(csi_dev_tag_t dev_tag, uint32_t idx, csi_dev_t *dev);
csi_error_t target_get_optimal_dma_channel(void *dma_list, uint32_t ctrl_num, csi_dev_t *parent_dev, void *ch_info);
// void mdelay(uint32_t ms);
// void udelay(uint32_t us);
void msleep(uint32_t ms);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_COMMON_H_ */

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@@ -0,0 +1 @@
Just include csi_core.h!

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/**************************************************************************//**
* @file ARMCM0.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ARMCM0_H
#define ARMCM0_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Processor Exceptions Numbers ----------------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ------------------- Processor Interrupt Numbers ------------------------------ */
Interrupt0_IRQn = 0,
Interrupt1_IRQn = 1,
Interrupt2_IRQn = 2,
Interrupt3_IRQn = 3,
Interrupt4_IRQn = 4,
Interrupt5_IRQn = 5,
Interrupt6_IRQn = 6,
Interrupt7_IRQn = 7,
Interrupt8_IRQn = 8,
Interrupt9_IRQn = 9
/* Interrupts 10 .. 31 are left out */
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM0_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 0U /* no MPU present */
#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#include "core_cm0.h" /* Processor and core peripherals */
#include "system_ARMCM0.h" /* System Header */
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
#ifdef __cplusplus
}
#endif
#endif /* ARMCM0_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file csi_core.h
* @brief Header File for csi_core
* @version V1.0
* @date 12. june 2019
******************************************************************************/
#ifndef _CSI_CORE_H_
#define _CSI_CORE_H_
#include <stddef.h>
#include <cmsis_gcc.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __GNUC__
__STATIC_INLINE size_t csi_irq_save(void)
{
uint32_t result;
result = __get_PRIMASK();
__disable_irq();
return (result);
}
__STATIC_INLINE void csi_irq_restore(size_t irq_state)
{
__set_PRIMASK(irq_state);
}
#else
static inline __asm size_t csi_irq_save(void)
{
MRS R0, PRIMASK
CPSID I
BX LR
return 0;
}
static inline __asm void csi_irq_restore(size_t irq_state)
{
MSR PRIMASK, R0
BX LR
}
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CSI_CORE_H_ */

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/**************************************************************************//**
* @file system_ARMCM0.h
* @brief CMSIS Device System Header File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_ARMCM0_H
#define SYSTEM_ARMCM0_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_ARMCM0_H */

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