fix: remove find partuuid

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>

.github/workflows/build.yml

@@ -0,0 +1,137 @@
+name: thead-u-boot-build
+
+on:
+  push:
+    tags:
+      - '*'
+    branches:
+      - '*'
+  pull_request:
+  workflow_dispatch:
+  schedule:
+    - cron: "0 2 * * *"
+
+env:
+  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1698113812618
+  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0-20231018.tar.gz
+  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.10.18
+  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2023.10.18-nightly.tar.gz
+  wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
+  ARCH: riscv
+  CROSS_COMPILE: riscv64-unknown-linux-gnu-
+
+jobs:
+  build:
+    strategy:
+      fail-fast: false
+      matrix:
+        name: [thead-gcc, gcc-13]
+
+    runs-on: ubuntu-22.04
+
+    steps:
+      - name: Install software
+        run: |
+              sudo apt update && \
+              sudo apt install -y gdisk dosfstools g++-12-riscv64-linux-gnu build-essential \
+                                  libncurses-dev gawk flex bison openssl libssl-dev tree \
+                                  dkms libelf-dev libudev-dev libpci-dev libiberty-dev autoconf device-tree-compiler
+
+      - name: Checkout uboot
+        uses: actions/checkout@v4
+
+      - name: uboot compile
+        run: |
+              mkdir output
+              if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
+                ${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
+                tar -xvf ${toolchain_file_name} -C /opt
+                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0/bin:$PATH"
+              else
+                ${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
+                tar -xvf ${mainline_toolchain_file_name} -C /opt
+                export PATH="/opt/riscv/bin:$PATH"
+              fi
+              ${CROSS_COMPILE}gcc -v
+
+              pushd $PWD
+                make light_lpi4a_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-16g.bin
+                make clean
+                make light_lpi4a_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a.bin
+                make clean
+                make light_lpi4a_console_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lcon4a.bin
+                make clean
+                make light_lpi4a_console_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lcon4a-16g.bin
+                make clean
+                make light_lpi4a_cluster_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a.bin
+                make clean
+                make light_lpi4a_cluster_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-16g.bin
+                make clean
+                make light_beagle_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-beagle.bin
+                make clean
+                make light_a_val_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-vala.bin
+                make clean
+                make light_milkv_meles_dualrank_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles.bin
+                make clean
+                make light_milkv_meles_singlerank_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles-4g.bin
+
+                # mainline support
+                make clean
+                make light_lpi4a_defconfig
+                sed -i 's#thead/light-lpi4a.dtb#thead/th1520-lichee-pi-4a.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-main.bin
+
+                make clean
+                make light_lpi4a_16g_defconfig
+                sed -i 's#thead/light-lpi4a-16gb.dtb#thead/th1520-lichee-pi-4a-16g.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-16g-main.bin
+
+                make clean
+                make light_lpi4a_cluster_defconfig
+                sed -i 's#thead/light-lpi4a-cluster.dtb#thead/th1520-lichee-cluster-4a.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-main.bin
+
+                make clean
+                make light_lpi4a_cluster_16g_defconfig
+                sed -i 's#thead/light-lpi4a-cluster-16gb.dtb#thead/th1520-lichee-cluster-4a-16g.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-16g-main.bin
+              popd
+              tree ${GITHUB_WORKSPACE}/output
+
+      - name: 'Upload Artifact'
+        uses: actions/upload-artifact@v3
+        with:
+          name: thead-u-uboot-${{ matrix.name }}
+          path: output/*.bin
+          retention-days: 30
+
+      - name: 'Create release by tag'
+        uses: softprops/action-gh-release@v1
+        if: ${{ startsWith(github.ref, 'refs/tags/') && matrix.name == 'thead-gcc' }}
+        with:
+          files: output/*.bin
+          token: ${{ secrets.GITHUB_TOKEN }}

Makefile

@@ -727,7 +727,6 @@ UBOOTINCLUDE    := \
 				-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
 		-I$(srctree)/arch/$(ARCH)/include \
 		$(if $(CONFIG_TARGET_LIGHT_C910), -I$(srctree)/lib/sec_library/include) \
-		$(if $(CONFIG_TARGET_LIGHT_C910), -I$(srctree)/lib/sec_library/include/soft_crypto) \
 		-include $(srctree)/include/linux/kconfig.h
 
 NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
@@ -758,8 +757,6 @@ libs-y += drivers/net/phy/
 libs-y += drivers/power/ \
 	drivers/power/domain/ \
 	drivers/power/fuel_gauge/ \
-	drivers/power/charge/ \
-	drivers/mcu/ \
 	drivers/power/mfd/ \
 	drivers/power/pmic/ \
 	drivers/power/battery/ \

arch/Kconfig

@@ -119,6 +119,7 @@ config SANDBOX
 	select SPI
 	select SUPPORT_OF_CONTROL
 	select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+	select SUPPORT_EXTENSION_SCAN
 	imply BITREVERSE
 	select BLOBLIST
 	imply CMD_DM
@@ -152,6 +153,7 @@ config SANDBOX
 	imply PHYLIB
 	imply DM_MDIO
 	imply DM_MDIO_MUX
+	imply CMD_EXTENSION
 
 config SH
 	bool "SuperH architecture"

arch/riscv/Makefile

@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
 	CMODEL = medany
 endif
 
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
+
+# Newer binutils versions default to ISA spec version 20191213 which moves some
+# instructions from the I extension to the Zicsr and Zifencei extensions.
+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
+ifeq ($(toolchain-need-zicsr-zifencei),y)
+	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
+endif
+
+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
 	     -mcmodel=$(CMODEL)
 
 PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)

arch/riscv/cpu/c9xx/cpu.c

@@ -125,10 +125,11 @@ void icache_enable(void)
 #ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
+// mhcr is 0x7c1
 	asm volatile (
-        "csrr x29, mhcr\n\t"
+        "csrr x29, 0x7c1\n\t"
         "ori x28, x29, 0x1\n\t"
-        "csrw mhcr, x28\n\t"
+        "csrw 0x7c1, x28\n\t"
     );
 #endif
 #endif
@@ -141,9 +142,9 @@ void dcache_enable(void)
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
 	asm volatile (
-		"csrr x29, mhcr\n\t"
-        "ori x28, x29, 0x2\n\t"
-        "csrw mhcr, x28\n\t"
+	"csrr x29, 0x7c1\n\t"
+	"ori x28, x29, 0x2\n\t"
+	"csrw 0x7c1, x28\n\t"
     );
 #endif
 #endif

arch/riscv/cpu/c9xx/dram.c

@@ -14,9 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
 int dram_init(void)
 {
 #ifdef CONFIG_DDR_BOARD_CONFIG
-	// already setup during ddr initial flow
-	gd->bd->bi_memsize = gd->ram_size;
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+extern unsigned long get_ddr_density(void);
+	// update ram_size from board config info
+	gd->ram_size = get_ddr_density();
 	return 0;
 #else
 	return fdtdec_setup_mem_size_base();

arch/riscv/cpu/cpu.c

@@ -27,15 +27,6 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
 u32 available_harts_lock = 1;
 #endif
 
-void arch_setup_gd(struct global_data *gd_ptr)
-{
-	// sync specific info from spl
-	gd_ptr->ram_size = gd->ram_size;
-
-	// setup gd ptr
-	gd = gd_ptr;
-}
-
 static inline bool supports_extension(char ext)
 {
 #ifdef CONFIG_CPU

arch/riscv/cpu/start.S

@@ -104,6 +104,12 @@ call_board_init_f_0:
 	mv	a0, sp
 	jal	board_init_f_alloc_reserve
 
+	/*
+	 * Set global data pointer here for all harts, uninitialized at this
+	 * point.
+	 */
+	mv	gp, a0
+
 	/* setup stack */
 #ifdef CONFIG_SMP
 	/* tp: hart id */
@@ -121,34 +127,16 @@ call_board_init_f_0:
 	la	t0, hart_lottery
 	li	s2, 1
 	amoswap.w s2, t1, 0(t0)
-	beqz	s2, call_board_init_f_1
-
-	/*
-	 * Set global data pointer here for secondary harts, uninitialized at this
-	 * point.
-	 */
-	mv	gp, a0
-
-	jal wait_for_gd_init
+	bnez	s2, wait_for_gd_init
 #else
-	beqz	tp, call_board_init_f_1
-
-	/*
-	 * Set global data pointer here for secondary harts, uninitialized at this
-	 * point.
-	 */
-	mv	gp, a0
-
-	jal secondary_hart_loop
+	bnez	tp, secondary_hart_loop
 #endif
 
-call_board_init_f_1:
 #ifdef CONFIG_OF_PRIOR_STAGE
 	la	t0, prior_stage_fdt_address
 	SREG	s1, 0(t0)
 #endif
 
-	 /* Set global data pointer here for main hart */
 	jal	board_init_f_init_reserve
 
 	/* save the boot hart id to global_data */

arch/riscv/dts/Makefile

@@ -5,7 +5,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
-dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb th1520-rvbook.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb light-milkv-meles.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-lpi4a-laptop.dtb
 
 targets += $(dtb-y)
 

arch/riscv/dts/light-a-val.dts

@@ -1,7 +1,4 @@
 /dts-v1/;
-
-#include <dt-bindings/pmic/light_pmic.h>
-
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -312,7 +309,7 @@
 			tpm@0{
 				compatible = "z32h330tc,z32h330tc-spi";
 				reg = <0>;
-				spi-max-frequency = <20000000>;
+				spi-max-frequency = <40000000>;
 			};
 		};
 
@@ -362,20 +359,6 @@
 			};
 		};
 
-		usb: usb@ffe7040000 {
-			compatible = "snps,dwc3";
-			reg = <0xff 0xe7040000 0x0 0x10000>;
-			interrupts = <68>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			maximum-speed = "super-speed";
-			dr_mode = "host";
-			dma-mask = <0xf 0xffffffff>;
-			snps,usb3_lpm_capable;
-			snps,usb_sofitpsync;
-			status = "okay";
-		};
-
 		pwm: pwm@ffec01c000 {
 			compatible = "thead,pwm-light";
 			reg = <0xff 0xec01c000 0x0 0x4000>;
@@ -496,429 +479,6 @@
 			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
 			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
 		};
-
-		aon {
-		compatible = "thead,light-aon";
-		status = "okay";
-
-		wakeup-by-gpio-on;
-		wakeup-by-rtc-on;
-
-		pd: light-aon-pd {
-			compatible = "thead,light-aon-pd";
-			#power-domain-cells = <1>;
-		};
-
-		light-regu-reg {
-			compatible = "thead,light-dialog-pmic";
-			status = "okay";
-
-			soc_dvdd18_aon_reg: soc_dvdd18_aon {
-				regulator-name = "soc_dvdd18_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
-				regulator-name = "soc_avdd33_usb3";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_aon_reg: soc_dvdd08_aon {
-				regulator-name = "soc_dvdd08_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
-				regulator-name = "soc_apcpu_dvdd_dvddm";
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1570000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
-				regulator-name = "soc_dvdd08_ddr";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
-				regulator-name = "soc_vdd_ddr_1v8";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
-				regulator-name = "soc_vdd_ddr_1v1";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
-				regulator-name = "soc_vdd_ddr_0v6";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_ap_reg: soc_dvdd18_ap {
-				regulator-name = "soc_dvdd18_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ap_reg: soc_dvdd08_ap {
-				regulator-name = "soc_dvdd08_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
-				regulator-name = "soc_avdd08_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
-				regulator-name = "soc_avdd18_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
-				regulator-name = "soc_dvdd33_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
-				regulator-name = "soc_vdd18_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_scan_reg: soc_dovdd18_scan {
-				regulator-name = "soc_dovdd18_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-			};
-			soc_vext_2v8_reg: soc_vext_2v8 {
-				regulator-name = "soc_vext_2v8";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dvdd12_scan_reg: soc_dvdd12_scan {
-				regulator-name = "soc_dvdd12_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-			};
-			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
-				regulator-name = "soc_avdd28_scan_en";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-			};
-			soc_avdd28_rgb_reg: soc_avdd28_rgb {
-				regulator-name = "soc_avdd28_rgb";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
-				regulator-name = "soc_dovdd18_rgb";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
-				regulator-name = "soc_dvdd12_rgb";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_avdd25_ir_reg: soc_avdd25_ir {
-				regulator-name = "soc_avdd25_ir";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_ir_reg: soc_dovdd18_ir {
-				regulator-name = "soc_dovdd18_ir";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dvdd12_ir_reg: soc_dvdd12_ir {
-				regulator-name = "soc_dvdd12_ir";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-	   };
-
-	    aon_pmic_config {
-			compatible = "thead,light-pmic-conf";
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			iic-config = <0 0 2>;
-			pmic_dev_0: pmic-dev@0 {
-			  pmic-name = "dialog,da9063,v1";
-			  pmic-addr = <0x5a 0x5b>;
-			  pmic_wdt_on;
-			  errio_gpio = <0 14 3>;
-			  status = "okay";
-			};
-
-			pmic_dev_1: pmic-dev@1 {
-			  pmic-name = "dialog,da9121,v1";
-			  pmic-addr = <0x68>;
-			  status = "okay";
-			};
-
-			pmic_dev_2: pmic-dev@2 {
-			  pmic-name = "dialog,slg51000,v1";
-			  pmic-addr = <0x75>;
-			  status = "okay";
-			};
-
-			regu_config_0 {
-                reg_info = <&soc_dvdd18_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
-				};
-			};
-
-			regu_config_1 {
-                reg_info = <&soc_avdd33_usb3_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
-				};
-			};
-
-			regu_config_2 {
-                reg_info = <&soc_dvdd08_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
-				};
-			};
-
-			regu_config_3 {
-                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
-					auto_on_info = <0 0 800000>;
-				};
-
-				regu_id@1 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
-					auto_on_info = <1 0 800000>;
-				};
-
-				coupling_info@0 {
-					negative-min;
-                    info = <0 1 5 30>;
-				};
-			};
-
-			regu_config_4 {
-                reg_info = <&soc_dvdd08_ddr_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
-				};
-			};
-
-			regu_config_5 {
-                reg_info = <&soc_vdd_ddr_1v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
-				};
-			};
-
-		    regu_config_6 {
-                reg_info = <&soc_vdd_ddr_1v1_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
-				};
-				regu_id@1 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
-				};
-
-			};
-
-			regu_config_7 {
-                reg_info = <&soc_vdd_ddr_0v6_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
-				};
-			};
-
-			regu_config_8 {
-                reg_info = <&soc_dvdd18_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
-				};
-			};
-
-            regu_config_9 {
-                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
-				};
-			};
-
-			regu_config_10 {
-                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
-				};
-			};
-
-			regu_config_11 {
-                reg_info = <&soc_dvdd33_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
-				};
-			};
-
-			regu_config_12 {
-                reg_info = <&soc_dovdd18_scan_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
-					auto_on_info = <2 1 1800000>;
-					auto_off_info = <7 1>;
-				};
-			};
-
-			regu_config_13 {
-                reg_info = <&soc_vext_2v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
-					auto_on_info = <3 1 2800000>;
-					auto_off_info = <8 1>;
-				};
-			};
-
-			regu_config_14 {
-                reg_info = <&soc_dvdd12_scan_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
-					auto_on_info = <4 1 1200000>;
-					auto_off_info = <9 1>;
-				};
-			};
-
-			regu_config_15 {
-                reg_info = <&soc_avdd28_scan_en_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>;
-					auto_on_info = <5 1 2800000>;
-					auto_off_info = <6 1>;
-				};
-			};
-
-			regu_config_16 {
-                reg_info = <&soc_dvdd08_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
-                    parent_pmic_dev = <&pmic_dev_0 2 0>;
-				};
-			};
-
-			regu_config_17 {
-                reg_info = <&soc_avdd28_rgb_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO1>;
-                    auto_on_info = <6 0 2800000>;
-					auto_off_info = <0 1>;
-				};
-			};
-
-			regu_config_18 {
-                reg_info = <&soc_avdd25_ir_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO2>;
-                    auto_on_info = <7 0 2500000>;
-					auto_off_info = <1 1>;
-				};
-			};
-
-			regu_config_19 {
-                reg_info = <&soc_dvdd18_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO3>;
-					parent_pmic_dev = <&pmic_dev_0 7 0>;
-				};
-			};
-
-			regu_config_20 {
-                reg_info = <&soc_dovdd18_rgb_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO4>;
-				    auto_on_info = <8 0 1800000>;
-					auto_off_info = <2 1>;
-				};
-			};
-
-			regu_config_21 {
-                reg_info = <&soc_dvdd12_rgb_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO5>;
-				    auto_on_info = <9 0 1200000>;
-					auto_off_info = <3 1>;
-				};
-			};
-
-			regu_config_22 {
-                reg_info = <&soc_dvdd12_ir_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO6>;
-				    auto_on_info = <10 0 1200000>;
-					auto_off_info = <4 1>;
-				};
-			};
-
-			 regu_config_23 {
-                reg_info = <&soc_dovdd18_ir_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO7>;
-				    auto_on_info = <11 0 1800000>;
-					auto_off_info = <5 1>;
-				};
-			};
-		};
-	};
-
 	};
 
 	chosen {

arch/riscv/dts/light-b-product.dts

@@ -1,7 +1,4 @@
 /dts-v1/;
-
-#include <dt-bindings/pmic/light_pmic.h>
-
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -472,362 +469,6 @@
 			lcd-en-gpios    = <&gpio1_porta 9 0>; /* active high */
 			lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
 		};
-
-		aon {
-		compatible = "thead,light-aon";
-		status = "okay";
-
-		wakeup-by-gpio-on;
-		wakeup-by-rtc-on;
-
-		pd: light-aon-pd {
-			compatible = "thead,light-aon-pd";
-			#power-domain-cells = <1>;
-		};
-
-		light-regu-reg {
-			compatible = "thead,light-dialog-pmic";
-			status = "okay";
-
-
-
-			soc_dvdd18_aon_reg: soc_dvdd18_aon {
-				regulator-name = "soc_dvdd18_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
-				regulator-name = "soc_avdd33_usb3";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_aon_reg: soc_dvdd08_aon {
-				regulator-name = "soc_dvdd08_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
-				regulator-name = "soc_apcpu_dvdd_dvddm";
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1570000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
-				regulator-name = "soc_dvdd08_ddr";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
-				regulator-name = "soc_vdd_ddr_1v8";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
-				regulator-name = "soc_vdd_ddr_1v1";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
-				regulator-name = "soc_vdd_ddr_0v6";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_ap_reg: soc_dvdd18_ap {
-				regulator-name = "soc_dvdd18_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ap_reg: soc_dvdd08_ap {
-				regulator-name = "soc_dvdd08_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
-				regulator-name = "soc_avdd08_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
-				regulator-name = "soc_avdd18_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
-				regulator-name = "soc_dvdd33_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
-				regulator-name = "soc_vdd18_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_scan_reg: soc_dovdd18_scan {
-				regulator-name = "soc_dovdd18_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-				status = "disabled";
-			};
-			soc_vext_2v8_reg: soc_vext_2v8 {
-				regulator-name = "soc_vext_2v8";
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_scan_reg: soc_dvdd12_scan {
-				regulator-name = "soc_dvdd12_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-				status = "disabled";
-			};
-			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
-				regulator-name = "soc_avdd28_scan_en";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				status = "disabled";
-			};
-			soc_avdd28_rgb_reg: soc_avdd28_rgb {
-				regulator-name = "soc_avdd28_rgb";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
-				regulator-name = "soc_dovdd18_rgb";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
-				regulator-name = "soc_dvdd12_rgb";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_avdd25_ir_reg: soc_avdd25_ir {
-				regulator-name = "soc_avdd25_ir";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dovdd18_ir_reg: soc_dovdd18_ir {
-				regulator-name = "soc_dovdd18_ir";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_ir_reg: soc_dvdd12_ir {
-				regulator-name = "soc_dvdd12_ir";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_adc_vref_reg: soc_adc_vref {
-				regulator-name = "soc_adc_vref";
-			};
-			soc_lcd0_en_reg: soc_lcd0_en {
-				regulator-name = "soc_lcd0_en";
-			};
-			soc_vext_1v8_reg: soc_vext_1v8 {
-				regulator-name = "soc_vext_1v8";
-			};
-	   };
-
-	    aon_pmic_config {
-			compatible = "thead,light-pmic-conf";
-			status = "okay";
-			#address-cells = <1>;
-		    #size-cells = <0>;
-			iic-config = <0 0 2>;
-			pmic_dev_0: pmic-dev@0 {
-			  pmic-name = "ricoh,rn5t567,v0";
-			  pmic-addr = <0x31>;
-			  pmic_wdt_on;
-			  status = "okay";
-			};
-
-			pmic_dev_1: pmic-dev@1 {
-			  pmic-name = "ricoh,rn5t567,v1";
-			  pmic-addr = <0x32>;
-			  status = "okay";
-			};
-
-			regu_config_0 {
-                reg_info = <&soc_dvdd18_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO4>;
-				};
-			};
-
-			regu_config_1 {
-                reg_info = <&soc_avdd33_usb3_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO1>;
-				};
-			};
-
-			regu_config_2 {
-                reg_info = <&soc_dvdd08_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO3>;
-				};
-			};
-
-			regu_config_3 {
-                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC3>;
-					auto_on_info = <2 0 800000>;
-				};
-
-				regu_id@1 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC4>;
-					auto_on_info = <3 0 800000>;
-				};
-
-				coupling_info@0 {
-					negative-min;
-                    info = <0 1 5 30>;
-				};
-			};
-
-			regu_config_4 {
-                reg_info = <&soc_dvdd08_ddr_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC1>;
-				};
-			};
-
-			regu_config_5 {
-                reg_info = <&soc_vdd_ddr_1v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO2>;
-				};
-			};
-
-		    regu_config_6 {
-                reg_info = <&soc_vdd_ddr_1v1_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC2>;
-				};
-			};
-
-			regu_config_7 {
-                reg_info = <&soc_vdd_ddr_0v6_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC1>;
-				};
-			};
-
-			regu_config_8 {
-                reg_info = <&soc_dvdd18_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO2>;
-				};
-			};
-
-            regu_config_9 {
-                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-					pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO3>;
-				};
-			};
-
-			regu_config_10 {
-                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO4>;
-				};
-			};
-
-			regu_config_11 {
-                reg_info = <&soc_dvdd33_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO1>;
-				};
-			};
-
-			regu_config_12 {
-                reg_info = <&soc_dvdd08_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_GPIO3>;
-				};
-			};
-
-			regu_config_13 {
-                reg_info = <&soc_dvdd18_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC3>;
-				};
-			};
-
-			regu_config_14 {
-                reg_info = <&soc_adc_vref_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO5>;
-				};
-			};
-
-			regu_config_15 {
-                reg_info = <&soc_lcd0_en_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO5>;
-					auto_on_info = <0 0 1800000>;
-				};
-			};
-
-			regu_config_16 {
-                reg_info = <&soc_vext_1v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC4>;
-					auto_on_info = <1 0 1800000>;
-				};
-			};
-		};
-	};
 	};
 
 	chosen {

arch/riscv/dts/light-lpi4a-laptop.dts

@@ -0,0 +1,45 @@
+#include "light-lpi4a.dts"
+
+/ {
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+        status = "okay";
+
+        pcal6408ahk_c: gpio@20 {
+                compatible = "nxp,pca9557";
+                reg = <0x18>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	status = "okay";
+	pcal6408ahk_d: gpio@20 {
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&lcd_backlight {
+	pwms = <&pwm 0 50000>;
+	brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
+	36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+	76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
+	default-brightness-level = <2>;
+};
+
+&panel0 {
+	status = "okay";
+	backlight = <&lcd_backlight>;
+	// 5v power cycle
+	// TODO: move into regulator
+	reset-gpios     = <&pcal6408ahk_c 0 0>; /* active low  */
+	/delete-property/ lcd-en-gpios;
+	/delete-property/ lcd-bias-en-gpios;
+};

arch/riscv/dts/light-lpi4a.dts

@@ -1,7 +1,4 @@
 /dts-v1/;
-
-#include <dt-bindings/pmic/light_pmic.h>
-
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -150,13 +147,6 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
-
-			pcal6408ahk_d: gpio@20 {
-				compatible = "nxp,pca9557";
-				reg = <0x18>;
-				gpio-controller;
-				#gpio-cells = <2>;
-			};
 		};
 
 		i2c4: i2c@ffe7f28000{
@@ -167,6 +157,13 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
 		};
 
 		i2c5: i2c@fff7f2c000{
@@ -385,20 +382,6 @@
 			reg = <0xff 0xef600000 0x0 0x100>;
 		};
 
-		usb: usb@ffe7040000 {
-			compatible = "snps,dwc3";
-			reg = <0xff 0xe7040000 0x0 0x10000>;
-			interrupts = <68>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			maximum-speed = "super-speed";
-			dr_mode = "host";
-			dma-mask = <0xf 0xffffffff>;
-			snps,usb3_lpm_capable;
-			snps,usb_sofitpsync;
-			status = "okay";
-		};
-
 		axiscr {
 			compatible = "thead,axiscr";
 			reg = <0xff 0xff004000 0x0 0x1000>;
@@ -489,376 +472,13 @@
 			default-brightness-level = <7>;
 		};
 
-		jadard_jd9365da {
-			compatible      = "jadard,jd9365da-h3";
+		panel0: dsi_panel0 {
+			compatible      = "ilitek,ili9881c";
 			backlight       = <&lcd_backlight>;
-			reset-gpio     = <&pcal6408ahk_d 7 0>;
-			hsvcc-gpio   = <&pcal6408ahk_d 6 1>;
-			vspn3v3-gpio = <&pcal6408ahk_d 5 1>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
+			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
 		};
-
-		aon {
-		compatible = "thead,light-aon";
-		status = "okay";
-
-		wakeup-by-gpio-on;
-		wakeup-by-rtc-on;
-
-		pd: light-aon-pd {
-			compatible = "thead,light-aon-pd";
-			#power-domain-cells = <1>;
-		};
-
-		light-regu-reg {
-			compatible = "thead,light-dialog-pmic";
-			status = "okay";
-
-
-
-			soc_dvdd18_aon_reg: soc_dvdd18_aon {
-				regulator-name = "soc_dvdd18_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
-				regulator-name = "soc_avdd33_usb3";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_aon_reg: soc_dvdd08_aon {
-				regulator-name = "soc_dvdd08_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
-				regulator-name = "soc_apcpu_dvdd_dvddm";
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1570000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
-				regulator-name = "soc_dvdd08_ddr";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
-				regulator-name = "soc_vdd_ddr_1v8";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
-				regulator-name = "soc_vdd_ddr_1v1";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
-				regulator-name = "soc_vdd_ddr_0v6";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_ap_reg: soc_dvdd18_ap {
-				regulator-name = "soc_dvdd18_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ap_reg: soc_dvdd08_ap {
-				regulator-name = "soc_dvdd08_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
-				regulator-name = "soc_avdd08_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
-				regulator-name = "soc_avdd18_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
-				regulator-name = "soc_dvdd33_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
-				regulator-name = "soc_vdd18_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_scan_reg: soc_dovdd18_scan {
-				regulator-name = "soc_dovdd18_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-			};
-			soc_vext_2v8_reg: soc_vext_2v8 {
-				regulator-name = "soc_vext_2v8";
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_scan_reg: soc_dvdd12_scan {
-				regulator-name = "soc_dvdd12_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-			};
-			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
-				regulator-name = "soc_avdd28_scan_en";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-			};
-			soc_avdd28_rgb_reg: soc_avdd28_rgb {
-				regulator-name = "soc_avdd28_rgb";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
-				regulator-name = "soc_dovdd18_rgb";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
-				regulator-name = "soc_dvdd12_rgb";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_avdd25_ir_reg: soc_avdd25_ir {
-				regulator-name = "soc_avdd25_ir";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dovdd18_ir_reg: soc_dovdd18_ir {
-				regulator-name = "soc_dovdd18_ir";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_ir_reg: soc_dvdd12_ir {
-				regulator-name = "soc_dvdd12_ir";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-	   };
-
-	    aon_pmic_config {
-			compatible = "thead,light-pmic-conf";
-			status = "okay";
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-			iic-config = <0 0 2>;
-			pmic_dev_0: pmic-dev@0 {
-			  pmic-name = "dialog,da9063,v1";
-			  pmic-addr = <0x5a 0x5b>;
-			  pmic_wdt_on;
-			  status = "okay";
-			};
-
-			pmic_dev_1: pmic-dev@1 {
-			  pmic-name = "dialog,da9121,v1";
-			  pmic-addr = <0x68>;
-			  status = "okay";
-			};
-
-			regu_config_0 {
-                reg_info = <&soc_dvdd18_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
-				};
-			};
-
-			regu_config_1 {
-                reg_info = <&soc_avdd33_usb3_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
-				};
-			};
-
-			regu_config_2 {
-                reg_info = <&soc_dvdd08_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
-				};
-			};
-
-			regu_config_3 {
-                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
-					auto_on_info = <0 0 800000>;
-				};
-
-				regu_id@1 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
-					auto_on_info = <1 0 800000>;
-				};
-
-				regu_id@2 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
-					auto_on_info = <2 0 800000>;
-				};
-
-				coupling_info@0 {
-					negative-min;
-                    info = <0 2 5 30>;
-				};
-
-				coupling_info@1 {
-					negative-min;
-                    info = <1 2 5 30>;
-				};
-			};
-
-			regu_config_4 {
-                reg_info = <&soc_dvdd08_ddr_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
-				};
-			};
-
-			regu_config_5 {
-                reg_info = <&soc_vdd_ddr_1v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
-				};
-			};
-
-		    regu_config_6 {
-                reg_info = <&soc_vdd_ddr_1v1_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
-				};
-			};
-
-			regu_config_7 {
-                reg_info = <&soc_vdd_ddr_0v6_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
-				};
-			};
-
-			regu_config_8 {
-                reg_info = <&soc_dvdd18_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
-				};
-			};
-
-            regu_config_9 {
-                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
-				};
-			};
-
-			regu_config_10 {
-                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
-				};
-			};
-
-			regu_config_11 {
-                reg_info = <&soc_dvdd33_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
-				};
-			};
-
-			regu_config_12 {
-                reg_info = <&soc_dovdd18_scan_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
-					auto_on_info = <3 1 1800000>;
-					auto_off_info = <1 1>;
-				};
-			};
-
-
-			regu_config_13 {
-                reg_info = <&soc_dvdd12_scan_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
-					auto_on_info = <4 1 1200000>;
-					auto_off_info = <2 1>;
-				};
-			};
-
-			regu_config_14 {
-                reg_info = <&soc_avdd28_scan_en_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
-					auto_on_info = <5 1 2800000>;
-					auto_off_info = <0 1>;
-				};
-			};
-
-			regu_config_15 {
-                reg_info = <&soc_dvdd08_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
-                    parent_pmic_dev = <&pmic_dev_0 2 0>;
-				};
-			};
-
-			regu_config_16 {
-                reg_info = <&soc_dvdd18_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
-					parent_pmic_dev = <&pmic_dev_0 7 0>;
-				};
-			};
-		};
-	};
-
 	};
 
 	chosen {

arch/riscv/dts/light-milkv-meles.dts

@@ -0,0 +1,288 @@
+/dts-v1/;
+/ {
+	model = "Milk-V Meles";
+	compatible = "milkv,meles", "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	config {
+		select-gpio = <&gpio1_porta 16 0>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+			};
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/th1520-rvbook.dts

@@ -1,947 +0,0 @@
-/dts-v1/;
-#include <dt-bindings/usb/pd.h>
-#include <dt-bindings/pmic/light_pmic.h>
-
-/ {
-	model = "T-HEAD c910 light";
-	compatible = "thead,c910_light";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	charge-animation {
-		compatible = "rockchip,uboot-charge";
-		uboot-low-power-voltage = <7300>;
-		powerkey-gpio= <&ao_gpio_porta 6 0>;
-		status = "okay";
-	};
-
-	leds {
-		status = "okay";
-		compatible = "gpio-leds";
-		red-led {
-			gpios = <&gpio1_porta 14 0>; // GPIO_ACTIVE_HIGH: 0
-			label = "battery_charging";
-			default-state = "off";
-		};
-
-		green-led {
-			gpios = <&gpio1_porta 13 0>; // GPIO_ACTIVE_HIGH: 0
-			label = "battery_full";
-			default-state = "off";
-		};
-
-		blue-led {
-			gpios = <&gpio1_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
-			label = "battery_start";
-			default-state = "off";
-		};
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0xc0000000 0x0 0x40000000>;
-	};
-
-	aliases {
-		spi0 = &spi0;
-		spi1 = &qspi0;
-		spi2 = &qspi1;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		timebase-frequency = <3000000>;
-		u-boot,dm-pre-reloc;
-		cpu@0 {
-			device_type = "cpu";
-			reg = <0>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdcvsu";
-			mmu-type = "riscv,sv39";
-			u-boot,dm-pre-reloc;
-		};
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-		u-boot,dm-pre-reloc;
-
-		intc: interrupt-controller@ffd8000000 {
-			compatible = "riscv,plic0";
-			reg = <0xff 0xd8000000 0x0 0x04000000>;
-			status = "disabled";
-		};
-
-		dummy_apb: apb-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <62500000>;
-			clock-output-names = "dummy_apb";
-			#clock-cells = <0>;
-			u-boot,dm-pre-reloc;
-		};
-
-		dummy_ahb: ahb-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <250000000>;
-			clock-output-names = "core";
-			#clock-cells = <0>;
-			u-boot,dm-pre-reloc;
-		};
-
-		dummy_spi: spi-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <396000000>;
-			clock-output-names = "dummy_spi";
-			#clock-cells = <0>;
-			u-boot,dm-pre-reloc;
-		};
-
-		dummy_qspi0: qspi0-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <792000000>;
-			clock-output-names = "dummy_qspi0";
-			#clock-cells = <0>;
-			u-boot,dm-pre-reloc;
-		};
-
-		dummy_uart_sclk: uart-sclk-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
-			clock-output-names = "dummy_uart_sclk";
-			#clock-cells = <0>;
-			u-boot,dm-pre-reloc;
-		};
-
-		dummy_i2c_icclk: i2c-icclk-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
-			clock-output-names = "dummy_i2c_icclk";
-			#clock-cells = <0>;
-			u-boot,dm-pre-reloc;
-		};
-
-		dummy_dpu_pixclk: dpu-pix-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <74250000>;
-			clock-output-names = "dummy_dpu_pixclk";
-			#clock-cells = <0>;
-			u-boot,dm-pre-reloc;
-		};
-
-		dummy_dphy_refclk: dphy-ref-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <24000000>;
-			clock-output-names = "dummy_dpu_refclk";
-			#clock-cells = <0>;
-			u-boot,dm-pre-reloc;
-		};
-
-		i2c0: i2c@ffe7f20000 {
-			compatible = "snps,designware-i2c";
-			reg = <0xff 0xe7f20000 0x0 0x4000>;
-			clocks = <&dummy_i2c_icclk>;
-			clock-frequency = <100000>;
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			usbc0: husb311_0@4e {
-				compatible = "hynetek,husb311";
-				int-n-gpios = <&gpio3_porta 10 1>;
-				reg = <0x4e>;
-				status = "okay";
-		
-				usb_con0: connector {
-					compatible = "usb-c-connector";
-					label = "USB-C";
-					data-role = "dual";
-					power-role = "dual";
-					try-power-role = "sink";
-					source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
-					sink-pdos =
-						<PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
-						PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
-						PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
-					op-sink-microwatt = <10000000>;
-				};
-			};
-		
-			cw2015@62 {
-				clock-frequency = <100000>;
-				status = "okay";
-				compatible = "cellwise,cw2015";
-				reg = <0x62>;
-				cellwise,battery-profile = /bits/ 8
-					<0x17 0x67 0x66 0x65 0x64 0x63 0x61 0x5E
-					0x52 0x6D 0x4D 0x58 0x5B 0x51 0x44 0x3B
-					0x33 0x2C 0x26 0x23 0x24 0x29 0x34 0x42
-					0x49 0x16 0x0E 0xB8 0x3D 0x5D 0x68 0x7D
-					0x78 0x75 0x7B 0x7A 0x3F 0x18 0x82 0x48
-					0x09 0x4A 0x1A 0x47 0x86 0x93 0x97 0x15
-					0x49 0x71 0x9A 0xC3 0x80 0x41 0x4F 0xCB
-					0x2F 0x00 0x64 0xA5 0xB5 0x0D 0xB8 0x91>;
-				cellwise,monitor-interval-ms = <5000>;
-				cellwise,dual-cell = <1>;
-			};
-
-			bq25703: bq25703@6b {
-				status = "okay";
-				compatible = "ti,bq25703";
-				reg = <0x6b>;
-				typec0-enable-gpios = <&gpio3_porta 13 0>;  //CHG_PATH_SEL0_180
-				typec1-enable-gpios = <&gpio3_porta 12 0>;  //CHG_PATH_SEL1_180		
-				ti,charge-current = <2500000>;
-				ti,max-input-voltage = <5000000>;
-				ti,input-current = <2000000>;
-			};
-		};
-
-		i2c1: i2c@ffe7f24000{
-			compatible = "snps,designware-i2c";
-			reg = <0xff 0xe7f24000 0x0 0x4000>;
-			clocks = <&dummy_i2c_icclk>;
-			clock-frequency = <100000>;
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			mcu_hc32fx:mcu-hc32fx@0x4c {
-				status = "okay";
-				compatible = "mcu_hc32fx";
-				reg = <0x4c>;
-			};
-
-			usbc1: husb311_1@4e {
-				compatible = "hynetek,husb311";
-				int-n-gpios = <&gpio1_porta 5 1>;
-				reg = <0x4e>;
-				status = "okay";
-
-				usb_con1: connector {
-					compatible = "usb-c-connector";
-					label = "USB-C";
-					data-role = "dual";
-					power-role = "dual";
-					try-power-role = "sink";
-					source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
-					sink-pdos =
-						<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
-						PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
-						PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
-					op-sink-microwatt = <10000000>;
-				};
-			};
-		};
-
-		i2c2: i2c@ffec00c000{
-			compatible = "snps,designware-i2c";
-			reg = <0xff 0xec00c000 0x0 0x4000>;
-			clocks = <&dummy_i2c_icclk>;
-			clock-frequency = <100000>;
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		i2c3: i2c@ffec014000{
-			compatible = "snps,designware-i2c";
-			reg = <0xff 0xec014000 0x0 0x4000>;
-			clocks = <&dummy_i2c_icclk>;
-			clock-frequency = <100000>;
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		i2c4: i2c@ffe7f28000{
-			compatible = "snps,designware-i2c";
-			reg = <0xff 0xe7f28000 0x0 0x4000>;
-			clocks = <&dummy_i2c_icclk>;
-			clock-frequency = <100000>;
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			pcal6408ahk_a: gpio@20 {
-				compatible = "nxp,pca9554";
-				reg = <0x20>;
-				gpio-controller;
-				#gpio-cells = <2>;
-			};
-		};
-
-		i2c5: i2c@fff7f2c000{
-			compatible = "snps,designware-i2c";
-			reg = <0xff 0xf7f2c000 0x0 0x4000>;
-			clocks = <&dummy_i2c_icclk>;
-			clock-frequency = <100000>;
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		serial@ffe7014000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0xff 0xe7014000 0x0 0x400>;
-			clocks = <&dummy_uart_sclk>;
-			clock-frequency = <100000000>;
-			clock-names = "baudclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			u-boot,dm-pre-reloc;
-		};
-
-		gmac0: ethernet@ffe7070000 {
-			compatible = "snps,dwmac";
-			reg = <0xff 0xe7070000 0x0 0x2000>;
-			clocks = <&dummy_apb>;
-			clock-names = "stmmaceth";
-			snps,pbl = <32>;
-			snps,fixed-burst;
-
-			phy-mode = "rgmii-id";
-			phy-handle = <&phy_88E1111_a>;
-			status = "disabled";
-			mdio0 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "snps,dwmac-mdio";
-
-				phy_88E1111_a: ethernet-phy@1 {
-					reg = <0x1>;
-				};
-
-				phy_88E1111_b: ethernet-phy@2 {
-					reg = <0x2>;
-				};
-			};
-		};
-
-		gmac1: ethernet@ffe7060000 {
-			compatible = "snps,dwmac";
-			reg = <0xff 0xe7060000 0x0 0x2000>;
-			clocks = <&dummy_apb>;
-			clock-names = "stmmaceth";
-			snps,pbl = <32>;
-			snps,fixed-burst;
-			phy-mode = "rgmii-id";
-			phy-handle = <&phy_88E1111_b>;
-			status = "disabled";
-		};
-
-		emmc: sdhci@ffe7080000 {
-			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7080000 0x0 0x10000>;
-			index = <0x0>;
-			clocks = <&dummy_ahb>;
-			clock-frequency = <198000000>;
-			clock-names = "core";
-			max-frequency = <198000000>;
-			sdhci-caps-mask = <0x0 0x1000000>;
-			mmc-hs400-1_8v;
-			non-removable;
-			no-sdio;
-			no-sd;
-			bus-width = <8>;
-			voltage= "1.8v";
-			pull_up;
-			io_fixed_1v8;
-			fifo-mode;
-			u-boot,dm-pre-reloc;
-		};
-
-		sdhci0: sd@ffe7090000 {
-			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7090000 0x0 0x10000>;
-			index = <0x1>;
-			clocks = <&dummy_ahb>;
-			clock-frequency = <198000000>;
-			max-frequency = <198000000>;
-			sd-uhs-sdr104;
-			pull_up;
-			clock-names = "core";
-			bus-width = <4>;
-			voltage= "3.3v";
-		};
-
-		qspi0: spi@ffea000000 {
-			compatible = "snps,dw-apb-ssi-quad";
-			reg = <0xff 0xea000000 0x0 0x1000>;
-			clocks = <&dummy_qspi0>;
-			num-cs = <1>;
-			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
-			spi-max-frequency = <100000000>;
-			#address-cells = <1>;
-			#size-cells =<0>;
-			spi-flash@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "spi-nand";
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				reg = <0>;
-			};
-		};
-
-		qspi1: spi@fff8000000 {
-			compatible = "snps,dw-apb-ssi-quad";
-			reg = <0xff 0xf8000000 0x0 0x1000>;
-			clocks = <&dummy_spi>;
-			num-cs = <1>;
-			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
-			spi-max-frequency = <66000000>;
-			#address-cells = <1>;
-			#size-cells =<0>;
-			spi-flash@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "spi-nand";
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				reg = <0>;
-			};
-		};
-
-		spi0: spi@ffe700c000 {
-			compatible = "snps,dw-apb-ssi";
-			reg = <0xff 0xe700c000 0x0 0x1000>;
-			clocks = <&dummy_spi>;
-			cs-gpio = <&gpio2_porta 15 0>;
-			spi-max-frequency = <100000000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			tpm@0{
-				compatible = "z32h330tc,z32h330tc-spi";
-				reg = <0>;
-				spi-max-frequency = <22000000>;
-			};
-		};
-
-		gpio2: gpio@ffe7f34000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xe7f34000 0x0 0x1000>;
-			clocks = <&dummy_apb>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			gpio2_porta: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				snps,nr-gpios = <32>;
-				reg = <0>;
-			};
-		};
-
-		gpio3: gpio@ffe7f38000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xe7f38000 0x0 0x1000>;
-			clocks = <&dummy_apb>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			gpio3_porta: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				snps,nr-gpios = <32>;
-				reg = <0>;
-			};
-		};
-
-		gpio0: gpio@ffec005000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xec005000 0x0 0x1000>;
-			clocks = <&dummy_apb>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			gpio0_porta: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				snps,nr-gpios = <32>;
-				reg = <0>;
-			};
-		};
-
-		ao_gpio: gpio@fffff41000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xfff41000 0x0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			ao_gpio_porta: ao_gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				nr-gpios-snps = <32>;
-				reg = <0>;
-
-			};
-		};
-
-		gpio1: gpio@ffec006000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xec006000 0x0 0x1000>;
-			clocks = <&dummy_apb>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			gpio1_porta: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				snps,nr-gpios = <32>;
-				reg = <0>;
-			};
-		};
-
-		pwm: pwm@ffec01c000 {
-			compatible = "thead,pwm-light";
-			reg = <0xff 0xec01c000 0x0 0x4000>;
-			#pwm-cells = <2>;
-		};
-
-		dsi_regs: dsi-controller@ffef500000 {
-			compatible = "thead,light-dsi-regs", "syscon";
-			reg = <0xff 0xef500000 0x0 0x10000>;
-			status = "okay";
-		};
-
-		vosys_regs: vosys@ffef528000 {
-			compatible = "thead,light-vo-subsys", "syscon";
-			reg = <0xff 0xef528000 0x0 0x1000>;
-			status = "okay";
-		};
-
-		dpu: dc8200@ffef600000 {
-			compatible = "verisilicon,dc8200";
-			reg = <0xff 0xef600000 0x0 0x100>;
-		};
-
-		axiscr {
-			compatible = "thead,axiscr";
-			reg = <0xff 0xff004000 0x0 0x1000>;
-			lock-read = "okay";
-			lock-write = "okay";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			u-boot,dm-pre-reloc;
-			axiscr0: axisrc@0 {
-				device_type = "axiscr";
-				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
-				status = "disabled";
-				#address-cells = <2>;
-				#size-cells = <2>;
-				u-boot,dm-pre-reloc;
-			};
-			axiscr1: axisrc@1 {
-				device_type = "axiscr";
-				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
-				status = "disabled";
-				#address-cells = <2>;
-				#size-cells = <2>;
-				u-boot,dm-pre-reloc;
-			};
-			axiscr2: axisrc@2 {
-				device_type = "axiscr";
-				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
-				status = "disabled";
-				#address-cells = <2>;
-				#size-cells = <2>;
-				u-boot,dm-pre-reloc;
-			};
-		};
-
-		axiparity {
-			compatible = "thead,axiparity";
-			reg = <0xff 0xff00c000 0x0 0x1000>;
-			lock = "okay";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			u-boot,dm-pre-reloc;
-			axiparity0: axiparity@0 {
-				device_type = "axiparity";
-				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
-				status = "disabled";
-				#address-cells = <2>;
-				#size-cells = <2>;
-				u-boot,dm-pre-reloc;
-			};
-			axiparity1: axiparity@1 {
-				device_type = "axiparity";
-				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
-				status = "disabled";
-				#address-cells = <2>;
-				#size-cells = <2>;
-				u-boot,dm-pre-reloc;
-			};
-		};
-
-		dsi_bridge: dsi-bridge {
-			compatible = "thead,light-dsi-bridge";
-			clocks = <&dummy_dpu_pixclk>;
-			clock-names = "pix-clk";
-			phys = <&dsi_dphy>;
-			phy-names = "dphy";
-		};
-
-		dsi_host: dsi-host {
-			compatible = "synopsys,dw-mipi-dsi";
-			regmap = <&dsi_regs>;
-			status = "okay";
-		};
-
-		dsi_dphy: dsi-dphy {
-			compatible = "synopsys,dw-dphy";
-			regmap = <&dsi_regs>;
-			vosys-regmap = <&vosys_regs>;
-			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
-			clock-names = "pix-clk", "ref-clk";
-			#phy-cells = <0>;
-			status = "okay";
-		};
-
-		lcd_backlight: pwm-backlight {
-			compatible = "pwm-backlight";
-			pwms = <&pwm 0 5000000>;
-			brightness-levels = <0 4 8 16 32 64 128 255>;
-			default-brightness-level = <7>;
-		};
-
-		ili9881c_panel {
-			status = "disabled";
-			compatible      = "ilitek,ili9881c";
-			backlight       = <&lcd_backlight>;
-			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
-			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
-			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
-		};
-
-		aon {
-			compatible = "thead,light-aon";
-			status = "okay";
-
-			wakeup-by-gpio-on;
-			wakeup-by-rtc-on;
-
-			pd: light-aon-pd {
-				compatible = "thead,light-aon-pd";
-				#power-domain-cells = <1>;
-			};
-
-			light-regu-reg {
-				compatible = "thead,light-dialog-pmic";
-				status = "okay";
-
-				soc_dvdd18_aon_reg: soc_dvdd18_aon {
-					regulator-name = "soc_dvdd18_aon";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_avdd33_usb3_reg: soc_avdd33_usb3 {
-					regulator-name = "soc_avdd33_usb3";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_dvdd08_aon_reg: soc_dvdd08_aon {
-					regulator-name = "soc_dvdd08_aon";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
-					regulator-name = "soc_apcpu_dvdd_dvddm";
-					regulator-min-microvolt = <300000>;
-					regulator-max-microvolt = <1570000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
-					regulator-name = "soc_dvdd08_ddr";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
-					regulator-name = "soc_vdd_ddr_1v8";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
-					regulator-name = "soc_vdd_ddr_1v1";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
-					regulator-name = "soc_vdd_ddr_0v6";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_dvdd18_ap_reg: soc_dvdd18_ap {
-					regulator-name = "soc_dvdd18_ap";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_dvdd08_ap_reg: soc_dvdd08_ap {
-					regulator-name = "soc_dvdd08_ap";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
-					regulator-name = "soc_avdd08_mipi_hdmi";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
-					regulator-name = "soc_avdd18_mipi_hdmi";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
-					regulator-name = "soc_dvdd33_emmc";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
-					regulator-name = "soc_vdd18_emmc";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-				soc_dovdd18_scan_reg: soc_dovdd18_scan {
-					regulator-name = "soc_dovdd18_scan";
-					regulator-min-microvolt = <900000>;
-					regulator-max-microvolt = <3600000>;
-				};
-				soc_vext_2v8_reg: soc_vext_2v8 {
-					regulator-name = "soc_vext_2v8";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-				soc_dvdd12_scan_reg: soc_dvdd12_scan {
-					regulator-name = "soc_dvdd12_scan";
-					regulator-min-microvolt = <900000>;
-					regulator-max-microvolt = <3600000>;
-				};
-				soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
-					regulator-name = "soc_avdd28_scan_en";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <2800000>;
-				};
-			};
-
-			aon_pmic_config {
-				compatible = "thead,light-pmic-conf";
-				status = "okay";
-
-				#address-cells = <1>;
-				#size-cells = <0>;
-				iic-config = <0 0 2>;
-				pmic_dev_0: pmic-dev@0 {
-					pmic-name = "dialog,da9063,v1";
-					pmic-addr = <0x5a 0x5b>;
-					pmic_wdt_on;
-					status = "okay";
-				};
-
-				pmic_dev_1: pmic-dev@1 {
-					pmic-name = "dialog,da9121,v1";
-					pmic-addr = <0x68>;
-					status = "okay";
-				};
-
-				regu_config_0 {
-					reg_info = <&soc_dvdd18_aon_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
-					};
-				};
-
-				regu_config_1 {
-					reg_info = <&soc_avdd33_usb3_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
-					};
-				};
-
-				regu_config_2 {
-					reg_info = <&soc_dvdd08_aon_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
-					};
-				};
-
-				regu_config_3 {
-					reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
-						auto_on_info = <0 0 800000>;
-					};
-
-					regu_id@1 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
-						auto_on_info = <1 0 800000>;
-					};
-
-					regu_id@2 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
-						auto_on_info = <2 0 800000>;
-					};
-
-					coupling_info@0 {
-						negative-min;
-						info = <0 2 5 30>;
-					};
-
-					coupling_info@1 {
-						negative-min;
-						info = <1 2 5 30>;
-					};
-				};
-
-				regu_config_4 {
-					reg_info = <&soc_dvdd08_ddr_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
-					};
-				};
-
-				regu_config_5 {
-					reg_info = <&soc_vdd_ddr_1v8_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
-					};
-				};
-
-				regu_config_6 {
-					reg_info = <&soc_vdd_ddr_1v1_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
-					};
-				};
-
-				regu_config_7 {
-					reg_info = <&soc_vdd_ddr_0v6_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
-					};
-				};
-
-				regu_config_8 {
-					reg_info = <&soc_dvdd18_ap_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
-					};
-				};
-
-				regu_config_9 {
-					reg_info = <&soc_dvdd08_ap_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
-						parent_pmic_dev = <&pmic_dev_0 2 0>;
-					};
-				};
-
-				regu_config_10 {
-					reg_info = <&soc_avdd08_mipi_hdmi_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
-					};
-				};
-
-				regu_config_11 {
-					reg_info = <&soc_avdd18_mipi_hdmi_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
-					};
-				};
-
-				regu_config_12 {
-					reg_info = <&soc_dvdd33_emmc_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
-					};
-				};
-
-				regu_config_13 {
-					reg_info = <&soc_dvdd18_emmc_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
-						parent_pmic_dev = <&pmic_dev_0 7 0>;
-					};
-				};
-
-				regu_config_14 {
-					reg_info = <&soc_dovdd18_scan_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
-						auto_on_info = <2 1 1800000>;
-						auto_off_info = <7 1>;
-					};
-				};
-
-				regu_config_15 {
-					reg_info = <&soc_vext_2v8_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
-						auto_on_info = <3 1 2800000>;
-						auto_off_info = <8 1>;
-					};
-				};
-
-				regu_config_16 {
-					reg_info = <&soc_dvdd12_scan_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
-						auto_on_info = <4 1 1200000>;
-						auto_off_info = <9 1>;
-					};
-				};
-
-				regu_config_17 {
-					reg_info = <&soc_avdd28_scan_en_reg>;
-					status = "okay";
-					regu_id@0 {
-						pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>;
-					};
-				};
-			};
-	   	};
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-		stdout-path = "/soc/serial@ffe7014000:115200";
-	};
-};

arch/riscv/include/asm/bitops.h

@@ -90,6 +90,16 @@ static inline int __test_and_clear_bit(int nr, void *addr)
 	return retval;
 }
 
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+	unsigned long flags = 0;
+	int out;
+
+	out = __test_and_clear_bit(nr, addr);
+
+	return out;
+}
+
 static inline int __test_and_change_bit(int nr, void *addr)
 {
 	int mask, retval;

arch/sandbox/dts/Makefile

@@ -6,6 +6,7 @@ else
 dtb-$(CONFIG_SANDBOX) += sandbox.dtb
 endif
 dtb-$(CONFIG_UT_DM) += test.dtb
+dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo
 
 targets += $(dtb-y)
 

arch/sandbox/dts/overlay0.dts

@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+&{/buttons} {
+	btn3 {
+		gpios = <&gpio_a 5 0>;
+		label = "button3";
+	};
+};

arch/sandbox/dts/overlay1.dts

@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+&{/buttons} {
+	btn4 {
+		gpios = <&gpio_a 5 0>;
+		label = "button4";
+	};
+};

board/sandbox/sandbox.c

@@ -12,6 +12,9 @@
 #include <os.h>
 #include <asm/test.h>
 #include <asm/u-boot-sandbox.h>
+#include <malloc.h>
+
+#include <extension_board.h>
 
 /*
  * Pointer to initial global data area
@@ -58,6 +61,26 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_EXTENSION
+int extension_board_scan(struct list_head *extension_list)
+{
+	struct extension *extension;
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		extension = calloc(1, sizeof(struct extension));
+		snprintf(extension->overlay, sizeof(extension->overlay), "overlay%d.dtbo", i);
+		snprintf(extension->name, sizeof(extension->name), "extension board %d", i);
+		snprintf(extension->owner, sizeof(extension->owner), "sandbox");
+		snprintf(extension->version, sizeof(extension->version), "1.1");
+		snprintf(extension->other, sizeof(extension->other), "Fictionnal extension board");
+		list_add_tail(&extension->list, extension_list);
+	}
+
+	return i;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {

board/thead/light-c910/Kconfig

@@ -86,10 +86,6 @@ config LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
     bool "light lpi4a security boot with verification"
     default n
 
-config LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK
-    bool "light lpi4a security boot with verification"
-    default n
-
 config TARGET_LIGHT_FPGA_FM_C910
     bool "light fullmask FPGA board"
     default n
@@ -130,21 +126,22 @@ config TARGET_LIGHT_FM_C910_LPI4A
     bool "light fullmask for Lichee Pi 4A board "
     default n
 
-config TARGET_LIGHT_FM_C910_RVBOOK
-    bool "light fullmask for RVBOOK board "
-    default n
-
 config TARGET_LIGHT_FM_C910_B_POWER
     bool "light fullmask for light-b-power board "
     default n
 
+config TARGET_LIGHT_FM_C910_MILKV_MELES
+    bool "light fullmask for Milk-V Meles board "
+    default n
+
 config SYS_TEXT_BASE
     default 0xc0000000 if RISCV_MMODE
     default 0x00200000 if RISCV_SMODE
 
 config SPL_TEXT_BASE
     hex
-    default 0xffe0000800
+    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
+    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
 
 config SPL_MAX_SIZE
     hex
@@ -261,11 +258,6 @@ config DDR_DDP
 	  Enabling this will support ddr Dual Die Package configuration.
 	  e.g. to support 8GB ddr device with 17-bit row address (16:0)
 
-config FIXUP_MEMORY_REGION
-	bool "self-adapt to query and fixup memory region"
-	help
-	  Enabling this will support self-adapt to query and fixup memory region
-
 config DDR_H32_MODE
         bool "LPDDR4/4X 32bit mode configuration"
         help

board/thead/light-c910/Makefile

@@ -7,10 +7,6 @@ DDR_SRC_PATH=lpddr4/src
 DDR_REGU_SRC=lpddr-regu
 DDR_FW_PATH=$(DDR_SRC_PATH)/ddr_phy_fw
 
-ifdef CONFIG_RV_BOOK
-obj-y += sys_clk.o
-endif
-
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 obj-y += sys_clk.o
@@ -27,7 +23,6 @@ obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/init_ddr.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/pinmux.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/waitfwdone.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
-obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/lpddr4_init.o
 ifdef CONFIG_DDR_DBI_OFF
@@ -68,7 +63,6 @@ obj-y += boot.o
 obj-y += sbmeta/sbmeta.o
 ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
-obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 endif
 

board/thead/light-c910/board.c

@@ -8,24 +8,14 @@
 #include <asm/io.h>
 #include <dwc3-uboot.h>
 #include <usb.h>
-#include <usb/xhci.h>
 #include <cpu_func.h>
+#include <asm/gpio.h>
 #include <abuf.h>
 #include "sec_library.h"
 
-#ifdef CONFIG_LIGHT_AON_CONF
-#include "../../../drivers/misc/light_regu.h"
-#include "dm/device.h"
-#include "dm/uclass.h"
-#endif
-
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
-#ifdef CONFIG_RV_BOOK
-	.maximum_speed = USB_SPEED_HIGH,
-#else
 	.maximum_speed = USB_SPEED_SUPER,
-#endif
 	.dr_mode = USB_DR_MODE_PERIPHERAL,
 	.index = 0,
 };
@@ -39,13 +29,6 @@ int usb_gadget_handle_interrupts(int index)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	dwc3_device_data.base = 0xFFE7040000UL;
-
-	if (init == USB_INIT_DEVICE) {
-		dwc3_device_data.dr_mode = USB_DR_MODE_PERIPHERAL;
-	} else {
-		dwc3_device_data.dr_mode = USB_DR_MODE_HOST;
-	}
-
 	return dwc3_uboot_init(&dwc3_device_data);
 }
 
@@ -55,28 +38,6 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	return 0;
 }
 
-int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
-{
-
-
-	int ret = board_usb_init(index, USB_INIT_HOST);
-	if (ret != 0) {
-		puts("Failed to initialize board for USB\n");
-		return ret;
-	}
-
-	*hccr = (struct xhci_hccr *)dwc3_device_data.base;
-	*hcor = (struct xhci_hcor *)(dwc3_device_data.base +
-			HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));;
-
-	return ret;
-}
-
-void xhci_hcd_stop(int index)
-{
-	board_usb_cleanup(index, USB_INIT_HOST);
-}
-
 int g_dnl_board_usb_cable_connected(void)
 {
 	return 1;
@@ -84,14 +45,9 @@ int g_dnl_board_usb_cable_connected(void)
 #endif
 
 #ifdef CONFIG_CMD_BOOT_SLAVE
-#ifdef CONFIG_LIGHT_AON_CONF
-#define E902_AON_CONFIG_SIZE 0xC00
-#else
-#define E902_AON_CONFIG_SIZE 0x000
-#endif
 #define E902_SYSREG_START	0xfffff48044
 #define E902_SYSREG_RESET	0xfffff44024
-#define E902_START_ADDRESS	(0xFFEF8000 + E902_AON_CONFIG_SIZE)
+#define E902_START_ADDRESS	0xFFEF8000
 #define C910_E902_START_ADDRESS 0xFFFFEF8000
 #define E902_IOPMP_BASE		0xFFFFC21000
 
@@ -131,124 +87,65 @@ void set_c906_cpu_entry(phys_addr_t entry_h, phys_addr_t entry_l)
 
 void boot_audio(void)
 {
-	writel(0x37, (volatile void *)C906_RESET_REG);
+        writel(0x37, (volatile void *)C906_RESET_REG);
 
-	set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
-	flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
+        set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
+        flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
 
-	writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
-	writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
-	writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
+        writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
+        writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
+        writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
 
-	writel(0x3f, (volatile void *)C906_RESET_REG);
+        writel(0x3f, (volatile void *)C906_RESET_REG);
 }
 
-#ifdef CONFIG_LIGHT_AON_CONF
-
-int get_and_set_aon_config_data(void)
+void boot_aon(void)
 {
-	int ret =0;
-    struct udevice *dev;
-	struct mic_regu_platdata *config_data =NULL;
-
-	ret = uclass_first_device_err(UCLASS_MISC, &dev);
-	if(ret){
-        printf("get light aon config faild %d\n", ret);
-		return ret;
-	}
-
-	config_data = (struct mic_regu_platdata *)(dev->platdata);
-
-    volatile aon_config_t* read_config = (aon_config_t* )C910_E902_START_ADDRESS;
-	if(strncmp((const char*)read_config->magic , AON_CONFIG_MAGIC, strlen(AON_CONFIG_MAGIC))) {
-        printf("No aon config magic found in aon bin, please check the aon bin\n");
-		return -1;
-	}
-
-	if(strncmp((const char*)read_config->version, AON_CONFIG_VERSION, strlen(AON_CONFIG_VERSION))) {
-       printf("Err aon config version, aon bin is:%s, u-boot is:%s\n", read_config->version, AON_CONFIG_VERSION);
-	   return -1;
-	}
-
-	if(PMIC_MAX_HW_ID_NUM >  read_config->max_hw_id_num) {
-        printf("Invald max hw id num, aon bin support %d , u-boot is %d\n",read_config->max_hw_id_num, PMIC_MAX_HW_ID_NUM);
-		return -1;
-	}
-
-	/*set pmic dev info */
-	int pmic_dev_num =  config_data->pmic_list.pmic_num;
-    int pmic_dev_list_offset   = sizeof(aon_config_t);
-	uint64_t pmic_dev_start_addr  =  C910_E902_START_ADDRESS + pmic_dev_list_offset;
-
-	int  regu_num            = config_data->regu_id_list.regu_id_num;
-	int  regu_id_list_offset = pmic_dev_list_offset + pmic_dev_num * sizeof(pmic_dev_info_t);
-	uint64_t regu_start_addr  = C910_E902_START_ADDRESS + regu_id_list_offset;
-    int aon_bin_size  =  regu_id_list_offset + regu_num* sizeof(csi_regu_id_t);
-    if( aon_bin_size > read_config->aon_config_partition_size) {
-         printf("Invalid aon partition size, aon bin support:%lld, u-boot is %d\n", read_config->aon_config_partition_size, aon_bin_size);
-		 return -1;
-	}
-
-	printf("pmic_dev_num:%d offset:%d addr:%lld\n",pmic_dev_num, pmic_dev_list_offset, pmic_dev_start_addr);
-
-	memcpy((void*)pmic_dev_start_addr, config_data->pmic_list.pmic_list, pmic_dev_num * sizeof(pmic_dev_info_t));
-    printf("regu_num:%d offset:%d addr:%lld\n",regu_num,regu_id_list_offset, regu_start_addr);
-
-	memcpy((void*)regu_start_addr, config_data->regu_id_list.regu_id_list, regu_num * sizeof(csi_regu_id_t));
-    
-	read_config->wakeup_flag = config_data->wakeup_flag;
-	read_config->aon_pmic.iic_config.iic_id = config_data->iic_config.iic_id;
-	read_config->aon_pmic.iic_config.addr_mode = config_data->iic_config.addr_mode;
-	read_config->aon_pmic.iic_config.speed  = config_data->iic_config.speed;
-	read_config->aon_pmic.pmic_dev_num =  pmic_dev_num;
-    read_config->aon_pmic.pmic_dev_list_offset   = pmic_dev_list_offset;
-
-	/*set regu list info*/
-	read_config->aon_pmic.regu_num =  regu_num;
-	read_config->aon_pmic.regu_id_list_offset = regu_id_list_offset;
-
-	memcpy((void*)read_config->uboot_set_magic, UBOOT_CONFIG_MAGIC, strlen(UBOOT_CONFIG_MAGIC));
-
-    flush_cache((uintptr_t)C910_E902_START_ADDRESS, aon_bin_size);
-
-	printf("-->pmic_dev_num:%d offset:%d\n",read_config->aon_pmic.pmic_dev_num, read_config->aon_pmic.pmic_dev_list_offset);
-	printf("-->regu_num:%d offset:%d\n",read_config->aon_pmic.regu_num,read_config->aon_pmic.regu_id_list_offset);
-	return 0;
-}
-#endif
-
-int do_boot_aon(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-#ifdef CONFIG_LIGHT_AON_CONF
-    int ret = 0;
-	ret = get_and_set_aon_config_data();
-	if(ret) {
-        printf("aon config and set faild %d", ret);
-		hang();
-		return ret;
-	}
-#endif
 	writel(0xffffffff, (void *)(E902_IOPMP_BASE + 0xc0));
 	disable_slave_cpu();
 	set_slave_cpu_entry(E902_START_ADDRESS);
 	flush_cache((uintptr_t)C910_E902_START_ADDRESS, 0x10000);
 	enable_slave_cpu();
-	return 0;
 }
 
-U_BOOT_CMD(
-	bootaon, CONFIG_SYS_MAXARGS, 0, do_boot_aon,
-	"Boot aon from memory  ",
-	" "
-);
-
 int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
+	boot_aon();
+	mdelay(100);
 	boot_audio();
 	return 0;
 }
 #endif
 
+static void light_c910_set_gpio_output_high(void)
+{
+	ofnode node;
+	struct gpio_desc select_gpio;
+
+	printf("%s: trying to set gpio output high\n", __func__);
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		printf("%s: no /config node?\n", __func__);
+		return;
+	}
+
+	if (gpio_request_by_name_nodev(node, "select-gpio", 0,
+				       &select_gpio, GPIOD_IS_OUT)) {
+		printf("%s: could not find a /config/select-gpio\n", __func__);
+		return;
+	}
+
+	dm_gpio_set_value(&select_gpio, 1);
+}
+
+int misc_init_r(void)
+{
+	light_c910_set_gpio_output_high();
+
+	return 0;
+}
+
 #ifdef CONFIG_BOARD_RNG_SEED
 const char pre_gen_seed[128] = {211, 134, 226, 116, 1, 13, 224, 196, 88, 213, 188, 219, 128, 41, 231, 228, 129, 123, 173, 234, 219, 79, 152, 154, 169, 27, 183, 166, 52, 21, 118, 7, 155, 89, 124, 156, 102, 92, 96, 190, 49, 28, 154, 177, 69, 129, 149, 199, 253, 66, 177, 216, 146, 73, 114, 59, 100, 41, 225, 152, 62, 88, 160, 217, 177, 28, 117, 23, 120, 213, 213, 169, 242, 111, 90, 55, 241, 239, 254, 238, 50, 175, 198, 196, 248, 56, 255, 92, 97, 224, 245, 160, 56, 149, 121, 233, 177, 239, 0, 41, 196, 214, 210, 182, 69, 44, 238, 54, 27, 236, 36, 77, 156, 234, 17, 148, 34, 16, 241, 132, 241, 230, 36, 41, 123, 157, 19, 44};
 /* Use hardware rng to seed Linux random. */

board/thead/light-c910/boot.c

@@ -15,7 +15,6 @@
 #include "../../../lib/sec_library/include/sec_crypto_sha.h"
 #include "../../../lib/sec_library/include/kdf.h"
 #include "../../../lib/sec_library/include/sec_crypto_mac.h"
-#include "fastboot.h"
 
 #if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 
@@ -25,14 +24,6 @@
 /* The macro is used to enable uboot version in efuse */
 #define	LIGHT_UBOOT_VERSION_IN_ENV	1
 
-/* The macro is used to enable secimg version in env */
-#define LIGHT_SECIMG_VERSION_IN_ENV 1
-
-/* vimage return value */
-#define VIMAGE_UPGRADE_NOT_REQUIRED  1
-#define VIMAGE_BREAK_VERSION_RULE_ERROR  2
-#define VIMAGE_SIGNATRE_VERIFICATION_FAILED  3
-
 /* The macro is used to enble RPMB ACCESS KEY from KDF */
 //#define LIGHT_KDF_RPMB_KEY	1
 
@@ -47,8 +38,7 @@ static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0
 												0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 #endif
 static unsigned int upgrade_image_version = 0;
-static char *current_slot = "a";
-static char *update_slot = "b";
+
 #define RPMB_EMMC_CID_SIZE 16
 #define RPMB_CID_PRV_OFFSET             9
 #define RPMB_CID_CRC_OFFSET             15
@@ -56,8 +46,8 @@ static char *update_slot = "b";
 static int tee_rpmb_key_gen(uint8_t* key, uint32_t * length)
 {
 	uint32_t data[RPMB_EMMC_CID_SIZE / 4];
-	uint8_t huk[32];
-	uint32_t huk_len;
+    uint8_t huk[32];
+    uint32_t huk_len;
 	struct mmc *mmc = find_mmc_device(0);
 	int i;
 	sc_mac_t mac_handle;
@@ -82,14 +72,14 @@ static int tee_rpmb_key_gen(uint8_t* key, uint32_t * length)
 	memset((void *)((uint64_t)data + RPMB_CID_PRV_OFFSET), 0, 1);
 	memset((void *)((uint64_t)data + RPMB_CID_CRC_OFFSET), 0, 1);
 
-    	/* Step1: Derive HUK from KDF function */
+    /* Step1: Derive HUK from KDF function */
 	ret = csi_kdf_gen_hmac_key(huk, &huk_len);
 	if (ret) {
 		printf("kdf gen hmac key faild[%d]\r\n", ret);
 		return -1;
 	}
 
-    	/* Step2: Using HUK and data to generate RPMB key */
+    /* Step2: Using HUK and data to generate RPMB key */
 	ret = sc_mac_init(&mac_handle, 0);
 	if (ret) {
 		printf("mac init faild[%d]\r\n", ret);
@@ -162,25 +152,22 @@ int csi_rpmb_write_access_key(void)
 
 int csi_tf_get_image_version(unsigned int *ver)
 {
-	int ret = 0;
-#if !LIGHT_SECIMG_VERSION_IN_ENV
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
+
 	/* tf version reside in RPMB block#0, offset#16*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
 	ret = run_command(runcmd, 0);
 	if (ret == 0) {
 		*ver = (blkdata[16] << 8) + blkdata[17];
 	}
-#else
-	*ver = env_get_hex("tf_version", 0);
-#endif
+
 	return ret;
 }
 
 int csi_tf_set_image_version(unsigned int ver)
 {
-#if !LIGHT_SECIMG_VERSION_IN_ENV
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
 	unsigned long *temp_rpmb_key_addr = NULL;
@@ -207,9 +194,7 @@ int csi_tf_set_image_version(unsigned int ver)
 
 	sprintf(runcmd, "mmc rpmb write 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
 	run_command(runcmd, 0);
-#else
-	env_set_hex("tf_version", ver);
-#endif
+
 	return 0;
 }
 
@@ -220,19 +205,17 @@ int csi_tf_set_upgrade_version(void)
 
 int csi_tee_get_image_version(unsigned int *ver)
 {
-	int ret = 0;
-#if !LIGHT_SECIMG_VERSION_IN_ENV
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
+
 	/* tf version reside in RPMB block#0, offset#0*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
 	ret = run_command(runcmd, 0);
 	if (ret == 0) {
 		*ver = (blkdata[0] << 8) + blkdata[1];
 	}
-#else
-	*ver = env_get_hex("tee_version", 0);
-#endif
+
 	return ret;
 }
 
@@ -251,7 +234,6 @@ int csi_kernel_get_image_version(unsigned int *ver)
 
 int csi_tee_set_image_version(unsigned int ver)
 {
-#if !LIGHT_SECIMG_VERSION_IN_ENV
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
 	unsigned long *temp_rpmb_key_addr = NULL;
@@ -277,9 +259,7 @@ int csi_tee_set_image_version(unsigned int ver)
 #endif
 	sprintf(runcmd, "mmc rpmb write 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
 	run_command(runcmd, 0);
-#else
-	env_set_hex("tee_version", ver);
-#endif
+
 	return 0;
 }
 
@@ -290,25 +270,22 @@ int csi_tee_set_upgrade_version(void)
 
 int csi_sbmeta_get_image_version(unsigned int *ver)
 {
-	int ret = 0;
-#if !LIGHT_SECIMG_VERSION_IN_ENV
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
+
 	/* sbmeta version reside in RPMB block#0, offset#48*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
 	ret = run_command(runcmd, 0);
 	if (ret == 0) {
 		*ver = (blkdata[48] << 8) + blkdata[49];
 	}
-#else
-	*ver = env_get_hex("sbmeta_version", 0);
-#endif
+
 	return ret;
 }
 
 int csi_sbmeta_set_image_version(unsigned int ver)
 {
-#if !LIGHT_SECIMG_VERSION_IN_ENV
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
 	unsigned long *temp_rpmb_key_addr = NULL;
@@ -333,9 +310,7 @@ int csi_sbmeta_set_image_version(unsigned int ver)
 #endif
 	sprintf(runcmd, "mmc rpmb write 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
 	run_command(runcmd, 0);
-#else
-	env_set_hex("sbmeta_version", ver);
-#endif
+
 	return 0;
 }
 
@@ -463,13 +438,13 @@ int verify_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
 		/* This is unsecure function */
 		if ((new_ver_y - cur_ver_y) == 0) {
 			printf("New version is equal to Current version, upgrade process terminates \n\n\n");
-			return VIMAGE_UPGRADE_NOT_REQUIRED;
+			return -1;
 		}
 		printf("This is unsecure function upgrade, going on uprade anyway\n");
 	} else if ((new_ver_x - cur_ver_x) != 1) {
 		/* Check the seure version rule */
 		printf("The upgrade version(X) breaks against the rule\n\n\n");
-		return VIMAGE_BREAK_VERSION_RULE_ERROR;
+		return -1;
 	}
 	printf("check image verison rule pass\n\n\n");
 
@@ -585,7 +560,7 @@ int light_vimage(int argc, char *const argv[])
 	unsigned long vimage_addr = 0;
 	unsigned int new_img_version = 0;
 	unsigned int cur_img_version = 0;
-	char imgname[32] = {0};
+    char imgname[32] = {0};
 
 	if (argc < 3)
 		return CMD_RET_USAGE;
@@ -600,43 +575,35 @@ int light_vimage(int argc, char *const argv[])
 		printf("get new img version fail\n");
 		return CMD_RET_FAILURE;
 	}
-	if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
-		new_img_version = (((new_img_version & 0xff )+1) << 8) | ((new_img_version & 0xff00)>>8);
-	}
+    if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
+        new_img_version = (((new_img_version & 0xff )+1) << 8) | ((new_img_version & 0xff00)>>8);
+    }
 	printf("Get new image version from image header: v%d.%d\n", (new_img_version & 0xff00)>>8, new_img_version & 0xff);
 
-	/* Check image version for ROLLBACK resisance */
+	/* Check image version for ROLLBACK resisance */ 
 	if (strcmp(imgname, TF_PART_NAME) == 0) {
+		
 		ret = csi_tf_get_image_version(&cur_img_version);
 		if (ret != 0) {
 			printf("Get tf img version fail\n");
 			return CMD_RET_FAILURE;
 		}
-#if LIGHT_NON_COT_BOOT
-		/* if in non-cot mode, tf and tee will not be signed at first */
-		if (image_have_head(vimage_addr) == 0 && ((cur_img_version & 0xFF00) >> 8 == 0)) {
-			return VIMAGE_UPGRADE_NOT_REQUIRED;
-		}
-#endif
 	} else if (strcmp(imgname, TEE_PART_NAME) == 0){
+
 		ret = csi_tee_get_image_version(&cur_img_version);
 		if (ret != 0) {
 			printf("Get tee img version fail\n");
 			return CMD_RET_FAILURE;
 		}
-#if LIGHT_NON_COT_BOOT
-		/* if in non-cot mode, tf and tee will not be signed at first */
-		if (image_have_head(vimage_addr) == 0 && ((cur_img_version & 0xFF00) >> 8 == 0)) {
-			return VIMAGE_UPGRADE_NOT_REQUIRED;
-		}
-#endif
 	} else if (strcmp(imgname, KERNEL_PART_NAME) == 0){
+
 		ret = csi_kernel_get_image_version(&cur_img_version);
 		if (ret != 0) {
 			printf("Get kernel img version fail\n");
 			return CMD_RET_FAILURE;
 		}
 	} else if (strcmp(imgname, SBMETA_PART_NAME) == 0){
+
 		ret = csi_sbmeta_get_image_version(&cur_img_version);
 		if (ret != 0) {
 			printf("Get sbmeta img version fail\n");
@@ -659,13 +626,13 @@ int light_vimage(int argc, char *const argv[])
 		printf("unsupport image file\n");
 		return CMD_RET_FAILURE;
 	}
-
+	
 	/* Verify image version rule */
 	ret = verify_image_version_rule(new_img_version, cur_img_version);
 	if (ret != 0) {
-                return ret;
+		return CMD_RET_FAILURE;
 	}
-
+	
 	/* Save new image version to allow caller upgrade image version */
 	upgrade_image_version = new_img_version;
 
@@ -679,27 +646,27 @@ int light_vimage(int argc, char *const argv[])
 	if (strcmp(imgname, TF_PART_NAME) == 0) {
 		ret = verify_customer_image(T_TF, vimage_addr);
 		if (ret != 0) {
-			return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
+			return CMD_RET_FAILURE;
 		}
 	} else if (strcmp(imgname, TEE_PART_NAME) == 0) {
 		ret = verify_customer_image(T_TEE, vimage_addr);
 		if (ret != 0) {
-			return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
+			return CMD_RET_FAILURE;
 		}
 	} else if (strcmp(imgname, KERNEL_PART_NAME) == 0) {
 		ret = verify_customer_image(T_KRLIMG, vimage_addr);
 		if (ret != 0) {
-			return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
+			return CMD_RET_FAILURE;
 		}
 	} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
 		ret = verify_customer_image(T_UBOOT, vimage_addr);
 		if (ret != 0) {
-			return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
+			return CMD_RET_FAILURE;
 		}
 	} else if (strcmp(imgname, SBMETA_PART_NAME) == 0) {
 		ret = verify_customer_image(T_SBMETA, vimage_addr);
 		if (ret != 0) {
-			return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
+			return CMD_RET_FAILURE;
 		}
 	} else {
 		printf("Error: unknow image name\n");
@@ -720,8 +687,8 @@ int light_secboot(int argc, char * const argv[])
 	printf("\n\n");
 	printf("Now, we start to verify all trust firmware before boot kernel !\n");
 
-	/* Enject RPMB KEY directly in startup */
-	csi_rpmb_write_access_key();
+    /* Enject RPMB KEY directly in startup */
+    csi_rpmb_write_access_key();
 
 	/* Initialize secure basis of functions */
 	ret = csi_sec_init();
@@ -858,317 +825,273 @@ void sec_firmware_version_dump(void)
 	printf("\n\n");
 }
 
-struct sec_img_upgrade_entry {
-	const char* filename;
-	const char* imgtype;
-	int (*set_version_func)(void);
-	const char *part_str;
-};
-
-static struct sec_img_upgrade_entry sec_img_list[] = {
-	{"sbmeta.bin", "sbmeta", csi_sbmeta_set_upgrade_version, "sbmeta"},
-	{"trust_firmware.bin", "tf", csi_tf_set_upgrade_version, "tee"},
-	{"tee.bin", "tee", csi_tee_set_upgrade_version, "tee"},
-        {NULL, NULL, NULL, NULL},
-};
-
-static struct blk_desc *dev_desc;
-static int ab_get_blk(void)
-{
-        struct disk_partition part_info;
-        dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
-	if (dev_desc == NULL) {
-		printf("Failed to find MMC device\n");
-		return -1;
-	}
-        return 0;
-}
-
-static int ab_get_sec_part(const char *part_str, int update_part)
-{
-	struct disk_partition part_info;
-        char partname[10] = {0};
-        int part = 0;
-
-        if (update_part) {
-                sprintf(partname, "%s_%s", part_str, update_slot);
-        } else {
-                sprintf(partname, "%s_%s", part_str, current_slot);
-        }
-
-        part = part_get_info_by_name(dev_desc, partname, &part_info);
-        if (part < 0) {
-		printf("Failed to find MMC device\n");
-	}
-
-        return part;
-}
-
-static int single_img_upgrade(struct sec_img_upgrade_entry *sec_img_entry)
+void sec_upgrade_thread(void)
 {
 	const unsigned long temp_addr=0x200000;
 	char runcmd[80];
-	uint8_t * image_buffer = NULL;
-	uint8_t * image_malloc_buffer = NULL;
-	unsigned int upgrade_file_size = 0;
-	const char *filename = NULL;
-	int update_part = 0;
-        int current_part = 0;
+    uint8_t * image_buffer = NULL;
+    uint8_t * image_malloc_buffer = NULL;
 	int ret = 0;
-        char *argv[3] = {"vimage", NULL, NULL};
-
-	if (sec_img_entry == NULL) {
-		return -1;
-	}
-
-	update_part = ab_get_sec_part(sec_img_entry->part_str, 1);
-        if (update_part < 0) {
-                return -1;
-        }
-
-	filename = sec_img_entry->filename;
-
-	/* STEP 1: read upgrade image from storage */
-	printf("read upgrade image (%s) from storage \n", filename);
-	sprintf(runcmd, "ext4load mmc ${mmcdev}:%x 0x%p %s", update_part, (void *)temp_addr, filename);
-	printf("runcmd:%s\n", runcmd);
-	ret = run_command(runcmd, 0);
-	if (ret != 0) {
-		printf("%s upgrade process is terminated due to some reason\n", filename);
-		return -1;
-	}
-	/* Fetch the total file size after read out operation end */
-	upgrade_file_size = env_get_hex("filesize", 0);
-	printf("upgrade file size: %d\n", upgrade_file_size);
-
-	/*store image to temp buffer as temp_addr may be decrypted*/
-	image_malloc_buffer = malloc(upgrade_file_size);
-	if (image_malloc_buffer == NULL) {
-		image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
-	} else {
-		image_buffer = image_malloc_buffer;
-	}
-	memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
-
-	/* STEP 2: verify secure image */
-        sprintf(runcmd, "0x%lx", temp_addr);
-        argv[1] = runcmd;
-        argv[2] = sec_img_entry->imgtype;
-        ret = light_vimage(3, argv);
-        if (ret == VIMAGE_UPGRADE_NOT_REQUIRED) {
-                printf("%s Image may not need upgrade\n", sec_img_entry->imgtype);
-                return 0;
-        } else if (ret != 0) {
-                return -1;
-        }
-
-	/* STEP 3: update partition image in another slot */
-        current_part = ab_get_sec_part(sec_img_entry->part_str, 0);
-        if (current_part < 0) {
-                return -1;
-        }
-	printf("write upgrade image (%s) into another slot \n", filename);
-	sprintf(runcmd, "ext4write mmc 0:%x 0x%p /%s 0x%x", current_part, (void *)image_buffer, filename, upgrade_file_size);
-	printf("runcmd:%s\n", runcmd);
-	ret = run_command(runcmd, 0);
-	if (ret != 0) {
-		printf("%s upgrade process is terminated due to some reason\n", filename);
-		return -1;
-	}
-
-	/* STEP 4: update secure image version */
-        sec_img_entry->set_version_func();
-
-	printf("\n\n%s image ugprade process is successful\n\n", filename);
-	return 0;
-}
-
-static int sec_img_upgrade(void)
-{
-        int ret = 0;
-        struct sec_img_upgrade_entry *sec_img_entry = sec_img_list;
-
-        ab_get_blk();
-
-        while (sec_img_entry->filename != NULL) {
-                ret = single_img_upgrade(sec_img_entry);
-                if (ret) {
-                        printf("Fail to upgrade image\n");
-                        return -1;
-                }
-
-                sec_img_entry++;
-        }
-	return 0;
-}
-
-extern int hibernate_image_cleaned_flag;
-extern void clean_hibernate_image_header(char *response);
-static char *response[FASTBOOT_RESPONSE_LEN] = {0};
-void sec_upgrade_thread(void)
-{
-        const unsigned long temp_addr=0x200000;
-        char runcmd[80];
-        int ret = 0;
-        unsigned int sec_upgrade_flag = 0;
-        unsigned int upgrade_file_size = 0;
-
-        sec_upgrade_flag = env_get_hex("sec_upgrade_mode", 0);
-        current_slot = env_get("slot_suffix");
-        update_slot = strcmp(current_slot, "a") == 0 ? "b" : "a";
-
-        if (sec_upgrade_flag == 0) {
-		return;
-        }
-
-	clean_hibernate_image_header(response);
-        printf("bootstrap: sec_upgrade_flag: %x\n", sec_upgrade_flag);
-        if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) {
-                unsigned int block_cnt;
-                struct blk_desc *dev_desc;
-                const unsigned long uboot_temp_addr=0x80000000;
-                #define BLOCK_SIZE 512
-                #define PUBKEY_HEADER_SIZE	0x1000
-
-                /* STEP 1: read upgrade image (u-boot-with-spl.bin) from stash partition */
-                printf("read upgrade image (u-boot-with-spl.bin) from stash partition \n");
-                sprintf(runcmd, "ext4load mmc 0:4 0x%p u-boot-with-spl.bin", (void *)temp_addr);
-                printf("runcmd:%s\n", runcmd);
-                ret = run_command(runcmd, 0);
-                if (ret != 0) {
-                        printf("UBOOT Upgrade process is terminated due to some reason\n");
-                        goto _upgrade_uboot_exit;
-                }
-
-                /* Fetch the total file size after read out operation end */
-                upgrade_file_size = env_get_hex("filesize", 0);
-                printf("uboot upgrade file size: %d\n", upgrade_file_size);
-
-                /* STEP 2: verify its authentiticy here */
-                memmove((void *)uboot_temp_addr, (const void *)temp_addr, upgrade_file_size);
-                sprintf(runcmd, "vimage 0x%p uboot", (void *)(uboot_temp_addr+PUBKEY_HEADER_SIZE));
-                printf("runcmd:%s\n", runcmd);
-                ret = run_command(runcmd, 0);
-                if (ret != 0) {
-                        printf("UBOOT Image verification fail and upgrade process terminates\n");
-                        goto _upgrade_uboot_exit;
-                }
-
-                /* STEP 3: update uboot partition */
-                printf("write upgrade image (u-boot-with-spl.bin) into uboot partition \n");
-                dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
-                if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
-                        printf("Invalid mmc device\n");
-                        goto _upgrade_uboot_exit;
-                }
-                block_cnt = upgrade_file_size / BLOCK_SIZE;
-                if (upgrade_file_size % BLOCK_SIZE) {
-                        block_cnt = block_cnt +1;
-                }
-
-                run_command("mmc partconf 0 1 0 1", 0);
-                sprintf(runcmd, "mmc write 0x%p 0 %x", (void *)temp_addr, block_cnt);
-                printf("runcmd:%s\n", runcmd);
-                ret = run_command(runcmd, 0);
-                run_command("mmc partconf 0 1 0 0", 0);
-                if (ret != 0) {
-                        printf("UBOOT upgrade process is terminated due to some reason\n");
-                        goto _upgrade_uboot_exit;
-                }
-
-                /* STEP 4: update tee version */
-                ret = csi_uboot_set_upgrade_version();
-                if (ret != 0) {
-                        printf("Set uboot upgrade version fail\n");
-                        goto _upgrade_uboot_exit;
-                }
-
-                printf("\n\nUBOOT image ugprade process is successful\n\n");
-_upgrade_uboot_exit:
-                /* set secure upgrade flag to 0 that indicate upgrade over */
-                run_command("env set sec_upgrade_mode 0", 0);
-                run_command("saveenv", 0);
-                run_command("reset", 0);
-        } else if ((sec_upgrade_flag >> 16) == SEC_IMG_UPGRADE_FLAG) {
-                ret = sec_img_upgrade();
-                if (ret) {
-                        printf("secure image upgrade failed\n");
-                        /* if failed, clear upgrade flag, terminate upgradation */
-                        sec_upgrade_flag = 0;
-                } else  {
-                        /* if succeed, clear secure flag */
-                        sec_upgrade_flag = sec_upgrade_flag & 0x0000FFFF;
-                        /* if boot need not update, switch current slot to update slot */
-                        if ((sec_upgrade_flag & 0xFF00) != BOOT_IMG_UPGRADE_FLAG) {
-                                sprintf(runcmd, "env set slot_suffix %s", update_slot);
-                                run_command(runcmd, 0);
-                        }
-                }
-                /* set upgrade flag */
-                sprintf(runcmd, "env set sec_upgrade_mode %x", sec_upgrade_flag);
-                run_command(runcmd, 0);
-
-                run_command("saveenv", 0);
-                run_command("reset", 0);
-        } else if (((sec_upgrade_flag & 0xFF00) != BOOT_IMG_UPGRADE_FLAG) &&
-			((sec_upgrade_flag & 0xFF) != ROOT_IMG_UPGRADE_FLAG)) {
-                printf("Unknown bootstrap, Force sysem reboot\n");
-                run_command("env set sec_upgrade_mode 0", 0);
-                run_command("saveenv", 0);
-                run_command("reset", 0);
-        }
-}
-
-void nonsec_upgrade_thread(void)
-{
-	unsigned int sec_upgrade_flag;
-	unsigned long retries;
-        char runcmd[32] = {0};
+	unsigned int sec_upgrade_flag = 0;
+	unsigned int upgrade_file_size = 0;
 
 	sec_upgrade_flag = env_get_hex("sec_upgrade_mode", 0);
-	retries = env_get_ulong("retries", 10, 5);
-        if (sec_upgrade_flag == 0) {
-		if (retries < 5 && retries > 0) {
-			printf("boot upgradation is successful!\n");
-                	run_command("env set retries 5", 0);
-                	run_command("env save", 0);
+	if (sec_upgrade_flag == 0)
+		return;
+	printf("bootstrap: sec_upgrade_flag: %x\n", sec_upgrade_flag);
+	if (sec_upgrade_flag == TF_SEC_UPGRADE_FLAG) {
+		/* STEP 1: read upgrade image (trust_firmware.bin) from stash partition */
+		printf("read upgrade image (trust_firmware.bin) from stash partition \n");
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p trust_firmware.bin", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("TF upgrade process is terminated due to some reason\n");
+			goto _upgrade_tf_exit;
 		}
-                return;
+		/* Fetch the total file size after read out operation end */
+		upgrade_file_size = env_get_hex("filesize", 0);
+		printf("upgrade file size: %d\n", upgrade_file_size);
+
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
         }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
 
-	/* when sec_upgrade_mode != 0 and the first time try to boot. switch current slot to update slot*/
-	if (retries == 5) {
-		printf("upgrade images are in slot %s...\n", update_slot);
-		sprintf(runcmd, "env set slot_suffix %s", update_slot);
-		run_command(runcmd, 0);
-	}
-	/* if ROOT image need upgrade, clear flag */
-	if ((sec_upgrade_flag & 0xFF) == ROOT_IMG_UPGRADE_FLAG) {
-		printf("in root image upgrade process...\n");
-		sec_upgrade_flag = sec_upgrade_flag & 0xFF00;
-		sprintf(runcmd, "env set sec_upgrade_mode %X", sec_upgrade_flag);
-		run_command(runcmd, 0);
-	}
-
-	/* if boot image need upgrade, decrement retries */
-	if ((sec_upgrade_flag & 0xFF00) == BOOT_IMG_UPGRADE_FLAG) {
-		printf("in boot image upgrade process...\n");
-		retries--;
-                printf("remaining retry times: %ld\n", retries);
-		if (retries == 0 || retries > 5) {
-			/*
-                         * upgrade failed. Now updated images are in current slot
-                         * switch to original slot
-                         */
-                        printf("boot images upgrade failed. switch slot to %s...\n", update_slot);
-                        sprintf(runcmd, "env set slot_suffix %s", update_slot);
-                        run_command(runcmd, 0);
-			run_command("env set sec_upgrade_mode 0", 0);
-			retries = 5;
+		/* STEP 2: verify its authentiticy here */
+		sprintf(runcmd, "vimage 0x%p tf", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("TF Image verification fail and upgrade process terminates\n");
+			goto _upgrade_tf_exit;
 		}
-                sprintf(runcmd, "env set retries %ld", retries);
-                run_command(runcmd, 0);
-                run_command("env save", 0);
+
+		/* STEP 3: update tf partition */
+		printf("read upgrade image (trust_firmware.bin) into tf partition \n");
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)image_buffer, upgrade_file_size);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("TF upgrade process is terminated due to some reason\n");
+			goto _upgrade_tf_exit;
+		}
+
+		/* STEP 4: update tf version */
+		ret = csi_tf_set_upgrade_version();
+		if (ret != 0) {
+			printf("Set trustfirmware upgrade version fail\n");
+			goto _upgrade_tf_exit;
+		}
+
+		printf("\n\nTF image ugprade process is successful\n\n");
+_upgrade_tf_exit:
+		/* set secure upgrade flag to 0 that indicate upgrade over */
+		run_command("env set sec_upgrade_mode 0", 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
+	} else if (sec_upgrade_flag == TEE_SEC_UPGRADE_FLAG) {
+
+ 		/* STEP 1: read upgrade image (tee.bin) from stash partition */
+		printf("read upgrade image (tee.bin) from stash partition \n");
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p tee.bin", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("TEE Upgrade process is terminated due to some reason\n");
+			goto _upgrade_tee_exit;
+		}
+		/* Fetch the total file size after read out operation end */
+		upgrade_file_size = env_get_hex("filesize", 0);
+		printf("TEE upgrade file size: %d\n", upgrade_file_size);
+
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
+
+		/* STEP 2: verify its authentiticy here */
+		sprintf(runcmd, "vimage 0x%p tee", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("TEE Image verification fail and upgrade process terminates\n");
+			goto _upgrade_tee_exit;
+		}
+
+		/* STEP 3: update tee partition */
+		printf("read upgrade image (tee.bin) into sbmeta partition \n");
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /tee.bin 0x%x", (void *)image_buffer, upgrade_file_size);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("TEE upgrade process is terminated due to some reason\n");
+			goto _upgrade_tee_exit;
+		}
+
+		/* STEP 4: update tee version */
+		ret = csi_tee_set_upgrade_version();
+		if (ret != 0) {
+			printf("Set tee upgrade version fail\n");
+			goto _upgrade_tee_exit;
+		}
+
+		printf("\n\nTEE image ugprade process is successful\n\n");
+_upgrade_tee_exit:
+		/* set secure upgrade flag to 0 that indicate upgrade over */
+		run_command("env set sec_upgrade_mode 0", 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
+	} else if (sec_upgrade_flag == SBMETA_SEC_UPGRADE_FLAG) {
+
+ 		/* STEP 1: read upgrade image (sbmeta.bin) from stash partition */
+		printf("read upgrade image (sbmeta.bin) from stash partition \n");
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p sbmeta.bin", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("SBMETA Upgrade process is terminated due to some reason\n");
+			goto _upgrade_sbmeta_exit;
+		}
+		/* Fetch the total file size after read out operation end */
+		upgrade_file_size = env_get_hex("filesize", 0);
+		printf("SBMETA upgrade file size: %d\n", upgrade_file_size);
+
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
+
+		/* STEP 2: verify its authentiticy here */
+		sprintf(runcmd, "vimage 0x%p sbmeta", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("SBMETA Image verification fail and upgrade process terminates\n");
+			goto _upgrade_sbmeta_exit;
+		}
+
+		/* STEP 3: update sbmeta partition */
+		printf("read upgrade image (SBMETA.bin) into sbmeta partition \n");
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /sbmeta.bin 0x%x", (void *)image_buffer, upgrade_file_size);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("SBMETA upgrade process is terminated due to some reason\n");
+			goto _upgrade_sbmeta_exit;
+		}
+
+		/* STEP 4: update sbmeta version */
+		ret = csi_sbmeta_set_upgrade_version();
+		if (ret != 0) {
+			printf("Set sbmeta upgrade version fail\n");
+			goto _upgrade_sbmeta_exit;
+		}
+
+		printf("\n\nSBMETA image ugprade process is successful\n\n");
+_upgrade_sbmeta_exit:
+		/* set secure upgrade flag to 0 that indicate upgrade over */
+		run_command("env set sec_upgrade_mode 0", 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
+	} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) {
+		unsigned int block_cnt;
+		struct blk_desc *dev_desc;
+		const unsigned long uboot_temp_addr=0x80000000;
+		#define BLOCK_SIZE 512
+		#define PUBKEY_HEADER_SIZE	0x1000
+
+		/* STEP 1: read upgrade image (u-boot-with-spl.bin) from stash partition */
+		printf("read upgrade image (u-boot-with-spl.bin) from stash partition \n");
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p u-boot-with-spl.bin", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("UBOOT Upgrade process is terminated due to some reason\n");
+			goto _upgrade_uboot_exit;
+		}
+
+		/* Fetch the total file size after read out operation end */
+		upgrade_file_size = env_get_hex("filesize", 0);
+		printf("uboot upgrade file size: %d\n", upgrade_file_size);
+
+		/* STEP 2: verify its authentiticy here */
+		memmove((void *)uboot_temp_addr, (const void *)temp_addr, upgrade_file_size);
+		sprintf(runcmd, "vimage 0x%p uboot", (void *)(uboot_temp_addr+PUBKEY_HEADER_SIZE));
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("UBOOT Image verification fail and upgrade process terminates\n");
+			goto _upgrade_uboot_exit;
+		}
+
+		/* STEP 3: update uboot partition */
+		printf("write upgrade image (u-boot-with-spl.bin) into boot partition \n");
+		dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+        if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+			printf("Invalid mmc device\n");
+			goto _upgrade_uboot_exit;
+        }
+		block_cnt = upgrade_file_size / BLOCK_SIZE;
+		if (upgrade_file_size % BLOCK_SIZE) {
+			block_cnt = block_cnt +1;
+		}
+
+		run_command("mmc partconf 0 1 0 1", 0);
+		sprintf(runcmd, "mmc write 0x%p 0 %x", (void *)temp_addr, block_cnt);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		run_command("mmc partconf 0 1 0 0", 0);
+		if (ret != 0) {
+			printf("UBOOT upgrade process is terminated due to some reason\n");
+			goto _upgrade_uboot_exit;
+		}
+
+		/* STEP 4: update tee version */
+		ret = csi_uboot_set_upgrade_version();
+		if (ret != 0) {
+			printf("Set uboot upgrade version fail\n");
+			goto _upgrade_uboot_exit;
+		}
+
+		printf("\n\nUBOOT image ugprade process is successful\n\n");
+_upgrade_uboot_exit:
+		/* set secure upgrade flag to 0 that indicate upgrade over */
+		run_command("env set sec_upgrade_mode 0", 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+	} else {
+		printf("Unknown bootstrap, Force sysem reboot\n");
+		run_command("reset", 0);
 	}
 }
 #endif
+
+

board/thead/light-c910/clock_config.c

@@ -1146,7 +1146,7 @@ void ap_mipi_dsi1_clk_endisable(bool en)
 	writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
 }
 
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
 {
 	unsigned long div_reg;
@@ -1220,7 +1220,7 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("C910 CPU FREQ: %ldMHz\n", rate / 1000000);
-#ifdef PERI_BUS_PLL_FREQ_PRINT
+
 	rate = clk_light_get_rate("ahb2_cpusys_hclk", CLK_DEV_MUX);
 	if (!rate)
 		return -EINVAL;
@@ -1262,7 +1262,6 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("DPU1 PLL POSTDIV FREQ: %ldMHZ\n", rate / 1000000);
-#endif
 
 #ifdef AUDIO_PLL_FREQ_PRINT
 	rate = clk_light_get_rate("audio_pll_foutpostdiv", CLK_DEV_PLL);
@@ -1305,7 +1304,7 @@ int clk_config(void)
 
 	/* The boards other than the LightA board perform the bus down-speed operation */
 
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 	ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
 	ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 12); /* Input frquency: 2376MHZ */
 	ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */

board/thead/light-c910/ddr.c

@@ -12,17 +12,3 @@ void init_ddr(void)
 {
 	writel(0x1ff << 4, (void *)0xffff005000);
 }
-
-int fixup_ddr_addrmap(unsigned long size)
-{
-	return 0;
-}
-
-int query_ddr_boundary(unsigned long size)
-{
-	return 0;
-}
-unsigned long get_ddr_density(void)
-{
-	return 0x100000000;
-}

board/thead/light-c910/lpddr-regu/ddr_regu.c

@@ -136,7 +136,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
 		REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
 	},
 };
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined(CONFIG_TARGET_LIGHT_FM_C910_RVBOOK)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 /**
  * board for ant-ref
  *
@@ -794,7 +794,7 @@ static void light_iopmp_config(void)
 	}
 }
 
-int aon_local_init(void)
+int pmic_ddr_regu_init(void)
 {
 #define AON_PADMUX_BASE (0xfffff4a000)
 	int ret;
@@ -955,7 +955,7 @@ int pmic_reset_apcpu_voltage(void)
 		return ret;
 	return 0;
 }
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined(CONFIG_TARGET_LIGHT_FM_C910_RVBOOK)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 int pmic_reset_apcpu_voltage(void)
 {
 	int                ret = -1;

board/thead/light-c910/lpddr-regu/ddr_regu.h

@@ -9,5 +9,5 @@
 #define __DDR_REGU_H__
 
 int pmic_ddr_set_voltage(void);
-int aon_local_init(void);
+int pmic_ddr_regu_init(void);
 #endif

board/thead/light-c910/lpddr4/include/aonsys_reg_define.h

@@ -1,218 +0,0 @@
-//------------------------------------------------------------
-// DONOT MODIFY THIS FILE
-// generated by JISHENGJU automatically
-//------------------------------------------------------------
-
-#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H
-#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H
-
-#define AONSYS_REG_BASE			0xFFFFF48000
-
-#define REG_AON_CPU_LP_MODE         (AONSYS_REG_BASE + 0x0  )
-#define REG_AON_CHIP_LP_MODE        (AONSYS_REG_BASE + 0x4  )
-#define REG_AON_AO_SERAM_TRN        (AONSYS_REG_BASE + 0x10 )
-#define REG_AON_AO_SERAM_INT        (AONSYS_REG_BASE + 0x14 )
-#define REG_AON_STR_SERAM_TRN       (AONSYS_REG_BASE + 0x18 )
-#define REG_AON_STR_SERAM_INT       (AONSYS_REG_BASE + 0x1c )
-#define REG_AON_STR_INDICATOR_0     (AONSYS_REG_BASE + 0x20 )
-#define REG_AON_STR_INDICATOR_1     (AONSYS_REG_BASE + 0x24 )
-#define REG_AON_STR_INDICATOR_2     (AONSYS_REG_BASE + 0x28 )
-#define REG_AON_STR_INDICATOR_3     (AONSYS_REG_BASE + 0x2c )
-#define REG_AON_PVTC_WR_LOCK        (AONSYS_REG_BASE + 0x30 )
-#define REG_AON_PVTC_TS_ALARM       (AONSYS_REG_BASE + 0x34 )
-#define REG_AON_PVTC_VM_ALARM       (AONSYS_REG_BASE + 0x38 )
-#define REG_AON_PVTC_PD_ALARM       (AONSYS_REG_BASE + 0x3c )
-#define REG_AON_E902_CNT_CLR        (AONSYS_REG_BASE + 0x40 )
-#define REG_AON_E902_RST_ADDR       (AONSYS_REG_BASE + 0x44 )
-#define REG_AON_C906_RST_ADDR_L     (AONSYS_REG_BASE + 0x48 )
-#define REG_AON_C906_RST_ADDR_H     (AONSYS_REG_BASE + 0x4c )
-#define REG_AON_RESERVED_REG_0      (AONSYS_REG_BASE + 0x50 )
-#define REG_AON_RESERVED_REG_1      (AONSYS_REG_BASE + 0x54 )
-#define REG_AON_RESERVED_REG_2      (AONSYS_REG_BASE + 0x58 )
-#define REG_AON_RESERVED_REG_3      (AONSYS_REG_BASE + 0x5c )
-#define REG_AON_AON_AHB_ADEXT       (AONSYS_REG_BASE + 0x60 )
-#define REG_AON_RC_EN               (AONSYS_REG_BASE + 0x70 )
-#define REG_AON_RC_FCAL             (AONSYS_REG_BASE + 0x74 )
-#define REG_AON_RC_MODE             (AONSYS_REG_BASE + 0x78 )
-#define REG_AON_RC_READY            (AONSYS_REG_BASE + 0x7c )
-#define REG_AON_ISO_CFG             (AONSYS_REG_BASE + 0x80 )
-#define REG_AON_OCRAM_ERR           (AONSYS_REG_BASE + 0x90 )
-#define REG_AON_TIMER_LINK          (AONSYS_REG_BASE + 0x100)
-#define REG_AON_PD_REQ              (AONSYS_REG_BASE + 0x110)
-#define REG_AON_PD_ISO_EN_SET       (AONSYS_REG_BASE + 0x114)
-#define REG_AON_PD_ISO_EN_CLR       (AONSYS_REG_BASE + 0x118)
-#define REG_AON_PD_SW_EN_SET        (AONSYS_REG_BASE + 0x11c)
-#define REG_AON_PD_SW_EN_CLR        (AONSYS_REG_BASE + 0x120)
-#define REG_AON_PD_SW_ACK           (AONSYS_REG_BASE + 0x124)
-#define REG_AON_PD_SW_CNT_EN        (AONSYS_REG_BASE + 0x128)
-#define REG_AON_PD_FSM_RST          (AONSYS_REG_BASE + 0x12c)
-#define REG_AON_PD_INT_MASK         (AONSYS_REG_BASE + 0x130)
-#define REG_AON_PD_FSM_STS_L        (AONSYS_REG_BASE + 0x134)
-#define REG_AON_PD_FSM_STS_H        (AONSYS_REG_BASE + 0x138)
-#define REG_AON_PD_INT_STS          (AONSYS_REG_BASE + 0x13c)
-#define REG_AON_PD_INT_CLR          (AONSYS_REG_BASE + 0x140)
-#define REG_AON_PD_BLK0_SW_CNT      (AONSYS_REG_BASE + 0x144)
-#define REG_AON_PD_BLK1_SW_CNT      (AONSYS_REG_BASE + 0x148)
-#define REG_AON_PD_BLK2_SW_CNT      (AONSYS_REG_BASE + 0x14c)
-#define REG_AON_PD_BLK3_SW_CNT      (AONSYS_REG_BASE + 0x150)
-#define REG_AON_PD_BLK4_SW_CNT      (AONSYS_REG_BASE + 0x154)
-#define REG_AON_PD_BLK5_SW_CNT      (AONSYS_REG_BASE + 0x158)
-#define REG_AON_PD_BLK6_SW_CNT      (AONSYS_REG_BASE + 0x15c)
-#define REG_AON_PD_BLK7_SW_CNT      (AONSYS_REG_BASE + 0x160)
-#define REG_AON_PD_BLK8_SW_CNT      (AONSYS_REG_BASE + 0x164)
-#define REG_AON_PD_BLK9_SW_CNT      (AONSYS_REG_BASE + 0x168)
-#define REG_AON_PD_BLK10_SW_CNT     (AONSYS_REG_BASE + 0x16c)
-#define REG_AON_PD_BLK0_INTV_CNT    (AONSYS_REG_BASE + 0x180)
-#define REG_AON_PD_BLK1_INTV_CNT    (AONSYS_REG_BASE + 0x184)
-#define REG_AON_PD_BLK2_INTV_CNT    (AONSYS_REG_BASE + 0x188)
-#define REG_AON_PD_BLK3_INTV_CNT    (AONSYS_REG_BASE + 0x18c)
-#define REG_AON_PD_BLK4_INTV_CNT    (AONSYS_REG_BASE + 0x190)
-#define REG_AON_PD_BLK5_INTV_CNT    (AONSYS_REG_BASE + 0x194)
-#define REG_AON_PD_BLK6_INTV_CNT    (AONSYS_REG_BASE + 0x198)
-#define REG_AON_PD_BLK7_INTV_CNT    (AONSYS_REG_BASE + 0x19c)
-#define REG_AON_PD_BLK8_INTV_CNT    (AONSYS_REG_BASE + 0x1a0)
-#define REG_AON_PD_BLK9_INTV_CNT    (AONSYS_REG_BASE + 0x1a4)
-#define REG_AON_PD_BLK10_INTV_CNT   (AONSYS_REG_BASE + 0x1a8)
-#define REG_AON_AUDIO_PMU_REQ       (AONSYS_REG_BASE + 0x1f8)
-#define REG_AON_AUDIO_PMU_STS       (AONSYS_REG_BASE + 0x1fc)
-#define REG_AON_AUDIO_PMU_INTR      (AONSYS_REG_BASE + 0x204)
-#define REG_AON_PMU_AUDIO_REQ       (AONSYS_REG_BASE + 0x208)
-#define REG_AON_PMU_AUDIO_STS       (AONSYS_REG_BASE + 0x20c)
-#define REG_AON_MEM_LP_MODE         (AONSYS_REG_BASE + 0x210)
-#define REG_AON_C910_DBG_MASK       (AONSYS_REG_BASE + 0x214)
-#define REG_AON_C910_L2CACHE        (AONSYS_REG_BASE + 0x218)
-#define REG_AON_BISR_CTRL           (AONSYS_REG_BASE + 0x220)
-#define REG_AON_EFUSE_PRELOAD_DONE  (AONSYS_REG_BASE + 0x224)
-#define REG_AON_GPIO_RTE            (AONSYS_REG_BASE + 0x228)
-#define REG_AON_PLL_DSKEW_LOCK      (AONSYS_REG_BASE + 0x22c)
-#define REG_AON_SRAM_AXI_CFG        (AONSYS_REG_BASE + 0x230)
-#define REG_AON_SRAM_AXI_ST         (AONSYS_REG_BASE + 0x234)
-#define REG_AON_SRAM_AXI_ERR_STS_0  (AONSYS_REG_BASE + 0x238)
-#define REG_AON_SRAM_AXI_ERR_STS_1  (AONSYS_REG_BASE + 0x23c)
-#define REG_AON_SRAM_AXI_ERR_STS_2  (AONSYS_REG_BASE + 0x240)
-#define REG_AON_SRAM_AXI_ERR_STS_3  (AONSYS_REG_BASE + 0x244)
-#define REG_AON_SRAM_AXI_ERR_STS_4  (AONSYS_REG_BASE + 0x248)
-#define REG_AON_SE_MUX_LOCK         (AONSYS_REG_BASE + 0x24c)
-#define REG_AON_CPU_DBG_DIS_LOCK    (AONSYS_REG_BASE + 0x270)
-#define REG_AON_RESERVED_REG_4      (AONSYS_REG_BASE + 0x300)
-#define REG_AON_RESERVED_REG_5      (AONSYS_REG_BASE + 0x304)
-#define REG_AON_RESERVED_REG_6      (AONSYS_REG_BASE + 0x308)
-#define REG_AON_RESERVED_REG_7      (AONSYS_REG_BASE + 0x30c)
-#define REG_AON_RESERVED_REG_8      (AONSYS_REG_BASE + 0x400)
-#define REG_AON_RESERVED_REG_9      (AONSYS_REG_BASE + 0x404)
-#define REG_AON_RESERVED_REG_10     (AONSYS_REG_BASE + 0x408)
-#define REG_AON_RESERVED_REG_11     (AONSYS_REG_BASE + 0x40c)
-#define REG_AON_RESERVED_REG_12     (AONSYS_REG_BASE + 0x500)
-#define REG_AON_RESERVED_REG_13     (AONSYS_REG_BASE + 0x504)
-#define REG_AON_RESERVED_REG_14     (AONSYS_REG_BASE + 0x508)
-#define REG_AON_RESERVED_REG_15     (AONSYS_REG_BASE + 0x50c)
-#define REG_AON_RESERVED_REG_16     (AONSYS_REG_BASE + 0x600)
-#define REG_AON_RESERVED_REG_17     (AONSYS_REG_BASE + 0x604)
-#define REG_AON_RESERVED_REG_18     (AONSYS_REG_BASE + 0x608)
-#define REG_AON_RESERVED_REG_19     (AONSYS_REG_BASE + 0x60c)
-
-#define CPU_LP_MODE_DFLT_VAL          0x3ff
-#define CHIP_LP_MODE_DFLT_VAL         0x0
-#define AO_SERAM_TRN_DFLT_VAL         0x0
-#define AO_SERAM_INT_DFLT_VAL         0x0
-#define STR_SERAM_TRN_DFLT_VAL        0x0
-#define STR_SERAM_INT_DFLT_VAL        0x0
-#define STR_INDICATOR_0_DFLT_VAL      0x0
-#define STR_INDICATOR_1_DFLT_VAL      0x0
-#define STR_INDICATOR_2_DFLT_VAL      0x0
-#define STR_INDICATOR_3_DFLT_VAL      0x0
-#define PVTC_WR_LOCK_DFLT_VAL         0x0
-#define PVTC_TS_ALARM_DFLT_VAL        0x0
-#define PVTC_VM_ALARM_DFLT_VAL        0x0
-#define PVTC_PD_ALARM_DFLT_VAL        0x0
-#define E902_CNT_CLR_DFLT_VAL         0x0
-#define E902_RST_ADDR_DFLT_VAL        0xffef8000
-#define C906_RST_ADDR_L_DFLT_VAL      0xc0000000
-#define C906_RST_ADDR_H_DFLT_VAL      0xff
-#define RESERVED_REG_0_DFLT_VAL       0x0
-#define RESERVED_REG_1_DFLT_VAL       0x0
-#define RESERVED_REG_2_DFLT_VAL       0x0
-#define RESERVED_REG_3_DFLT_VAL       0x0
-#define AON_AHB_ADEXT_DFLT_VAL        0x0
-#define RC_EN_DFLT_VAL                0x1
-#define RC_FCAL_DFLT_VAL              0x77f
-#define RC_MODE_DFLT_VAL              0x1
-#define RC_READY_DFLT_VAL             0x0
-#define ISO_CFG_DFLT_VAL              0x0
-#define OCRAM_ERR_DFLT_VAL            0x0
-#define TIMER_LINK_DFLT_VAL           0x0
-#define PD_REQ_DFLT_VAL               0x0
-#define PD_ISO_EN_SET_DFLT_VAL        0x0
-#define PD_ISO_EN_CLR_DFLT_VAL        0x0
-#define PD_SW_EN_SET_DFLT_VAL         0x0
-#define PD_SW_EN_CLR_DFLT_VAL         0x0
-#define PD_SW_ACK_DFLT_VAL            0x3fffff
-#define PD_SW_CNT_EN_DFLT_VAL         0x0
-#define PD_FSM_RST_DFLT_VAL           0x0
-#define PD_INT_MASK_DFLT_VAL          0x3fffff
-#define PD_FSM_STS_L_DFLT_VAL         0x0
-#define PD_FSM_STS_H_DFLT_VAL         0x0
-#define PD_INT_STS_DFLT_VAL           0x0
-#define PD_INT_CLR_DFLT_VAL           0x0
-#define PD_BLK0_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK1_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK2_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK3_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK4_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK5_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK6_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK7_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK8_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK9_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK10_SW_CNT_DFLT_VAL      0xff00ff
-#define PD_BLK0_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK1_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK2_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK3_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK4_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK5_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK6_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK7_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK8_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK9_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK10_INTV_CNT_DFLT_VAL    0xff0ffff
-#define AUDIO_PMU_REQ_DFLT_VAL        0x0
-#define AUDIO_PMU_STS_DFLT_VAL        0x0
-#define AUDIO_PMU_INTR_DFLT_VAL       0x0
-#define PMU_AUDIO_REQ_DFLT_VAL        0x0
-#define PMU_AUDIO_STS_DFLT_VAL        0x0
-#define MEM_LP_MODE_DFLT_VAL          0x0
-#define C910_DBG_MASK_DFLT_VAL        0x0
-#define C910_L2CACHE_DFLT_VAL         0x0
-#define BISR_CTRL_DFLT_VAL            0x0
-#define EFUSE_PRELOAD_DONE_DFLT_VAL   0x0
-#define GPIO_RTE_DFLT_VAL             0x0
-#define PLL_DSKEW_LOCK_DFLT_VAL       0x0
-#define SRAM_AXI_CFG_DFLT_VAL         0x0
-#define SRAM_AXI_ST_DFLT_VAL          0x0
-#define SRAM_AXI_ERR_STS_0_DFLT_VAL   0x0
-#define SRAM_AXI_ERR_STS_1_DFLT_VAL   0x0
-#define SRAM_AXI_ERR_STS_2_DFLT_VAL   0x0
-#define SRAM_AXI_ERR_STS_3_DFLT_VAL   0x0
-#define SRAM_AXI_ERR_STS_4_DFLT_VAL   0x0
-#define SE_MUX_LOCK_DFLT_VAL          0x0
-#define CPU_DBG_DIS_LOCK_DFLT_VAL     0x0
-#define RESERVED_REG_4_DFLT_VAL       0x0
-#define RESERVED_REG_5_DFLT_VAL       0x0
-#define RESERVED_REG_6_DFLT_VAL       0x0
-#define RESERVED_REG_7_DFLT_VAL       0x0
-#define RESERVED_REG_8_DFLT_VAL       0x0
-#define RESERVED_REG_9_DFLT_VAL       0x0
-#define RESERVED_REG_10_DFLT_VAL      0x0
-#define RESERVED_REG_11_DFLT_VAL      0x0
-#define RESERVED_REG_12_DFLT_VAL      0x0
-#define RESERVED_REG_13_DFLT_VAL      0x0
-#define RESERVED_REG_14_DFLT_VAL      0x0
-#define RESERVED_REG_15_DFLT_VAL      0x0
-#define RESERVED_REG_16_DFLT_VAL      0x0
-#define RESERVED_REG_17_DFLT_VAL      0x0
-#define RESERVED_REG_18_DFLT_VAL      0x0
-#define RESERVED_REG_19_DFLT_VAL      0x0
-
-
-#endif

board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h

@@ -1,90 +0,0 @@
-//------------------------------------------------------------
-// DONOT MODIFY THIS FILE
-// generated by JISHENGJU automatically
-//------------------------------------------------------------
-
-#ifndef AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
-#define AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
-
-#define AONSYS_RSTGEN_REG_BASE	0xFFFFF44000
-
-#define REG_AON_RST_CNT             (AONSYS_RSTGEN_REG_BASE + 0x0   )
-#define REG_AON_SYS_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x10  )
-#define REG_AON_RTC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x14  )
-#define REG_AON_AOGPIO_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x18  )
-#define REG_AON_AOI2C_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x1c  )
-#define REG_AON_PVTC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x20  )
-#define REG_AON_E902_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x24  )
-#define REG_AON_AOTIMER_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x28  )
-#define REG_AON_AOWDT_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x2c  )
-#define REG_AON_APSYS_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x30  )
-#define REG_AON_NPUSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x34  )
-#define REG_AON_DDRSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x38  )
-#define REG_AON_AUDIO_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x3c  )
-#define REG_AON_BISR_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x50  )
-#define REG_AON_DSP0_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x54  )
-#define REG_AON_DSP1_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x58  )
-#define REG_AON_GPU_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x5c  )
-#define REG_AON_VDEC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x60  )
-#define REG_AON_VENC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x64  )
-#define REG_AON_ADC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x70  )
-#define REG_AON_AUDGPIO_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x74  )
-#define REG_AON_AOUART_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x78  )
-#define REG_AON_RST_CLR_0           (AONSYS_RSTGEN_REG_BASE + 0x100 )
-#define REG_AON_RST_CLR_1           (AONSYS_RSTGEN_REG_BASE + 0x104 )
-#define REG_AON_RST_CLR_2           (AONSYS_RSTGEN_REG_BASE + 0x108 )
-#define REG_AON_RST_CLR_3           (AONSYS_RSTGEN_REG_BASE + 0x10c )
-#define REG_AON_RST_CLR_4           (AONSYS_RSTGEN_REG_BASE + 0x110 )
-#define REG_AON_RST_STS_0           (AONSYS_RSTGEN_REG_BASE + 0x120 )
-#define REG_AON_RST_STS_1           (AONSYS_RSTGEN_REG_BASE + 0x124 )
-#define REG_AON_RST_STS_2           (AONSYS_RSTGEN_REG_BASE + 0x128 )
-#define REG_AON_RST_STS_3           (AONSYS_RSTGEN_REG_BASE + 0x12c )
-#define REG_AON_RST_STS_4           (AONSYS_RSTGEN_REG_BASE + 0x130 )
-#define REG_AON_RST_REQ_EN_0        (AONSYS_RSTGEN_REG_BASE + 0x140 )
-#define REG_AON_RST_REQ_EN_1        (AONSYS_RSTGEN_REG_BASE + 0x144 )
-#define REG_AON_RST_REQ_EN_2        (AONSYS_RSTGEN_REG_BASE + 0x148 )
-#define REG_AON_RST_REQ_EN_3        (AONSYS_RSTGEN_REG_BASE + 0x14c )
-#define REG_AON_SRAM_AXI_RST_CFG    (AONSYS_RSTGEN_REG_BASE + 0x11f4)
-#define REG_AON_SE_RST_CFG          (AONSYS_RSTGEN_REG_BASE + 0x160 )
-
-#define RST_CNT_DFLT_VAL              0xf0f
-#define SYS_RST_CFG_DFLT_VAL          0x0
-#define RTC_RST_CFG_DFLT_VAL          0x3
-#define AOGPIO_RST_CFG_DFLT_VAL       0x3
-#define AOI2C_RST_CFG_DFLT_VAL        0x1
-#define PVTC_RST_CFG_DFLT_VAL         0x1
-#define E902_RST_CFG_DFLT_VAL         0x2
-#define AOTIMER_RST_CFG_DFLT_VAL      0x3
-#define AOWDT_RST_CFG_DFLT_VAL        0x1
-#define APSYS_RST_CFG_DFLT_VAL        0x1
-#define NPUSYS_RST_CFG_DFLT_VAL       0x1
-#define DDRSYS_RST_CFG_DFLT_VAL       0x1
-#define AUDIO_RST_CFG_DFLT_VAL        0x0
-#define BISR_RST_CFG_DFLT_VAL         0x3
-#define DSP0_RST_CFG_DFLT_VAL         0x1
-#define DSP1_RST_CFG_DFLT_VAL         0x1
-#define GPU_RST_CFG_DFLT_VAL          0x1
-#define VDEC_RST_GEN_RST_CFG_DFLT_VAL         0x1
-#define VENC_RST_CFG_DFLT_VAL         0x1
-#define ADC_RST_CFG_DFLT_VAL          0x1
-#define AUDGPIO_RST_CFG_DFLT_VAL      0x3
-#define AOUART_RST_CFG_DFLT_VAL       0x3
-#define RST_CLR_0_DFLT_VAL            0x0
-#define RST_CLR_1_DFLT_VAL            0x0
-#define RST_CLR_2_DFLT_VAL            0x0
-#define RST_CLR_3_DFLT_VAL            0x0
-#define RST_CLR_4_DFLT_VAL            0x0
-#define RST_STS_0_DFLT_VAL            0x0
-#define RST_STS_1_DFLT_VAL            0x0
-#define RST_STS_2_DFLT_VAL            0x0
-#define RST_STS_3_DFLT_VAL            0x0
-#define RST_STS_4_DFLT_VAL            0x0
-#define RST_REQ_EN_0_DFLT_VAL         0x11100
-#define RST_REQ_EN_1_DFLT_VAL         0xbb000000
-#define RST_REQ_EN_2_DFLT_VAL         0x0
-#define RST_REQ_EN_3_DFLT_VAL         0x0
-#define SRAM_AXI_RST_CFG_DFLT_VAL     0x5f
-#define SE_RST_CFG_DFLT_VAL           0x1
-
-
-#endif

board/thead/light-c910/lpddr4/include/common_lib.h

@@ -7,8 +7,6 @@
 #include "ddr_reg_define.h"
 #include "ddr_sysreg_registers_struct.h"
 #include "ddr_sysreg_registers.h"
-#include "aonsys_reg_define.h"
-#include "aonsys_rstget_reg_define.h"
 #include "define_ddr.h"
 #include "DWC_ddr_umctl2_c_struct.h"
 #include "DWC_ddr_umctl2_header.h"

board/thead/light-c910/lpddr4/include/ddr_common_func.h

@@ -15,9 +15,6 @@ enum DDR_BITWIDTH {
 
 unsigned long get_ddr_density(void);
 enum DDR_TYPE get_ddr_type(void);
-int get_ddr_rank_number(void);
-int get_ddr_freq(void);
-enum DDR_BITWIDTH get_ddr_bitwidth(void);
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data);
 unsigned int ddr_sysreg_rd(unsigned long int addr);
 
@@ -52,8 +49,4 @@ void addrmap(int rank_num, enum DDR_BITWIDTH bits);
 void ctrl_en(enum DDR_BITWIDTH bits);
 void enable_auto_refresh(void);
 void lpddr4_auto_selref(void);
-int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
-                    enum DDR_BITWIDTH bits, unsigned long size);
-int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
-                    enum DDR_BITWIDTH bits, unsigned long size);
 #endif // DDR_COMMON_FUNCE_H

board/thead/light-c910/lpddr4/include/ddr_retention.h

@@ -1,38 +0,0 @@
-#ifndef DDR_RETENTION_H
-#define DDR_RETENTION_H
-
-///data structure to store ddr misc register address, value
-typedef struct Reg_Misc_Addr_Val {
-  uint32_t Address; ///< register address
-  uint32_t Value;   ///< register value
-} Reg_Misc_Addr_Val_t;
-
-///data structure to store register address, value pairs
-typedef struct Reg_Phy_Addr_Val {
-  uint32_t Address; ///< register address
-  uint16_t Value0;   ///< register value phy0
-  uint16_t Value1;   ///< register value phy1
-} Reg_Phy_Addr_Val_t;
-
-/// enumeration of instructions for PhyInit Register Interface
-typedef enum {
-  saveRegs,         ///< save(read) tracked register values
-  restoreRegs,      ///< restore (write) saved register values
-} regInstr;
-
-// typedef struct Reg_Addr_Value {
-//   uint32_t reg_num;
-//   Reg_Addr_Val_t reg[0];
-// } Reg_Addr_Value_t;
-
-typedef struct Ddr_Reg_Config {
-    uint32_t misc_reg_num;
-    uint32_t phy_reg_num;
-    uint8_t  ddr_rank;
-    uint8_t  reserve[55];
-} Ddr_Reg_Config_t;
-
-int dwc_ddrphy_phyinit_regInterface(regInstr myRegInstr);
-void dwc_ddr_misc_regu_save(void);
-
-#endif

board/thead/light-c910/lpddr4/src/ddr_common_func.c

@@ -2,14 +2,9 @@
 #include <linux/sizes.h>
 #include "../include/common_lib.h"
 #include "../include/ddr_common_func.h"
-#include "../include/ddr_retention.h"
 
 DDR_SYSREG_REG_SW_REG_S ddr_sysreg;
 
-#ifdef CONFIG_DDR_MSG
-#define DDR_DEBUG(x) printf(x)
-#endif
-
 #ifndef CONFIG_DDR_RANK_SIZE
 #define CONFIG_DDR_RANK_SIZE SZ_4G
 #endif
@@ -39,44 +34,6 @@ enum DDR_TYPE get_ddr_type() {
 #endif // #ifdef CONFIG_LPDDR4X
 }
 
-int get_ddr_rank_number() {
-#ifdef CONFIG_DDR_SINGLE_RANK
-	return 1;
-#elif defined CONFIG_DDR_DUAL_RANK
-	return 2;
-#else
-#ifdef CONFIG_DDR_MSG
-	DDR_DEBUG("unsupported ddr rank type!!!\n");
-#endif
-    return NULL;
-#endif
-}
-
-int get_ddr_freq() {
-#ifdef CONFIG_DDR_4266
-    return 4266;
-#elif CONFIG_DDR_3733
-    return 3733;
-#elif CONFIG_DDR_3200
-    return 3200;
-#elif CONFIG_DDR_2133
-	return 2133;
-#else
-    printf("unsupport lpddr4 freq!!!\n");
-    return -1;
-#endif
-}
-
-enum DDR_BITWIDTH get_ddr_bitwidth() {
-#ifdef CONFIG_DDR_H32_MODE
-    return DDR_BITWIDTH_32;
-#elif CONFIG_DDR_H16_MODE
-    return DDR_BITWIDTH_16;
-#else
-    return DDR_BITWIDTH_64;
-#endif
-}
-
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data) {
   wr(addr+DDR_SYSREG_BADDR,wr_data);
 }
@@ -147,114 +104,75 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
 
   void lp4_mrw(int addr, int wdata,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
-  uint32_t val_t0,val_t1;
   if(dch==0) {
-        while ((rd(MRSTAT) & 0x1) == 0x1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
-        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
-        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-
-        //udelay(10);
-        //delay 5us
-        val_t0=rd(0xFFF4D004);
-        val_t1=rd(0xFFF4D004);
-        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
-
-        while ((rd(MRSTAT) & 0x1) == 0x1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
+  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
   }
   else {
-        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
-        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
-        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-
-        //udelay(10);
-        //delay 5us
-        val_t0=rd(0xFFF4D004);
-        val_t1=rd(0xFFF4D004);
-        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
-        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
+  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  }
   }
-}
 
   int lp4_mrr(int addr,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
   if(dch==0) {
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
-        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
+  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
-        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-
-        udelay(20);
-        while ((rd(MRSTAT) & 0x1) == 0x1);
-        return ddr_sysreg_rd(MRR_STS_CH0);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
   }
   else {
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
-        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
+  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
-        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-
-        udelay(20);
-        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
-        return ddr_sysreg_rd(MRR_STS_CH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
   }
   }
 
@@ -318,15 +236,15 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
     if(port & 0x4) wr(PCTRL_2,0);
     if(port & 0x8) wr(PCTRL_3,0);
     if(port & 0x10) wr(PCTRL_4,0);
-    while (rd(PSTAT) != 0x0);
-    if ((port & 0x1F) == 0x1F) { //all ports are disabled
-        wr(DBG1, 2);
-        wr(DBG1_DCH1, 2);
+    if(port & 0x1F) { //at least one port is not disabled
+        wr(DBG1,0);
+        wr(DBG1_DCH1,0);
     }
-    else { //at least one port is not disabled
-        wr(DBG1, 0);
-        wr(DBG1_DCH1, 0);
+    else { //all ports are disabled
+        wr(DBG1,3);
+        wr(DBG1_DCH1,3);
     }
+
   }
 
   void enable_axi_port(int port) {
@@ -539,7 +457,7 @@ if(bits==64) {
   wr(DFITMG0,0x05a3820e);//[28:24] dft_t_ctrl_delay [22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000c0303);
-  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
+  wr(DFILPCFG0,0x0351a001);
   //wr(DFIUPD0,0x00400018); //[31:30]=0 use ctrlupd enable
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x00000000);//[31]=0 disable phy ctrlupdate
@@ -639,7 +557,7 @@ if(bits==64) {
   wr(DFITMG0,0x059f820c);//[28:24] dfi_t_ctrl_delay
 #endif
   wr(DFITMG1,0x000c0303);//dfi_t_wrdata_delay=tctrl+6+BL/2+trainedTdqsdly=24, may need take care cmd pipe
-  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
+  wr(DFILPCFG0,0x0351a001);
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -727,7 +645,7 @@ if(bits==64) {
   wr(DFITMG0,0x059b820a); //[22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
+  wr(DFILPCFG0,0x0351a001);
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -812,7 +730,7 @@ if(bits==64) {
   wr(ZQCTL2,0x00000000);
   wr(DFITMG0,0x048f8206);
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
+  wr(DFILPCFG0,0x0351a001);
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -938,28 +856,17 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 32bit mode\n");
 #endif
+  wr(ADDRMAP0,0x001f001f);  //
   if(rank_num==2) {
-#ifdef CONFIG_DDR_DDP
-    wr(ADDRMAP0,0x001f0018);//max 8GB
-#else
-    wr(ADDRMAP0,0x001f0017); //4GB
-#endif
-  }
-  else {
-    wr(ADDRMAP0,0x001f001f); //cs_bit0: NULL
+  wr(ADDRMAP0,0x001f0017);//4GB
   }
   wr(ADDRMAP1,0x00080808); //bank +2
   wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2  +2
   wr(ADDRMAP3,0x00000000); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x070f0707); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x07070707); //row 15
-  wr(ADDRMAP7,0x00000f0f); //row16: NULL
-#ifdef CONFIG_DDR_DDP
-  if(rank_num==2) {
-    wr(ADDRMAP7,0x00000f07); //max row16
-  }
-#endif
+  wr(ADDRMAP6,0x07070707); //max row 15
+  wr(ADDRMAP7,0x00000f0f);
   wr(ADDRMAP9,0x07070707);
   wr(ADDRMAP10,0x07070707);
   wr(ADDRMAP11,0x00000007);
@@ -967,12 +874,12 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 64bit mode, 256B interleaving\n");
 #endif
-  wr(ADDRMAP0,0x0004001f); //cs_bit0: NULL
+  wr(ADDRMAP0,0x0004001f);  // +2
   if(rank_num==2) {
 #ifdef CONFIG_DDR_DDP
-    wr(ADDRMAP0,0x00040019);//max 16GB
+  wr(ADDRMAP0,0x00040019);//16GB
 #else
-    wr(ADDRMAP0,0x00040018);//8GB
+  wr(ADDRMAP0,0x00040018);//8GB
 #endif
   }
   wr(ADDRMAP1,0x00090909); //bank +2
@@ -980,11 +887,11 @@ if(bits==64) {
   wr(ADDRMAP3,0x01010101); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x08080808); //row15
+  wr(ADDRMAP6,0x08080808);
 #ifdef CONFIG_DDR_DDP
-  wr(ADDRMAP7,0x00000f08); //row16
+  wr(ADDRMAP7,0x00000f08);
 #else
-  wr(ADDRMAP7,0x00000f0f); //row16: NULL
+  wr(ADDRMAP7,0x00000f0f);
 #endif
   wr(ADDRMAP9,0x08080808);
   wr(ADDRMAP10,0x08080808);
@@ -994,156 +901,6 @@ if(bits==64) {
  }
 }
 
-#define MEMSIZE_MIN_MB (1*1024)
-#define MEMSIZE_MAX_MB (16*1024)
-#define UNIT_MB (1024*1024)
-int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
-					enum DDR_BITWIDTH bits, unsigned long size)
-{
-  if ((size < (unsigned long)MEMSIZE_MIN_MB*UNIT_MB) ||
-    (size > (unsigned long)MEMSIZE_MAX_MB*UNIT_MB))
-    goto err_ret;
-
-  if (bits == DDR_BITWIDTH_32) {// only phy0
-    if (rank_num == 2) {
-      if (size == 0x80000000) //2GB
-        goto ret_ok;
-      else if (size == 0x100000000) //4GB
-        goto ret_ok;
-      else if (size == 0x200000000) //8GB
-        goto ret_ok;
-      else
-        goto err_ret;
-    }
-    else { // single rank
-      if (size == 0x40000000) //1GB
-        goto ret_ok;
-      else if (size == 0x80000000) //2GB
-        goto ret_ok;
-      else if (size == 0x100000000) //4GB
-        goto ret_ok;
-      else
-        goto err_ret;
-    }
-  }
-  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
-    if (rank_num == 2) {
-      if (size == 0x100000000) //4GB
-        goto ret_ok;
-      else if (size == 0x200000000) //8GB
-        goto ret_ok;
-      else if (size == 0x400000000) //16GB
-        goto ret_ok;
-      else
-        goto err_ret;
-    }
-    else { // single rank
-      if (size == 0x80000000) //2GB
-        goto ret_ok;
-      else if (size == 0x100000000) //4GB
-        goto ret_ok;
-      else if (size == 0x200000000) //8GB
-        goto ret_ok;
-      else
-        goto err_ret;
-    }
-  }
-  else {
-    goto err_ret;
-  }
-
-ret_ok:
-  return 0;
-
-err_ret:
-  return -1;
-}
-
-int adjust_ddr_addrmap(enum DDR_TYPE type, int rank_num, int speed,
-					enum DDR_BITWIDTH bits, unsigned long size)
-{
-  if (lpddr4_query_boundary(type, rank_num, speed, bits, size) < 0)
-    goto err_ret;
-
-  if (bits == DDR_BITWIDTH_32) {// only phy0
-    if (rank_num == 2) {
-      if (size == 0x80000000) {//2GB
-        wr(ADDRMAP0,0x001f0016); // cs_bit0: HIF[28]
-        wr(ADDRMAP6,0x0f070707); // row15: NULL
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x100000000) {//4GB
-        wr(ADDRMAP0,0x001f0017); // cs_bit0: HIF[29]
-        wr(ADDRMAP6,0x07070707); // row15: HIF[28]
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x200000000) {//8GB
-        wr(ADDRMAP0,0x001f0018); // cs_bit0: HIF[30]
-        wr(ADDRMAP6,0x07070707); // row15: HIF[28]
-        wr(ADDRMAP7,0x00000f07); // row16: HIF[29]
-      }
-    }
-	else { // single rank
-      wr(ADDRMAP0,0x001f001f); // cs_bit0: NULL
-      if (size == 0x40000000) {//1GB
-        wr(ADDRMAP6,0x0f070707); // row15: NULL
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x80000000) {//2GB
-        wr(ADDRMAP6,0x07070707); // row15: HIF[28]
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x100000000) {//4GB
-        wr(ADDRMAP6,0x07070707); // row15: HIF[28]
-        wr(ADDRMAP7,0x00000f07); // row16: HIF[29]
-      }
-    }
-  }
-  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
-    if (rank_num == 2) {
-      if (size == 0x100000000) {//4GB
-        wr(ADDRMAP0,0x00040017); // cs_bit0: HIF[29]
-        wr(ADDRMAP6,0x0f080808); // row15: NULL
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x200000000) {//8GB
-        wr(ADDRMAP0,0x00040018); // cs_bit0: HIF[30]
-        wr(ADDRMAP6,0x08080808); // row15: HIF[29]
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x400000000) {//16GB
-        wr(ADDRMAP0,0x00040019); // cs_bit0: HIF[31]
-        wr(ADDRMAP6,0x08080808); // row15: HIF[29]
-        wr(ADDRMAP7,0x00000f08); // row16: HIF[30]
-      }
-    }
-    else { // single rank
-      wr(ADDRMAP0,0x0004001f); // cs_bit0: NULL
-      if (size == 0x80000000) {//2GB
-        wr(ADDRMAP6,0x0f080808); // row15: NULL
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x100000000) {//4GB
-        wr(ADDRMAP6,0x08080808); // row15: HIF[29]
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x200000000) {//8GB
-        wr(ADDRMAP6,0x08080808); // row15: HIF[29]
-        wr(ADDRMAP7,0x00000f08); // row16: HIF[30]
-      }
-    }
-  }
-  else {
-    // nothing
-  }
-
-  return 0;
-
-err_ret:
-  printf("unsupport memsize %ld\n", size);
-  return -1;
-}
-
   void quasi_reg_write(unsigned long int reg,int wdata) {
     DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
 
@@ -1258,11 +1015,11 @@ void lpddr4_enter_selfrefresh(int pwdn_en,int dis_dram_clk,int mode) {
     umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     if(pwdn_en) {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 2) //wait sdram enter selfrefresh-powerdown state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
     }
     else {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 1) //wait sdram enter selfrefresh state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
     }
 #ifdef CONFIG_DDR_MSG
     printf("[lpddr4_enter_selfrefresh]: CH1 STAT is :%x after enter selfrefresh state\n",umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32);
@@ -1298,8 +1055,7 @@ void lpddr4_auto_ps_en(int pwdn_en,int selfref_en,int clock_auto_disable ) {
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32 = ddr_sysreg_rd(DDR_CFG0);
-    //ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
-    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1FA;
+    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
     ddr_sysreg_wr(DDR_CFG0,ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32);
   }
 
@@ -1319,7 +1075,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 #ifdef CONFIG_DDR_MSG
   printf("[dfi_freq_change]: start dfi_freq_change, target dfi_freq is %x \n",dfi_freq);
 #endif
-  //wr(DBG1,3);
+  wr(DBG1,3);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
   wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
@@ -1330,6 +1086,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_frequency = dfi_freq;
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_complete_en = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
 
@@ -1340,28 +1097,15 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   while( umctl2_reg.dwc_ddr_umctl2_c_struct_swstat.sw_done_ack == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWSTAT);
 
-  wr(SWCTL,0x0);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
-  wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
-  wr(SWCTL,0x1);
-  while(rd(SWSTAT)!=0x00000001);
   rdata = rd(DFISTAT);
-  while ((rdata & 0x1) != 0) //wait dfi_init_complete = 0
-    rdata = rd(DFISTAT);
-
-#ifndef CONFIG_DDR_H32_MODE
-  rdata = rd(DCH1_DFISTAT);
   while((rdata & 0x1) != 0) //wait dfi_init_complete = 0
-    rdata = rd(DCH1_DFISTAT);
-#endif
-
+  rdata = rd(DFISTAT);
   //change dfi clk freq here
   //pull down dfi_init_start
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
-  wr(SWCTL, umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
- 
+  wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
+
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
@@ -1375,17 +1119,9 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
   while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
-
-  //wait dfi_init_complete = 1
-#ifndef CONFIG_DDR_H32_MODE
-  umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
-  while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
-    umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
-#endif
-
-  //wr(DBG1,0);
+  wr(DBG1,0);
 #ifdef CONFIG_DDR_MSG
-  printf("[dfi_freq_change]: dfi_freq_change, end \n");
+  printf("[dfi_freq_change]: dfi_freq_change, end \n",dfi_freq);
 #endif
 }
 
@@ -1410,168 +1146,3 @@ void lpddr4_auto_selref(void)
   wr(PWRCTL,0x0000000b); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
   wr(DCH1_PWRCTL,0x0000000b);
 }
-
-void ctrl_en_lp3_exit(enum DDR_BITWIDTH bits) {
-  //skip DRAM init, because this has done 
-  wr(SWCTL,0x00000000);
-  wr(INIT0,0xc0020002);
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-  //dfi frequency change proto ,to PS0
-  wr(SWCTL,0x00000000);
-  wr(DFIMISC,0x00000000);// [5]dfi_freq=0x0
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-  wr(SWCTL,0x00000000);
-  wr(DFIMISC,0x00000020);// [5]dfi_init_start=0x1
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-
-  while(rd(DFISTAT)!=0x00000001); //polling dfi_init_complete
-if(bits==64) {
-  while(rd(DCH1_DFISTAT)!=0x00000001);
- }
-  wr(SWCTL,0x00000000);
-  wr(DFIMISC,0x00000000);
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-
-  wr(SWCTL,0x00000000);
-  wr(DFIMISC,0x00000001);
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-  //for low power,
-  wr(SWCTL,0x00000000);
-  wr(PWRCTL,0x0000000a); //[3] dfi_dram_clk_disable [1] powerdown_en
-  wr(DCH1_PWRCTL,0x0000000a);
-  wr(SWCTL,0x00000001);
-  while (rd(SWSTAT) != 0x00000001);
-  //detect until umctrl into normal state
-  while (rd(STAT) != 0x00000001);
-  if(bits==64) {
-    while(rd(DCH1_STAT) != 0x00000001);
-  }
-
-  //en phy master proto
-  wr(DFIPHYMSTR,0x14000001);
-
-#ifdef CONFIG_DDR_MSG
-    DDR_DEBUG("DFIPHYMSTR is %0x \n", rd(DFIPHYMSTR));
-    DDR_DEBUG("DFIUPD0    is %0x \n", rd(DFIUPD0));
-    DDR_DEBUG("DFIUPD1    is %0x \n", rd(DFIUPD1));
-    DDR_DEBUG("ZQCTL0     is %0x \n", rd(ZQCTL0));
-    DDR_DEBUG("ADDRMAP0     is %0x \n", rd(ADDRMAP0));
-    DDR_DEBUG("ADDRMAP1     is %0x \n", rd(ADDRMAP1));
-#endif
-}
-
-int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
-					enum DDR_BITWIDTH bits, unsigned long size)
-{
-    int ret;
-    unsigned int rdata;
-
-    //a.
-    ddr_sysreg_wr(DDR_CFG1, 0xa000011f);   //remove core clock after xx
-    wr(PWRCTL, 0x00000000); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
-    wr(DCH1_PWRCTL, 0x00000000);
-
-    // use phy value stored in spl
-    //dwc_ddrphy_phyinit_regInterface(saveRegs);
-
-    //b.dis axi port
-    disable_axi_port(0x1f);
-    while (rd(PSTAT) != 0x0);
-
-#ifdef CONFIG_DDR_MSG
-    DDR_DEBUG("Axi prot idle\n");
-#endif
-    wr(DFIPHYMSTR, 0x14000000);
-    //check status.
-    while ((rd(STAT) & 0x3) == 0x03);
-
-#ifndef CONFIG_DDR_H32_MODE
-    while ((rd(STAT_DCH1) & 0x3) == 0x03);
-#endif
-    //c.poll cam empty flag
-    while ((rd(DBGCAM) & 0x36000000) != 0x36000000);
-    //d.save phy regs
-    //e.SRE
-    lpddr4_enter_selfrefresh(1, 0, 0);
-    //f.LP3 enter
-    dfi_freq_change(0x1f, 0x3);
-    //g.PwrOk disassert
-    rdata = ddr_sysreg_rd(DDR_CFG0);
-    rdata &= ~(0x1 << 6);
-    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
-
-    //p.phy reset
-    rdata = ddr_sysreg_rd(DDR_CFG0);
-    rdata &= ~(0x1 << 7);
-    rdata &= 0x0;
-    ddr_sysreg_wr(DDR_CFG0, rdata);   //Phy reset .DDR_CFG0 ALL reset
-
-    //r.ddr core reset
-    rdata = ddr_sysreg_rd(DDR_CFG0);
-    rdata &= ~(0x1 << 5);
-    ddr_sysreg_wr(DDR_CFG0, rdata);   //ctrl sw reset
-
-    //s.pwr ok assert
-    rdata = ddr_sysreg_rd(DDR_CFG0);
-    rdata |= (0x1 << 6);
-    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
-
-    //t.ctrl init
-    //dwc_umctl_init_skip_traing(type, rank_num, speed, bits);
-    ddr_sysreg_wr(DDR_CFG0, 0x50);  // release apb presetn
-    ddr_sysreg_wr(DDR_CFG0, 0x50);
-    ddr_sysreg_wr(DDR_CFG0, 0x50);
-    if (bits == 32) {
-        ddr_sysreg_wr(DDR_CFG0, 0x52);
-    }
-    ctrl_init(rank_num, speed);
-    addrmap(rank_num, bits);
-    ret = adjust_ddr_addrmap(type, rank_num, speed, bits, size);
-
-    // msic regu restore for str
-    dwc_ddr_misc_regu_save();
-
-    de_assert_other_reset_ddr(); //after this step, only PwrOk is staill low
-
-    dq_pinmux(bits);
-
-    //u.phy restor
-	  dwc_ddrphy_phyinit_regInterface(restoreRegs);
-
-    //v.ctrl en ,hs
-    ctrl_en_lp3_exit(bits);
-
-    //w.SRE
-    lpddr4_selfrefresh_exit(0);
-
-    //y.en auto refresh
-    enable_auto_refresh();
- 
-    //x.en axi port
-    enable_axi_port(0x1f);
-    wr(DFIPHYMSTR, 0x14000001);
-    lpddr4_auto_selref();
-
-    if(rd(PSTAT))
-    {
-#ifdef CONFIG_DDR_MSG
-	    DDR_DEBUG("***** DDR busy in LP3 Mode *****\n");
-#endif
-    }else{
-#ifdef CONFIG_DDR_MSG
-	    DDR_DEBUG("***** AXI port idle *****\n");
-#endif
-    }
-    return ret;
- }
-

board/thead/light-c910/sbmeta/sbmeta.c

@@ -29,7 +29,7 @@
 #define DMSG(fmt, args...)      trace_printer("", fmt, ##args)
 #endif
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
 #if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 /* digest_size corresponding to digest_scheme specified in sbmeta_info_t */
 static const int digest_size[] = {0, 20, 16, 28, 32, 48, 64, 32};
@@ -62,8 +62,7 @@ typedef struct {
     char        filename[MAX_NAME_SIZE];
     uint8_t     digest[MAX_DIGEST_SIZE];
     uint32_t    relocated_addr;
-    uint8_t     security_level;
-    uint8_t     reserved[15];
+    uint32_t    reserved[4];
 } sbmeta_info_t;
 
 static int is_sbmeta_info(uint32_t entry_src_addr)
@@ -108,11 +107,6 @@ static int dump_sbmeta_info(sbmeta_info_t *sbmeta_info)
         IMSG("Image has been loaded\r\n");
     }
 
-    if (sbmeta_info->security_level > SBMETA_SECURITY_LEVEL_SIGN || sbmeta_info->security_level < SBMETA_SECURITY_LEVEL_NONE) {
-        EMSG("security level is invalid\n");
-        return CMD_RET_FAILURE;
-    }
-
     /* dump sbmeta_info_t */
     DMSG("image medium type: %d\n", sbmeta_info->medium_type);
     DMSG("image load part: mmc %d:%d\n", sbmeta_info->dev, sbmeta_info->part);
@@ -142,10 +136,6 @@ static int sbmeta_field_verify(sbmeta_info_t *sbmeta_info, unsigned long img_src
         return CMD_RET_FAILURE;
     }
 
-    if (sbmeta_info->security_level < SBMETA_SECURITY_LEVEL_SIGN) {
-        return 0;
-    }
-
     /* if image has secure header, check with sbmeta field */
     if (image_have_head(img_src_addr)) {
         phead = (img_header_t *)img_src_addr;
@@ -231,7 +221,7 @@ static int sbmeta_verify_image(uint32_t image_load_addr, sbmeta_info_t *sbmeta_i
     uint8_t checksum_scheme = sbmeta_info->checksum_scheme;
     uint8_t *digest = sbmeta_info->digest;
     uint8_t is_encrypted = sbmeta_info->isencrypted;
-    uint32_t security_level = sbmeta_info->security_level;
+    uint32_t security_level = env_get_hex("sbmeta_security_level", 3);
     uint32_t filesize = 0;
     char buf[64] = {0};
 
@@ -263,11 +253,11 @@ static int sbmeta_verify_image(uint32_t image_load_addr, sbmeta_info_t *sbmeta_i
 
     /* start verifying images */
     IMSG("Process %s image verification ...\n", image_name);
-    if (security_level == SBMETA_SECURITY_LEVEL_SIGN || is_encrypted != 0) {
+    if (security_level == 3 || is_encrypted != 0) {
         if (verify_customer_image(image_type, image_load_addr) != 0) {
             return CMD_RET_FAILURE;
         }
-    } else if (security_level == SBMETA_SECURITY_LEVEL_HASH) {
+    } else if (security_level == 2) {
         if (memcmp(digest, buf, 64) == 0) {
             EMSG("sbmeta info doesn't specify digest value in security level 2\r\n");
             return CMD_RET_FAILURE;
@@ -319,8 +309,7 @@ static int light_sbmetaboot(int argc, char *const argv[])
     sbmeta_info_t *sbmeta_info = NULL;
 
     /* Load sbmeta image to memory */
-    snprintf(cmd, sizeof(cmd), "ext4load mmc ${mmcdev}:${mmcsbmetapart} 0x%x %s", (void *)(uintptr_t)LIGHT_SBMETA_ADDR, SBMETA_FILENAME);
-    printf("%s\n",cmd);
+    snprintf(cmd, sizeof(cmd), "ext4load mmc $mmcdev:%x 0x%p %s", SBMETA_PART, (void *)(uintptr_t)LIGHT_SBMETA_ADDR, SBMETA_FILENAME);
     if (run_command(cmd, 0) != 0) {
         /* if sbmeta doesn't exist, do secboot by default */
         IMSG("SBMETA doesn't exist, go to verify tf/tee\r\n");
@@ -335,6 +324,7 @@ static int light_sbmetaboot(int argc, char *const argv[])
 
         return 0;
     }
+
     /* initialize crypto algorithm interfaces */
     if (csi_sec_init() != 0) {
         return CMD_RET_FAILURE;

board/thead/light-c910/sbmeta/sbmeta.h

@@ -14,9 +14,10 @@
 #define MAX_DIGEST_SIZE     64
 #define SBMETA_MAGIC        0x544D4253  /* = {'S', 'B', 'M', 'T'} */
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
 #define LIGHT_SBMETA_ADDR   0x10000000
 #endif
+#define SBMETA_PART         5
 #define ENTRY_SIZE          128
 #define PLAIN_SBMETA_TEXT   4096
 #define SBMETA_SIZE         4736  /* 4K SMBETA image + 640 footer */
@@ -26,8 +27,8 @@
 #define SIGN_TYPE_NUM       6
 #define SBMETA_FILENAME     "sbmeta.bin"
 
-#define SBMETA_SECURITY_LEVEL_SIGN      3   /* verify signature and hash */
-#define SBMETA_SECURITY_LEVEL_HASH      2   /* verify checksum */
-#define SBMETA_SECURITY_LEVEL_NONE      1   /* no verification */
+#define SBMETA_SECURITY_LEVEL_H      3   /* verify signature and hash */
+#define SBMETA_SECURITY_LEVEL_M      2   /* verify checksum */
+#define SBMETA_SECURITY_LEVEL_L      1   /* no verification */
 
 #endif

board/thead/light-c910/sec_check.c

@@ -75,7 +75,7 @@ void designware_get_mac_from_fuse(unsigned char *mac)
 	}
 }
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
 /* Secure function for image verificaiton here */
 int get_image_version(unsigned long img_src_addr)
 {

board/thead/light-c910/spl.c

@@ -26,11 +26,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void init_ddr(void);
-#ifdef CONFIG_FIXUP_MEMORY_REGION
-extern int fixup_ddr_addrmap(unsigned long size);
-extern int query_ddr_boundary(unsigned long size);
-#endif
-extern unsigned long get_ddr_density(void);
 extern void cpu_clk_config(int cpu_freq);
 extern void sys_clk_config(void);
 extern void ddr_clk_config(int ddr_freq);
@@ -98,25 +93,6 @@ void setup_ddr_pmp(void)
 	sync_is();
 }
 
-void clear_ddr_pmp(void)
-{
-	/* restore pmp entry0,entry1 setting in bootrom */
-	writel(0x0400000000 >> 12, (void *)(PMP_BASE_ADDR + 0x104));
-	writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x100));
-	writel(0xffe1000000 >> 12, (void *)(PMP_BASE_ADDR + 0x10c));
-	writel(0xffe0180000 >> 12, (void *)(PMP_BASE_ADDR + 0x108));
-
-	writel(0x4040, (void *)(PMP_BASE_ADDR + 0x000));
-
-	sync_is();
-}
-
-static inline void _l2cache_ciall(void)
-{
-	asm volatile (".long 0x0170000b");
-}
-
-
 int get_rng(unsigned int *rng, int cnt)
 {
 	int i;
@@ -321,113 +297,20 @@ void setup_ddr_parity(void)
 	}
 }
 
-#ifdef CONFIG_FIXUP_MEMORY_REGION
-
-#define MAGIC_DATA (0xF4240)
-#define MAGIC_DATA2 (0x5AA5)
-#define MAGIC_DATA3 (0x3C3C)
-#define MAGIC_DATA4 (0xF0F0)
-
-/*
-return: 0: found boundary;
-*/
-int boundary_verify(unsigned long boundary) {
-	phys_addr_t verify_addr = (phys_addr_t)CONFIG_SYS_SDRAM_BASE;
-	phys_addr_t verify_addr2 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/4;
-	phys_addr_t verify_addr3 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/2;
-	phys_addr_t verify_addr4 = (phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE;
-
-	// verify data accessing result firstly
-	writel(MAGIC_DATA2, verify_addr);
-	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
-	if (readl(verify_addr) != MAGIC_DATA2) {
-		printf("ddr rw test failed\n");
-		return -1;
-	}
-	writel(MAGIC_DATA, verify_addr);  // writing at beginning
-	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
-	if (readl(verify_addr) != MAGIC_DATA) {
-		printf("ddr rw test failed\n");
-		return -1;
-	}
-	writel(MAGIC_DATA2, verify_addr2); // writing at one-quarter addr
-	writel(MAGIC_DATA3, verify_addr3); // writing at half addr
-	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
-	invalidate_dcache_range(verify_addr2, verify_addr2 + CONFIG_SYS_CACHELINE_SIZE);
-	invalidate_dcache_range(verify_addr3, verify_addr3 + CONFIG_SYS_CACHELINE_SIZE);
-
-	if (boundary == (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB) { // boundary by design
-		if ((readl(verify_addr) == MAGIC_DATA) &&
-			(readl(verify_addr2) == MAGIC_DATA2) &&
-			(readl(verify_addr3) == MAGIC_DATA3))
-			return 0;
-	}
-	else {
-		writel(MAGIC_DATA4, verify_addr4); // writing out of boundary
-		invalidate_dcache_range(verify_addr4, verify_addr4 + CONFIG_SYS_CACHELINE_SIZE);
-		if ((readl(verify_addr) == MAGIC_DATA4) && // overwrite by verify_addr4
-			(readl(verify_addr2) == MAGIC_DATA2) &&
-			(readl(verify_addr3) == MAGIC_DATA3) &&
-			(readl(verify_addr4) == MAGIC_DATA4))
-			return 0;
-	}
-
-	return -1;
-}
-
-int setup_ddr_addrmap(void)
-{
-	unsigned long boundary = (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB;
-
-	// verify data accessing result firstly
-	writel(MAGIC_DATA, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
-	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
-	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA) {
-		printf("ddr rw test failed\n");
-		goto addrmap_err;
-	}
-	writel(MAGIC_DATA2, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
-	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
-	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA2) {
-		printf("ddr rw test failed\n");
-		goto addrmap_err;
-	}
-
-	// try to find memory boundary
-	while (boundary >= (unsigned long)MINIMAL_DDR_DENSITY_MB * UNIT_MB) {
-		if (query_ddr_boundary(boundary) == 0) {
-			clear_ddr_pmp();
-			fixup_ddr_addrmap(boundary);
-			setup_ddr_pmp();
-			if (boundary_verify(boundary) == 0) {
-				gd->ram_size = boundary;
-				printf("found ddr boundary <0x%lx>\n", boundary);
-				return 0;
-			}
-		}
-		boundary = boundary >> 1;
-	}
-
-	gd->ram_size = get_ddr_density();
-addrmap_err:
-	printf("failed to setup ddr addrmap\n");
-	return -1;
-}
-#endif
-
 void cpu_performance_enable(void)
 {
 #define CSR_MHINT2_E	0x7cc
 #define CSR_MHINT4	0x7ce
 	csr_write(CSR_SMPEN, 0x1);
-	csr_write(CSR_MCCR2, 0xe2490009);
-	csr_write(CSR_MXSTATUS, 0x638000);
-	csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
-	// FIXME: Clear bit[12] to disable L0BTB.
-	csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
 	// FIXME set mhint2[22] to enable core icg en
 	csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x420000);
 	csr_write(CSR_MHINT4, csr_read(CSR_MHINT4) | 0x410);
+	csr_write(CSR_MCCR2, 0xe2490009);
+	// FIXME: Clear bit[12] to disable L0BTB.
+	csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
+	csr_write(CSR_MXSTATUS, 0x638000);
+	csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
+	mdelay(50); // workaround
 }
 
 static int bl1_img_have_head(unsigned long img_src_addr)
@@ -489,9 +372,9 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 
 #ifdef CONFIG_PMIC_VOL_INIT
-	ret = aon_local_init();
+	ret = pmic_ddr_regu_init();
 	if (ret) {
-		printf("%s aon local init failed %d \n",__func__,ret);
+		printf("%s pmic init failed %d \n",__func__,ret);
 		hang();
 	}
 
@@ -506,24 +389,15 @@ void board_init_f(ulong dummy)
 		printf("%s set apcpu voltage failed \n",__func__);
 		hang();
 	}
+
 #endif
 	ddr_clk_config(0);
-#ifdef CONFIG_RV_BOOK
-	cpu_clk_config(750000000);
-#else
 	cpu_clk_config(0);
-#endif
 
 	init_ddr();
 	setup_ddr_scramble();
 	setup_ddr_parity();
 	setup_ddr_pmp();
-#ifdef CONFIG_FIXUP_MEMORY_REGION
-	setup_ddr_addrmap();
-#else
-	// update ram_size from board config
-	gd->ram_size = get_ddr_density();
-#endif
 
 	printf("ddr initialized, jump to uboot\n");
 	light_board_init_r(NULL, 0);

board/thead/light-c910/sys_clk.c

@@ -20,106 +20,12 @@
 #define LIGHT_APSYS_RSTGEN_ADDRBASE	0xffff015000
 #define LIGHT_DPU_CLOCK_GATING_CTRL0	0xffef601A28
 #define LIGHT_DPU_CLOCK_GATING_CTRL1    0xffef601A2C
-#ifdef CONFIG_RV_BOOK
-#define LIGHT_CPU_PLL_IDX(x)            (x)
-#endif
 
 void show_sys_clk(void)
 {
 	/* Do nothing for FPGA */
 }
 
-#ifdef CONFIG_RV_BOOK
-
-static int _light_get_pllid(void)
-{
-	unsigned int val;
-	int ret;
-	val = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
-	if(val & 0x1)
-		ret = LIGHT_CPU_PLL_IDX(1);
-	else
-		ret = LIGHT_CPU_PLL_IDX(0);
-	return ret;
-}
-
-void update_cpu_freq(uint32_t val)
-{
-	if(_light_get_pllid() == LIGHT_CPU_PLL_IDX(0))
-	{
-        /* update cpupll1*/
-		writel(0x20000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
-		writel(val, (void *)LIGHT_APCLK_ADDRBASE + 0x10);
-		writel(0x23000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
-		udelay(3);
-		writel(0x03000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
-		readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
-		readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
-		while(!(readl((void *)LIGHT_APCLK_ADDRBASE + 0x80) & 0x10));
-		udelay(11);
-	}else{
-        /* update cpupll0*/
-		writel(0x20000000, (void *)LIGHT_APCLK_ADDRBASE + 0x04);
-		writel(val, (void *)LIGHT_APCLK_ADDRBASE + 0x00);
-		writel(0x23000000, (void *)LIGHT_APCLK_ADDRBASE + 0x04);
-		udelay(3);
-		writel(0x03000000, (void *)LIGHT_APCLK_ADDRBASE + 0x04);
-		readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
-		readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
-		while(!(readl((void *)LIGHT_APCLK_ADDRBASE + 0x80) & 0x02));
-		udelay(11);
-    }
-}
-
-void cpu_clk_config(int32_t cpu_freq)
-{
-#ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910 /* for sillicon */
-       unsigned int tmp;
-
-    switch(cpu_freq){
-        case 750000000:
-            {
-               /* 4. update c910_cclk to 750Mhz */
-            update_cpu_freq(0x1407d01);
-               /* config bus: cpu clk ratio to 1:1 */
-               writel((readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
-               writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
-               writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
-            printf("cpu frequency to 750\n");
-        }
-        break;
-        case 1500000000:
-            {
-               /* 4. update c910_cclk to 1.5Ghz */
-            update_cpu_freq(0x01207d01);
-               /* config bus: cpu clk ratio to 1:2 */
-               writel((readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x7<<8))) | (0x1<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
-               writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
-               writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
-            printf("cpu frequency to 1500\n");
-            }
-        break;
-        default:
-            return;
-    }
-        if(_light_get_pllid() == LIGHT_CPU_PLL_IDX(0))
-        {
-               /* switch c910_cclk to cpu_pll1_foutpostdiv */
-               tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
-               tmp |= 0x1;
-               writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x100);
-        }else
-        {
-               /* switch c910_cclk to cpu_pll0_foutpostdiv */
-               tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
-               tmp &= ~0x1;
-               writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x100);
-        }
-       udelay(1);
-#endif
-}
-
-#else
 void cpu_clk_config(uint32_t cpu_freq)
 {
 #ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910 /* for sillicon */
@@ -148,7 +54,6 @@ void cpu_clk_config(uint32_t cpu_freq)
 	udelay(1);
 #endif
 }
-#endif
 
 void sys_clk_config(void)
 {
@@ -431,24 +336,6 @@ void sys_clk_config(void)
 #endif
 }
 
-#ifndef CONFIG_SPL_BUILD
-static int cpu_switch_freq(cmd_tbl_t *cmdtp, int flag, int argc,
-                      char * const argv[])
-{
-    cpu_clk_config(1500000000);
-    return 0;
-}
-
-U_BOOT_CMD(
-        cpufreq_switch,
-        2,
-        0,
-        cpu_switch_freq,
-        "switch cpu freq to highest",
-        ""
-);
-#endif
-
 void ddr_clk_config(int ddr_freq)
 {
 	/* Do nothing for FPGA */

cmd/Kconfig

@@ -375,6 +375,18 @@ config CMD_FDT
 	help
 	  Do FDT related setup before booting into the Operating System.
 
+config SUPPORT_EXTENSION_SCAN
+	bool
+
+config CMD_EXTENSION
+	bool "Extension board management command"
+	select CMD_FDT
+	depends on SUPPORT_EXTENSION_SCAN
+	help
+	  Enables the "extension" command, which allows to detect
+	  extension boards connected to the system, and apply
+	  corresponding Device Tree overlays.
+
 config CMD_GO
 	bool "go"
 	default y

cmd/Makefile

@@ -48,6 +48,7 @@ ifdef CONFIG_POST
 obj-$(CONFIG_CMD_DIAG) += diag.o
 endif
 obj-$(CONFIG_CMD_DTIMG) += dtimg.o
+obj-$(CONFIG_CMD_EXTENSION) += extension_board.o
 obj-$(CONFIG_CMD_ECHO) += echo.o
 obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
 obj-$(CONFIG_CMD_EEPROM) += eeprom.o
@@ -137,7 +138,6 @@ obj-$(CONFIG_CMD_TPM) += tpm-common.o
 obj-$(CONFIG_CMD_TPM_V1) += tpm-v1.o
 obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
 obj-$(CONFIG_CMD_TPM_V2) += tpm-v2.o
-obj-$(CONFIG_CMD_MEASURED_BOOT) += mboot.o
 obj-$(CONFIG_CMD_CROS_EC) += cros_ec.o
 obj-$(CONFIG_CMD_TSI148) += tsi148.o
 obj-$(CONFIG_CMD_UBI) += ubi.o

cmd/bootandroid.c

@@ -237,15 +237,9 @@ static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start
 			if (ramdisk_entry->ramdisk_type != VENDOR_RAMDISK_TYPE_RECOVERY) {
 				continue;
 			}
-			printf("find recovery from ramdisk table.\n");
+			printf("find recovery from ramdisk table.");
 			int ramdisk_start = env_get_hex(ENV_RAMDISK_ADDR, DEFAULT_RAMDISK_ADDR);
 			int recovery_ramdisk_offset = vendor_boot_pagesize * o + ramdisk_entry->ramdisk_offset;
-
-			printf("ramdisk_start:%x, ramdisk_size:%x, dtb_start:%x\n", ramdisk_start, ramdisk_entry->ramdisk_size, dtb_start);
-			if (ramdisk_start + ramdisk_entry->ramdisk_size > dtb_start) {
-				printf("ramdisk space are overlaped !!!\n");
-			}
-
 			memcpy((void *)(uint64_t)ramdisk_start, vendor_boot_data + recovery_ramdisk_offset,
 													 ramdisk_entry->ramdisk_size);//ramdisk
 			//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
@@ -298,10 +292,10 @@ static void prepare_loaded_parttion_data(const uint8_t* data, bool isRecovery)
 		printf("Boot image kernel_start:%x, kernel_offset:%x, kernel_size:%d\n", kernel_start, kernel_offset, hdr->kernel_size);
 		printf("Boot image ramdisk_start:%x, ramdisk_offset:%x, ramdisk_size:%d\n", ramdisk_start, ramdisk_offset, hdr->ramdisk_size);
 		printf("Boot image page_size:%d\n", hdr->page_size);
-		printf("dtb_start:%x, dtb_offset:%x, dtb_size:%d\n", dtb_start, dtb_offset, hdr->dtb_size);
+		printf("dtb_offset:%x, dtb_size:%d\n", dtb_offset, hdr->dtb_size);
 
-		if (kernel_start + hdr->kernel_size > ramdisk_start || kernel_start + hdr->kernel_size > dtb_start || ramdisk_start + hdr->ramdisk_size > dtb_start) {
-			printf("boot.img kernel space and ramdisk space are overlaped !!!\n");
+ 		if (kernel_start + hdr->kernel_size > ramdisk_start || kernel_start + hdr->kernel_size > dtb_start) {
+			printf("boot.img kernel space and ramdis space are overlaped !!!\n");
 		} else {
 			memcpy((void *)(uint64_t)kernel_start, data + kernel_offset, hdr->kernel_size);
 			if (!isRecovery) {

cmd/booti.c

@@ -118,7 +118,7 @@ U_BOOT_CMD(
 
 #endif
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
 #if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 extern int light_secboot(int argc, char * const argv[]);
 #endif
@@ -137,91 +137,6 @@ U_BOOT_CMD(
 	"vimage addr imgname[[tee/tf]	- verify specifed image resides in addr\n"
 );
 
-/* check whether partition numbers are consistent with the slot suffix */
-static int do_light_bootab(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
-	char *slot_suffix = env_get("slot_suffix");
-	int teepart = env_get_hex("mmcteepart", 3);
-
-	struct disk_partition part_info;
-	struct blk_desc *dev_desc;
-	int part = 0;
-
-        dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
-	if (dev_desc == NULL) {
-		printf("Failed to find MMC device\n");
-		return 1;
-	}
-
-	if ((strcmp(slot_suffix, "a") == 0) && (teepart != 3)) {
-		part = part_get_info_by_name(dev_desc, "boot_a", &part_info);
-		if (part < 0) {
-			printf("Failed to find MMC device\n");
-			return 1;
-		}
-		env_set_hex("mmcbootpart", part);
-
-		part = part_get_info_by_name(dev_desc, "tee_a", &part_info);
-		if (part < 0) {
-			printf("Failed to find MMC device\n");
-			return 1;
-		}
-		env_set_hex("mmcteepart", part);
-
-		part = part_get_info_by_name(dev_desc, "sbmeta_a", &part_info);
-		if (part < 0) {
-			printf("Failed to find MMC device\n");
-			return 1;
-		}
-		env_set_hex("mmcsbmetapart", part);
-
-		part = part_get_info_by_name(dev_desc, "root_a", &part_info);
-		if (part < 0) {
-			printf("root AB partition is not enabled\n");
-		} else {
-			env_set_hex("mmcpart", part);
-		}
-
-		run_command("env save", 0);
-	} else if ((strcmp(slot_suffix, "b") == 0) && (teepart != 10)) {
-		part = part_get_info_by_name(dev_desc, "boot_b", &part_info);
-		if (part < 0) {
-			printf("Failed to find MMC device\n");
-			return 1;
-		}
-		env_set_hex("mmcbootpart", part);
-
-		part = part_get_info_by_name(dev_desc, "tee_b", &part_info);
-		if (part < 0) {
-			printf("Failed to find MMC device\n");
-			return 1;
-		}
-		env_set_hex("mmcteepart", part);
-
-		part = part_get_info_by_name(dev_desc, "sbmeta_b", &part_info);
-		if (part < 0) {
-			printf("Failed to find MMC device\n");
-			return 1;
-		}
-		env_set_hex("mmcsbmetapart", part);
-
-		part = part_get_info_by_name(dev_desc, "root_b", &part_info);
-		if (part < 0) {
-			printf("root AB partition is not enabled\n");
-		} else {
-			env_set_hex("mmcpart", part);
-		}
-		run_command("env save", 0);
-	}
-	printf("current active slot is:%s\n", slot_suffix);
-	return CMD_RET_SUCCESS;
-}
-
-U_BOOT_CMD(
-	light_bootab, CONFIG_SYS_MAXARGS, 1, do_light_bootab,
-	"Light A/B updates",
-	NULL
-);
-
 #endif
 
 #endif

cmd/extension_board.c

@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <extension_board.h>
+#include <mapmem.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+static LIST_HEAD(extension_list);
+
+static int extension_apply(struct extension *extension)
+{
+	char *overlay_cmd;
+	ulong extrasize, overlay_addr;
+	struct fdt_header *blob;
+
+	if (!working_fdt) {
+		printf("No FDT memory address configured. Please configure\n"
+		       "the FDT address via \"fdt addr <address>\" command.\n");
+		return CMD_RET_FAILURE;
+	}
+
+	overlay_cmd = env_get("extension_overlay_cmd");
+	if (!overlay_cmd) {
+		printf("Environment extension_overlay_cmd is missing\n");
+		return CMD_RET_FAILURE;
+	}
+
+	overlay_addr = env_get_hex("extension_overlay_addr", 0);
+	if (!overlay_addr) {
+		printf("Environment extension_overlay_addr is missing\n");
+		return CMD_RET_FAILURE;
+	}
+
+	env_set("extension_overlay_name", extension->overlay);
+	if (run_command(overlay_cmd, 0) != 0)
+		return CMD_RET_FAILURE;
+
+	extrasize = env_get_hex("filesize", 0);
+	if (!extrasize)
+		return CMD_RET_FAILURE;
+
+	fdt_shrink_to_minimum(working_fdt, extrasize);
+
+	blob = map_sysmem(overlay_addr, 0);
+	if (!fdt_valid(&blob))
+		return CMD_RET_FAILURE;
+
+	/* apply method prints messages on error */
+	if (fdt_overlay_apply_verbose(working_fdt, blob))
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_extension_list(struct cmd_tbl *cmdtp, int flag,
+			     int argc, char *const argv[])
+{
+	int i = 0;
+	struct extension *extension;
+
+	if (list_empty(&extension_list)) {
+		printf("No extension registered - Please run \"extension scan\"\n");
+		return CMD_RET_SUCCESS;
+	}
+
+	list_for_each_entry(extension, &extension_list, list) {
+		printf("Extension %d: %s\n", i++, extension->name);
+		printf("\tManufacturer: \t\t%s\n", extension->owner);
+		printf("\tVersion: \t\t%s\n", extension->version);
+		printf("\tDevicetree overlay: \t%s\n", extension->overlay);
+		printf("\tOther information: \t%s\n", extension->other);
+	}
+	return CMD_RET_SUCCESS;
+}
+
+static int do_extension_scan(struct cmd_tbl *cmdtp, int flag,
+			     int argc, char *const argv[])
+{
+	struct extension *extension, *next;
+	int extension_num;
+
+	list_for_each_entry_safe(extension, next, &extension_list, list) {
+		list_del(&extension->list);
+		free(extension);
+	}
+	extension_num = extension_board_scan(&extension_list);
+
+	if (extension_num < 0)
+		return CMD_RET_FAILURE;
+
+	printf("Found %d extension board(s).\n", extension_num);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_extension_apply(struct cmd_tbl *cmdtp, int flag,
+			      int argc, char *const argv[])
+{
+	struct extension *extension = NULL;
+	struct list_head *entry;
+	int i = 0, extension_id, ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (strcmp(argv[1], "all") == 0) {
+		list_for_each_entry(extension, &extension_list, list) {
+			ret = extension_apply(extension);
+			if (ret != CMD_RET_SUCCESS)
+				break;
+		}
+	} else {
+		extension_id = simple_strtol(argv[1], NULL, 10);
+		list_for_each(entry, &extension_list) {
+			if (i == extension_id) {
+				extension = list_entry(entry, struct extension,  list);
+				break;
+			}
+			i++;
+		}
+
+		if (!extension) {
+			printf("Wrong extension number\n");
+			return CMD_RET_FAILURE;
+		}
+
+		ret = extension_apply(extension);
+	}
+
+	return ret;
+}
+
+static struct cmd_tbl cmd_extension[] = {
+	U_BOOT_CMD_MKENT(scan, 1, 1, do_extension_scan, "", ""),
+	U_BOOT_CMD_MKENT(list, 1, 0, do_extension_list, "", ""),
+	U_BOOT_CMD_MKENT(apply, 2, 0, do_extension_apply, "", ""),
+};
+
+static int do_extensionops(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	struct cmd_tbl *cp;
+
+	/* Drop the extension command */
+	argc--;
+	argv++;
+
+	cp = find_cmd_tbl(argv[0], cmd_extension, ARRAY_SIZE(cmd_extension));
+	if (cp)
+		return cp->cmd(cmdtp, flag, argc, argv);
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(extension, 3, 1, do_extensionops,
+	"Extension board management sub system",
+	"scan - scan plugged extension(s) board(s)\n"
+	"extension list - lists available extension(s) board(s)\n"
+	"extension apply <extension number|all> - applies DT overlays corresponding to extension boards\n"
+);

cmd/fdt.c

@@ -27,7 +27,6 @@
  */
 DECLARE_GLOBAL_DATA_PTR;
 
-static int fdt_valid(struct fdt_header **blobp);
 static int fdt_parse_prop(char *const*newval, int count, char *data, int *len);
 static int fdt_print(const char *pathp, char *prop, int depth);
 static int is_printable_string(const void *data, int len);
@@ -732,54 +731,6 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 /****************************************************************************/
 
-/**
- * fdt_valid() - Check if an FDT is valid. If not, change it to NULL
- *
- * @blobp: Pointer to FDT pointer
- * @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
- */
-static int fdt_valid(struct fdt_header **blobp)
-{
-	const void *blob = *blobp;
-	int err;
-
-	if (blob == NULL) {
-		printf ("The address of the fdt is invalid (NULL).\n");
-		return 0;
-	}
-
-	err = fdt_check_header(blob);
-	if (err == 0)
-		return 1;	/* valid */
-
-	if (err < 0) {
-		printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
-		/*
-		 * Be more informative on bad version.
-		 */
-		if (err == -FDT_ERR_BADVERSION) {
-			if (fdt_version(blob) <
-			    FDT_FIRST_SUPPORTED_VERSION) {
-				printf (" - too old, fdt %d < %d",
-					fdt_version(blob),
-					FDT_FIRST_SUPPORTED_VERSION);
-			}
-			if (fdt_last_comp_version(blob) >
-			    FDT_LAST_SUPPORTED_VERSION) {
-				printf (" - too new, fdt %d > %d",
-					fdt_version(blob),
-					FDT_LAST_SUPPORTED_VERSION);
-			}
-		}
-		printf("\n");
-		*blobp = NULL;
-		return 0;
-	}
-	return 1;
-}
-
-/****************************************************************************/
-
 /*
  * Parse the user's input, partially heuristic.  Valid formats:
  * <0x00112233 4 05>	- an array of cells.  Numbers follow standard

cmd/mboot.c

@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2018 Bootlin
- * Author: Miquel Raynal <miquel.raynal@bootlin.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <log.h>
-#include <mapmem.h>
-#include <tpm-common.h>
-#include <tpm-v2.h>
-#include <env.h>
-#include <env_internal.h>
-#include "tpm-user-utils.h"
-#include "sec_library.h"
-
-enum mboot_type {
-	UBOOT_IMAGE = 0,
-	KERNEL_IMAGE,
-	PARTITIONS_STR,
-	MBOOT_TYPE_MAX,
-};
-enum pcr_index {
-	PCR_0 = 0,
-	PCR_1,
-	PCR_2,
-	PCR_3,
-	PCR_4,
-	PCR_5,
-	PCR_6,
-	PCR_7,
-};
-static uint8_t image_digest[32] __attribute__((aligned(64))) = { 0 };
-
-#define CHECK_RET_WITH_RET(x, ret)                                                                 \
-    do {                                                                                           \
-        if (!(x)) {                                                                                \
-            return ret;                                                                            \
-        }                                                                                          \
-    } while (0)
-
-static uint32_t hash_image_sha256(long image_addr, size_t size, void *digest, uint32_t *digest_len)
-{
-	uint32_t ret;
-	sc_sha_t sha;
-	sc_sha_context_t ctx;
-
-	CHECK_RET_WITH_RET(ret = csi_sec_library_init(), ret);
-	CHECK_RET_WITH_RET(ret = sc_sha_init(&sha, 0), ret);
-	CHECK_RET_WITH_RET(ret = sc_sha_start(&sha, &ctx, SC_SHA_MODE_256), ret);
-	CHECK_RET_WITH_RET(ret = sc_sha_trans_config(&sha, &ctx, SC_SHA_DMA_MODE), ret);
-	CHECK_RET_WITH_RET(ret = sc_sha_update(&sha, &ctx, (void *)image_addr, size), ret);
-	CHECK_RET_WITH_RET(ret = sc_sha_finish(&sha, &ctx, digest, digest_len), ret);
-
-	return SC_OK;
-}
-
-static int do_measured_boot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	struct udevice *dev;
-	struct tpm_chip_priv *priv;
-	uint32_t index, type;
-	uint32_t rc;
-	int ret;
-	long image_addr = 0;
-	size_t image_size = 0;
-	uint32_t image_digest_len = 0;
-	char *partitions_str = NULL;
-
-	if (argc != 1)
-		return CMD_RET_USAGE;
-
-	ret = get_tpm(&dev);
-	if (ret)
-		return ret;
-
-	tpm_init(dev); /* Initialization TPM2 chip */
-	rc = tpm2_startup(dev, TPM2_SU_CLEAR); /* Startup TPM2 chip with mode TPM_ST_CLEAR*/
-	if (rc)
-		report_return_code(rc);
-
-	priv = dev_get_uclass_priv(dev);
-	if (!priv)
-		return -EINVAL;
-
-	for (type = UBOOT_IMAGE; type < MBOOT_TYPE_MAX; type++) {
-		if (type == UBOOT_IMAGE) { /*U-BOOT Image */
-			index = PCR_0;
-			image_addr = CONFIG_SPL_TEXT_BASE;
-			image_size = CONFIG_SPL_MAX_SIZE+CONFIG_SYS_MONITOR_LEN;
-		} else if (type == KERNEL_IMAGE) { /* KERNEL Image */
-			index = PCR_0;
-			image_addr = 0x00200000;
-			if (fs_set_blk_dev("mmc", "0:2", 2))
-				return -EINVAL;
-			if (fs_size("Image", &image_size) < 0)
-				return -EINVAL;
-		} else if (type == PARTITIONS_STR) { /* PARTITIONS */
-			index = PCR_5;
-			partitions_str = env_get("partitions");
-			image_addr = (long)partitions_str;
-			image_size = strlen(partitions_str);
-		}
-
-		rc = hash_image_sha256(image_addr, image_size, image_digest, &image_digest_len);
-		if (rc)
-			return -EINVAL;
-
-		rc = tpm2_pcr_extend(dev, index, image_digest);
-		if (rc)
-			break;
-	}
-
-	return report_return_code(rc);
-}
-
-U_BOOT_CMD(
-	measured_boot, CONFIG_SYS_MAXARGS, 1, do_measured_boot,
-	"extend hash(u-boot), hash(kernel), hash(partitions str) to pcr0 and pcr5",
-	""
-);

cmd/net.c

@@ -458,22 +458,3 @@ U_BOOT_CMD(
 );
 
 #endif  /* CONFIG_CMD_LINK_LOCAL */
-
-/* moved from board_init_r sequence here to save normal boot time */
-static int do_eth_init(cmd_tbl_t *cmdtp, int flag, int argc,
-			char * const argv[])
-{
-	puts("Net:   ");
-	eth_initialize();
-#if defined(CONFIG_RESET_PHY_R)
-	debug("Reset Ethernet PHY\n");
-	reset_phy();
-#endif
-	return 0;
-}
-
-U_BOOT_CMD(
-	eth,	6,	1,	do_eth_init,
-	"eth initialize",
-	""
-);

cmd/pxe_utils.c

@@ -9,6 +9,8 @@
 #include <malloc.h>
 #include <mapmem.h>
 #include <lcd.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
 #include <linux/string.h>
 #include <linux/ctype.h>
 #include <errno.h>
@@ -279,6 +281,9 @@ static void label_destroy(struct pxe_label *label)
 	if (label->fdtdir)
 		free(label->fdtdir);
 
+	if (label->fdtoverlays)
+		free(label->fdtoverlays);
+
 	free(label);
 }
 
@@ -326,6 +331,92 @@ static int label_localboot(struct pxe_label *label)
 	return run_command_list(localcmd, strlen(localcmd), 0);
 }
 
+/*
+ * Loads fdt overlays specified in 'fdtoverlays'.
+ */
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+static void label_boot_fdtoverlay(struct cmd_tbl *cmdtp, struct pxe_label *label)
+{
+	char *fdtoverlay = label->fdtoverlays;
+	struct fdt_header *working_fdt;
+	char *fdtoverlay_addr_env;
+	ulong fdtoverlay_addr;
+	ulong fdt_addr;
+	int err;
+
+	/* Get the main fdt and map it */
+	fdt_addr = simple_strtoul(env_get("fdt_addr_r"), NULL, 16);
+	working_fdt = map_sysmem(fdt_addr, 0);
+	err = fdt_check_header(working_fdt);
+	if (err)
+		return;
+
+	/* Get the specific overlay loading address */
+	fdtoverlay_addr_env = env_get("fdtoverlay_addr_r");
+	if (!fdtoverlay_addr_env) {
+		printf("Invalid fdtoverlay_addr_r for loading overlays\n");
+		return;
+	}
+
+	fdtoverlay_addr = simple_strtoul(fdtoverlay_addr_env, NULL, 16);
+
+	/* Cycle over the overlay files and apply them in order */
+	do {
+		struct fdt_header *blob;
+		char *overlayfile;
+		char *end;
+		int len;
+
+		/* Drop leading spaces */
+		while (*fdtoverlay == ' ')
+			++fdtoverlay;
+
+		/* Copy a single filename if multiple provided */
+		end = strstr(fdtoverlay, " ");
+		if (end) {
+			len = (int)(end - fdtoverlay);
+			overlayfile = malloc(len + 1);
+			strncpy(overlayfile, fdtoverlay, len);
+			overlayfile[len] = '\0';
+		} else
+			overlayfile = fdtoverlay;
+
+		if (!strlen(overlayfile))
+			goto skip_overlay;
+
+		/* Load overlay file */
+		err = get_relfile_envaddr(cmdtp, overlayfile,
+					  "fdtoverlay_addr_r");
+		if (err < 0) {
+			printf("Failed loading overlay %s\n", overlayfile);
+			goto skip_overlay;
+		}
+
+		/* Resize main fdt */
+		fdt_shrink_to_minimum(working_fdt, 8192);
+
+		blob = map_sysmem(fdtoverlay_addr, 0);
+		err = fdt_check_header(blob);
+		if (err) {
+			printf("Invalid overlay %s, skipping\n",
+			       overlayfile);
+			goto skip_overlay;
+		}
+
+		err = fdt_overlay_apply_verbose(working_fdt, blob);
+		if (err) {
+			printf("Failed to apply overlay %s, skipping\n",
+			       overlayfile);
+			goto skip_overlay;
+		}
+
+skip_overlay:
+		if (end)
+			free(overlayfile);
+	} while ((fdtoverlay = strstr(fdtoverlay, " ")));
+}
+#endif
+
 /*
  * Boot according to the contents of a pxe_label.
  *
@@ -520,6 +611,11 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 				       label->name);
 				goto cleanup;
 			}
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+			if (label->fdtoverlays)
+				label_boot_fdtoverlay(cmdtp, label);
+#endif
 		} else {
 			bootm_argv[3] = NULL;
 		}
@@ -577,6 +673,7 @@ enum token_type {
 	T_INCLUDE,
 	T_FDT,
 	T_FDTDIR,
+	T_FDTOVERLAYS,
 	T_ONTIMEOUT,
 	T_IPAPPEND,
 	T_BACKGROUND,
@@ -611,6 +708,7 @@ static const struct token keywords[] = {
 	{"fdt", T_FDT},
 	{"devicetreedir", T_FDTDIR},
 	{"fdtdir", T_FDTDIR},
+	{"fdtoverlays", T_FDTOVERLAYS},
 	{"ontimeout", T_ONTIMEOUT,},
 	{"ipappend", T_IPAPPEND,},
 	{"background", T_BACKGROUND,},
@@ -1043,6 +1141,11 @@ static int parse_label(char **c, struct pxe_menu *cfg)
 				err = parse_sliteral(c, &label->fdtdir);
 			break;
 
+		case T_FDTOVERLAYS:
+			if (!label->fdtoverlays)
+				err = parse_sliteral(c, &label->fdtoverlays);
+			break;
+
 		case T_LOCALBOOT:
 			label->localboot = 1;
 			err = parse_integer(c, &label->localboot_val);

cmd/pxe_utils.h

@@ -43,6 +43,7 @@ struct pxe_label {
 	char *initrd;
 	char *fdt;
 	char *fdtdir;
+	char *fdtoverlays;
 	int ipappend;
 	int attempted;
 	int localboot;

common/fdt_support.c

@@ -1822,3 +1822,49 @@ int fdt_overlay_apply_verbose(void *fdt, void *fdto)
 	return err;
 }
 #endif
+
+/**
+ * fdt_valid() - Check if an FDT is valid. If not, change it to NULL
+ *
+ * @blobp: Pointer to FDT pointer
+ * @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
+ */
+int fdt_valid(struct fdt_header **blobp)
+{
+	const void *blob = *blobp;
+	int err;
+
+	if (!blob) {
+		printf("The address of the fdt is invalid (NULL).\n");
+		return 0;
+	}
+
+	err = fdt_check_header(blob);
+	if (err == 0)
+		return 1;	/* valid */
+
+	if (err < 0) {
+		printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
+		/*
+		 * Be more informative on bad version.
+		 */
+		if (err == -FDT_ERR_BADVERSION) {
+			if (fdt_version(blob) <
+			    FDT_FIRST_SUPPORTED_VERSION) {
+				printf(" - too old, fdt %d < %d",
+				       fdt_version(blob),
+				       FDT_FIRST_SUPPORTED_VERSION);
+			}
+			if (fdt_last_comp_version(blob) >
+			    FDT_LAST_SUPPORTED_VERSION) {
+				printf(" - too new, fdt %d > %d",
+				       fdt_version(blob),
+				       FDT_LAST_SUPPORTED_VERSION);
+			}
+		}
+		printf("\n");
+		*blobp = NULL;
+		return 0;
+	}
+	return 1;
+}

common/image-fdt.c

@@ -416,7 +416,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 				 * FDT blob
 				 */
 				debug("*  fdt: raw FDT blob\n");
-				debug("## Flattened Device Tree blob at %08lx\n",
+				printf("## Flattened Device Tree blob at %08lx\n",
 				       (long)fdt_addr);
 			}
 			break;
@@ -425,7 +425,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 			goto no_fdt;
 		}
 
-		debug("   Booting using the fdt blob at %#08lx\n", fdt_addr);
+		printf("   Booting using the fdt blob at %#08lx\n", fdt_addr);
 		fdt_blob = map_sysmem(fdt_addr, 0);
 	} else if (images->legacy_hdr_valid &&
 			image_check_type(&images->legacy_hdr_os_copy,

common/spl/spl.c

@@ -735,6 +735,30 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	jump_to_image_no_args(&spl_image);
 }
 
+static void print_ruyisdk_logo(void)
+{
+	//  _____             _  _____ _____  _  __
+	// |  __ \           (_)/ ____|  __ \| |/ /
+	// | |__) |   _ _   _ _| (___ | |  | | ' / 
+	// |  _  / | | | | | | |\___ \| |  | |  <  
+	// | | \ \ |_| | |_| | |____) | |__| | . \ 
+	// |_|  \_\__,_|\__, |_|_____/|_____/|_|\_\
+	//               __/ |                     
+	//              |___/                      
+
+	printf("-----------------------------------------\n");
+	printf("  _____             _  _____ _____  _  __\n");
+	printf(" |  __ \\           (_)/ ____|  __ \\| |/ /\n");
+	printf(" | |__) |   _ _   _ _| (___ | |  | | ' / \n");
+	printf(" |  _  / | | | | | | |\\___ \\| |  | |  <  \n");
+	printf(" | | \\ \\ |_| | |_| | |____) | |__| | . \\ \n");
+	printf(" |_|  \\_\\__,_|\\__, |_|_____/|_____/|_|\\_\\\n");
+	printf("               __/ |                     \n");
+	printf("              |___/                      \n");
+	printf("                    -- Presented by ISCAS\n");
+	printf("-----------------------------------------\n");
+}
+
 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 /*
  * This requires UART clocks to be enabled.  In order for this to work the
@@ -748,6 +772,8 @@ void preloader_console_init(void)
 
 	gd->have_console = 1;
 
+	print_ruyisdk_logo();
+
 #if CONFIG_IS_ENABLED(BANNER_PRINT)
 	puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - "
 	     U_BOOT_TIME " " U_BOOT_TZ ")\n");

configs/light_a_val_android_defconfig

@@ -18,7 +18,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_a_val_defconfig

@@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_A=y
 # CONFIG_THEAD_PLIC is not set
 # CONFIG_THEAD_LIGHT_TIMER is not set
 # CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
@@ -17,22 +18,21 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_SYS_PROMPT="Light VAL-A# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MTD=y
-CONFIG_CMD_USB=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_SPI_NAND=y
@@ -77,17 +78,16 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
-# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="light-a-val.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -107,5 +107,4 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_a_val_sec_defconfig

@@ -18,14 +18,12 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 # CONFIG_TPM is not set
 # CONFIG_TPM_Z32H330TC_SPI is not set
 # CONFIG_TPM_V2 is not set
 # CONFIG_CMD_TPM_V2 is not set
 # CONFIG_CMD_TPM is not set
 # CONFIG_CMD_TPM_TEST is not set
-# CONFIG_CMD_MEASURED_BOOT is not set
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -36,6 +34,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -80,9 +79,6 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -100,7 +96,6 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
-CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
@@ -113,7 +108,3 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y
-# CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION is not set
-# CONFIG_FASTBOOT_ECIES_AUTH is not set

configs/light_ant_ref_android_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_ant_ref_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_ant_ref_sec_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_b_product_android_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_b_product_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -105,5 +104,3 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y

configs/light_b_product_sec_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -105,7 +104,3 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y
-# CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION is not set
-# CONFIG_FASTBOOT_ECIES_AUTH is not set

configs/light_beagle_android_defconfig

@@ -19,7 +19,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -115,4 +114,4 @@ CONFIG_ANDROID_AB=y
 CONFIG_CMD_AB_SELECT=y
 CONFIG_XBC=y
 CONFIG_BOARD_RNG_SEED=y
-CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_SPL_TEXT_BASE=0xffe0000800

configs/light_beagle_defconfig

@@ -6,39 +6,41 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
 CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
-# CONFIG_THEAD_PLIC is not set
-# CONFIG_THEAD_LIGHT_TIMER is not set
-# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+CONFIG_DDR_BOARD_CONFIG=y
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/light-beagle.dtb"
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
-CONFIG_DDR_LP4X_3733_SINGLERANK=y
-# CONFIG_DDR_LP4_3733_DUALRANK is not set
-CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_SYS_PROMPT="Light AHead# "
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
-CONFIG_DDR_PRBS_TEST=n
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_DEFAULT_DEVICE_TREE="light-beagle"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_UDP_FUNCTION_FASTBOOT=y
@@ -47,11 +49,12 @@ CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
-CONFIG_DWAPB_GPIO=y
 # CONFIG_MMC_SPI is not set
-CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
@@ -59,19 +62,21 @@ CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_SNPS=y
 CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_SPI_NAND=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_ETH_DESIGNWARE=y
 CONFIG_PHY_REALTEK=y
 CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
@@ -82,25 +87,15 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
-# CONFIG_SPL_USE_TINY_PRINTF is not set
-# CONFIG_EFI_LOADER is not set
-# CONFIG_LIGHT_SEC_BOOT is not set
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_DM_VIDEO=y
-CONFIG_PHY=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CMD_BMP=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_DM_PCA953X=y
-CONFIG_VIDEO_VS_DPU=y
+CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_VS_DPU=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
-CONFIG_VIDEO_DW_DSI_HOST=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_PMIC_VOL_INIT=y
-CONFIG_DDR_REGU_0V6=600000
-CONFIG_DDR_REGU_0V8=800000
-CONFIG_DDR_REGU_1V1=1100000
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_16g_defconfig

@@ -1,4 +1,3 @@
-CONFIG_RV_BOOK=y
 CONFIG_RISCV=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_ENV_SIZE=0x20000
@@ -7,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
-CONFIG_TARGET_LIGHT_FM_C910_RVBOOK=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
 # CONFIG_THEAD_PLIC is not set
 # CONFIG_THEAD_LIGHT_TIMER is not set
 # CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
@@ -19,11 +18,11 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_SYS_PROMPT="Light LPI4A 16G# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -38,7 +37,7 @@ CONFIG_DDR_PRBS_TEST=n
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="th1520-rvbook"
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_CLK=y
@@ -65,6 +64,7 @@ CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_SPI_NAND=y
@@ -84,9 +84,11 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-16gb.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -98,7 +100,6 @@ CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
 CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
-CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -107,24 +108,4 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_TPM=y
-CONFIG_TPM_V2=y
-CONFIG_TPM_Z32H330TC_SPI=y
-CONFIG_CMD_TPM=y
-CONFIG_CMD_TPM_V2=y
-CONFIG_CMD_TPM_TEST=y
-CONFIG_DM_CHARGE_DISPLAY=y
-CONFIG_CHARGE_ANIMATION=y
-CONFIG_DM_FUEL_GAUGE=y
-CONFIG_POWER_FG_CW201X=y
-CONFIG_CHARGER_BQ25700=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_DM_MCU=y
-CONFIG_MCU_HC32fX=y
-CONFIG_DM_POWER_DELIVERY=y
-CONFIG_TYPEC_TCPM=y
-CONFIG_TYPEC_TCPCI=y
-CONFIG_TYPEC_HUSB311=y
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_android_defconfig

@@ -19,7 +19,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -93,7 +92,7 @@ CONFIG_CMD_BMP=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_JD9365DA=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y

configs/light_lpi4a_cluster_16g_defconfig

@@ -1,4 +1,3 @@
-CONFIG_RV_BOOK=y
 CONFIG_RISCV=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_ENV_SIZE=0x20000
@@ -7,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
 # CONFIG_THEAD_PLIC is not set
 # CONFIG_THEAD_LIGHT_TIMER is not set
 # CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
@@ -18,11 +18,11 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_SYS_PROMPT="LicheeCluster4A 16G # "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -37,7 +37,7 @@ CONFIG_DDR_PRBS_TEST=n
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="th1520-rvbook"
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_CLK=y
@@ -64,6 +64,7 @@ CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_SPI_NAND=y
@@ -83,11 +84,11 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
-
-CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK=y
-CONFIG_LIGHT_SEC_UPGRADE=y
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster-16gb.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -99,7 +100,6 @@ CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
 CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
-CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -108,25 +108,4 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_TPM=y
-CONFIG_TPM_V2=y
-CONFIG_TPM_Z32H330TC_SPI=y
-CONFIG_CMD_TPM=y
-CONFIG_CMD_TPM_V2=y
-CONFIG_CMD_TPM_TEST=y
-CONFIG_DM_CHARGE_DISPLAY=y
-CONFIG_CHARGE_ANIMATION=y
-CONFIG_DM_FUEL_GAUGE=y
-CONFIG_POWER_FG_CW201X=y
-CONFIG_CHARGER_BQ25700=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_DM_MCU=y
-CONFIG_MCU_HC32fX=y
-CONFIG_DM_POWER_DELIVERY=y
-CONFIG_TYPEC_TCPM=y
-CONFIG_TYPEC_TCPCI=y
-CONFIG_TYPEC_HUSB311=y
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y
-CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_cluster_defconfig

@@ -0,0 +1,110 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeCluster4A # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_console_16g_defconfig

@@ -0,0 +1,111 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeConsole4A 16G # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console-16g.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_console_defconfig

@@ -0,0 +1,110 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeConsole4A # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_defconfig

@@ -18,11 +18,10 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_SYS_PROMPT="Light LPI4A# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -33,6 +32,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_SPI_NAND=y
@@ -77,17 +78,16 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -95,13 +95,10 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
-CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
-CONFIG_VIDEO_LCD_JD9365DA=y
-CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -110,6 +107,4 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y
-
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_sec_defconfig

@@ -22,7 +22,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -33,6 +32,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -77,9 +77,6 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -96,13 +93,10 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
-CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
-CONFIG_VIDEO_LCD_JD9365DA=y
-CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -111,7 +105,3 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y
-# CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION is not set
-# CONFIG_FASTBOOT_ECIES_AUTH is not set

configs/light_milkv_meles_defconfig

@@ -0,0 +1,89 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set

configs/light_milkv_meles_dualrank_defconfig

@@ -0,0 +1,90 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y

configs/light_milkv_meles_singlerank_defconfig

@@ -0,0 +1,90 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles-4g.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles 4G# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y

configs/tools-only_defconfig

@@ -6,6 +6,7 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXTENSION is not set
 # CONFIG_CMD_DATE is not set
 CONFIG_OF_CONTROL=y
 CONFIG_OF_HOSTFILE=y

doc/README.pxe

@@ -89,6 +89,9 @@ pxe boot
      fdt_addr - the location of a fdt blob. 'fdt_addr' will be passed to bootm
      command if it is set and 'fdt_addr_r' is not passed to bootm command.
 
+     fdtoverlay_addr_r - location in RAM at which 'pxe boot' will temporarily store
+     fdt overlay(s) before applying them to the fdt blob stored at 'fdt_addr_r'.
+
 pxe file format
 ===============
 The pxe file format is nearly a subset of the PXELINUX file format; see
@@ -148,6 +151,12 @@ kernel <path>	    - if this label is chosen, use tftp to retrieve the kernel
 		      It useful for overlay selection in pxe file
 		      (see: doc/uImage.FIT/overlay-fdt-boot.txt)
 
+fdtoverlays <path> [...] - if this label is chosen, use tftp to retrieve the DT
+                      overlay(s) at <path>. it will be temporarily stored at the
+                      address indicated in the fdtoverlay_addr_r environment variable,
+                      and then applied in the load order to the fdt blob stored at the
+                      address indicated in the fdt_addr_r environment variable.
+
 append <string>	    - use <string> as the kernel command line when booting this
 		      label.
 

doc/usage/extension.rst

@@ -0,0 +1,111 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright 2021, Kory Maincent <kory.maincent@bootlin.com>
+
+U-Boot extension board usage (CONFIG_EXTENSION)
+===============================================
+
+Synopsis
+--------
+
+::
+
+    extension scan
+    extension list
+    extension apply <extension number|all>
+
+Description
+-----------
+
+The "extension" command proposes a generic U-Boot mechanism to detect
+extension boards connected to the HW platform, and apply the appropriate
+Device Tree overlays depending on the detected extension boards.
+
+The "extension" command comes with three sub-commands:
+
+ - "extension scan" makes the generic code call the board-specific
+   extension_board_scan() function to retrieve the list of detected
+   extension boards.
+
+ - "extension list" allows to list the detected extension boards.
+
+ - "extension apply <number>|all" allows to apply the Device Tree
+   overlay(s) corresponding to one, or all, extension boards
+
+The latter requires two environment variables to exist:
+
+ - extension_overlay_addr: the RAM address where to load the Device
+   Tree overlays
+
+ - extension_overlay_cmd: the U-Boot command to load one overlay.
+   Indeed, the location and mechanism to load DT overlays is very setup
+   specific.
+
+In order to enable this mechanism, board-specific code must implement
+the extension_board_scan() function that fills in a linked list of
+"struct extension", each describing one extension board. In addition,
+the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig
+boolean.
+
+Usage example
+-------------
+
+1. Make sure your devicetree is loaded and set as the working fdt tree.
+
+::
+
+    => run loadfdt
+    => fdt addr $fdtaddr
+
+2. Prepare the environment variables
+
+::
+
+    => setenv extension_overlay_addr 0x88080000
+    => setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}'
+
+3. Detect the plugged extension board
+
+::
+
+    => extension scan
+
+4. List the plugged extension board information and the devicetree
+   overlay name
+
+::
+
+    => extension list
+
+5. Apply the appropriate devicetree overlay
+
+For apply the selected overlay:
+
+::
+
+    => extension apply 0
+
+For apply all the overlays:
+
+::
+
+    => extension apply all
+
+Simple extension_board_scan function example
+--------------------------------------------
+
+.. code-block:: c
+
+    int extension_board_scan(struct list_head *extension_list)
+    {
+        struct extension *extension;
+
+        extension = calloc(1, sizeof(struct extension));
+        snprintf(extension->overlay, sizeof(extension->overlay), "overlay.dtbo");
+        snprintf(extension->name, sizeof(extension->name), "extension board");
+        snprintf(extension->owner, sizeof(extension->owner), "sandbox");
+        snprintf(extension->version, sizeof(extension->version), "1.1");
+        snprintf(extension->other, sizeof(extension->other), "Extension board information");
+        list_add_tail(&extension->list, extension_list);
+
+        return 1;
+    }

drivers/Kconfig

@@ -130,8 +130,6 @@ source "drivers/w1-eeprom/Kconfig"
 
 source "drivers/watchdog/Kconfig"
 
-source "drivers/mcu/Kconfig"
-
 config PHYS_TO_BUS
 	bool "Custom physical to bus address mapping"
 	help

drivers/Makefile

@@ -85,9 +85,6 @@ obj-y += misc/
 obj-$(CONFIG_MMC) += mmc/
 obj-$(CONFIG_NVME) += nvme/
 obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/
-ifdef CONFIG_RV_BOOK
-obj-$(CONFIG_DM_POWER_DELIVERY) += power/power_delivery/
-endif
 obj-y += dfu/
 obj-$(CONFIG_PCH) += pch/
 obj-y += phy/allwinner/

drivers/fastboot/Kconfig

@@ -135,14 +135,6 @@ config FASTBOOT_CMD_OEM_FORMAT
 	  relies on the env variable partitions to contain the list of
 	  partitions as required by the gpt command.
 
-config FASTBOOT_CMD_OEM_NV_OPERATION
-	bool "Enable the 'oem nv get/set' command"
-	help
-	  Add support for the "oem get/set" command from a client.
-
-config FASTBOOT_ECIES_AUTH
-	bool "Enabled ecies fastboot auth"
-
 endif # FASTBOOT
 
 endmenu

drivers/fastboot/Makefile

@@ -3,7 +3,5 @@
 obj-y += fb_common.o
 obj-y += fb_getvar.o
 obj-y += fb_command.o
-obj-$(CONFIG_FASTBOOT_ECIES_AUTH) += fb_ecies.o
 obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o
 obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o
-obj-$(CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION) += fb_nv_operation.o

drivers/fastboot/fb_command.c

@@ -45,19 +45,6 @@ static void oem_format(char *, char *);
 static void oem_command(char *, char *);
 int image_have_head(unsigned long img_src_addr);
 
-#if CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION
-void oem_nv_get_proccess(char *cmd_parameter, char *response);
-void oem_nv_set_proccess(char *cmd_parameter, char *response);
-void oem_nv_factory_recovery_process(char *cmd_parameter, char *response);
-static void oem_nv_get(char *cmd_parameter, char *response);
-static void oem_nv_set(char *cmd_parameter, char *response);
-static void oem_fcty(char *cmd_parameter, char *response);
-#endif
-
-#ifdef CONFIG_FASTBOOT_ECIES_AUTH
-int ecies_process_data(uint8_t * data, int data_size,char *response);
-#endif
-
 static const struct {
 	const char *command;
 	void (*dispatch)(char *cmd_parameter, char *response);
@@ -110,20 +97,6 @@ static const struct {
 		.command = "oem command",
 		.dispatch = oem_command,
 	},
-#if CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION
-	[FASTBOOT_COMMAND_OEM_NV_GET] = {
-		.command = "oem nv get",
-		.dispatch = oem_nv_get,
-	},
-	[FASTBOOT_COMMAND_OEM_NV_SET] = {
-		.command = "oem nv set",
-		.dispatch = oem_nv_set,
-	},
-	[FASTBOOT_COMMAND_OEM_FCTY] = {
-		.command = "oem fcty",
-		.dispatch = oem_fcty,
-	},
-#endif
 };
 
 /**
@@ -321,90 +294,7 @@ int check_image_board_id(uint8_t *image_data)
 	return 0;
 }
 
-int hibernate_image_cleaned_flag = 0;
-void clean_hibernate_image_header(char *response)
-{
-	struct blk_desc *dev_desc;
-	disk_partition_t info;
-	if(0x03 == hibernate_image_cleaned_flag) //already erased all
-	{
-		return;
-	}
-	dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
-	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
-		fastboot_fail("invalid mmc device", response);
-		return;
-	}
-	char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096);
-	if(!buf) {
-		printf(" mem alloc for hibernate partition header failed!\n");
-		return;
-	}
-	/* if fastresume partition exists, earse the old image header */
-	if(part_get_info_by_name(dev_desc, "fastresume", &info)) {
-		printf(" find fastresume partition , erase the header:\n");
-		memset(buf,0xff,4096);
-		if(blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf) != 4096/info.blksz)
-		{
-			printf(" fastresume header write failed!\n");
-			hibernate_image_cleaned_flag = 0;
-		}
-		else
-		{
-			hibernate_image_cleaned_flag |= 0x1;
-		}
-	}
-	/* if swap partition exists, earse the old image header */
-	if(part_get_info_by_name(dev_desc, "swap", &info)) {
-		printf(" find swap partition , erase the header:\n");
-		memset(buf,0xff,4096);
-		if(blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf) != 4096/info.blksz)
-		{
-			printf(" swap header write failed!\n");
-			hibernate_image_cleaned_flag = 0;
-		}
-		else
-		{
-			hibernate_image_cleaned_flag |= 0x2;
-		}
-	}
-	free(buf);
-}
-
 #if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
-void fasboot_uboot_write_process(void *buf, char *response)
-{
-	char cmdbuf[32];
-	u32 block_cnt;
-	struct blk_desc *dev_desc;
-	int ret = 0;
-	disk_partition_t info;
-
-	ret = check_image_board_id(buf);
-	if (ret != 0) {
-		fastboot_fail("U-BOOT image does not match the type of BOARD", response);
-		return;
-	}
-
-	dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
-	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
-		fastboot_fail("invalid mmc device", response);
-		return;
-	}
-
-	run_command("mmc partconf 0 1 0 1", 0);
-
-	block_cnt = image_size / BLOCK_SIZE;
-	if (image_size % BLOCK_SIZE) {
-		block_cnt = block_cnt +1;
-	}
-
-	sprintf(cmdbuf, "mmc write 0x%p 0 %x", buf, block_cnt);
-
-	run_command(cmdbuf, 0);
-	run_command("mmc partconf 0 1 0 0", 0);
-}
-
 /**
  * flash() - write the downloaded image to the indicated partition.
  *
@@ -418,10 +308,35 @@ static void flash(char *cmd_parameter, char *response)
 {
 #ifdef THEAD_LIGHT_FASTBOOT
 	char cmdbuf[32];
+	u32 block_cnt;
 	struct blk_desc *dev_desc;
-	disk_partition_t info;
+	int ret = 0;
+
 	if (strcmp(cmd_parameter, "uboot") == 0) {
-		fasboot_uboot_write_process(fastboot_buf_addr, response);
+		ret = check_image_board_id(fastboot_buf_addr);
+		if (ret != 0) {
+			fastboot_fail("U-BOOT image does not match the type of BOARD", response);
+			return;
+		}
+
+		dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+		if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+			fastboot_fail("invalid mmc device", response);
+			return;
+        }
+
+		run_command("mmc partconf 0 1 0 1", 0);
+
+		block_cnt = image_size / BLOCK_SIZE;
+		if (image_size % BLOCK_SIZE) {
+			block_cnt = block_cnt +1;
+		}
+
+		sprintf(cmdbuf, "mmc write 0x%p 0 %x", fastboot_buf_addr, block_cnt);
+
+		run_command(cmdbuf, 0);
+		run_command("mmc partconf 0 1 0 0", 0);
+
 	} else if ((strcmp(cmd_parameter, "fw") == 0)) {
 		memcpy((void *)LIGHT_FW_ADDR, fastboot_buf_addr, image_size);
 	} else if ((strcmp(cmd_parameter, "uImage") == 0)) {
@@ -437,41 +352,6 @@ static void flash(char *cmd_parameter, char *response)
 	} else if ((strcmp(cmd_parameter, TEE_PART_NAME) == 0)) {
 		memcpy((void *)LIGHT_TEE_FW_ADDR, fastboot_buf_addr, image_size);
 	}
-#ifdef CONFIG_RV_BOOK
-	else if ((strcmp(cmd_parameter, "boot") == 0)) {
-		dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
-		if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
-				fastboot_fail("invalid mmc device", response);
-				return;
-		}
-				/* if fastresume partition exists, earse the old image header */
-		if(part_get_info_by_name(dev_desc, "fastresume", &info)) {
-			printf(" find fastresume partition , erase the header:\n");
-			char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096);
-			if(!buf) {
-				printf(" fastresume partition header mem alloc failed\n");
-				return;
-			}
-			memset(buf,0xff,4096);
-			blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf);
-			free(buf);
-		}
-	}
-#endif
-#ifdef CONFIG_FASTBOOT_ECIES_AUTH
-	else if ((strcmp(cmd_parameter, "ecies") == 0)) {
-		ecies_process_data(fastboot_buf_addr, image_size,response);
-		return;
-	}
-#endif
-
-	//If version is updated, hibernate image may not compatible with current,erase it.
-	if ((strcmp(cmd_parameter, "boot") == 0)
-		|| (strcmp(cmd_parameter, "uboot") == 0)
-		|| (strcmp(cmd_parameter, "root") == 0)) {
-
-		clean_hibernate_image_header(response);
-	}
 
 	if(strcmp(cmd_parameter, "uboot") == 0 || (strcmp(cmd_parameter, "fw") == 0) ||
 	   (strcmp(cmd_parameter, "uImage") == 0) || (strcmp(cmd_parameter, "dtb") == 0) ||
@@ -482,7 +362,54 @@ static void flash(char *cmd_parameter, char *response)
 #endif
 
 #if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
-	if (strcmp(cmd_parameter, UBOOT_IMG_UPD_NAME) == 0) {
+	if(strcmp(cmd_parameter, TF_IMG_UPD_NAME) == 0) {
+		#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
+		/* tee/tf/uboot image must be written into stash partition */
+		sprintf(cmdbuf, "%s", STASH_PART_NAME);
+		fastboot_mmc_flash_write(cmdbuf, fastboot_buf_addr, image_size, response);
+		#endif
+		/* Send ACK to host */
+		fastboot_okay(NULL, response);
+
+		/* set secure upgrade flag to indicate it is TF image upgrade*/
+		sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", TF_SEC_UPGRADE_FLAG);
+		run_command(cmdbuf, 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+		return;
+	} else if (strcmp(cmd_parameter, TEE_IMG_UPD_NAME) == 0) {
+		#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
+		/* tee/tf/uboot image must be written into stash partition */
+		sprintf(cmdbuf, "%s", STASH_PART_NAME);
+		fastboot_mmc_flash_write(cmdbuf, fastboot_buf_addr, image_size, response);
+		#endif
+
+		/* Send ACK to host */
+		fastboot_okay(NULL, response);
+
+		/* set secure upgrade flag to indicate it is TEE image upgrade*/
+		sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", TEE_SEC_UPGRADE_FLAG);
+		run_command(cmdbuf, 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+		return;
+	} else if (strcmp(cmd_parameter, SBMETA_IMG_UPD_NAME) == 0) {
+		#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
+		/* tee/tf/uboot image must be written into stash partition */
+		sprintf(cmdbuf, "%s", STASH_PART_NAME);
+		fastboot_mmc_flash_write(cmdbuf, fastboot_buf_addr, image_size, response);
+		#endif
+
+		/* Send ACK to host */
+		fastboot_okay(NULL, response);
+
+		/* set secure upgrade flag to indicate it is TEE image upgrade*/
+		sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", SBMETA_SEC_UPGRADE_FLAG);
+		run_command(cmdbuf, 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+		return;
+	} else if (strcmp(cmd_parameter, UBOOT_IMG_UPD_NAME) == 0) {
 		#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
 
 		env_set_hex("ubootupdsize", image_size);
@@ -585,38 +512,3 @@ static void oem_command(char *cmd_parameter, char *response)
 	else
 		fastboot_okay(NULL, response);
 }
-
-#if CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION
-/**
- * oem_nv_get() - Execute the OEM NV GET command
- *
- * @cmd_parameter: Pointer to command parameter
- * @response: Pointer to fastboot response buffer
- */
- static void oem_nv_get(char *cmd_parameter, char *response)
- {
-	oem_nv_get_proccess(cmd_parameter,response);
- }
-
-/**
- * oem_nv_set() - Execute the OEM NV Set command
- *
- * @cmd_parameter: Pointer to command parameter
- * @response: Pointer to fastboot response buffer
- */
- static void oem_nv_set(char *cmd_parameter, char *response)
- {
-	oem_nv_set_proccess(cmd_parameter,response);
- }
-
-/**
- * oem_fcty() - Execute the OEM fcty command
- *
- * @cmd_parameter: Pointer to command parameter
- * @response: Pointer to fastboot response buffer
- */
- static void oem_fcty(char *cmd_parameter, char *response)
- {
-	oem_nv_factory_recovery_process(cmd_parameter,response);
- }
- #endif

drivers/fastboot/fb_ecies.c

@@ -1,198 +0,0 @@
-#include <sec_ecies_session.h>
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fastboot.h>
-#include <fastboot-internal.h>
-#include <fb_mmc.h>
-#include <fb_nand.h>
-#include <part.h>
-#include <stdlib.h>
-#include <csi_sec_img_verify.h>
-
-#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
-extern void fasboot_uboot_write_process(void *buf, char *response);
-#define MAX_ECIES_IMAGE_SIZE (9*1024*1024)
-#define ECIES_MALLOC_START (MAX_ECIES_IMAGE_SIZE * 2)
-
-typedef struct {
-	uint32_t magic;
-	uint32_t file_size;
-	char partition_name[64];
-} __attribute__((__packed__)) send_file_info_t;
-
-static uint32_t ecies_file_pos = 0;
-static int slave_init = 0;
-
-static int current_pos = 0;
-
-void *csi_ecies_malloc(uint32_t size)
-{
-    void * ptr = NULL;
-
-    if (current_pos + size >= CONFIG_FASTBOOT_BUF_SIZE) {
-        current_pos = 0;
-    }
-
-    ptr = (void *)(long)(CONFIG_FASTBOOT_BUF_ADDR + ECIES_MALLOC_START + current_pos);
-    current_pos += size;
-    return ptr;
-};
-
-void csi_ecies_free(void *buffer)
-{
-    return;
-};
-
-static int ecies_data_write(uint8_t *buf,uint8_t *data,int data_len)
-{
-    char response[FASTBOOT_RESPONSE_LEN];
-
-    if (data_len == 0  || buf == NULL || data == NULL) {
-        return -1;
-    }
-
-    memcpy(buf + ecies_file_pos,data,data_len);
-    ecies_file_pos += data_len;
-    if (ecies_file_pos == sizeof(send_file_info_t) + ((send_file_info_t *)buf)->file_size) {
-        if (strcmp(((send_file_info_t *)buf)->partition_name, TEE_PART_NAME) == 0) {
-            memcpy((void *)LIGHT_TEE_FW_ADDR, buf + sizeof(send_file_info_t), ((send_file_info_t *)buf)->file_size);
-            #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
-            fastboot_mmc_flash_write(((send_file_info_t *)buf)->partition_name, buf + sizeof(send_file_info_t),  ((send_file_info_t *)buf)->file_size,
-                        response);
-            #endif
-            #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)
-            fastboot_nand_flash_write(((send_file_info_t *)buf)->partition_name,  buf + sizeof(send_file_info_t), ((send_file_info_t *)buf)->file_size,
-                        response);
-            #endif
-        } else if (strcmp(((send_file_info_t *)buf)->partition_name, UBOOT_PART_NAME) == 0) {
-            fasboot_uboot_write_process(buf + sizeof(send_file_info_t),response);
-        } else {
-            printf("unknown partition name\n");
-            return -2;
-        }
-
-        ecies_file_pos = 0;
-    } else if(ecies_file_pos > sizeof(send_file_info_t) + ((send_file_info_t *)buf)->file_size) {
-        return -3;
-    }
-
-    return 0;
-}
-
-static void hex_to_str(char *dest, const uint8_t *src, int len)
-{
-    char ddl = 0;
-    char ddh = 0;
-    int i = 0;
-
-    for (i = 0; i < len; i++) {
-        ddh = 48 + src[i] / 16;
-        ddl = 48 + src[i] % 16;
-
-        if (ddh > 57) {
-            ddh = ddh + 7;
-        }
-
-        if (ddl > 57) {
-            ddl = ddl + 7;
-        }
-
-        dest[i * 2] = ddh;
-        dest[i * 2 + 1] = ddl;
-    }
-
-    dest[len * 2] = '\0';
-}
-
-int ecies_process_data(uint8_t * data, int data_size,char *response)
-{
-    static ecies_session_t ss_slave;
-    char apduResponse[ECIES_INIT_RESPONSE_LEN] = {0};
-    uint8_t *plaintext = csi_ecies_malloc(MAX_ECIES_IMAGE_SIZE);
-    uint32_t plaintextLen = 0;
-    uint32_t apduResponseLen = 0;
-    int ret = 0;
-    uint8_t cla = 0;
-    uint8_t errcode = 0;
-
-    if (plaintext == NULL) {
-        ret = -1;
-        goto end;
-    }
-
-    if (!slave_init) {
-        csi_sec_library_init();
-        ret = hal_ecies_slave_init(&ss_slave);
-        if (ret != 0) {
-            strcpy(response,"hal_ecies_slave_init ERROR");
-            ret = -2;
-            goto end;
-        }
-    }
-    ret = hal_ecies_slave_session_comm(&ss_slave, data, data_size, (uint8_t *)apduResponse, &apduResponseLen, plaintext, &plaintextLen);
-    if (ret != 0) {
-        ret = hal_ecies_status_get((uint8_t *)apduResponse, apduResponseLen, &cla, &errcode);
-        if (ret != 0) {
-            strcpy(response,"hal_ecies_errcode_get ERROR");
-            ret = -3;
-            goto end;
-        }
-
-        if (cla == ECIES_CLA_INITIALIZE_UPDATE_RESPONSE && errcode == ECIES_RESPONSE_SESSION_OPENED_ERROR) {
-            slave_init = 0;
-            ecies_file_pos = 0;
-            hal_ecies_slave_uninit(&ss_slave);
-            ret = hal_ecies_slave_init(&ss_slave);
-            if (ret != 0) {
-                strcpy(response,"hal_ecies_slave_init ERROR");
-                ret = -4;
-                goto end;
-            }
-            ret = hal_ecies_slave_session_comm(&ss_slave, data, data_size,  (uint8_t*)apduResponse, &apduResponseLen, plaintext, &plaintextLen);
-            if (ret != 0) {
-                strcpy(response,"hal_ecies_slave_session_comm ERROR");
-                ret = -5;
-                goto end;
-            }
-        } else if(errcode != ECIES_RESPONSE_OK) {
-            if (errcode == ECIES_CLA_SDATA_SEND_RESPONSE) {
-                strcpy(response,"ECIES_CLA_SDATA_SEND_RESPONSE ERROR");
-                ret = -6;
-                goto end;
-            } else if (errcode == ECIES_CLA_SESSION_CLOSE) {
-                strcpy(response,"ECIES_CLA_SESSION_CLOSE ERROR");
-                ret = -7;
-                goto end;
-            } else if (errcode == ECIES_CLA_INITIALIZE_UPDATE) {
-                strcpy(response,"ECIES_CLA_INITIALIZE_UPDATE ERROR");
-                ret = -8;
-                goto end;
-            }
-        }
-    }
-
-    if (slave_init && plaintextLen) {
-        ret = ecies_data_write((uint8_t*)(long)(CONFIG_FASTBOOT_BUF_ADDR + MAX_ECIES_IMAGE_SIZE),plaintext,plaintextLen);
-        if (ret != 0) {
-            strcpy(response,"ecies_data_write ERROR");
-            ret = -8;
-            goto end;
-        }
-    }
-
-    slave_init = 1;
-
-    strcpy(response,"SUCCESS:");
-    hex_to_str(response + strlen(response),(uint8_t*)apduResponse,apduResponseLen);
-    ret = 0;
-end:
-    if (plaintext) {
-        csi_ecies_free(plaintext);
-        plaintext = NULL;
-    }
-
-    return ret;
-}
-
-#endif

drivers/fastboot/fb_nv_operation.c

@@ -1,342 +0,0 @@
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-
-#include <common.h>
-#include <fb_mmc.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/types.h>
-#include <configs/light-c910.h>
-#include <thead/clock_config.h>
-#include <linux/bitops.h>
-#include <asm/arch-thead/light-iopmp.h>
-#include "../lib/sec_library/include/soc.h"
-
-#define MAX_NV_NUMBER_SIZE 32
-#define MAX_NV_DATA_SIZE 128
-#define NV_BLOCK_SIZE 512
-
-extern int32_t wj_efuse_get_lc(long unsigned int, int *lc);
-
-typedef enum {
-	FB_SYS_ACTION_FACTORY_RECOVER,
-	FB_SYS_ACTION_READ_EFUSE,
-} fb_sys_action_t;
-
-static int nv_get(uint8_t *data,int offset,int data_len)
-{
-	struct blk_desc *dev_desc;
-	struct disk_partition part_info;
-	ulong block_start;
-	uint8_t data_nv[NV_BLOCK_SIZE] = {0};
-	int ret;
-	int n;
-
-	dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
-	if (dev_desc == NULL) {
-		return -1;
-	}
-
-	ret = part_get_info_by_name(dev_desc, NV_PARTITION_NAME, &part_info);
-	if (ret < 0) {
-                return -2;
-	}
-
-        if(NV_BLOCK_SIZE != dev_desc->blksz) {
-                return -4;
-        }
-
-	block_start = part_info.start + offset / dev_desc->blksz;
-	n = blk_dread(dev_desc, block_start, 1, data_nv);
-	if (n != 1) {
-                return -5;
-	}
-
-        memcpy(data,data_nv + offset % NV_BLOCK_SIZE,data_len);
-
-        return 0;
-}
-
-static int nv_set(uint8_t *data,int offset,int data_len)
-{
-        struct blk_desc *dev_desc;
-	struct disk_partition part_info;
-	ulong block_start;
-        uint8_t data_nv[NV_BLOCK_SIZE] = {0};
-        int ret;
-        int n;
-
-
-	dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
-	if (dev_desc == NULL) {
-		return -1;
-	}
-
-	ret = part_get_info_by_name(dev_desc, NV_PARTITION_NAME, &part_info);
-	if (ret < 0) {
-                return -2;
-	}
-
-	if (NV_BLOCK_SIZE != dev_desc->blksz) {
-                return -3;
-        }
-
-	block_start = part_info.start + offset / dev_desc->blksz;
-
-	n = blk_dread(dev_desc, block_start, 1, data_nv);
-        if (n != 1) {
-                return -4;
-        }
-        memcpy(data_nv + offset % NV_BLOCK_SIZE,data,data_len);
-	n = blk_dwrite(dev_desc, block_start, 1, data_nv);
-	if (n != 1) {
-                return -5;
-	}
-
-    return 0;
-}
-
-static int factory_recovery(char *response)
-{
-#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
-        fastboot_mmc_erase("metadata", response);
-        if (strcmp(response, "OKAY") != 0) {
-                return -1;
-        }
-        fastboot_mmc_erase("misc", response);
-        if (strcmp(response, "OKAY") != 0) {
-                return -2;
-        }
-#endif
-#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)
-        fastboot_nand_erase("metadata", response);
-        if (strcmp(response, "OKAY") != 0) {
-                return -3;
-        }
-        fastboot_nand_erase("misc", response);
-        if (strcmp(response, "OKAY") != 0) {
-                return -4;
-        }
-#endif
-
-        strcpy(response,"OKAY");
-
-        return 0;
-}
-
-static int read_efuse_status(char *response)
-{
-        int ret;
-        int lc = 0;
-        ret = wj_efuse_get_lc(WJ_EFUSE_BASE, &lc);
-        if (ret) {
-                return -1;
-        }
-
-        if(lc == 0) {
-                strcpy(response,"LC_INIT");
-        } else {
-                strcpy(response,"LC_BLOWNED");
-        }
-
-        return 0;
-
-}
-
-static int sys_action(int flag,char *response)
-{
-        if (flag == FB_SYS_ACTION_FACTORY_RECOVER) {
-                return factory_recovery(response);
-        } else if (flag == FB_SYS_ACTION_READ_EFUSE) {
-                return read_efuse_status(response);
-        } else {
-                return -1;
-        }
-
-        return 0;
-}
-
-static int toupper(int c)
-{
-        if (c >= 'a' && c <= 'z') {
-                return c - 32;
-        }
-
-        return c;
-}
-
-static void str_to_hex(uint8_t *dest, const char *src, int len)
-{
-        char h1, h2;
-        unsigned char s1, s2;
-
-        for (int i = 0; i < len; i++) {
-                h1 = src[2 * i];
-                h2 = src[2 * i + 1];
-                s1 = toupper(h1) - 48;
-                s2 = toupper(h2) - 48;
-                if (s1 > 9) {
-                        s1 = s1 - 7;
-                }
-
-                if (s2 > 9) {
-                        s2 = s2 - 7;
-                }
-
-                dest[i] = s1 * 16 + s2;
-        }
-}
-
-static void hex_to_str(char *dest, const uint8_t *src, int len)
-{
-        char ddl = 0;
-        char ddh = 0;
-        int i = 0;
-
-        for (i = 0; i < len; i++) {
-                ddh = 48 + src[i] / 16;
-                ddl = 48 + src[i] % 16;
-
-                if (ddh > 57) {
-                        ddh = ddh + 7;
-                }
-
-                if (ddl > 57) {
-                        ddl = ddl + 7;
-                }
-
-                dest[i * 2] = ddh;
-                dest[i * 2 + 1] = ddl;
-        }
-
-        dest[len * 2] = '\0';
-}
-
-static int char_to_int(char *data,int *out)
-{
-        *out = 0;
-        while(*data) {
-                if(*data < '0' || *data > '9')
-                return -1;
-
-                *out = *out * 10 + (*data - '0');
-                ++data;
-        }
-
-	return 0;
-}
-#if CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION
-void oem_nv_factory_recovery_process(char *cmd_parameter, char *response)
-{
-        int ret = 0;
-        int flag = 0;
-
-        ret = char_to_int(cmd_parameter,&flag);
-        if (ret != 0) {
-                strcpy(response,"ERROR FLAG INVALID");
-                return;
-        }
-
-        ret = sys_action(flag,response);
-        if (ret != 0) {
-                strcpy(response,"ERROR SYS ACTION FAILED");
-                return;
-        }
-}
-
-
-void oem_nv_get_proccess(char *cmd_parameter, char *response)
- {
-        char *sep = NULL;
-        char offset[MAX_NV_NUMBER_SIZE] = {0};
-        char len[MAX_NV_NUMBER_SIZE] = {0};
-        int sep_pos = 0;
-        uint8_t nv_data[MAX_NV_DATA_SIZE + 32] = {0};
-        char nv_data_str[MAX_NV_DATA_SIZE * 2 + 1] = {0};
-        int ret;
-        int offset_int = 0;
-        int len_int = 0;
-
-        sep = strstr(cmd_parameter, ":");
-        if (sep == NULL) {
-                strcpy(response,"ERROR INVALID PARAM");
-                return;
-        }
-
-        sep_pos = sep - cmd_parameter;
-        memcpy(offset,cmd_parameter,sep - cmd_parameter);
-        memcpy(len,cmd_parameter + (sep - cmd_parameter) + 1,strlen(cmd_parameter) - sep_pos - 1);
-
-        ret = char_to_int(offset,&offset_int);
-        if (ret != 0) {
-                strcpy(response,"ERROR OFFSET INVALID");
-                return;
-        }
-
-        ret = char_to_int(len,&len_int);
-        if (ret != 0) {
-                strcpy(response,"ERROR LEN INVALID");
-                return;
-        }
-
-        if (len_int > MAX_NV_DATA_SIZE) {
-                strcpy(response,"ERROR NV SIZE TOO LARGE");
-                return;
-        }
-
-        ret = nv_get(nv_data, offset_int, len_int);
-        if (ret != 0) {
-                printf("nv_get failed:%d\n",ret);
-                strcpy(response,"ERROR NV GET FAILED");
-                return;
-        }
-
-        hex_to_str(nv_data_str,nv_data,len_int);
-        strcpy(response,"SUCCESS:");
-        strcat(response,nv_data_str);
- }
-
-void oem_nv_set_proccess(char *cmd_parameter, char *response)
-{
-        char *sep = NULL;
-        char offset[MAX_NV_NUMBER_SIZE] = {0};
-        uint8_t nv_data[MAX_NV_DATA_SIZE + 32] = {0};
-        char *nv_data_str;
-        int data_len;
-        int ret;
-        int offset_int = 0;
-
-        sep = strstr(cmd_parameter, ":");
-        if (sep == NULL) {
-                strcpy(response,"ERROR INVALID PARAM");
-                return;
-        }
-
-        memcpy(offset,cmd_parameter,sep - cmd_parameter);
-        nv_data_str = cmd_parameter + (sep - cmd_parameter) + 1;
-
-        data_len = strlen(nv_data_str) / 2;
-
-        ret = char_to_int(offset,&offset_int);
-        if (ret != 0) {
-                strcpy(response,"ERROR OFFSET INVALID");
-                return;
-        }
-
-        if (data_len > MAX_NV_DATA_SIZE) {
-                strcpy(response,"ERROR NV SIZE TOO LARGE");
-                return;
-        }
-
-        str_to_hex(nv_data,nv_data_str,data_len);
-
-        ret = nv_set(nv_data, offset_int, data_len);
-        if (ret != 0) {
-                strcpy(response,"ERROR NV SET FAILED");
-                return;
-        }
-
-        strcpy(response,"OKAY");
- }
- #endif

drivers/mcu/Kconfig

@@ -1,15 +0,0 @@
-menu "MCU Support"
-
-config DM_MCU
-	bool "Enable driver model for mcu device support"
-	depends on DM
-	help
-	  This adds a simple uclass for mcu device.
-	  
-config MCU_HC32fX
-	bool "Enable HC32fX MCU support"
-	depends on DM_MCU
-	help
-	  This adds a driver for the HC32fX MCU support.
-
-endmenu

drivers/mcu/Makefile

@@ -1,9 +0,0 @@
-#
-# Copyright (c) 2015 Google, Inc
-# Written by Simon Glass <sjg@chromium.org>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_DM_MCU)	+= mcu-uclass.o
-obj-$(CONFIG_MCU_HC32fX) += mcu_hc32fx.o

drivers/mcu/mcu-uclass.c

@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <mcu/mcu-uclass.h>
-#include <dm/root.h>
-#include <dm/uclass-internal.h>
-
-int _mcu_shutdown(struct udevice *dev)
-{
-	struct mcu_ops *ops = dev_get_driver_ops(dev);
-
-	if (!ops->shutdown)
-		return -ENOSYS;
-
-	return ops->shutdown(dev);
-}
-
-int _mcu_poweron(struct udevice *dev)
-{
-	struct mcu_ops *ops = dev_get_driver_ops(dev);
-
-	if (!ops->poweron)
-		return -ENOSYS;
-
-	return ops->poweron(dev);
-}
-
-int mcu_poweron(void)
-{
-	struct udevice *mcu;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_MCU, 0, &mcu);
-	if (ret) {
-		printf("Get UCLASS_MCU failed, ret=%d\n", ret);
-		return ret;
-	}
-
-	return _mcu_poweron(mcu);
-}
-
-int mcu_shutdown(void)
-{
-	struct udevice *mcu;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_MCU, 0, &mcu);
-	if (ret) {
-		printf("Get charge display failed, ret=%d\n", ret);
-		return ret;
-	}
-
-	return _mcu_shutdown(mcu);
-}
-
-UCLASS_DRIVER(mcu) = {
-	.id		= UCLASS_MCU,
-	.name		= "mcu",
-};

drivers/mcu/mcu_hc32fx.c

@@ -1,97 +0,0 @@
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <mcu/mcu-uclass.h>
-#include <dm/lists.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define HC32FX_POWEROFF_20    0x20
-#define HC32FX_POWERON_30    0x30
-#define POWER_OFF   0x55
-#define POWER_ON   0x01
-
-struct hc32fx_info {
-	struct udevice *dev;
-};
-
-static u8 hc32fx_read(struct hc32fx_info *hc32fx, u8 reg)
-{
-	u8 val;
-	int ret;
-
-	ret = dm_i2c_read(hc32fx->dev, reg, &val, 1);
-	if (ret) {
-		printf("write error to device: %p register: %#x!",
-		      hc32fx->dev, reg);
-		return ret;
-	}
-
-	return val;
-}
-
-static int hc32fx_write(struct hc32fx_info *hc32fx, u8 reg, u8 val)
-{
-	int ret;
-
-	ret = dm_i2c_write(hc32fx->dev, reg, &val, 1);
-	if (ret) {
-		printf("write error to device: %p register: %#x!",
-		      hc32fx->dev, reg);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int mcu_hc32fx_poweron(struct udevice *dev)
-{
-	struct hc32fx_info *hc32fx = dev_get_priv(dev);
-	int ret;
-
-	ret = hc32fx_write(hc32fx, HC32FX_POWERON_30, POWER_ON);
-	if(ret)
-		printf("set mcu POWERON fail\n");
-
-	return ret;
-}
-
-static int mcu_hc32fx_shutdown(struct udevice *dev)
-{
-	struct hc32fx_info *hc32fx = dev_get_priv(dev);
-	int ret;
-
-	ret = hc32fx_write(hc32fx, HC32FX_POWEROFF_20, POWER_OFF);
-	if(ret)
-		printf("set mcu POWEROFF fail\n");
-
-	return ret;
-}
-
-static int mcu_gpio_probe(struct udevice *dev)
-{
-	struct hc32fx_info *priv = dev_get_priv(dev);
-	priv->dev = dev;
-
-	return 0;
-}
-
-static const struct mcu_ops mcu_hc32fx_ops = {
-	.poweron	= mcu_hc32fx_poweron,
-	.shutdown	= mcu_hc32fx_shutdown,
-};
-
-static const struct udevice_id hc32fx_ops_ids[] = {
-	{ .compatible = "mcu_hc32fx" },
-	{ }
-};
-
-U_BOOT_DRIVER(mcu_gpio) = {
-	.name	= "hc32fx-mcu",
-	.id	= UCLASS_MCU,
-	.of_match = hc32fx_ops_ids,
-	.ops	= &mcu_hc32fx_ops,
-	.priv_auto_alloc_size = sizeof(struct hc32fx_info),
-	.probe	= mcu_gpio_probe,
-};

drivers/misc/Kconfig

@@ -439,10 +439,4 @@ config K3_AVS0
 	  optimized voltage from the efuse, so that it can be programmed
 	  to the PMIC on board.
 
-config LIGHT_AON_CONF
-	bool "Light aon config support"
-	depends on MISC
-	help
-	  Select this to enable aon config by dts.
-
 endmenu

drivers/misc/Makefile

@@ -68,4 +68,3 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
 obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
 obj-$(CONFIG_K3_AVS0) += k3_avs.o
-obj-$(CONFIG_LIGHT_AON_CONF) += light_regu.o

drivers/misc/light_regu.h

@@ -1,271 +0,0 @@
-#ifndef __LIGHT_REGU_H__
-#define __LIGHT_REGU_H__
-
-typedef enum
-{
-	SOC_DVDD18_AON,		  /*da9063:  ldo-3 */
-	SOC_AVDD33_USB3,	  /*da9063:  ldo-9 */
-	SOC_DVDD08_AON,		  /*da9063:  ldo-2 */
-	SOC_APCPU_DVDD_DVDDM, /*da9063:  vbcore1 & vbcore2*/
-	SOC_DVDD08_DDR,		  /*da9063:  buckperi */
-	SOC_VDD_DDR_1V8,	  /*da9063:  ldo-4  */
-	SOC_VDD_DDR_1V1,	  /*da9063:  buckmem & buckio  */
-	SOC_VDD_DDR_0V6,	  /*da9063:  buckpro */
-	SOC_DVDD18_AP,		  /*da9063:  ldo-11 */
-	SOC_DVDD08_AP,		  /*da9121:  da9121_ex */
-	SOC_AVDD08_MIPI_HDMI, /*da9063:  ldo-1  */
-	SOC_AVDD18_MIPI_HDMI, /*da9063:  ldo-5  */
-	SOC_DVDD33_EMMC,	  /*da9063:  ldo-10 */
-	SOC_DVDD18_EMMC,	  /*slg51000:ldo-3 */
-	SOC_DOVDD18_SCAN,	  /*da9063:  ldo-6 */
-	SOC_VEXT_2V8,		  /*da9063:  ldo-7 */
-	SOC_DVDD12_SCAN,	  /*da9063:  ldo-8 */
-	SOC_AVDD28_SCAN_EN,	  /*da9063:  gpio-4,SGM2019-ADJ */
-	SOC_AVDD28_RGB,		  /*slg51000:ldo-1 */
-	SOC_DOVDD18_RGB,	  /*slg51000:ldo-4 */
-	SOC_DVDD12_RGB,		  /*slg51000:ldo-5 */
-	SOC_AVDD25_IR,		  /*slg51000:ldo-2 */
-	SOC_DOVDD18_IR,		  /*slg51000:ldo-7 */
-	SOC_DVDD12_IR,		  /*slg51000:ldo-6 */
-	SOC_ADC_VREF,
-	SOC_LCD0_EN,
-	SOC_VEXT_1V8,
-
-	SOC_REGU_INVALID = 0xFF
-} soc_virtual_id_en;
-
-#define REGU_DTS_NAME "light-regu-reg"
-#define AON_CONF_NAME "aon_pmic_config"
-#define PMIC_DEV_DTS_NAME "pmic-dev"
-#define PMIC_PARENT_CTRL_NAME "pmic_ctrl_info"
-#define REGU_ID_CONF_NAME "regu_config"
-#define REGU_ID_NAME "regu_id"
-#define COUPLING_ID_INFO_NAME "coupling_info"
-
-#define PMIC_DEV_ENABLE_WDT (1U << 0)
-#define PMIC_DEV_ENABLE_ERR_IO (1U << 1)
-#define PMIC_DEV_ENABLE_LPM_IO (1U << 2)
-
-#define HW_ID_NO_SOFT_AUTO_ON (0xff)
-#define HW_ID_NO_SOFT_AUTO_OFF (0xff)
-#define HW_ID_INVALID (0xff)
-#define PMIC_ID_INVALID (0xff)
-#define REGU_SUB_ID_INVALID (0xff)
-
-#define REGU_EXT_ID_NAME_LEN 30
-#define PMIC_DEV_NAME_LEN 20
-#define PMIC_DEV_VERSION_LEN 20
-
-#define PMIC_MAX_HW_ID_NUM 3
-#define PMIC_MAX_COUPLING_NUM 3
-
-#define AON_WAKEUP_BY_GPIO (1 << 0)
-#define AON_WAKEUP_BY_RTC (1 << 1)
-
-#define AON_CONFIG_MAGIC "AON_CONFIG"
-#define UBOOT_CONFIG_MAGIC "UBOOT_SET"
-#define AON_CONFIG_VERSION "1.0.0"
-
-typedef enum
-{
-	HW_ID_ACTIVATE_HIGH = 0U,
-	HW_ID_ACTIVATE_LOW = 1U,
-} hw_activate_status_en;
-
-typedef struct __packed
-{
-	uint8_t pmic_id;
-	uint8_t io_hw_id;
-	uint8_t activate_status;
-} pmic_parent_hw_io_ctrl_info_t;
-
-typedef struct __packed
-{
-	uint8_t on_order;
-	uint8_t on_delay_ms;
-	uint32_t init_target_uv;
-} regu_soft_power_ctrl_on_t;
-
-typedef struct __packed
-{
-	uint8_t off_order;
-	uint8_t off_delay_ms;
-} regu_soft_power_ctrl_off_t;
-
-typedef struct __packed
-{
-	regu_soft_power_ctrl_on_t on_info;
-	regu_soft_power_ctrl_off_t off_info;
-} regu_soft_power_ctrl_t;
-
-typedef struct __packed
-{
-	uint8_t id0;
-	uint8_t id1;
-	int8_t max_spread; // mv/10
-	int8_t min_spread; // mv/10
-} coupling_desc_t;
-
-typedef enum
-{
-	GPIO_IRQ_MODE_RISING_EDGE = 0, ///< Interrupt mode for rising edge
-	GPIO_IRQ_MODE_FALLING_EDGE,	   ///< Interrupt mode for falling edge
-	GPIO_IRQ_MODE_BOTH_EDGE,	   ///< Interrupt mode for both edge
-	GPIO_IRQ_MODE_LOW_LEVEL,	   ///< Interrupt mode for low level
-	GPIO_IRQ_MODE_HIGH_LEVEL,	   ///< Interrupt mode for high level
-} csi_gpio_irq_mode_t;
-
-typedef enum
-{
-	IIC_ADDRESS_7BIT = 0U, ///< 7-bit address mode
-	IIC_ADDRESS_10BIT	   ///< 10-bit address mode
-} csi_iic_addr_mode_t;
-
-typedef enum
-{
-	IIC_BUS_SPEED_STANDARD = 0U, ///< Standard Speed  (<=100kHz)
-	IIC_BUS_SPEED_FAST,			 ///< Fast Speed      (<=400kHz)
-	IIC_BUS_SPEED_FAST_PLUS,	 ///< Fast plus Speed (<=  1MHz)
-	IIC_BUS_SPEED_HIGH			 ///< High Speed      (<=3.4MHz)
-} csi_iic_speed_t;
-
-typedef struct __packed
-{
-	uint8_t pmic_id;
-	uint8_t hw_id;
-	uint8_t benable;
-	pmic_parent_hw_io_ctrl_info_t parent_hw_info;
-	regu_soft_power_ctrl_t soft_power_ctrl_info;
-} pmic_hw_info_t;
-
-typedef struct __packed
-{
-	coupling_desc_t coupling_list[PMIC_MAX_COUPLING_NUM];
-	pmic_hw_info_t id[PMIC_MAX_HW_ID_NUM]; ///<  sub id1 for single-rail or first src of dual-rail
-} pmic_hw_id_t;
-
-typedef struct __packed
-{
-	uint8_t regu_ext_id;						 ///< virtual global regulator id
-	char regu_ext_id_name[REGU_EXT_ID_NAME_LEN]; ///< vitual regu-id name
-	pmic_hw_id_t sub;							 ///<  sub id set for dual-rail/single-rail regulator
-} csi_regu_id_t;
-
-typedef enum
-{
-	PMIC_CTRL_BY_AON_GPIO = 0U,
-	PMIC_CTRL_BY_PMIC_GPIO = 1U,
-	PMIC_CTRL_BY_NOTHINTG = 0xFF,
-} pmic_ctrl_info_en;
-
-typedef struct __packed
-{
-	uint8_t gpio_port;
-	uint8_t pin;
-	uint8_t activate_status;
-} pmic_ctrl_by_aon_info_t;
-
-typedef struct __packed
-{
-	uint8_t pmic_id;
-	uint8_t io_hw_id;
-	uint8_t activate_status;
-} pmic_ctrl_by_pmic_info_t;
-
-typedef struct __packed
-{
-	uint8_t pmic_ctrl_type;
-	union
-	{
-		pmic_ctrl_by_aon_info_t aon_io;
-		pmic_ctrl_by_pmic_info_t pmic_io;
-	} info;
-} pmic_parent_ctrl_info_t;
-
-typedef struct __packed
-{
-	uint8_t gpio_port;
-	uint8_t pin;
-	uint8_t trigger_mode;
-} pmic_interrupt_io_info_t;
-
-typedef struct __packed
-{
-	char device_name[PMIC_DEV_NAME_LEN];
-	char version_name[PMIC_DEV_VERSION_LEN];
-	uint8_t pmic_id;
-	uint8_t addr1;
-	uint8_t addr2;
-	uint8_t flag; /*support wdt|errio| lpm io*/
-	uint8_t slew_rate;
-	uint32_t wdt_len;
-	pmic_interrupt_io_info_t err_io_info;
-	pmic_interrupt_io_info_t lpm_io_info;
-	pmic_parent_ctrl_info_t ctrl_info;
-} pmic_dev_info_t;
-
-typedef struct
-{
-	soc_virtual_id_en id;
-	char virtual_id_name[REGU_EXT_ID_NAME_LEN];
-	int min_uv;
-	int max_uv;
-} soc_virtual_id_t;
-
-typedef struct
-{
-	int regu_num;
-	soc_virtual_id_t *regu_list;
-} virtual_regu_list_t;
-
-typedef struct
-{
-	int pmic_num;
-	pmic_dev_info_t *pmic_list;
-} pmic_dev_list_t;
-
-typedef struct
-{
-	int regu_id_num;
-	csi_regu_id_t *regu_id_list;
-} regu_id_list_t;
-
-typedef struct __packed
-{
-	uint8_t iic_id;	   ///< iic id
-	uint8_t addr_mode; ///< iic addr_mode  ---> csi_iic_addr_mode_t
-	uint8_t speed;	   ///< iic speed type  ---> csi_iic_speed_t
-	uint8_t reserved[1];
-} csi_pmic_if_config_t;
-
-struct mic_regu_platdata
-{
-	const char *name;
-	uint32_t wakeup_flag;
-	csi_pmic_if_config_t iic_config;
-	virtual_regu_list_t regu_list;
-	pmic_dev_list_t pmic_list;
-	regu_id_list_t regu_id_list;
-};
-
-typedef struct __packed
-{
-	csi_pmic_if_config_t iic_config;
-	uint8_t pmic_dev_num;
-	uint8_t regu_num;
-	uint32_t pmic_dev_list_offset;
-	uint32_t regu_id_list_offset;
-} aon_pmic_config_t;
-
-typedef struct __packed
-{
-	const char magic[11];
-	const char version[11];
-	const char uboot_set_magic[11];
-	uint8_t max_hw_id_num;
-	uint64_t aon_config_partition_size;
-	uint32_t wakeup_flag;
-	aon_pmic_config_t aon_pmic;
-} aon_config_t;
-
-#endif

drivers/misc/misc-uclass.c

@@ -13,6 +13,7 @@
  * general classes. A set of generic read, write and ioctl methods may
  * be used to access the device.
  */
+
 int misc_read(struct udevice *dev, int offset, void *buf, int size)
 {
 	const struct misc_ops *ops = device_get_ops(dev);

drivers/mmc/sdhci.c

@@ -38,7 +38,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
 		timeout--;
 		udelay(1000);
 	}
-
+#ifdef CONFIG_TARGET_LIGHT_C910
+	mdelay(50);
+#endif
 }
 
 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)

drivers/power/Kconfig

@@ -2,22 +2,10 @@ menu "Power"
 
 source "drivers/power/domain/Kconfig"
 
-source "drivers/power/fuel_gauge/Kconfig"
-
 source "drivers/power/pmic/Kconfig"
 
 source "drivers/power/regulator/Kconfig"
 
-source "drivers/power/charge/Kconfig"
-
-source "drivers/power/power_delivery/Kconfig"
-
-config DM_CHARGE_DISPLAY
-	bool "Enable driver model for charge display support"
-	depends on DM
-	help
-	This adds a simple uclass for charge display.
-
 choice
 	prompt "Select Sunxi PMIC Variant"
 	depends on ARCH_SUNXI
@@ -84,13 +72,6 @@ config SY8106A_POWER
 
 endchoice
 
-config CHARGE_ANIMATION
-	bool "Enable charge animation"
-	depends on DM_CHARGE_DISPLAY && DM_FUEL_GAUGE
-	select ARM_CPU_SUSPEND
-	help
-	This adds a simple function for charge animation display.
-
 config AXP_DCDC1_VOLT
 	int "axp pmic dcdc1 voltage"
 	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER

drivers/power/Makefile

@@ -3,13 +3,11 @@
 # Copyright (c) 2009 Wind River Systems, Inc.
 # Tom Rix <Tom.Rix at windriver.com>
 
-obj-$(CONFIG_DM_CHARGE_DISPLAY)        += charge-display-uclass.o
 obj-$(CONFIG_AXP152_POWER)	+= axp152.o
 obj-$(CONFIG_AXP209_POWER)	+= axp209.o
 obj-$(CONFIG_AXP221_POWER)	+= axp221.o
 obj-$(CONFIG_AXP809_POWER)	+= axp809.o
 obj-$(CONFIG_AXP818_POWER)	+= axp818.o
-obj-$(CONFIG_CHARGE_ANIMATION) += charge_animation.o
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
 obj-$(CONFIG_SY8106A_POWER)	+= sy8106a.o

drivers/power/charge-display-uclass.c

@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <command.h>
-#include <common.h>
-#include <dm.h>
-#include <power/charge_display.h>
-
-int charge_display_show(struct udevice *dev)
-{
-	const struct dm_charge_display_ops *ops = dev_get_driver_ops(dev);
-
-	if (!ops || !ops->show)
-		return -ENOSYS;
-
-	return ops->show(dev);
-}
-
-int charge_display(void)
-{
-	struct udevice *dev;
-	struct udevice *fg_dev;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_CHARGE_DISPLAY, 0, &dev);
-	if (ret) {
-		debug("Get charge display failed, ret=%d\n", ret);
-		return ret;
-	}
-	
-	return charge_display_show(dev);
-}
-
-UCLASS_DRIVER(charge_display) = {
-	.id	= UCLASS_CHARGE_DISPLAY,
-	.name	= "charge_display",
-};