PCB: update Rev.E assembly diagrams

FPGA: updated project files
PCB: Rev.E2 WIP
2012-01-14 23:35:14 +01:00 · 2012-01-14 23:16:57 +01:00 · 2012-01-14 23:13:38 +01:00 · 2012-01-14 23:12:45 +01:00 · 2012-01-14 23:08:12 +01:00 · 2012-01-14 12:18:13 +01:00
74 changed files with 48468 additions and 724 deletions
--- a/11
+++ b/11
@@ -11,3 +11,14 @@ v0.1.1a (bugfix release)
   - SuperCIC pair mode was erroneously enabled in firmware binary
   - SNES menu crashed on empty database

+
+v0.1.2
+======
+
+ * Auto region override (eliminate "This game pak is not designed..." messages)
+ * Improved mapper detection (fixes Batman vs. Joker and many PD ROMs)
+ * Improved data streaming performance
+   (should reduce MSU1 errors with some cards)
+ * A and B buttons swapped in menu to match common key mappings
+ * Fixes:
+   - MSU1: Stop audio playback on end of audio file
--- a/pcb/kicad/RevE/fpga.sch
+++ b/pcb/kicad/RevE/fpga.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 02 Dec 2011 09:50:04 AM CET
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:06 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A3 16535 11700
 encoding utf-8
 Sheet 6 6
 Title "sd2snes Mark II"
-Date "2 dec 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""
--- a/pcb/kicad/RevE/mcu.sch
+++ b/pcb/kicad/RevE/mcu.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 02 Dec 2011 09:50:04 AM CET
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:06 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A4 11700 8267
 encoding utf-8
 Sheet 4 6
 Title "sd2snes Mark II"
-Date "2 dec 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""
--- a/pcb/kicad/RevE/memory.sch
+++ b/pcb/kicad/RevE/memory.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 02 Dec 2011 09:50:04 AM CET
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:05 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A4 11700 8267
 encoding utf-8
 Sheet 3 6
 Title "sd2snes Mark II"
-Date "2 dec 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""
@@ -322,7 +322,7 @@ L R R513
 U 1 1 4BF2FDAC
 P 9150 5700
 F 0 "R513" V 9230 5700 50  0000 C CNN
-F 1 "1k" V 9150 5700 50  0000 C CNN
+F 1 "100k" V 9150 5700 50  0000 C CNN
 F 2 "SM0805_FIXEDMASK" H 9150 5700 60  0001 C CNN
 	1    9150 5700
 	1    0    0    -1  
--- a/pcb/kicad/RevE/pwr_misc.sch
+++ b/pcb/kicad/RevE/pwr_misc.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 02 Dec 2011 09:50:04 AM CET
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:06 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A4 11700 8267
 encoding utf-8
 Sheet 5 6
 Title "sd2snes Mark II"
-Date "2 dec 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""
--- a/pcb/kicad/RevE/sd2snes-BOM-with-supplier.ods
+++ b/pcb/kicad/RevE/sd2snes-BOM-with-supplier.ods
--- a/pcb/kicad/RevE/sd2snes-components-back.png
+++ b/pcb/kicad/RevE/sd2snes-components-back.png
--- a/pcb/kicad/RevE/sd2snes-components-front.png
+++ b/pcb/kicad/RevE/sd2snes-components-front.png
--- a/pcb/kicad/RevE/sd2snes.brd
+++ b/pcb/kicad/RevE/sd2snes.brd
@@ -1,4 +1,4 @@
-PCBNEW-BOARD Version 1 date Sat 12 Nov 2011 04:56:02 PM CET
+PCBNEW-BOARD Version 1 date Fri 02 Dec 2011 02:55:43 PM CET

 # Created by Pcbnew(2011-07-02 BZR 2664)-stable

@@ -9,8 +9,8 @@ Ly 1FFF8001
 EnabledLayers 1FFF8001
 Links 668
 NoConn 0
-Di 36595 16630 77260 64790
-Ndraw 239
+Di 36595 16630 83771 64790
+Ndraw 241
 Ntrack 4007
 Nzone 0
 BoardThickness 630
@@ -21,7 +21,7 @@ $EndGENERAL
 $SHEETDESCR
 Sheet A4 11700 8267
 Title "sd2snes Mark II"
-Date "12 nov 2011"
+Date "2 dec 2011"
 Rev "C2"
 Comp "Maximilian Rehkopf"
 Comment1 ""
@@ -7484,7 +7484,7 @@ AR /4B6ED75B/4BEECBCD
 Op 0 0 0
 At SMD 
 T0 0 600 320 320 2700 70 N V 21 N "C408"
-T1 0 0 320 320 2700 70 N I 21 N "22p"
+T1 0 0 320 320 2700 70 N I 21 N "10p"
 DS 200 350 650 350 75 21
 DS -650 350 -200 350 75 21
 DS 650 -350 200 -350 75 21
@@ -8708,7 +8708,7 @@ AR /4B6ED75B/4BEECBD1
 Op 0 0 0
 At SMD 
 T0 -25 -600 320 320 900 70 N V 21 N "C409"
-T1 0 0 320 320 900 70 N I 21 N "22p"
+T1 0 0 320 320 900 70 N I 21 N "10p"
 DS 200 350 650 350 75 21
 DS -650 350 -200 350 75 21
 DS 650 -350 200 -350 75 21
@@ -12481,6 +12481,32 @@ Ne 0 ""
 Po 14331 3780
 $EndPAD
 $EndMODULE  SNESCART_EXT2
+$COTATION
+Ge 0 24 0
+Va 32677
+Te "83.000 mm"
+Po 81111 38031 600 800 120 2701 1
+Sb 0 80471 21693 80471 54370 120
+Sd 0 65630 54370 81751 54370 120
+Sg 0 65630 21693 81751 21693 120
+S1 0 80471 54370 80241 53927 120
+S2 0 80471 54370 80701 53927 120
+S3 0 80471 21693 80241 22136 120
+S4 0 80471 21693 80701 22136 120
+$endCOTATION
+$COTATION
+Ge 0 24 0
+Va 40000
+Te "101.600 mm"
+Po 57165 59419 600 800 120 0 1
+Sb 0 37165 58779 77165 58779 120
+Sd 0 77165 34606 77165 60059 120
+Sg 0 37165 34606 37165 60059 120
+S1 0 77165 58779 76722 59009 120
+S2 0 77165 58779 76722 58549 120
+S3 0 37165 58779 37608 59009 120
+S4 0 37165 58779 37608 58549 120
+$endCOTATION
 $TEXTPCB
 Te "USE_BATT"
 Po 46575 27525 320 320 80 0
--- a/pcb/kicad/RevE/sd2snes.net
+++ b/pcb/kicad/RevE/sd2snes.net
@@ -1,4 +1,4 @@
-# EESchema Netlist Version 1.1 created  Fri 02 Dec 2011 09:50:17 AM CET
+# EESchema Netlist Version 1.1 created  Fri 09 Dec 2011 10:46:12 PM CET
 (
 ( /4B6E16F2/4D97B45F $noname  RA114 100 {Lib=R_PACK4}
  (    1 N-000108 )
@@ -176,7 +176,7 @@
  (    1 SNES_IRQ_EN )
  (    2 N-000036 )
 )
- ( /4B6E16F2/4C7EAEBF $noname  R102 1k {Lib=R}
+ ( /4B6E16F2/4C7EAEBF $noname  R102 100k {Lib=R}
  (    1 N-000036 )
  (    2 GND )
 )
@@ -489,7 +489,7 @@
  (    1 /Memory/SRAM_Vcc )
  (    2 /Memory/RAM_/CE )
 )
- ( /4BAA6ABD/4BF2FDAC SM0805_FIXEDMASK  R513 1k {Lib=R}
+ ( /4BAA6ABD/4BF2FDAC SM0805_FIXEDMASK  R513 100k {Lib=R}
  (    1 N-000344 )
  (    2 GND )
 )
--- a/pcb/kicad/RevE/sd2snes.sch
+++ b/pcb/kicad/RevE/sd2snes.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 02 Dec 2011 09:50:04 AM CET
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:05 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A4 11700 8267
 encoding utf-8
 Sheet 1 6
 Title "sd2snes Mark II"
-Date "2 dec 2011"
+Date "9 dec 2011"
 Rev "E"
 Comp "Maximilian Rehkopf"
 Comment1 ""
--- a/pcb/kicad/RevE/snesslot.sch
+++ b/pcb/kicad/RevE/snesslot.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 02 Dec 2011 09:50:04 AM CET
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:05 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A3 16535 11700
 encoding utf-8
 Sheet 2 6
 Title "sd2snes Mark II"
-Date "2 dec 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""
@@ -1125,7 +1125,7 @@ L R R102
 U 1 1 4C7EAEBF
 P 6850 8600
 F 0 "R102" V 6930 8600 50  0000 C CNN
-F 1 "1k" V 6850 8600 50  0000 C CNN
+F 1 "100k" V 6850 8600 50  0000 C CNN
 	1    6850 8600
 	1    0    0    -1  
 $EndComp
--- a/pcb/kicad/RevE2/fpga.sch
+++ b/pcb/kicad/RevE2/fpga.sch
--- a/pcb/kicad/RevE2/mcu.sch
+++ b/pcb/kicad/RevE2/mcu.sch
--- a/pcb/kicad/RevE2/memory.sch
+++ b/pcb/kicad/RevE2/memory.sch
@@ -0,0 +1,807 @@
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:snescart
+LIBS:misc-74
+LIBS:vreg
+LIBS:lpc1754
+LIBS:sd_card
+LIBS:cy62148ev30
+LIBS:mt45w8mw16
+LIBS:cs4344
+LIBS:double_sch_kcom
+LIBS:usb_minib
+LIBS:mic23250
+LIBS:sd2snes-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 3 6
+Title "sd2snes Mark II"
+Date "2 jan 2012"
+Rev "E2"
+Comp "Maximilian Rehkopf"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Text Label 7650 2000 0    50   ~ 0
+SRAM_Vcc
+Wire Wire Line
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+Wire Wire Line
+	8350 5050 8350 5250
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+Text Label 4350 2450 0    50   ~ 0
+ROM_DQ3
+Text Label 4350 2350 0    50   ~ 0
+ROM_DQ2
+Text Label 4350 2250 0    50   ~ 0
+ROM_DQ1
+Text Label 4350 2150 0    50   ~ 0
+ROM_DQ0
+Text Label 2100 4750 0    50   ~ 0
+ROM_/WE
+Text Label 2100 4650 0    50   ~ 0
+ROM_/OE
+Text Label 2100 4550 0    50   ~ 0
+ROM_/CE
+Text Label 2100 4350 0    50   ~ 0
+ROM_A22
+Text Label 2100 4250 0    50   ~ 0
+ROM_A21
+Text Label 2100 4150 0    50   ~ 0
+ROM_A20
+Text Label 2100 4050 0    50   ~ 0
+ROM_A19
+Text Label 2100 3950 0    50   ~ 0
+ROM_A18
+Text Label 2100 3850 0    50   ~ 0
+ROM_A17
+Text Label 2100 3750 0    50   ~ 0
+ROM_A16
+Text Label 2100 3650 0    50   ~ 0
+ROM_A15
+Text Label 2100 3550 0    50   ~ 0
+ROM_A14
+Text Label 2100 3450 0    50   ~ 0
+ROM_A13
+Text Label 2100 3350 0    50   ~ 0
+ROM_A12
+Text Label 2100 3250 0    50   ~ 0
+ROM_A11
+Text Label 2100 3150 0    50   ~ 0
+ROM_A10
+Text Label 2100 3050 0    50   ~ 0
+ROM_A9
+Text Label 2100 2950 0    50   ~ 0
+ROM_A8
+Text Label 2100 2850 0    50   ~ 0
+ROM_A7
+Text Label 2100 2750 0    50   ~ 0
+ROM_A6
+Text Label 2100 2650 0    50   ~ 0
+ROM_A5
+Text Label 2100 2550 0    50   ~ 0
+ROM_A4
+Text Label 2100 2450 0    50   ~ 0
+ROM_A3
+Text Label 2100 2350 0    50   ~ 0
+ROM_A2
+Text Label 2100 2250 0    50   ~ 0
+ROM_A1
+Text Label 2100 2150 0    50   ~ 0
+ROM_A0
+Text GLabel 2050 4550 0    50   Input ~ 0
+ROM_/CE
+Text GLabel 9000 4050 2    50   Input ~ 0
+RAM_/WE
+Text GLabel 9000 3950 2    50   Input ~ 0
+RAM_/OE
+Text GLabel 9000 3250 2    50   BiDi ~ 0
+RAM_DQ7
+Text GLabel 9000 3150 2    50   BiDi ~ 0
+RAM_DQ6
+Text GLabel 9000 3050 2    50   BiDi ~ 0
+RAM_DQ5
+Text GLabel 9000 2950 2    50   BiDi ~ 0
+RAM_DQ4
+Text GLabel 9000 2850 2    50   BiDi ~ 0
+RAM_DQ3
+Text GLabel 9000 2750 2    50   BiDi ~ 0
+RAM_DQ2
+Text GLabel 9000 2650 2    50   BiDi ~ 0
+RAM_DQ1
+Text GLabel 9000 2550 2    50   BiDi ~ 0
+RAM_DQ0
+Text GLabel 6300 4350 0    50   Input ~ 0
+RAM_A18
+Text GLabel 6300 4250 0    50   Input ~ 0
+RAM_A17
+Text GLabel 6300 4150 0    50   Input ~ 0
+RAM_A16
+Text GLabel 6300 4050 0    50   Input ~ 0
+RAM_A15
+Text GLabel 6300 3950 0    50   Input ~ 0
+RAM_A14
+Text GLabel 6300 3850 0    50   Input ~ 0
+RAM_A13
+Text GLabel 6300 3750 0    50   Input ~ 0
+RAM_A12
+Text GLabel 6300 3650 0    50   Input ~ 0
+RAM_A11
+Text GLabel 6300 3550 0    50   Input ~ 0
+RAM_A10
+Text GLabel 6300 3450 0    50   Input ~ 0
+RAM_A9
+Text GLabel 6300 3350 0    50   Input ~ 0
+RAM_A8
+Text GLabel 6300 3250 0    50   Input ~ 0
+RAM_A7
+Text GLabel 6300 3150 0    50   Input ~ 0
+RAM_A6
+Text GLabel 6300 3050 0    50   Input ~ 0
+RAM_A5
+Text GLabel 6300 2950 0    50   Input ~ 0
+RAM_A4
+Text GLabel 6300 2850 0    50   Input ~ 0
+RAM_A3
+Text GLabel 6300 2750 0    50   Input ~ 0
+RAM_A2
+Text GLabel 6300 2650 0    50   Input ~ 0
+RAM_A1
+Text GLabel 6300 2550 0    50   Input ~ 0
+RAM_A0
+Text GLabel 4750 4150 2    50   Input ~ 0
+ROM_/UB
+Text GLabel 4750 4050 2    50   Input ~ 0
+ROM_/LB
+Text GLabel 4750 3750 2    50   BiDi ~ 0
+ROM_DQ15
+Text GLabel 4750 3650 2    50   BiDi ~ 0
+ROM_DQ14
+Text GLabel 4750 3550 2    50   BiDi ~ 0
+ROM_DQ13
+Text GLabel 4750 3450 2    50   BiDi ~ 0
+ROM_DQ12
+Text GLabel 4750 3350 2    50   BiDi ~ 0
+ROM_DQ11
+Text GLabel 4750 3250 2    50   BiDi ~ 0
+ROM_DQ10
+Text GLabel 4750 3150 2    50   BiDi ~ 0
+ROM_DQ9
+Text GLabel 4750 3050 2    50   BiDi ~ 0
+ROM_DQ8
+Text GLabel 4750 2850 2    50   BiDi ~ 0
+ROM_DQ7
+Text GLabel 4750 2750 2    50   BiDi ~ 0
+ROM_DQ6
+Text GLabel 4750 2650 2    50   BiDi ~ 0
+ROM_DQ5
+Text GLabel 4750 2550 2    50   BiDi ~ 0
+ROM_DQ4
+Text GLabel 4750 2450 2    50   BiDi ~ 0
+ROM_DQ3
+Text GLabel 4750 2350 2    50   BiDi ~ 0
+ROM_DQ2
+Text GLabel 4750 2250 2    50   BiDi ~ 0
+ROM_DQ1
+Text GLabel 4750 2150 2    50   BiDi ~ 0
+ROM_DQ0
+Text GLabel 2050 4350 0    50   Input ~ 0
+ROM_A22
+Text GLabel 2050 4250 0    50   Input ~ 0
+ROM_A21
+Text GLabel 2050 4150 0    50   Input ~ 0
+ROM_A20
+Text GLabel 2050 4050 0    50   Input ~ 0
+ROM_A19
+Text GLabel 2050 3950 0    50   Input ~ 0
+ROM_A18
+Text GLabel 2050 3850 0    50   Input ~ 0
+ROM_A17
+Text GLabel 2050 3750 0    50   Input ~ 0
+ROM_A16
+Text GLabel 2050 3650 0    50   Input ~ 0
+ROM_A15
+Text GLabel 2050 3550 0    50   Input ~ 0
+ROM_A14
+Text GLabel 2050 3450 0    50   Input ~ 0
+ROM_A13
+Text GLabel 2050 3350 0    50   Input ~ 0
+ROM_A12
+Text GLabel 2050 3250 0    50   Input ~ 0
+ROM_A11
+Text GLabel 2050 3150 0    50   Input ~ 0
+ROM_A10
+Text GLabel 2050 3050 0    50   Input ~ 0
+ROM_A9
+Text GLabel 2050 2950 0    50   Input ~ 0
+ROM_A8
+Text GLabel 2050 2850 0    50   Input ~ 0
+ROM_A7
+Text GLabel 2050 2750 0    50   Input ~ 0
+ROM_A6
+Text GLabel 2050 2650 0    50   Input ~ 0
+ROM_A5
+Text GLabel 2050 2550 0    50   Input ~ 0
+ROM_A4
+Text GLabel 2050 2450 0    50   Input ~ 0
+ROM_A3
+Text GLabel 2050 2350 0    50   Input ~ 0
+ROM_A2
+Text GLabel 2050 2250 0    50   Input ~ 0
+ROM_A1
+Text GLabel 2050 2150 0    50   Input ~ 0
+ROM_A0
+NoConn ~ 4250 4550
+$Comp
+L GND #PWR036
+U 1 1 4BCA30BF
+P 4750 5400
+F 0 "#PWR036" H 4750 5400 30  0001 C CNN
+F 1 "GND" H 4750 5330 30  0001 C CNN
+	1    4750 5400
+	1    0    0    -1  
+$EndComp
+Text GLabel 2050 4750 0    50   Input ~ 0
+ROM_/WE
+Text GLabel 2050 4650 0    50   Input ~ 0
+ROM_/OE
+$Comp
+L C C502
+U 1 1 4BAD3D55
+P 3550 7000
+F 0 "C502" H 3600 7100 50  0000 L CNN
+F 1 "100n" H 3600 6900 50  0000 L CNN
+F 2 "SM0805_FIXEDMASK" H 3550 7000 60  0001 C CNN
+	1    3550 7000
+	1    0    0    -1  
+$EndComp
+$Comp
+L C C511
+U 1 1 4BAD3D53
+P 10150 2000
+F 0 "C511" H 10200 2100 50  0000 L CNN
+F 1 "100n" H 10200 1900 50  0000 L CNN
+F 2 "SM0805_FIXEDMASK" H 10150 2000 60  0001 C CNN
+	1    10150 2000
+	0    -1   1    0   
+$EndComp
+$Comp
+L C C501
+U 1 1 4BAD3D47
+P 3250 7000
+F 0 "C501" H 3300 7100 50  0000 L CNN
+F 1 "100n" H 3300 6900 50  0000 L CNN
+F 2 "SM0805_FIXEDMASK" H 3250 7000 60  0001 C CNN
+	1    3250 7000
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR037
+U 1 1 4BAD3D2B
+P 3550 7300
+F 0 "#PWR037" H 3550 7300 30  0001 C CNN
+F 1 "GND" H 3550 7230 30  0001 C CNN
+	1    3550 7300
+	1    0    0    -1  
+$EndComp
+$Comp
+L +1.8V #PWR038
+U 1 1 4BAD3D27
+P 3550 6700
+F 0 "#PWR038" H 3550 6840 20  0001 C CNN
+F 1 "+1.8V" H 3550 6810 30  0000 C CNN
+	1    3550 6700
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR039
+U 1 1 4BAD3D20
+P 3250 7300
+F 0 "#PWR039" H 3250 7300 30  0001 C CNN
+F 1 "GND" H 3250 7230 30  0001 C CNN
+	1    3250 7300
+	1    0    0    -1  
+$EndComp
+$Comp
+L +3.3V #PWR040
+U 1 1 4BAD3D0B
+P 3250 6700
+F 0 "#PWR040" H 3250 6660 30  0001 C CNN
+F 1 "+3.3V" H 3250 6810 30  0000 C CNN
+	1    3250 6700
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR041
+U 1 1 4BAD33A7
+P 3400 5400
+F 0 "#PWR041" H 3400 5400 30  0001 C CNN
+F 1 "GND" H 3400 5330 30  0001 C CNN
+	1    3400 5400
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR042
+U 1 1 4BAD339F
+P 7650 5000
+F 0 "#PWR042" H 7650 5000 30  0001 C CNN
+F 1 "GND" H 7650 4930 30  0001 C CNN
+	1    7650 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L +1.8V #PWR043
+U 1 1 4BAD32D2
+P 3300 1550
+F 0 "#PWR043" H 3300 1690 20  0001 C CNN
+F 1 "+1.8V" H 3300 1660 30  0000 C CNN
+	1    3300 1550
+	1    0    0    -1  
+$EndComp
+$Comp
+L +3.3V #PWR044
+U 1 1 4BAD32BE
+P 3500 1550
+F 0 "#PWR044" H 3500 1510 30  0001 C CNN
+F 1 "+3.3V" H 3500 1660 30  0000 C CNN
+	1    3500 1550
+	1    0    0    -1  
+$EndComp
+Text Notes 6300 5700 0    60   ~ 0
+4Mbits 45ns SRAM (battery RAM + custom chip work RAM)
+Text Notes 2650 5700 0    60   ~ 0
+128Mbits 70ns PSRAM (ROM area)
+$Comp
+L MT45W8MW16 U501
+U 1 1 4B868602
+P 3400 3450
+F 0 "U501" H 3400 3550 60  0000 C CNN
+F 1 "MT45W8MW16" H 3400 3450 60  0000 C CNN
+F 2 "VFBGA54" H 3400 3450 60  0001 C CNN
+	1    3400 3450
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
--- a/pcb/kicad/RevE2/padreduce.sh
+++ b/pcb/kicad/RevE2/padreduce.sh
@@ -0,0 +1,17 @@
+cp "$1" "$1".bak
+
+sed -e 's/^%ADD\(..\)R/%ADD\1O/g' < "$1" > "$1".tmp1
+
+grep ^%ADD..O "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; Y=${ln:17:8}; X2=`echo $X-.001 | bc -l`; Y2=`echo $Y-.001 | bc -l`; echo $LS`printf '%01.6f' $X2`X`printf '%01.6f' $Y2`*%; done > "$1".tmp2
+
+grep ^%ADD..C "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; X2=`echo $X-.001 | bc -l`; echo $LS`printf '%01.6f' $X2`*%; done >> "$1".tmp2
+
+while read ln; do echo "$ln" | grep '^%ADD' >/dev/null && break; echo "$ln"; done < "$1".tmp1 > "$1"
+
+cat "$1".tmp2 >> "$1"
+
+grep -A100000 'G04 APERTURE END LIST\*' "$1".tmp1 >> "$1"
+
+rm "$1".tmp1 "$1".tmp2
+
+
--- a/pcb/kicad/RevE2/pwr_misc.sch
+++ b/pcb/kicad/RevE2/pwr_misc.sch
--- a/pcb/kicad/RevE2/sd2snes.brd
+++ b/pcb/kicad/RevE2/sd2snes.brd
--- a/pcb/kicad/RevE2/sd2snes.cmp
+++ b/pcb/kicad/RevE2/sd2snes.cmp
--- a/pcb/kicad/RevE2/sd2snes.net
+++ b/pcb/kicad/RevE2/sd2snes.net
--- a/pcb/kicad/RevE2/sd2snes.pro
+++ b/pcb/kicad/RevE2/sd2snes.pro
@@ -0,0 +1,116 @@
+update=Wed 28 Dec 2011 06:55:00 PM CET
+version=1
+last_client=pcbnew
+[general]
+version=1
+[cvpcb]
+version=1
+NetIExt=net
+[cvpcb/libraries]
+EquName1=devcms
+[eeschema]
+version=1
+LibDir=../../kicad
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=50
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=libs/snescart
+LibName32=libs/misc-74
+LibName33=libs/vreg
+LibName34=libs/lpc1754
+LibName35=libs/sd_card
+LibName36=libs/cy62148ev30
+LibName37=libs/mt45w8mw16
+LibName38=libs/cs4344
+LibName39=libs/double_sch_kcom
+LibName40=libs/usb_minib
+LibName41=libs/mic23250
+[pcbnew]
+version=1
+PadDrlX=512
+PadDimH=512
+PadDimV=512
+BoardThickness=630
+TxtPcbV=800
+TxtPcbH=600
+TxtModV=600
+TxtModH=600
+TxtModW=120
+VEgarde=40
+DrawLar=70
+EdgeLar=40
+TxtLar=120
+MSegLar=79
+LastNetListRead=sd2snes.net
+[pcbnew/libraries]
+LibDir=../../kicad
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=libcms
+LibName7=display
+LibName8=valves
+LibName9=led
+LibName10=dip_sockets
+LibName11=libs/mypackages
+LibName12=libs/snescart
+LibName13=libs/sdcard
+LibName14=libs/snail
--- a/pcb/kicad/RevE2/sd2snes.sch
+++ b/pcb/kicad/RevE2/sd2snes.sch
@@ -0,0 +1,94 @@
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:snescart
+LIBS:misc-74
+LIBS:vreg
+LIBS:lpc1754
+LIBS:sd_card
+LIBS:cy62148ev30
+LIBS:mt45w8mw16
+LIBS:cs4344
+LIBS:double_sch_kcom
+LIBS:usb_minib
+LIBS:mic23250
+LIBS:sd2snes-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 6
+Title "sd2snes Mark II"
+Date "2 jan 2012"
+Rev "E2"
+Comp "Maximilian Rehkopf"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Notes Line
+	3650 4200 6150 4200
+Text Notes 3300 3250 0    100  ~ 0
+Changes from Rev.A / TODO:\n [x] remove FPGA from JTAG chain\n [x] remove SNES IRQ_DIR+IRQ, replace with IRQ_OE. IRQ is unidirectional cart -> console\n      (replace 1gate w/ transistor)\n [x] disconnect P2.10 from FPGA, using a different GPIO for IRQ / INIT_B\n [x] add pullup to P2.10\n [ ] add JTAG pullups\n [x] add series resistor for CPU_CLK\n [x] add a jumper in PIC MCLR line to MCU\n [x] change PIC to DIP8 type for easier preprogramming\n [x] change "P1" to "P401" in pin description in silk screen\n [x] filter CIC data lines\n [x] rearrange SD card interface/LEDs on MCU\n [x] RAs for SNES signals?\n [x] reroute/add decoupling capacitors\n [x] filter SNES control signals (RD, WR, PARD, PAWR, CPU_CLK, IRQ)\n [x] replace 4Mbit SRAM with much cheaper TSOP-II type\n [x] add inverse polarity protection\n [x] separate GND plane for DAC\n [ ] separate JTAG pads for FPGA\n [x] add USE_BATT jumper\n [x] move PROG_B to P1.15
+$Sheet
+S 1250 1250 1700 1250
+U 4B6E16F2
+F0 "SNES Slot" 60
+F1 "snesslot.sch" 60
+$EndSheet
+Text Notes 750  7700 0    500  ~ 100
+sd2snes Mark II
+$Sheet
+S 1250 3300 1600 1150
+U 4BAA6ABD
+F0 "Memory" 60
+F1 "memory.sch" 60
+$EndSheet
+$Sheet
+S 8050 1250 1600 1250
+U 4B6ED75B
+F0 "MCU" 60
+F1 "mcu.sch" 60
+$EndSheet
+$Sheet
+S 5900 1250 1600 1250
+U 4B6EC9C3
+F0 "Power Supply / Misc." 60
+F1 "pwr_misc.sch" 60
+$EndSheet
+$Sheet
+S 3650 1250 1650 1250
+U 4B6E18FC
+F0 "FPGA" 60
+F1 "fpga.sch" 60
+$EndSheet
+$EndSCHEMATC
--- a/pcb/kicad/RevE2/snesslot.sch
+++ b/pcb/kicad/RevE2/snesslot.sch
--- a/pcb/kicad/libs/mypackages.mod
+++ b/pcb/kicad/libs/mypackages.mod
@@ -1,4 +1,4 @@
-PCBNEW-LibModule-V1  Wed 14 Sep 2011 12:39:55 AM CEST
+PCBNEW-LibModule-V1  Tue 27 Dec 2011 12:29:40 AM CET
 # encoding utf-8
 $INDEX
 BT_KEYSTONE_1059_20MM
@@ -7,11 +7,14 @@ DIP-36
 HC49US
 LED-3MM-FIXED
 LQFP80-.5
+L_4.2X4.2
 PAD_1x1mm
 PQFP208_ALTPADS
 QFN10-2x2
 QFN10-2x2_LONGPADS
 R_PACK_0804
+R_PACK_0804_LONGPADS
+R_PACK_1206
 SM0805_FIXEDMASK
 SM1210L
 SM1210L_NEW
@@ -23,7 +26,9 @@ TSOP40
 TSOPII-32
 TSOPII-44
 TSSOP10
+TSSOP10_LONGPADS
 TSSOP48
+TSSOP48_LONGPADS
 USB-MINIB-THT
 VFBGA36
 VFBGA48
@@ -4107,41 +4112,6 @@ Of 0.000000 0.000000 0.000000
 Ro 0.000000 0.000000 0.000000
 $EndSHAPE3D
 $EndMODULE  SM1210L_NEW
-$MODULE LED-3MM-FIXED
-Po 0 0 0 15 4D251EA9 00000000 ~~
-Li LED-3MM-FIXED
-Cd LED 3mm - Lead pitch 100mil (2,54mm)
-Kw LED led 3mm 3MM 100mil 2,54mm
-Sc 00000000
-AR /4B6ED75B/4C0DA78D
-Op 0 0 0
-At VIRTUAL
-T0 -300 -2125 320 320 0 70 N V 21 N"D403"
-T1 25 3575 320 320 2700 70 N V 21 N"LED_2mA_1.7V,_red"
-DS 669 669 669 394 80 21
-DS 669 -669 669 -394 80 21
-DA 0 0 669 669 2700 80 21
-$PAD
-Sh "1" C 660 660 0 0 0
-Dr 400 0 0
-At STD N 00E8FFFF
-Ne 1 "+3.3V"
-Po -500 0
-$EndPAD
-$PAD
-Sh "2" C 660 660 0 0 0
-Dr 400 0 0
-At STD N 00E8FFFF
-Ne 2 "N-000262"
-Po 500 0
-$EndPAD
-$SHAPE3D
-Na "libs/led3_vertical_red.wrl"
-Sc 1.000000 1.000000 1.000000
-Of 0.000000 0.000000 0.000000
-Ro 0.000000 0.000000 0.000000
-$EndSHAPE3D
-$EndMODULE  LED-3MM-FIXED
 $MODULE HC49US
 Po 0 0 0 15 4D2590A9 00000000 ~~
 Li HC49US
@@ -5668,4 +5638,638 @@ Ne 33 "N-000035"
 Po -3828 1870
 $EndPAD
 $EndMODULE  TSOP40
+$MODULE R_PACK_1206
+Po 0 0 0 15 4EF2E0E8 00000000 ~~
+Li R_PACK_1206
+Sc 00000000
+AR R_PACK_1206
+Op 0 0 0
+T0 0 0 600 600 0 120 N V 21 N "R_PACK_1206"
+T1 0 0 600 600 0 120 N V 21 N "VAL**"
+DS -866 -827 866 -827 79 21
+DS 866 -827 866 827 79 21
+DS 866 827 -866 827 79 21
+DS -866 827 -866 -827 79 21
+$PAD
+Sh "1" R 248 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -510 384
+$EndPAD
+$PAD
+Sh "2" R 173 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -157 384
+$EndPAD
+$PAD
+Sh "3" R 173 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 157 384
+$EndPAD
+$PAD
+Sh "4" R 248 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 510 384
+$EndPAD
+$PAD
+Sh "5" R 248 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 510 -384
+$EndPAD
+$PAD
+Sh "6" R 173 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 157 -384
+$EndPAD
+$PAD
+Sh "7" R 173 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -157 -384
+$EndPAD
+$PAD
+Sh "8" R 248 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -510 -384
+$EndPAD
+$EndMODULE  R_PACK_1206
+$MODULE R_PACK_0804_LONGPADS
+Po 0 0 0 15 4EF2E2A7 00000000 ~~
+Li R_PACK_0804_LONGPADS
+Sc 00000000
+AR
+Op 0 0 0
+T0 0 0 320 320 0 70 N V 21 N "R_PACK_0804"
+T1 0 0 320 320 0 70 N V 21 N "VAL**"
+DS 551 591 551 -591 79 21
+DS -551 -591 -551 591 79 21
+DS -551 -591 551 -591 79 21
+DS 551 591 -551 591 79 21
+$PAD
+Sh "7" R 118 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -98 -276
+$EndPAD
+$PAD
+Sh "6" R 118 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 98 -276
+$EndPAD
+$PAD
+Sh "2" R 118 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -98 276
+$EndPAD
+$PAD
+Sh "3" R 118 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 98 276
+$EndPAD
+$PAD
+Sh "8" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -335 -276
+$EndPAD
+$PAD
+Sh "5" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 335 -276
+$EndPAD
+$PAD
+Sh "4" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 335 276
+$EndPAD
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -335 276
+$EndPAD
+$EndMODULE  R_PACK_0804_LONGPADS
+$MODULE TSSOP10_LONGPADS
+Po 0 0 0 15 4EF2E58B 00000000 ~~
+Li TSSOP10_LONGPADS
+Sc 00000000
+AR
+Op 0 0 0
+T0 0 0 600 600 0 120 N V 21 N "Test"
+T1 0 0 600 600 0 120 N V 21 N "VAL**"
+DC -394 394 -315 394 60 21
+DS -590 -590 590 -590 60 21
+DS 590 -590 590 590 60 21
+DS -590 590 590 590 60 21
+DS -590 -590 -590 590 60 21
+$PAD
+Sh "1" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -393 965
+$EndPAD
+$PAD
+Sh "2" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -196 965
+$EndPAD
+$PAD
+Sh "3" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 0 965
+$EndPAD
+$PAD
+Sh "4" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 196 965
+$EndPAD
+$PAD
+Sh "5" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 393 965
+$EndPAD
+$PAD
+Sh "6" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 393 -965
+$EndPAD
+$PAD
+Sh "7" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 196 -965
+$EndPAD
+$PAD
+Sh "8" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 0 -965
+$EndPAD
+$PAD
+Sh "9" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -196 -965
+$EndPAD
+$PAD
+Sh "10" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -393 -965
+$EndPAD
+$EndMODULE  TSSOP10_LONGPADS
+$MODULE TSSOP48_LONGPADS
+Po 0 0 0 15 4B6E17E6 00000000 ~~
+Li TSSOP48_LONGPADS
+Sc 00000000
+AR
+Op 0 0 0
+T0 0 -551 600 600 0 120 N V 21 N "Test"
+T1 0 630 600 600 0 120 N V 21 N "VAL**"
+DC -2205 945 -2087 945 40 21
+DS -2460 -1200 2460 -1200 47 21
+DS 2460 -1200 2460 1200 47 21
+DS -2460 1200 2460 1200 47 21
+DS -2460 -1200 -2460 1200 47 21
+$PAD
+Sh "1" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -2263 1614
+$EndPAD
+$PAD
+Sh "2" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -2066 1614
+$EndPAD
+$PAD
+Sh "3" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1870 1614
+$EndPAD
+$PAD
+Sh "4" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1673 1614
+$EndPAD
+$PAD
+Sh "5" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1476 1614
+$EndPAD
+$PAD
+Sh "6" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1279 1614
+$EndPAD
+$PAD
+Sh "7" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1082 1614
+$EndPAD
+$PAD
+Sh "8" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -885 1614
+$EndPAD
+$PAD
+Sh "9" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -688 1614
+$EndPAD
+$PAD
+Sh "10" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -492 1614
+$EndPAD
+$PAD
+Sh "11" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -295 1614
+$EndPAD
+$PAD
+Sh "12" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -98 1614
+$EndPAD
+$PAD
+Sh "13" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 98 1614
+$EndPAD
+$PAD
+Sh "14" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 295 1614
+$EndPAD
+$PAD
+Sh "15" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 492 1614
+$EndPAD
+$PAD
+Sh "16" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 688 1614
+$EndPAD
+$PAD
+Sh "17" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 885 1614
+$EndPAD
+$PAD
+Sh "18" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1082 1614
+$EndPAD
+$PAD
+Sh "19" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1279 1614
+$EndPAD
+$PAD
+Sh "20" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1476 1614
+$EndPAD
+$PAD
+Sh "21" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1673 1614
+$EndPAD
+$PAD
+Sh "22" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1870 1614
+$EndPAD
+$PAD
+Sh "23" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 2066 1614
+$EndPAD
+$PAD
+Sh "24" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 2263 1614
+$EndPAD
+$PAD
+Sh "25" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 2263 -1614
+$EndPAD
+$PAD
+Sh "26" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 2066 -1614
+$EndPAD
+$PAD
+Sh "27" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1870 -1614
+$EndPAD
+$PAD
+Sh "28" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1673 -1614
+$EndPAD
+$PAD
+Sh "29" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1476 -1614
+$EndPAD
+$PAD
+Sh "30" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1279 -1614
+$EndPAD
+$PAD
+Sh "31" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1082 -1614
+$EndPAD
+$PAD
+Sh "32" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 885 -1614
+$EndPAD
+$PAD
+Sh "33" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 688 -1614
+$EndPAD
+$PAD
+Sh "34" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 492 -1614
+$EndPAD
+$PAD
+Sh "35" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 295 -1614
+$EndPAD
+$PAD
+Sh "36" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 98 -1614
+$EndPAD
+$PAD
+Sh "37" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -98 -1614
+$EndPAD
+$PAD
+Sh "38" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -295 -1614
+$EndPAD
+$PAD
+Sh "39" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -492 -1614
+$EndPAD
+$PAD
+Sh "40" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -688 -1614
+$EndPAD
+$PAD
+Sh "41" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -885 -1614
+$EndPAD
+$PAD
+Sh "42" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1082 -1614
+$EndPAD
+$PAD
+Sh "43" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1279 -1614
+$EndPAD
+$PAD
+Sh "44" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1476 -1614
+$EndPAD
+$PAD
+Sh "45" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1673 -1614
+$EndPAD
+$PAD
+Sh "46" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1870 -1614
+$EndPAD
+$PAD
+Sh "47" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -2066 -1614
+$EndPAD
+$PAD
+Sh "48" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -2263 -1614
+$EndPAD
+$EndMODULE  TSSOP48_LONGPADS
+$MODULE L_4.2X4.2
+Po 0 0 0 15 4EF777D2 00000000 ~~
+Li L_4.2X4.2
+Sc 00000000
+AR
+Op 0 0 0
+T0 0 0 600 600 0 120 N V 21 N "L_4.2X4.2"
+T1 0 0 600 600 0 120 N V 21 N "VAL**"
+DS -1024 -984 1024 -984 79 21
+DS 1024 -984 1024 984 79 21
+DS 1024 984 -1024 984 79 21
+DS -1024 984 -1024 -984 79 21
+$PAD
+Sh "1" R 591 1654 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -571 0
+$EndPAD
+$PAD
+Sh "2" R 591 1654 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 571 0
+$EndPAD
+$EndMODULE  L_4.2X4.2
+$MODULE LED-3MM-FIXED
+Po 0 0 0 15 4EF9035D 00000000 ~~
+Li LED-3MM-FIXED
+Cd LED 3mm - Lead pitch 100mil (2,54mm)
+Kw LED led 3mm 3MM 100mil 2,54mm
+Sc 00000000
+AR /4B6ED75B/4C0DA78D
+Op 0 0 0
+At VIRTUAL 
+T0 -300 -2125 320 320 0 70 N V 21 N "D403"
+T1 25 3575 320 320 2700 70 N V 21 N "LED_2mA_1.7V,_red"
+DS 669 669 669 394 80 21
+DS 669 -669 669 -394 80 21
+DA 0 0 669 669 2700 80 21
+$PAD
+Sh "1" C 660 660 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 1 "+3.3V"
+Po -500 0
+$EndPAD
+$PAD
+Sh "2" C 660 660 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000262"
+Po 500 0
+$EndPAD
+$SHAPE3D
+Na "libs/led3_vertical_red.wrl"
+Sc 1.000000 1.000000 1.000000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  LED-3MM-FIXED
 $EndLIBRARY
--- a/pcb/kicad/libs/sdcard.bak
+++ b/pcb/kicad/libs/sdcard.bak
@@ -1,7 +1,8 @@
-PCBNEW-LibModule-V1  Mon 26 Jul 2010 02:13:00 PM CEST
+PCBNEW-LibModule-V1  Tue 27 Dec 2011 01:25:51 AM CET
+# encoding utf-8
 $INDEX
-SD-RSMT-2-MQ-WF
 HRS-DM1AA
+SD-RSMT-2-MQ-WF
 $EndINDEX
 $MODULE SD-RSMT-2-MQ-WF
 Po 0 0 0 15 4C4D74E3 00000000 ~~
@@ -124,40 +125,39 @@ Po 3740 709
 $EndPAD
 $EndMODULE  SD-RSMT-2-MQ-WF
 $MODULE HRS-DM1AA
-Po 0 0 0 15 4C4D706D 00000000 ~~
+Po 0 0 0 15 4EF9108C 00000000 ~~
 Li HRS-DM1AA
 Sc 00000000
-AR 
+AR HRS-DM1AA
 Op 0 0 0
-T0 0 0 300 300 0 60 N V 21 N"HRS-DM1AA"
-T1 0 0 300 300 0 60 N V 21 N"VAL**"
-DS -5906 4725 -5906 4686 120 21
-DS 5905 6025 5905 4686 120 21
-DS 5905 -2637 5905 3584 120 21
-DS 5905 -5983 5905 -3779 120 21
+T0 0 0 300 300 0 60 N V 21 N "HRS-DM1AA"
+T1 0 0 300 300 0 60 N V 21 N "VAL**"
+DS 4134 -5984 5512 -5984 120 21
+DS 5512 6024 -5512 6024 120 21
+DS -5512 -5984 -4685 -5984 120 21
+DS -5512 4685 -5512 6024 120 21
+DS 5511 6025 5511 4686 120 21
+DS 5511 -2637 5511 3584 120 21
+DS 5511 -5983 5511 -3779 120 21
 DS 4133 -5511 3779 -5511 120 21
 DS -4686 -5511 -4529 -5511 120 21
-DS -5906 6025 -5906 4725 120 21
-DS -5906 2521 -5906 2796 120 21
-DS -5906 -983 -5906 1773 120 21
-DS -5906 -2637 -5906 -1731 120 21
-DS -5906 -5983 -5906 -3779 120 21
-DS -5906 -5983 -4686 -5983 120 21
+DS -5512 2521 -5512 2796 120 21
+DS -5512 -983 -5512 1773 120 21
+DS -5512 -2637 -5512 -1731 120 21
+DS -5512 -5983 -5512 -3779 120 21
 DS -4686 -5983 -4686 -5511 120 21
 DS 4133 -5511 4133 -5983 120 21
-DS 4133 -5983 5905 -5983 120 21
-DS 5905 6025 -5906 6025 120 21
 $PAD
-Sh "~" C 512 512 0 0 0
+Sh "~" C 510 510 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At STD N 0000FFFF
 Ne 0 ""
 Po -4686 -4999
 $EndPAD
 $PAD
-Sh "~" C 512 512 0 0 0
+Sh "~" C 510 510 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At STD N 0000FFFF
 Ne 0 ""
 Po 4133 -4999
 $EndPAD
--- a/pcb/kicad/libs/sdcard.mod
+++ b/pcb/kicad/libs/sdcard.mod
@@ -1,7 +1,8 @@
-PCBNEW-LibModule-V1  Mon 26 Jul 2010 09:33:33 PM CEST
+PCBNEW-LibModule-V1  Tue 27 Dec 2011 12:52:27 PM CET
+# encoding utf-8
 $INDEX
-SD-RSMT-2-MQ-WF
 HRS-DM1AA
+SD-RSMT-2-MQ-WF
 $EndINDEX
 $MODULE SD-RSMT-2-MQ-WF
 Po 0 0 0 15 4C4D74E3 00000000 ~~
@@ -124,13 +125,13 @@ Po 3740 709
 $EndPAD
 $EndMODULE  SD-RSMT-2-MQ-WF
 $MODULE HRS-DM1AA
-Po 0 0 0 15 4C4DE307 00000000 ~~
+Po 0 0 0 15 4EF9108C 00000000 ~~
 Li HRS-DM1AA
 Sc 00000000
-AR 
+AR HRS-DM1AA
 Op 0 0 0
-T0 0 0 300 300 0 60 N V 21 N"HRS-DM1AA"
-T1 0 0 300 300 0 60 N V 21 N"VAL**"
+T0 0 0 300 300 0 60 N V 21 N "HRS-DM1AA"
+T1 0 0 300 300 0 60 N V 21 N "VAL**"
 DS 4134 -5984 5512 -5984 120 21
 DS 5512 6024 -5512 6024 120 21
 DS -5512 -5984 -4685 -5984 120 21
@@ -149,14 +150,14 @@ DS 4133 -5511 4133 -5983 120 21
 $PAD
 Sh "~" C 512 512 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At STD N 0000FFFF
 Ne 0 ""
 Po -4686 -4999
 $EndPAD
 $PAD
 Sh "~" C 512 512 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At STD N 0000FFFF
 Ne 0 ""
 Po 4133 -4999
 $EndPAD
--- a/snes/Makefile
+++ b/snes/Makefile
@@ -1,19 +1,23 @@
-OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 # gfx.o65 # vars.o65
+OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 # gfx.o65 # vars.o65

-all: menu.bin
+all: clean menu.bin map

 smc: menu.bin
 	cat menu.bin sd2snes.rom > menu.smc
+
+map: menu.bin
+	utils/mkmap.sh $(OBJS)
+
 menu.bin: $(OBJS)
-	sneslink -fsmc -o $@ $^
+	sneslink -fsmc -o $@ $^ 2>&1 | tee link.log

 # Generic rule to create .o65 out from .a65
 %.o65: %.a65
-	snescom -J -Wall -o $@ $<
+	snescom -J -Wall -o $@ $< 2>&1 | tee $@.log

 # Generic rule to create .ips out from .a65
 %.ips: %.a65
-	snescom -I -J -Wall -o $@ $<
+	snescom -I -J -Wall -o $@ $< 2>&1 | tee $@.log

 clean:
 	rm -f *.ips *.o65 *~ menu.bin
--- a/snes/const.a65
+++ b/snes/const.a65
@@ -136,8 +136,10 @@ window_nh	.byt 24
 window_sh	.byt 25
 window_wv	.byt 26
 window_ev	.byt 27
-text_clkset	.byt 28,"Please set the clock.", 29,0
-text_buttonB	.byt "Dpad: sel/chg, B: OK", 0
+window_tl	.byt 28
+window_tr	.byt 29
+text_clkset	.byt "Please set the clock.", 0
+text_buttonB	.byt "Dpad: sel/chg, A: OK", 0
 time_win_x	.byt 18
 time_win_y	.byt 15
 time_win_w	.byt 27
@@ -146,7 +148,11 @@ main_win_x	.byt 18
 main_win_y	.byt 11
 main_win_w	.byt 27
 main_win_h	.byt 13
-text_mainmenu	.byt 28,"Main Menu", 29, 0
+text_mainmenu	.byt "Main Menu", 0
+sysinfo_win_x	.byt 10
+sysinfo_win_y	.byt 9
+sysinfo_win_w	.byt 43
+sysinfo_win_h	.byt 17

 text_mm_file		.byt "File Browser", 0
 text_mm_last		.byt "Run last game", 0
@@ -154,5 +160,5 @@ text_mm_time		.byt "Set Clock", 0
 text_mm_scic		.byt "Enable SuperCIC", 0
 text_mm_vmode_menu	.byt "Menu video mode", 0
 text_mm_vmode_game	.byt "Game video mode", 0
-
-text_statusbar_keys	.byt "B:Select A:Back X:Menu", 0
+text_mm_sysinfo		.byt "System Information", 0
+text_statusbar_keys	.byt "A:Select B:Back X:Menu", 0
--- a/snes/data.a65
+++ b/snes/data.a65
@@ -1,3 +1,4 @@
+*=$7E0000
 .data
 ;don't anger the stack!
 dirptr_addr	.word	0
@@ -77,6 +78,7 @@ time_y10	.byt 0
 time_y100	.byt 0
 time_sel	.byt 0
 time_exit	.byt 0
+time_cancel	.byt 0
 time_ptr	.byt 0
 time_tmp	.byt 0
 ;--
--- a/snes/header.a65
+++ b/snes/header.a65
@@ -1,6 +1,16 @@
-; This file is part of the snescom-asm demo - a demo of how to build a SNES program.
+; This file is a modified version of the header.a65 file from:
+; snescom-asm demo - a demo of how to build a SNES program.
 ; See http://bisqwit.iki.fi/source/snescom.html for details.

+; fill whole area beforehand so the linker does not create multiple
+; objects from it. (necessary for map creation)
+
+*= $C0FF00
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+
 ; Begin assembling to this address.
 *= $C0FF00

--- a/snes/mainmenu.a65
+++ b/snes/mainmenu.a65
@@ -1,6 +1,6 @@
 #include "memmap.i65"
 ;number of menu entries
-main_entries    .byt 1
+main_entries    .byt 2
 ;menu entry data
 main_enttab     ;Set Clock
 		.word !text_mm_time
@@ -8,6 +8,11 @@ main_enttab     ;Set Clock
                .word !time_init-1
                .byt ^time_init
                .byt 1, 0
+                ;System Information
+                .word !text_mm_sysinfo
+                .byt ^text_mm_sysinfo
+                .word !show_sysinfo-1
+		.byt ^show_sysinfo
                ;SuperCIC
 		.word !text_mm_scic
                .byt ^text_mm_scic
@@ -115,13 +120,13 @@ mm_menuloop
 	and pad1trig+1
 	bne mmkey_b
 	bra mm_menuloop
-mmkey_a
+mmkey_b
 	jsr restore_screen
 	plp
 	rts

-mmkey_b
-	jsr mmkey_b_2
+mmkey_a
+	jsr mmkey_a_2
 	jmp mm_redraw

 mmkey_down
@@ -151,10 +156,10 @@ mmkey_up_2
 +
 	rts

-mmkey_b_2
+mmkey_a_2
 	jsr restore_screen
 	phk			; push return bank for subroutine
-	per mmkey_b_2_return-1	; push return addr for subroutine
+	per mmkey_a_2_return-1	; push return addr for subroutine
 	xba
 	lda #$00
 	xba
@@ -170,7 +175,7 @@ mmkey_b_2
 	pha			; push subroutine addr
 	sep #$20 : .as
 	rtl			; jump to subroutine
-mmkey_b_2_return
+mmkey_a_2_return
 	rts

 mm_do_refresh
--- a/snes/memmap.i65
+++ b/snes/memmap.i65
@@ -20,5 +20,8 @@
 #define AVR_CMD		$307000
 #define AVR_PARAM	$307004
 #define RTC_STATUS	$307100
+#define SYSINFO_BLK	$307110

 #define ROOT_DIR	$C10000
+
+#define CMD_SYSINFO	$03
--- a/snes/menu.a65
+++ b/snes/menu.a65
@@ -210,11 +210,12 @@ redraw_filelist_loop
 redraw_filelist_dirend
 	dey                        ; recover last valid direntry number
 	dey                        ; (we had 2x iny of the direntry pointer above,
+	beq +
 	dey                        ;  so account for those too)
 	dey
 	dey
 	dey
-	sty dirend_idx             ; dirend_idx <- last valid directory entry.
+	sty dirend_idx             ; dirend_idx <- last valid directory entry.
 	lda #$01                   ; encountered during redraw, so must be on screen
 	sta dirend_onscreen
 	bra redraw_filelist_out
@@ -441,7 +442,7 @@ menu_key_right:
 	sep #$20 : .as
 	rts

-menu_key_b:
+menu_key_a:
 	jsr select_item
 	rts

@@ -455,15 +456,15 @@ do_setup448
 	jsr setup_448
 	rts

-menu_key_a:
+menu_key_b:
 	rep #$20 : .al
 	lda dirstart_addr
-	beq skip_key_a
+	beq skip_key_b
 	sta dirptr_addr
 	lda #$0000
 	sta menu_sel
 	bra select_item
-skip_key_a
+skip_key_b
 	sep #$20 : .as
 	rts

--- a/snes/text.a65
+++ b/snes/text.a65
@@ -1,5 +1,6 @@
 .text
 #include "memmap.i65"
+.byt "===HIPRINT==="
 hiprint:
 	sep #$20 : .as
 	lda print_count
@@ -53,7 +54,9 @@ print_loop
 	phx	; source addr
 print_loop_inner
 	lda !0,x
-	asl
+	bne +
+	jmp print_end2
+	asl
 	sta @$2180
 	lda @print_pal
 	asl
@@ -81,6 +84,7 @@ print_loop2
 	lda @print_count
 	dec
 	sta @print_count_tmp
+	beq print_end2
 	lda #$00
 	pha
 	plb
@@ -100,7 +104,9 @@ print_loop2
 	plb
 print_loop2_inner
 	lda !0,x
-	asl
+	bne +
+	jmp print_end
+	asl
 	sta @$2180
 	lda @print_pal
 	asl
@@ -124,6 +130,10 @@ print_loop2_inner
 	beq print_end
 	bmi print_end
 	bra print_loop2_inner
+print_end2 ; clean up the stack (6 bytes)
+	ply
+	ply
+	ply
 print_end
 	lda #$00
 	pha
@@ -157,7 +167,7 @@ loprint:
 	sta $2183
 	ldx !print_src
 	lda !print_bank
-	pha 
+	pha
 	plb
 loprint_loop_inner
 	lda !0,x
@@ -257,16 +267,39 @@ draw_window:
 	jsr hiprint

 ; print window title
+	lda print_x
+	pha
 	inc print_x
 	inc print_x
+	lda #^window_tl
+	sta print_bank
+	ldx #!window_tl
+	stx print_src
+	lda #$01
+	sta print_count
+	jsr hiprint
+	inc print_x
 	lda window_tbank
 	sta print_bank
 	ldx window_taddr
 	stx print_src
+	lda window_w
+	sta print_count
 	jsr hiprint
-	dec print_x
-	dec print_x
-
+	lda print_done
+	adc print_x
+	sta print_x
+	lda #^window_tr
+	sta print_bank
+	ldx #!window_tr
+	stx print_src
+	lda #$01
+	sta print_count
+	jsr hiprint
+	lda window_w
+	sta print_count
+	pla
+	sta print_x
 ; draw left+right borders + space inside window
 	lda #^stringbuf
 	sta print_bank
--- a/snes/time.a65
+++ b/snes/time.a65
@@ -2,7 +2,7 @@
 #include "dma.i65"

 timebox_data
-        ; string offset, selection width, bcdtime offset, 1s limit, 10s limit
+        ; string offset, selection width, bcdtime offset
 	.byt  0, 4, 9
 	.byt  5, 2, 8
 	.byt  8, 2, 6
@@ -46,6 +46,7 @@ time_init:
 	jsr gettime
 	stz time_sel
 	stz time_exit
+	stz time_cancel
 	lda #^text_buttonB
 	sta print_bank
 	ldx #!text_buttonB
@@ -120,17 +121,29 @@ timeloop1
 	lda #$80
 	and pad1trig+1
 	bne tkey_b
+	lda #$80
+	and pad1trig
+	bne tkey_a
 	; do stuff
 	lda time_exit
-	beq timeloop1
+	bne timesave
 	; set clock
+	lda time_cancel
+	bne timenosave
+	beq timeloop1
+timesave
 	jsr settime
+timenosave
 	; restore text area
 	jsr restore_screen
 	plp
 	rtl

 tkey_b
+	inc time_cancel
+	jmp time_update
+
+tkey_a
 	inc time_exit
 	jmp time_update

--- a/snes/utils/mkmap.sh
+++ b/snes/utils/mkmap.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+args=("$@")
+objcount=0
+
+grep object_ link.log | \
+sed -e 's/object_//g; s/_code//g; s/_data//g' | \
+while read obj; do
+  objcount=$((objcount+1))
+  read base idx <<< "$obj"
+  base="0x${base}"
+  fn=${args[$idx-1]}
+  echo ======$fn, base=$base====== > ${fn%%.*}.map
+  sed -e '/^Externs/,$d;/^Labels/d' < $fn.log | \
+  while read line; do
+    read addr label <<< "$line"
+    addr="0x$addr"
+    decaddr=`printf "%d" $addr`
+    [ "$decaddr" -gt "65535" ] && base=0
+    ea=`printf "%X" $((base+addr))`
+    echo $ea $label >> ${fn%%.*}.map
+  done
+done
+
--- a/src/Makefile
+++ b/src/Makefile
@@ -55,7 +55,7 @@ TARGET = $(OBJDIR)/sd2snes


 # List C source files here. (C dependencies are automatically generated.)
-SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c crc16.c
+SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c crc16.c sysinfo.c

 # usbcontrol.c usb_hid.c usbhw_lpc.c usbinit.c usbstdreq.c

--- a/src/bootldr/clock.c
+++ b/src/bootldr/clock.c
@@ -14,8 +14,8 @@ void clock_disconnect() {

 void clock_init() {

-/* set flash access time to 5 clks (80<f<=100MHz) */
-  setFlashAccessTime(5);
+/* set flash access time to 6 clks (safe setting) */
+  setFlashAccessTime(6);

 /* setup PLL0 for ~44100*256*8 Hz
   Base clock: 12MHz
--- a/src/bootldr/config.h
+++ b/src/bootldr/config.h
@@ -56,7 +56,7 @@
 #define CONFIG_UART_PCLKDIV       1
 #define CONFIG_UART_TX_BUF_SHIFT  8
 #define CONFIG_UART_BAUDRATE      921600
-//#define CONFIG_UART_DEADLOCKABLE
+#define CONFIG_UART_DEADLOCKABLE

 #define SSP_CLK_DIVISOR_FAST 2
 #define SSP_CLK_DIVISOR_SLOW 250
--- a/src/bootldr/ffconf.h
+++ b/src/bootldr/ffconf.h
@@ -14,7 +14,7 @@
 / Function and Buffer Configurations
 /----------------------------------------------------------------------------*/

-#define	_FS_TINY	0		/* 0:Normal or 1:Tiny */
+#define	_FS_TINY	1		/* 0:Normal or 1:Tiny */
 /* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
 /  object instead of the sector buffer in the individual file object for file
 /  data transfer. This reduces memory consumption 512 bytes each file object. */
@@ -57,7 +57,7 @@
 / Locale and Namespace Configurations
 /----------------------------------------------------------------------------*/

-#define _CODE_PAGE	1252
+#define _CODE_PAGE	1
 /* The _CODE_PAGE specifies the OEM code page to be used on the target system.
 /  Incorrect setting of the code page can cause a file open failure.
 /
--- a/src/bootldr/iap.c
+++ b/src/bootldr/iap.c
@@ -72,10 +72,12 @@ FLASH_RES check_flash() {
 }

 IAP_RES iap_wrap(uint32_t *iap_cmd, uint32_t *iap_res) {
-  NVIC_DisableIRQ(RIT_IRQn);
-  NVIC_DisableIRQ(UART_IRQ);
+//  NVIC_DisableIRQ(RIT_IRQn);
+//  NVIC_DisableIRQ(UART_IRQ);
+  for(volatile int i=0; i<2048; i++);
  iap_entry(iap_cmd, iap_res);
-  NVIC_EnableIRQ(UART_IRQ);
+  for(volatile int i=0; i<2048; i++);
+//  NVIC_EnableIRQ(UART_IRQ);
  return iap_res[0];
 }

@@ -153,12 +155,16 @@ FLASH_RES flash_file(uint8_t *filename) {

    writeled(1);
    DBG_BL printf("erasing flash...\n");
+    DBG_UART uart_putc('P');
    if((res = iap_prepare_for_write(FW_START / 0x1000, FLASH_SECTORS)) != CMD_SUCCESS) {
      DBG_BL printf("error %ld while preparing for erase\n", res);
+      DBG_UART uart_putc('X');
      return ERR_FLASHPREP;
    };
+    DBG_UART uart_putc('E');
    if((res = iap_erase(FW_START / 0x1000, FLASH_SECTORS)) != CMD_SUCCESS) {
      DBG_BL printf("error %ld while erasing\n", res);
+      DBG_UART uart_putc('X');
      return ERR_FLASHERASE;
    }
    DBG_BL printf("writing... @%08lx\n", flash_addr);
@@ -174,18 +180,23 @@ FLASH_RES flash_file(uint8_t *filename) {
      DBG_BL printf("current_sec=%d flash_addr=%08lx\n", current_sec, flash_addr);
      DBG_UART uart_putc('.');
      if(current_sec < (FW_START / 0x1000)) return ERR_FLASH;
+      DBG_UART uart_putc(current_sec["0123456789ABCDEFGH"]);
+      DBG_UART uart_putc('p');
      if((res = iap_prepare_for_write(current_sec, current_sec)) != CMD_SUCCESS) {
        DBG_BL printf("error %ld while preparing sector %d for write\n", res, current_sec);
+        DBG_UART uart_putc('X');
        return ERR_FLASH;
      }
+      DBG_UART uart_putc('w');
      if((res = iap_ram2flash(flash_addr, file_buf, 512)) != CMD_SUCCESS) {
        DBG_BL printf("error %ld while writing to address %08lx (sector %d)\n", res, flash_addr, current_sec);
+        DBG_UART uart_putc('X');
        return ERR_FLASH;
      }
    }
    if(total_read != (file_header.size + 0x100)) {
      DBG_BL printf("wrote less data than expected! (%08lx vs. %08lx)\n", total_read, file_header.size);
-      DBG_UART uart_putc('X');
+//      DBG_UART uart_putc('X');
      return ERR_FILECHK;
    }
    writeled(0);
--- a/src/bootldr/timer.c
+++ b/src/bootldr/timer.c
@@ -18,32 +18,6 @@ extern volatile int sd_changed;
 volatile tick_t ticks;
 volatile int wokefromrit;

-void __attribute__((weak,noinline)) SysTick_Hook(void) {
-  /* Empty function for hooking the systick handler */
-}
-
-/* Systick interrupt handler */
-void SysTick_Handler(void) {
-  ticks++;
-  static uint16_t sdch_state = 0;
-  sdch_state = (sdch_state << 1) | SDCARD_DETECT | 0xe000;
-  if((sdch_state == 0xf000) || (sdch_state == 0xefff)) {
-    sd_changed = 1;
-  }
-  sdn_changed();
-  SysTick_Hook();
-}
-
-void __attribute__((weak,noinline)) RIT_Hook(void) {
-}
-
-void RIT_IRQHandler(void) {
-  LPC_RIT->RICTRL = BV(RITINT);
-  NVIC_ClearPendingIRQ(RIT_IRQn);
-  wokefromrit = 1;
-  RIT_Hook();
-}
-
 void timer_init(void) {
  /* turn on power to RIT */
  BITBAND(LPC_SC->PCONP, PCRIT) = 1;
@@ -54,8 +28,6 @@ void timer_init(void) {
  /* PCLK = CCLK */
  BITBAND(LPC_SC->PCLKSEL1, 26) = 1;
  BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1;
-  /* enable SysTick */
-  SysTick_Config((SysTick->CALIB & SysTick_CALIB_TENMS_Msk));
 }

 void delay_us(unsigned int time) {
@@ -84,21 +56,3 @@ void delay_ms(unsigned int time) {
  LPC_RIT->RICTRL = 0;
 }

-void sleep_ms(unsigned int time) {
-
-  wokefromrit = 0;
-  /* Prepare RIT */
-  LPC_RIT->RICOUNTER = 0;
-  LPC_RIT->RICOMPVAL = (CONFIG_CPU_FREQUENCY / 1000) * time;
-  LPC_RIT->RICTRL    = BV(RITEN) | BV(RITINT);
-  NVIC_EnableIRQ(RIT_IRQn);
-
-  /* Wait until RIT signals an interrupt */
-//uart_putc(';');
-  while(!wokefromrit) {
-    __WFI();
-  }
-  NVIC_DisableIRQ(RIT_IRQn);
-  /* Disable RIT */
-  LPC_RIT->RICTRL = BV(RITINT);
-}
--- a/src/bootldr/uart.c
+++ b/src/bootldr/uart.c
@@ -74,65 +74,14 @@
  }
 }
 */
-static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT];
+//static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT];
 static volatile unsigned int read_idx,write_idx;

-void UART_HANDLER(void) {
-  int iir = UART_REGS->IIR;
-  if (!(iir & 1)) {
-    /* Interrupt is pending */
-    switch (iir & 14) {
-#if CONFIG_UART_NUM == 1
-    case 0: /* modem status */
-      (void) UART_REGS->MSR; // dummy read to clear
-      break;
-#endif
-
-    case 2: /* THR empty - send */
-      if (read_idx != write_idx) {
-        int maxchars = 16;
-        while (read_idx != write_idx && --maxchars > 0) {
-          UART_REGS->THR = (unsigned char)txbuf[read_idx];
-          read_idx = (read_idx+1) & (sizeof(txbuf)-1);
-        }
-        if (read_idx == write_idx) {
-          /* buffer empty - turn off THRE interrupt */
-          BITBAND(UART_REGS->IER, 1) = 0;
-        }
-      }
-      break;
-      
-    case 12: /* RX timeout */
-    case  4: /* data received - not implemented yet */
-      (void) UART_REGS->RBR; // dummy read to clear
-      break;
-
-    case 6: /* RX error */
-      (void) UART_REGS->LSR; // dummy read to clear
-
-    default: break;
-    }
-  }
-}
-
 void uart_putc(char c) {
  if (c == '\n')
    uart_putc('\r');
-
-  unsigned int tmp = (write_idx+1) & (sizeof(txbuf)-1) ;
-
-  if (read_idx == write_idx && (BITBAND(UART_REGS->LSR, 5))) {
-    /* buffer empty, THR empty -> send immediately */
-    UART_REGS->THR = (unsigned char)c;
-  } else {
-#ifdef CONFIG_UART_DEADLOCKABLE
-    while (tmp == read_idx) ;
-#endif
-    BITBAND(UART_REGS->IER, 1) = 0; // turn off UART interrupt
-    txbuf[write_idx] = c;
-    write_idx = tmp;
-    BITBAND(UART_REGS->IER, 1) = 1;
-  }
+  while(!(UART_REGS->LSR & (0x20)));
+  UART_REGS->THR = c;
 }

 /* Polling version only */
@@ -183,10 +132,6 @@ void uart_init(void) {
  /* reset and enable FIFO */
  UART_REGS->FCR = BV(0);

-  /* enable transmit interrupt */
-  BITBAND(UART_REGS->IER, 1) = 1;
-  NVIC_EnableIRQ(UART_IRQ);
-
  UART_REGS->THR = '?';
 }

--- a/src/cic.c
+++ b/src/cic.c
@@ -5,11 +5,16 @@
 #include "cic.h"

 char *cicstatenames[4] = { "CIC_OK", "CIC_FAIL", "CIC_PAIR", "CIC_SCIC" };
+char *cicstatefriendly[4] = {"Original or no CIC", "Original CIC(failed)", "SuperCIC enhanced", "SuperCIC detected, not used"};

 void print_cic_state() {
  printf("CIC state: %s\n", get_cic_statename(get_cic_state()));
 }

+inline char *get_cic_statefriendlyname(enum cicstates state) {
+  return cicstatefriendly[state];
+}
+
 inline char *get_cic_statename(enum cicstates state) {
  return cicstatenames[state];
 }
--- a/src/cic.h
+++ b/src/cic.h
@@ -13,6 +13,7 @@ enum cic_region { CIC_NTSC = 0, CIC_PAL };

 void print_cic_state(void);
 char *get_cic_statename(enum cicstates state);
+char *get_cic_statefriendlyname(enum cicstates state);
 enum cicstates get_cic_state(void);
 void cic_init(int allow_pairmode);

--- a/src/cli.c
+++ b/src/cli.c
@@ -134,7 +134,7 @@ static int8_t parse_wordlist(char *wordlist) {
    do {
      // If current word list character is \0: No match found
      if (c == 0) {
-        printf("Unknown word: %s\n",curchar);
+        printf("Unknown word: %s\n(use ? for help)",curchar);
        return -1;
      }

--- a/src/config
+++ b/src/config
@@ -1,4 +1,4 @@
-CONFIG_VERSION=0.1.1
-#FWVER=000101
-CONFIG_FWVER=257
+CONFIG_VERSION="0.1.2"
+#FWVER=00010200
+CONFIG_FWVER=66048
 CONFIG_MCU_FOSC=12000000
--- a/src/config.h
+++ b/src/config.h
@@ -1,12 +1,13 @@
 #ifndef _CONFIG_H
 #define _CONFIG_H

+#include "autoconf.h"
+
 // #define DEBUG_FS
 // #define DEBUG_SD
 // #define DEBUG_IRQ
 // #define DEBUG_MSU1

-#define VER                       "0.0.1(NSFW)"
 #define IN_AHBRAM                 __attribute__ ((section(".ahbram")))

 #define SD_DT_INT_SETUP()         do {\
--- a/src/ff.c
+++ b/src/ff.c
@@ -2639,8 +2639,16 @@ FRESULT f_lseek (
 						fp->flag &= ~FA__DIRTY;
 					}
 #endif
-					if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)
-						ABORT(fp->fs, FR_DISK_ERR);
+					if(!ff_sd_offload) {
+						sd_offload_partial=0;
+						if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)
+							ABORT(fp->fs, FR_DISK_ERR);
+					} else {
+						sd_offload_partial=1;
+						sd_offload_partial_start = fp->fptr % SS(fp->fs);
+					}
+//					if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)
+//						ABORT(fp->fs, FR_DISK_ERR);
 #endif
 					fp->dsect = dsc;
 				}
--- a/src/filetypes.c
+++ b/src/filetypes.c
@@ -66,6 +66,8 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
  static uint32_t parent_tgt;
  static uint32_t dir_end = 0;
  static uint8_t was_empty = 0;
+  static uint16_t num_files_total = 0;
+  static uint16_t num_dirs_total = 0;
  uint32_t dir_tgt;
  uint16_t numentries;
  uint32_t dirsize;
@@ -91,6 +93,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
  numentries=0;
  for(pass = 0; pass < 2; pass++) {
    if(pass) {
+      num_dirs_total++;
      dirsize = 4*(numentries);
      next_subdir_tgt += dirsize + 4;
      if(parent_tgt) next_subdir_tgt += 4;
@@ -180,6 +183,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
        } else {
          SNES_FTYPE type = determine_filetype((char*)fn);
          if(type != TYPE_UNKNOWN) {
+            num_files_total++;
            numentries++;
            if(pass) {
              if(mkdb) {
@@ -250,6 +254,8 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
 //  printf("db_tgt=%lx dir_end=%lx\n", db_tgt, dir_end);
  sram_writelong(db_tgt, SRAM_DB_ADDR+4);
  sram_writelong(dir_end, SRAM_DB_ADDR+8);
+  sram_writeshort(num_files_total, SRAM_DB_ADDR+12);
+  sram_writeshort(num_dirs_total, SRAM_DB_ADDR+14);
  return crc;
 }

--- a/src/fpga_spi.c
+++ b/src/fpga_spi.c
@@ -47,9 +47,15 @@
                                s: Bit 2 = partial, Bit 1:0 = target
                                target: see above

-	60	sssseeee	set SD DMA partial transfer start+end
-				ssss = start offset (msb first)
-				eeee = end offset (msb first)
+	60	xsssyeee	set SD DMA partial transfer parameters
+				x: 0 = read from sector start (skip until
+				       start offset reached)
+				   8 = assume mid-sector position and read
+				       immediately
+				sss = start offset (msb first)
+				y: 0 = skip rest of SD sector
+				   8 = stop mid-sector if end offset reached
+				eee = end offset (msb first)

 	8p	-		read (RAM only)
 				p: 0 = no increment after read
@@ -80,6 +86,7 @@
 	EB	-		put DSP into reset
 	EC	-		release DSP from reset
 	ED	-		set feature enable bits (see below)
+	EE	-		set $213f override value (0=NTSC, 1=PAL)
 	F0	-		receive test token (to see if FPGA is alive)
 	F1	-		receive status (16bit, MSB first), see below

@@ -97,7 +104,7 @@
 	 15	SD DMA busy (0=idle, 1=busy)
 	 14	DAC read pointer MSB
 	 13	MSU read pointer MSB
-	 12	[TODO SD DMA CRC status (0=ok, 1=error); valid after bit 15 -> 0]
+	 12	reserved (0)
 	 11	reserved (0)
 	 10	reserved (0)
 	  9	reserved (0)
@@ -117,7 +124,7 @@
 	 7	-
 	 6	-
 	 5	-
-	 4	-
+	 4	enable $213F override
 	 3	enable MSU1 registers
 	 2	enable SRTC registers
 	 1	enable ST0010 mapping
@@ -238,7 +245,7 @@ void fpga_sddma(uint8_t tgt, uint8_t partial) {
  }
  DBG_SD printf("...complete\n");
  FPGA_DESELECT();
-  if(test<5)printf("loopy: %ld %02x\n", test, status);
+//  if(test<5)printf("loopy: %ld %02x\n", test, status);
  BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
 }

@@ -411,3 +418,11 @@ void fpga_set_features(uint8_t feat) {
  FPGA_DESELECT();
 }

+void fpga_set_213f(uint8_t data) {
+  printf("set 213f: %d\n", data);
+  FPGA_SELECT();
+  FPGA_TX_BYTE(0xee);
+  FPGA_TX_BYTE(data);
+  FPGA_DESELECT();
+}
+
--- a/src/fpga_spi.h
+++ b/src/fpga_spi.h
@@ -50,12 +50,14 @@
 #define FPGA_SPI_FAST()    spi_set_speed(SPI_SPEED_FPGA_FAST)
 #define FPGA_SPI_SLOW()    spi_set_speed(SPI_SPEED_FPGA_SLOW)

-#define FEAT_CX4           (1 << 4)
+#define FEAT_213F          (1 << 4)
 #define FEAT_MSU1          (1 << 3)
 #define FEAT_SRTC          (1 << 2)
 #define FEAT_ST0010        (1 << 1)
 #define FEAT_DSPX          (1 << 0)

+#define FEAT_CX4           (1 << 4)
+
 #define FPGA_WAIT_RDY()    do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)

 void fpga_spi_init(void);
@@ -90,4 +92,5 @@ void fpga_write_dspx_pgm(uint32_t data);
 void fpga_write_dspx_dat(uint16_t data);
 void fpga_dspx_reset(uint8_t reset);
 void fpga_set_features(uint8_t feat);
+void fpga_set_213f(uint8_t data);
 #endif
--- a/src/main.c
+++ b/src/main.c
@@ -26,6 +26,7 @@
 #include "smc.h"
 #include "msu1.h"
 #include "rtc.h"
+#include "sysinfo.h"

 #define EMC0TOGGLE	(3<<4)
 #define MR0R		(1<<1)
@@ -34,6 +35,8 @@ int i;

 int sd_offload = 0, ff_sd_offload = 0, sd_offload_tgt = 0;
 int sd_offload_partial = 0;
+int sd_offload_start_mid = 0;
+int sd_offload_end_mid = 0;
 uint16_t sd_offload_partial_start = 0;
 uint16_t sd_offload_partial_end = 0;

@@ -75,7 +78,7 @@ int main(void) {
  LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
 led_pwm();
  sdn_init();
-  printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
+  printf("\n\nsd2snes mk.2\n============\nfw ver.: " CONFIG_VERSION "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
 printf("PCONP=%lx\n", LPC_SC->PCONP);

  file_init();
@@ -208,7 +211,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
      sram_writebyte(0x00, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
      set_fpga_time(get_bcdtime());
    }
-
+    sram_memset(SRAM_SYSINFO_ADDR, 13*40, 0x20);
    printf("SNES GO!\n");
    snes_reset(1);
    delay_ms(1);
@@ -243,8 +246,13 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
          /* set RTC */
          set_bcdtime(btime);
          set_fpga_time(btime);
-	  cmd=0; /* stay in loop */
+	  cmd=0; /* stay in menu loop */
 	  break;
+        case SNES_CMD_SYSINFO:
+          /* go to sysinfo loop */
+          sysinfo_loop();
+          cmd=0; /* stay in menu loop */
+          break;
 	default:
 	  printf("unknown cmd: %d\n", cmd);
 	  cmd=0; /* unknown cmd: stay in loop */
--- a/src/memory.c
+++ b/src/memory.c
@@ -281,7 +281,9 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
  printf("done\n");

  romprops.fpga_features |= FEAT_SRTC;
+  romprops.fpga_features |= FEAT_213F;

+  fpga_set_213f(romprops.region);
  fpga_set_features(romprops.fpga_features);

  if(flags & LOADROM_WITH_RESET) {
--- a/src/memory.h
+++ b/src/memory.h
@@ -30,19 +30,20 @@
 #include <arm/NXP/LPC17xx/LPC17xx.h>
 #include "smc.h"

-#define SRAM_ROM_ADDR (0x000000L)
-#define SRAM_SAVE_ADDR (0xE00000L)
+#define SRAM_ROM_ADDR           (0x000000L)
+#define SRAM_SAVE_ADDR          (0xE00000L)

-#define SRAM_MENU_ADDR (0xE00000L)
-#define SRAM_DB_ADDR (0xE40000L)
-#define SRAM_DIR_ADDR (0xE10000L)
-#define SRAM_CMD_ADDR (0xFF1000L)
-#define SRAM_PARAM_ADDR (0xFF1004L)
-#define SRAM_STATUS_ADDR (0xFF1100L)
-#define SRAM_MENU_SAVE_ADDR (0xFF0000L)
-#define SRAM_SCRATCHPAD (0xFFFF00L)
-#define SRAM_DIRID (0xFFFFF0L)
-#define SRAM_RELIABILITY_SCORE (0x100)
+#define SRAM_MENU_ADDR          (0xE00000L)
+#define SRAM_DB_ADDR            (0xE40000L)
+#define SRAM_DIR_ADDR           (0xE10000L)
+#define SRAM_CMD_ADDR           (0xFF1000L)
+#define SRAM_PARAM_ADDR         (0xFF1004L)
+#define SRAM_STATUS_ADDR        (0xFF1100L)
+#define SRAM_SYSINFO_ADDR       (0xFF1110L)
+#define SRAM_MENU_SAVE_ADDR     (0xFF0000L)
+#define SRAM_SCRATCHPAD         (0xFFFF00L)
+#define SRAM_DIRID              (0xFFFFF0L)
+#define SRAM_RELIABILITY_SCORE  (0x100)

 #define LOADROM_WITH_SRAM	(1)
 #define LOADROM_WITH_RESET	(2)
--- a/src/msu1.c
+++ b/src/msu1.c
@@ -127,21 +127,21 @@ int msu1_loop() {

      /* get trackno */
      msu_track = get_msu_track();
-      printf("Audio requested! Track=%d\n", msu_track);
+      DBG_MSU1 printf("Audio requested! Track=%d\n", msu_track);

      /* open file, fill buffer */
      f_close(&file_handle);
      snprintf(suffix, sizeof(suffix), "-%d.pcm", msu_track);
      strcpy((char*)file_buf, (char*)file_lfn);
      strcpy(strrchr((char*)file_buf, (int)'.'), suffix);
-      printf("filename: %s\n", file_buf);
+      DBG_MSU1 printf("filename: %s\n", file_buf);
      f_open(&file_handle, (const TCHAR*)file_buf, FA_READ);
      file_handle.cltbl = pcm_cltbl;
      pcm_cltbl[0] = CLTBL_SIZE;
      f_lseek(&file_handle, CREATE_LINKMAP);
      f_lseek(&file_handle, 4L);
      f_read(&file_handle, &msu_loop_point, 4, &bytes_read);
-      printf("loop point: %ld samples\n", msu_loop_point);
+      DBG_MSU1 printf("loop point: %ld samples\n", msu_loop_point);
      ff_sd_offload=1;
      sd_offload_tgt=1;
      f_lseek(&file_handle, 8L);
@@ -159,12 +159,12 @@ int msu1_loop() {
    if(fpga_status_now & 0x0010) {
      /* get address */
      msu_offset=get_msu_offset();
-      printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start);
+      DBG_MSU1 printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start);
      if(   ((msu_offset < msu_page1_start)
 	 || (msu_offset >= msu_page1_start + msu_page_size))
 	 && ((msu_offset < msu_page2_start)
 	 || (msu_offset >= msu_page2_start + msu_page_size))) {
-	printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start,
+	DBG_MSU1 printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start,
 	       msu_page1_start+msu_page_size-1, msu_page2_start, msu_page2_start+msu_page_size-1);
 	/* "cache miss" */
 	/* fill buffer */
@@ -220,19 +220,19 @@ int msu1_loop() {
      if(fpga_status_now & 0x0004) {
 	msu_repeat = 1;
 	set_msu_status(0x04, 0x01); /* set bit 2, reset bit 0 */
-	printf("Repeat set!\n");
+	DBG_MSU1 printf("Repeat set!\n");
      } else {
 	msu_repeat = 0;
 	set_msu_status(0x00, 0x05); /* set no bits, reset bit 0+2 */
-	printf("Repeat clear!\n");
+	DBG_MSU1 printf("Repeat clear!\n");
      }

      if(fpga_status_now & 0x0002) {
-	printf("PLAY!\n");
+	DBG_MSU1 printf("PLAY!\n");
 	set_msu_status(0x02, 0x01); /* set bit 0, reset bit 1 */
 	dac_play();
      } else {
-	printf("PAUSE!\n");
+	DBG_MSU1 printf("PAUSE!\n");
 	set_msu_status(0x00, 0x03); /* set no bits, reset bit 1+0 */
 	dac_pause();
      }
@@ -245,7 +245,7 @@ int msu1_loop() {
      ff_sd_offload=0;
      sd_offload=0;
      if(msu_repeat) {
-	printf("loop\n");
+	DBG_MSU1 printf("loop\n");
 	ff_sd_offload=1;
 	sd_offload_tgt=1;
 	f_lseek(&file_handle, 8L+msu_loop_point*4);
@@ -254,6 +254,7 @@ int msu1_loop() {
 	f_read(&file_handle, file_buf, (MSU_DAC_BUFSIZE / 2) - bytes_read, &bytes_read);
      } else {
 	set_msu_status(0x00, 0x02); /* clear play bit */
+	dac_pause();
      }
      bytes_read = MSU_DAC_BUFSIZE;
    }
--- a/src/sdnative.c
+++ b/src/sdnative.c
@@ -111,14 +111,16 @@
 uint8_t cmd[6]={0,0,0,0,0,0};
 uint8_t rsp[17];
 uint8_t csd[17];
+uint8_t cid[17];
 uint8_t ccs=0;
 uint32_t rca;

-enum trans_state { TRANS_NONE = 0, TRANS_READ, TRANS_WRITE };
+enum trans_state { TRANS_NONE = 0, TRANS_READ, TRANS_WRITE, TRANS_MID };
 enum cmd_state { CMD_RSP = 0, CMD_RSPDAT, CMD_DAT };

 int during_blocktrans = TRANS_NONE;
 uint32_t last_block = 0;
+uint16_t last_offset = 0;

 volatile int sd_changed;

@@ -158,6 +160,17 @@ static uint32_t getbits(void *buffer, uint16_t start, int8_t bits) {
  return result;
 }

+void sdn_checkinit(BYTE drv) {
+  if(disk_state == DISK_CHANGED) {
+    disk_initialize(drv);
+  }
+}
+
+uint8_t* sdn_getcid() {
+  sdn_checkinit(0);
+  return cid;
+}
+
 static inline void wiggle_slow_pos(uint16_t times) {
  while(times--) {
    delay_us(2);
@@ -383,7 +396,6 @@ int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){
      printf("CMD%d timed out\n", cmdno);
      return 0; /* no response within timeout */
    }
-
    i=rsplen;
    uint8_t cmddata=0, datdata=0;
    while(i--) { /* process response */
@@ -448,20 +460,31 @@ int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){
      state=CMD_DAT;
      j=datcnt;
      datshift=8;
+      timeout=2000000;
      DBG_SD printf("response over, waiting for data...\n");
      /* wait for data start bit on DAT0 */
      while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) {
        wiggle_fast_neg1();
      }
+//printf("%ld\n", timeout);
      DBG_SD if(!timeout) printf("timed out!\n");
      wiggle_fast_neg1(); /* eat the start bit */
      if(sd_offload) {
        if(sd_offload_partial) {
+          if(sd_offload_partial_start != 0) {
+            if(during_blocktrans == TRANS_MID) sd_offload_partial_start |= 0x8000;
+          }
+          if(sd_offload_partial_end != 512) {
+            sd_offload_partial_end |= 0x8000;
+          }
+          DBG_SD printf("new partial %d - %d\n", sd_offload_partial_start, sd_offload_partial_end);
          fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end);
          fpga_sddma(sd_offload_tgt, 1);
-          sd_offload_partial=0;
+//          sd_offload_partial=0;
+          last_offset=sd_offload_partial_end;
        } else {
          fpga_sddma(sd_offload_tgt, 0);
+          last_offset=0;
        }
        state=CMD_RSP;
        return rsplen;
@@ -578,12 +601,6 @@ int acmd_fast(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* r
  return cmd_fast(cmd, param, crc, dat, rsp);
 }

-void sdn_checkinit(BYTE drv) {
-  if(disk_state == DISK_CHANGED) {
-    disk_initialize(drv);
-  }
-}
-
 int stream_datablock(uint8_t *buf) {
 //  uint8_t datshift=8;
  int j=512;
@@ -591,17 +608,24 @@ int stream_datablock(uint8_t *buf) {
  uint32_t timeout=1000000;

  DBG_SD printf("stream_datablock: wait for ready...\n");
-  while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) {
-    wiggle_fast_neg1();
+  if(during_blocktrans != TRANS_MID) {
+    while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) {
+      wiggle_fast_neg1();
+    }
+    DBG_SD if(!timeout) printf("timeout!\n");
+    wiggle_fast_neg1(); /* eat the start bit */
  }
-  DBG_SD if(!timeout) printf("timeout!\n");
-
-  wiggle_fast_neg1(); /* eat the start bit */
  if(sd_offload) {
    if(sd_offload_partial) {
+      if(sd_offload_partial_start != 0) {
+        if(during_blocktrans == TRANS_MID) sd_offload_partial_start |= 0x8000;
+      }
+      if(sd_offload_partial_end != 512) {
+        sd_offload_partial_end |= 0x8000;
+      }
+      DBG_SD printf("str partial %d - %d\n", sd_offload_partial_start, sd_offload_partial_end);
      fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end);
      fpga_sddma(sd_offload_tgt, 1);
-      sd_offload_partial=0;
    } else {
      fpga_sddma(sd_offload_tgt, 0);
    }
@@ -753,6 +777,7 @@ void send_datablock(uint8_t *buf) {
 }

 void read_block(uint32_t address, uint8_t *buf) {
+  DBG_SD printf("read_block addr=%08lx last_addr=%08lx  offld=%d/%d offst=%04x offed=%04x last_off=%04x\n", address, last_block, sd_offload, sd_offload_partial, sd_offload_partial_start, sd_offload_partial_end, last_offset);
  if(during_blocktrans == TRANS_READ && (last_block == address-1)) {
 //uart_putc('r');
 #ifdef CONFIG_SD_DATACRC
@@ -766,7 +791,21 @@ void read_block(uint32_t address, uint8_t *buf) {
 #else
    stream_datablock(buf);
 #endif
-    last_block=address;
+    last_block = address;
+    last_offset = sd_offload_partial_end & 0x1ff;
+    if(sd_offload_partial && sd_offload_partial_end != 512) {
+      during_blocktrans = TRANS_MID;
+    }
+    sd_offload_partial = 0;
+  } else if (during_blocktrans == TRANS_MID
+             && last_block == address
+             && last_offset == sd_offload_partial_start
+             && sd_offload_partial) {
+    sd_offload_partial_start |= 0x8000;
+    stream_datablock(buf);
+    during_blocktrans = TRANS_READ;
+    last_offset = sd_offload_partial_end & 0x1ff;
+    sd_offload_partial = 0;
  } else {
    if(during_blocktrans) {
 //      uart_putc('_');
@@ -774,7 +813,8 @@ void read_block(uint32_t address, uint8_t *buf) {
      /* send STOP_TRANSMISSION to end an open READ/WRITE_MULTIPLE_BLOCK */
      cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp);
    }
-    last_block=address;
+    during_blocktrans = TRANS_READ;
+    last_block = address;
    if(!ccs) {
      address <<= 9;
    }
@@ -786,8 +826,9 @@ void read_block(uint32_t address, uint8_t *buf) {
 #else
    cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp);
 #endif
-    during_blocktrans = TRANS_READ;
+    sd_offload_partial = 0;
  }
+//  printf("trans state = %d\n", during_blocktrans);
 }

 void write_block(uint32_t address, uint8_t* buf) {
@@ -887,7 +928,10 @@ DRESULT sdn_initialize(BYTE drv) {
  }

  /* record CSD for getinfo */
-  cmd_slow(SEND_CSD, rca, 0, NULL, rsp);
+  cmd_slow(SEND_CSD, rca, 0, NULL, csd);
+
+  /* record CID */
+  cmd_slow(SEND_CID, rca, 0, NULL, cid);

  /* select the card */
  if(cmd_slow(SELECT_CARD, rca, 0, NULL, rsp)) {
--- a/src/sdnative.h
+++ b/src/sdnative.h
@@ -24,6 +24,7 @@ DRESULT sdn_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count);
 DRESULT sdn_getinfo(BYTE drv, BYTE page, void *buffer);

 void    sdn_changed(void);
+uint8_t* sdn_getcid(void);

 #endif

--- a/src/smc.c
+++ b/src/smc.c
@@ -34,28 +34,6 @@
 snes_romprops_t romprops;

 uint32_t hdr_addr[6] = {0xffb0, 0x101b0, 0x7fb0, 0x81b0, 0x40ffb0, 0x4101b0};
-uint8_t countAllASCII(uint8_t* data, int size) {
-  uint8_t res = 0;
-  do {
-    size--;
-    if(data[size] >= 0x20 && data[size] <= 0x7e) {
-      res++;
-    }
-  } while (size);
-  return res;
-}
-
-uint8_t countAllJISX0201(uint8_t* data, int size) {
-  uint8_t res = 0;
-  do {
-    size--;
-    if((data[size] >= 0x20 && data[size] <= 0x7e)
-       ||(data[size] >= 0xa1 && data[size] <= 0xdf)) {
-      res++;
-    }
-  } while (size);
-  return res;
-}

 uint8_t isFixed(uint8_t* data, int size, uint8_t value) {
  uint8_t res = 1;
@@ -72,7 +50,7 @@ uint8_t checkChksum(uint16_t cchk, uint16_t chk) {
  uint32_t sum = cchk + chk;
  uint8_t res = 0;
  if(sum==0x0000ffff) {
-    res = 0x10;
+    res = 1;
  }
  return res;
 }
@@ -87,32 +65,13 @@ void smc_id(snes_romprops_t* props) {
  props->fpga_features = 0;
  props->fpga_conf = NULL;
  for(uint8_t num = 0; num < 6; num++) {
-    if(!file_readblock(header, hdr_addr[num], sizeof(snes_header_t))
-       || file_res) {
-      score = 0;
-    } else {
-      score = smc_headerscore(header)/(1+(num&1));
-      if((file_handle.fsize & 0x2ff) == 0x200) {
-        if(num&1) {
-          score+=20;
-        } else {
-          score=0;
-        }
-      } else {
-        if(!(num&1)) {
-          score+=20;
-        } else {
-          score=0;
-        }
-      }
-    }
-//printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */
+    score = smc_headerscore(hdr_addr[num], header);
+    printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */
    if(score>=maxscore) {
      score_idx=num;
      maxscore=score;
    }
  }
-
  if(score_idx & 1) {
    props->offset = 0x200;
  } else {
@@ -163,7 +122,7 @@ void smc_id(snes_romprops_t* props) {
          (header->map == 0x30 && header->carttype == 0x05 && header->licensee != 0xb2)) {
        props->has_dspx = 1;
        props->fpga_features |= FEAT_DSPX;
-        // Pilotwings uses DSP1 instead of DSP1B
+        /* Pilotwings uses DSP1 instead of DSP1B */
        if(!memcmp(header->name, "PILOTWINGS", 10)) {
          props->dsp_fw = DSPFW_1;
        } else {
@@ -236,17 +195,86 @@ void smc_id(snes_romprops_t* props) {
  if(props->ramsize_bytes > 32768 || props->ramsize_bytes < 2048) {
    props->ramsize_bytes = 0;
  }
+  props->region = (header->destcode <= 1 || header->destcode >= 13) ? 0 : 1;
+
 /*dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); */
 }

-uint8_t smc_headerscore(snes_header_t* header) {
-  uint8_t score=0;
-  score += countAllASCII(header->maker, sizeof(header->maker));
-  score += countAllASCII(header->gamecode, sizeof(header->gamecode));
-  score += isFixed(header->fixed_00, sizeof(header->fixed_00), 0x00);
-  score += countAllJISX0201(header->name, sizeof(header->name));
-  score += 3*isFixed(&header->licensee, sizeof(header->licensee), 0x33);
-  score += checkChksum(header->cchk, header->chk);
+uint8_t smc_headerscore(uint32_t addr, snes_header_t* header) {
+  int score=0;
+  uint8_t reset_inst;
+  uint16_t header_offset;
+  if((addr & 0xfff) == 0x1b0) {
+    header_offset = 0x200;
+  } else {
+    header_offset = 0;
+  }
+  if((file_readblock(header, addr, sizeof(snes_header_t)) < sizeof(snes_header_t))
+     || file_res) {
+    return 0;
+  }
+  uint8_t mapper = header->map & ~0x10;
+  uint16_t resetvector = header->vect_reset; /* not endian safe! */
+  uint32_t file_addr = (((addr - header_offset) & ~0x7fff) | (resetvector & 0x7fff)) + header_offset;
+  if(resetvector < 0x8000) return 0;
+
+  score += 2*isFixed(&header->licensee, sizeof(header->licensee), 0x33);
+  score += 4*checkChksum(header->cchk, header->chk);
+  if(header->carttype < 0x08) score++;
+  if(header->romsize < 0x10) score++;
+  if(header->ramsize < 0x08) score++;
+  if(header->destcode < 0x0e) score++;
+
+  if((addr-header_offset) == 0x007fc0 && mapper == 0x20) score += 2;
+  if((addr-header_offset) == 0x00ffc0 && mapper == 0x21) score += 2;
+  if((addr-header_offset) == 0x007fc0 && mapper == 0x22) score += 2;
+  if((addr-header_offset) == 0x40ffc0 && mapper == 0x25) score += 2;
+
+  file_readblock(&reset_inst, file_addr, 1);
+  switch(reset_inst) {
+    case 0x78: /* sei */
+    case 0x18: /* clc */
+    case 0x38: /* sec */
+    case 0x9c: /* stz abs */
+    case 0x4c: /* jmp abs */
+    case 0x5c: /* jml abs */
+      score += 8;
+      break;
+
+    case 0xc2: /* rep */
+    case 0xe2: /* sep */
+    case 0xad: /* lda abs */
+    case 0xae: /* ldx abs */
+    case 0xac: /* ldy abs */
+    case 0xaf: /* lda abs long */
+    case 0xa9: /* lda imm */
+    case 0xa2: /* ldx imm */
+    case 0xa0: /* ldy imm */
+    case 0x20: /* jsr abs */
+    case 0x22: /* jsl abs */
+      score += 4;
+      break;
+
+    case 0x40: /* rti */
+    case 0x60: /* rts */
+    case 0x6b: /* rtl */
+    case 0xcd: /* cmp abs */
+    case 0xec: /* cpx abs */
+    case 0xcc: /* cpy abs */
+      score -= 4;
+      break;
+
+    case 0x00: /* brk */
+    case 0x02: /* cop */
+    case 0xdb: /* stp */
+    case 0x42: /* wdm */
+    case 0xff: /* sbc abs long indexed */
+      score -= 8;
+      break;
+  }
+
+  if(score && addr > 0x400000) score += 4;
+  if(score < 0) score = 0;
  return score;
 }

--- a/src/smc.h
+++ b/src/smc.h
@@ -54,6 +54,19 @@ typedef struct _snes_header {
  uint8_t ver;          /* 0xDB */
  uint16_t cchk;        /* 0xDC */
  uint16_t chk;         /* 0xDE */
+  uint32_t pad1;        /* 0xE0 */
+  uint16_t vect_cop16;	/* 0xE4 */
+  uint16_t vect_brk16;  /* 0xE6 */
+  uint16_t vect_abt16;  /* 0xE8 */
+  uint16_t vect_nmi16;  /* 0xEA */
+  uint16_t vect_irq16;  /* 0xEE */
+  uint16_t pad2;        /* 0xF0 */
+  uint16_t vect_cop8;   /* 0xF4 */
+  uint32_t pad3;        /* 0xF6 */
+  uint16_t vect_abt8;   /* 0xF8 */
+  uint16_t vect_nmi8;   /* 0xFA */
+  uint16_t vect_reset;  /* 0xFC */
+  uint16_t vect_brk8;   /* 0xFE */
 } snes_header_t;

 typedef struct _snes_romprops {
@@ -66,14 +79,15 @@ typedef struct _snes_romprops {
  const uint8_t* dsp_fw;      /* DSP (NEC / Hitachi) ROM filename */
  const uint8_t* fpga_conf;   /* FPGA config file to load (default: base) */
  uint8_t has_dspx;           /* DSP[1-4] presence flag */
-  uint8_t has_st0010;         /* st0010 presence flag (additional to dspx)*/
+  uint8_t has_st0010;         /* st0010 presence flag (additional to dspx) */
  uint8_t has_msu1;           /* MSU1 presence flag */
  uint8_t has_cx4;            /* CX4 presence flag */
  uint8_t fpga_features;      /* feature/peripheral enable bits*/
+  uint8_t region;             /* game region (derived from destination code) */
  snes_header_t header;       /* original header from ROM image */
 } snes_romprops_t;

 void smc_id(snes_romprops_t*);
-uint8_t smc_headerscore(snes_header_t*);
+uint8_t smc_headerscore(uint32_t addr, snes_header_t* header);

 #endif
--- a/src/snes.h
+++ b/src/snes.h
@@ -29,6 +29,7 @@

 #define SNES_CMD_LOADROM   (1)
 #define SNES_CMD_SETRTC    (2)
+#define SNES_CMD_SYSINFO   (3)

 #define MENU_ERR_OK		(0)
 #define MENU_ERR_NODSP	(1)
--- a/src/tests/Makefile
+++ b/src/tests/Makefile
@@ -55,7 +55,7 @@ TARGET = $(OBJDIR)/sd2snes


 # List C source files here. (C dependencies are automatically generated.)
-SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c crc16.c tests.c
+SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c tests.c

 # usbcontrol.c usb_hid.c usbhw_lpc.c usbinit.c usbstdreq.c

--- a/verilog/sd2snes/address.v
+++ b/verilog/sd2snes/address.v
@@ -19,9 +19,10 @@
 //////////////////////////////////////////////////////////////////////////////////
 module address(
  input CLK,
-  input [3:0] featurebits,  // peripheral enable/disable
+  input [7:0] featurebits,  // peripheral enable/disable
  input [2:0] MAPPER,       // MCU detected mapper
  input [23:0] SNES_ADDR,   // requested address from SNES
+  input [7:0] SNES_PA,      // peripheral address from SNES
  output [23:0] ROM_ADDR,   // Address to request from SRAM0
  output ROM_SEL,           // enable SRAM0 (active low)
  output IS_SAVERAM,        // address/CS mapped as SRAM?
@@ -35,14 +36,16 @@ module address(
  input [14:0] bsx_regs,
  output dspx_enable,
  output dspx_dp_enable,
-  output dspx_a0
+  output dspx_a0,
+  output r213f_enable
 );

 parameter [2:0]
  FEAT_DSPX = 0,
  FEAT_ST0010 = 1,
  FEAT_SRTC = 2,
-  FEAT_MSU1 = 3
+  FEAT_MSU1 = 3,
+  FEAT_213F = 4
 ;

 wire [23:0] SRAM_SNES_ADDR;
@@ -223,10 +226,6 @@ assign dspx_a0 = featurebits[FEAT_DSPX]
                 ?SNES_ADDR[0]
                 :1'b1;

-//reg [7:0] dspx_dp_enable_r;
-//initial dspx_dp_enable_r = 8'b00000000;
-//always @(posedge CLK) dspx_dp_enable_r <= {dspx_dp_enable_r[6:0], dspx_dp_enable_w};
-//assign dspx_dp_enable = &dspx_dp_enable_r[5:2];
 assign dspx_dp_enable = dspx_dp_enable_w;

 reg [5:0] dspx_enable_r;
@@ -234,5 +233,10 @@ initial dspx_enable_r = 6'b000000;
 always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[4:0], dspx_enable_w};
 assign dspx_enable = &dspx_enable_r[5:2];

+wire r213f_enable_w = (SNES_PA == 8'h3f);
+reg [5:0] r213f_enable_r;
+initial r213f_enable_r = 6'b000000;
+always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
+assign r213f_enable = &r213f_enable_r[5:2] & featurebits[FEAT_213F];

 endmodule
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -460,6 +460,28 @@ NET "SNES_READ" LOC = P115;
 NET "SNES_REFRESH" LOC = P155;
 NET "SNES_WRITE" LOC = P94;

+NET "SNES_PA[0]" IOSTANDARD = LVCMOS33;
+NET "SNES_PA[0]" LOC = P90;
+NET "SNES_PA[1]" IOSTANDARD = LVCMOS33;
+NET "SNES_PA[1]" LOC = P93;
+NET "SNES_PA[2]" IOSTANDARD = LVCMOS33;
+NET "SNES_PA[2]" LOC = P86;
+NET "SNES_PA[3]" IOSTANDARD = LVCMOS33;
+NET "SNES_PA[3]" LOC = P87;
+NET "SNES_PA[4]" IOSTANDARD = LVCMOS33;
+NET "SNES_PA[4]" LOC = P81;
+NET "SNES_PA[5]" IOSTANDARD = LVCMOS33;
+NET "SNES_PA[5]" LOC = P85;
+NET "SNES_PA[6]" IOSTANDARD = LVCMOS33;
+NET "SNES_PA[6]" LOC = P152;
+NET "SNES_PA[7]" IOSTANDARD = LVCMOS33;
+NET "SNES_PA[7]" LOC = P154;
+
+NET "SNES_PARD" IOSTANDARD = LVCMOS33;
+NET "SNES_PARD" LOC = P149;
+NET "SNES_PAWR" IOSTANDARD = LVCMOS33;
+NET "SNES_PAWR" LOC = P150;
+
 NET "SPI_MISO" LOC = P72;


@@ -521,3 +543,95 @@ NET "SD_DAT[3]" IOSTANDARD = LVCMOS33;

 NET "SNES_SYSCLK" LOC = P180;
 NET "SNES_SYSCLK" IOSTANDARD = LVCMOS33;
+NET "SNES_SYSCLK" TNM_NET = "SNES_SYSCLK";
+TIMESPEC TS_SNES_SYSCLK = PERIOD "SNES_SYSCLK" 21.5 MHz HIGH 50 %;
+
+#NET "RAM_DATA[0]" IOSTANDARD = LVCMOS33;
+#NET "RAM_DATA[0]" DRIVE = 8;
+#NET "RAM_DATA[0]" LOC = P26;
+#NET "RAM_DATA[1]" IOSTANDARD = LVCMOS33;
+#NET "RAM_DATA[1]" DRIVE = 8;
+#NET "RAM_DATA[1]" LOC = P22;
+#NET "RAM_DATA[2]" IOSTANDARD = LVCMOS33;
+#NET "RAM_DATA[2]" DRIVE = 8;
+#NET "RAM_DATA[2]" LOC = P20;
+#NET "RAM_DATA[3]" IOSTANDARD = LVCMOS33;
+#NET "RAM_DATA[3]" DRIVE = 8;
+#NET "RAM_DATA[3]" LOC = P19;
+#NET "RAM_DATA[4]" IOSTANDARD = LVCMOS33;
+#NET "RAM_DATA[4]" DRIVE = 8;
+#NET "RAM_DATA[4]" LOC = P21;
+#NET "RAM_DATA[5]" IOSTANDARD = LVCMOS33;
+#NET "RAM_DATA[5]" DRIVE = 8;
+#NET "RAM_DATA[5]" LOC = P24;
+#NET "RAM_DATA[6]" IOSTANDARD = LVCMOS33;
+#NET "RAM_DATA[6]" DRIVE = 8;
+#NET "RAM_DATA[6]" LOC = P27;
+#NET "RAM_DATA[7]" IOSTANDARD = LVCMOS33;
+#NET "RAM_DATA[7]" DRIVE = 8;
+#NET "RAM_DATA[7]" LOC = P29;
+#
+#NET "RAM_OE" IOSTANDARD = LVCMOS33;
+#NET "RAM_OE" DRIVE = 8;
+#NET "RAM_OE" LOC = P36;
+#NET "RAM_WE" IOSTANDARD = LVCMOS33;
+#NET "RAM_WE" DRIVE = 8;
+#NET "RAM_WE" LOC = P50;
+#
+#NET "RAM_ADDR[0]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[0]" DRIVE = 8;
+#NET "RAM_ADDR[0]" LOC = P28;
+#NET "RAM_ADDR[1]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[1]" DRIVE = 8;
+#NET "RAM_ADDR[1]" LOC = P31;
+#NET "RAM_ADDR[2]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[2]" DRIVE = 8;
+#NET "RAM_ADDR[2]" LOC = P33;
+#NET "RAM_ADDR[3]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[3]" DRIVE = 8;
+#NET "RAM_ADDR[3]" LOC = P35;
+#NET "RAM_ADDR[4]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[4]" DRIVE = 8;
+#NET "RAM_ADDR[4]" LOC = P37;
+#NET "RAM_ADDR[5]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[5]" DRIVE = 8;
+#NET "RAM_ADDR[5]" LOC = P40;
+#NET "RAM_ADDR[6]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[6]" DRIVE = 8;
+#NET "RAM_ADDR[6]" LOC = P43;
+#NET "RAM_ADDR[7]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[7]" DRIVE = 8;
+#NET "RAM_ADDR[7]" LOC = P45;
+#NET "RAM_ADDR[8]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[8]" DRIVE = 8;
+#NET "RAM_ADDR[8]" LOC = P44;
+#NET "RAM_ADDR[9]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[9]" DRIVE = 8;
+#NET "RAM_ADDR[9]" LOC = P42;
+#NET "RAM_ADDR[10]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[10]" DRIVE = 8;
+#NET "RAM_ADDR[10]" LOC = P34;
+#NET "RAM_ADDR[11]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[11]" DRIVE = 8;
+#NET "RAM_ADDR[11]" LOC = P39;
+#NET "RAM_ADDR[12]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[12]" DRIVE = 8;
+#NET "RAM_ADDR[12]" LOC = P48;
+#NET "RAM_ADDR[13]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[13]" DRIVE = 8;
+#NET "RAM_ADDR[13]" LOC = P46;
+#NET "RAM_ADDR[14]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[14]" DRIVE = 8;
+#NET "RAM_ADDR[14]" LOC = P51;
+#NET "RAM_ADDR[15]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[15]" DRIVE = 8;
+#NET "RAM_ADDR[15]" LOC = P58;
+#NET "RAM_ADDR[16]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[16]" DRIVE = 8;
+#NET "RAM_ADDR[16]" LOC = P57;
+#NET "RAM_ADDR[17]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[17]" DRIVE = 8;
+#NET "RAM_ADDR[17]" LOC = P61;
+#NET "RAM_ADDR[18]" IOSTANDARD = LVCMOS33;
+#NET "RAM_ADDR[18]" DRIVE = 8;
+#NET "RAM_ADDR[18]" LOC = P52;
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -35,6 +35,10 @@ module main(
  output SNES_DATABUS_DIR,
  input SNES_SYSCLK,

+  input [7:0] SNES_PA,
+  input SNES_PARD,
+  input SNES_PAWR,
+  
  /* SRAM signals */
  /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  inout [15:0] ROM_DATA,
@@ -124,7 +128,7 @@ wire [15:0] dspx_dat_data;
 wire [10:0] dspx_dat_addr;
 wire dspx_dat_we;

-wire [3:0] featurebits;
+wire [7:0] featurebits;

 wire [23:0] MAPPED_SNES_ADDR;
 wire ROM_ADDR0;
@@ -140,7 +144,9 @@ sd_dma snes_sd_dma(
  .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
-  .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
+  .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
+  .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
+  .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
 );

 wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
@@ -289,6 +295,8 @@ mcu_cmd snes_mcu_cmd(
  .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
+  .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
+  .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
  .dac_addr_out(dac_addr),
  .DAC_STATUS(DAC_STATUS),
 //  .dac_volume_out(dac_volume),
@@ -321,7 +329,8 @@ mcu_cmd snes_mcu_cmd(
  .featurebits_out(featurebits),
  .mcu_rrq(MCU_RRQ),
  .mcu_wrq(MCU_WRQ),
-  .mcu_rq_rdy(MCU_RDY)
+  .mcu_rq_rdy(MCU_RDY),
+  .region_out(mcu_region)
 );

 wire [7:0] DCM_STATUS;
@@ -334,17 +343,29 @@ my_dcm snes_dcm(
  .STATUS(DCM_STATUS)
 );

+my_dcm snes_dcm2(
+  .CLKIN(SNES_SYSCLK),
+  .CLKFX(SYSCLK2),
+  .RST(DCM_RST)
+);
+
 assign DCM_RST=0;

+reg [5:0] SNES_PARDr;
 reg [5:0] SNES_READr;
 reg [5:0] SNES_WRITEr;
 reg [5:0] SNES_CPU_CLKr;

+wire SNES_PARD_start = (SNES_PARDr == 6'b111110);
 wire SNES_RD_start = (SNES_READr == 6'b111110);
 wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
 wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
 wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);

+always @(posedge SYSCLK2) begin
+  SNES_PARDr <= {SNES_PARDr[4:0], SNES_PARD};
+end
+
 always @(posedge CLK2) begin
  SNES_READr <= {SNES_READr[4:0], SNES_READ};
  SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
@@ -356,6 +377,7 @@ address snes_addr(
  .MAPPER(MAPPER),
  .featurebits(featurebits),
  .SNES_ADDR(SNES_ADDR), // requested address from SNES
+  .SNES_PA(SNES_PA),
  .ROM_ADDR(MAPPED_SNES_ADDR),   // Address to request from SRAM (active low)
  .ROM_SEL(ROM_SEL),     // which SRAM unit to access
  .IS_SAVERAM(IS_SAVERAM),
@@ -373,7 +395,8 @@ address snes_addr(
  //uPD77C25
  .dspx_enable(dspx_enable),
  .dspx_dp_enable(dspx_dp_enable),
-  .dspx_a0(DSPX_A0)
+  .dspx_a0(DSPX_A0),
+  .r213f_enable(r213f_enable)
 );

 parameter MODE_SNES = 1'b0;
@@ -414,11 +437,23 @@ assign BSX_SNES_DATA_IN = SNES_DATA;
 reg [7:0] SNES_DINr;
 reg [7:0] ROM_DOUTr;

-assign SNES_DATA = (!SNES_READ) ? (srtc_enable ? SRTC_SNES_DATA_OUT
+reg [7:0] r213fr;
+reg r213f_forceread;
+reg [2:0] r213f_delay;
+reg [1:0] r213f_state;
+initial r213fr = 8'h55;
+initial r213f_forceread = 0;
+initial r213f_state = 2'b01;
+initial r213f_delay = 3'b011;
+
+
+assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr
+                   :(!SNES_READ ^ r213f_forceread)
+                                ? (srtc_enable ? SRTC_SNES_DATA_OUT
                                  :dspx_enable ? DSPX_SNES_DATA_OUT
-											 :dspx_dp_enable ? DSPX_SNES_DATA_OUT
-											 :msu_enable ? MSU_SNES_DATA_OUT
-											 :bsx_data_ovr ? BSX_SNES_DATA_OUT
+                                  :dspx_dp_enable ? DSPX_SNES_DATA_OUT
+                                  :msu_enable ? MSU_SNES_DATA_OUT
+                                  :bsx_data_ovr ? BSX_SNES_DATA_OUT
                                  :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;

 reg [3:0] ST_MEM_DELAYr;
@@ -446,14 +481,14 @@ assign MCU_RDY = RQ_MCU_RDYr;
 always @(posedge CLK2) begin
  if(MCU_RRQ) begin
    MCU_RD_PENDr <= 1'b1;
-	 RQ_MCU_RDYr <= 1'b0;
+    RQ_MCU_RDYr <= 1'b0;
  end else if(MCU_WRQ) begin
    MCU_WR_PENDr <= 1'b1;
-	 RQ_MCU_RDYr <= 1'b0;
+    RQ_MCU_RDYr <= 1'b0;
  end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
    MCU_RD_PENDr <= 1'b0;
-	 MCU_WR_PENDr <= 1'b0;
-	 RQ_MCU_RDYr <= 1'b1;
+    MCU_WR_PENDr <= 1'b0;
+    RQ_MCU_RDYr <= 1'b1;
  end
 end

@@ -470,7 +505,7 @@ always @(posedge CLK2) begin
 		  ROM_ADDRr <= MAPPED_SNES_ADDR;
 		  if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
 		  else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
-        else STATE <= ST_IDLE;
+      else STATE <= ST_IDLE;
 		end
 		ST_SNES_RD_ADDR: begin
 		  STATE <= ST_SNES_RD_WAIT;
@@ -564,7 +599,22 @@ always @(posedge CLK2) begin
 		  STATE <= ST_IDLE;
 		end

-	 endcase
+    endcase
+  end
+end
+
+always @(posedge SYSCLK2) begin
+  if(SNES_PARD_start & r213f_enable) begin
+    r213f_forceread <= 1'b1;
+    r213f_delay <= 3'b001;
+    r213f_state <= 2'b10;
+  end else if(r213f_state == 2'b10) begin
+    r213f_delay <= r213f_delay - 1;
+    if(r213f_delay == 3'b000) begin
+      r213f_forceread <= 1'b0;
+      r213f_state <= 2'b01;
+      r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
+    end
  end
 end

@@ -595,12 +645,15 @@ assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
                         msu_enable ? 1'b0 :
                         bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
                         srtc_enable ? (SNES_READ & SNES_WRITE) :
+                         r213f_enable & !SNES_PARD ? 1'b0 :
                         ((IS_ROM & SNES_CS)
                          |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
                          |(SNES_READ & SNES_WRITE)
                         );

-assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
+assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & r213f_enable))
+                           ? 1'b1 ^ r213f_forceread
+                           : 1'b0;

 assign IRQ_DIR = 1'b0;
 assign SNES_IRQ = 1'bZ;
--- a/verilog/sd2snes/mcu_cmd.v
+++ b/verilog/sd2snes/mcu_cmd.v
@@ -48,7 +48,9 @@ module mcu_cmd(
  output SD_DMA_PARTIAL,
  output [10:0] SD_DMA_PARTIAL_START,
  output [10:0] SD_DMA_PARTIAL_END,
-
+  output reg SD_DMA_START_MID_BLOCK,
+  output reg SD_DMA_END_MID_BLOCK,
+  
  // DAC
  output [10:0] dac_addr_out,
  input DAC_STATUS,
@@ -91,8 +93,9 @@ module mcu_cmd(
  output reg dspx_reset_out,

  // feature enable
-  output reg [3:0] featurebits_out,
+  output reg [7:0] featurebits_out,
  
+  output reg region_out,
  // SNES sync/clk
  input snes_sysclk
 );
@@ -101,6 +104,9 @@ initial begin
  dspx_pgm_addr_out = 11'b00000000000;
  dspx_dat_addr_out = 10'b0000000000;
  dspx_reset_out = 1'b1;
+  region_out = 0;
+  SD_DMA_START_MID_BLOCK = 0;
+  SD_DMA_END_MID_BLOCK = 0;
 end

 wire [31:0] snes_sysclk_freq;
@@ -177,6 +183,7 @@ initial begin
  MSU_ADDR_OUT_BUF = 0;
  SD_DMA_ENr = 0;
  MAPPER_BUF = 1;
+  SD_DMA_PARTIALr = 0;
 end

 // command interpretation
@@ -219,12 +226,16 @@ always @(posedge clk) begin
        SD_DMA_ENr <= 1'b0;
      8'h6x:
        case (spi_byte_cnt)
-          32'h2:
+          32'h2: begin
+            SD_DMA_START_MID_BLOCK <= param_data[7];
            SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
+          end
          32'h3:
            SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
-          32'h4:
+          32'h4: begin
+            SD_DMA_END_MID_BLOCK <= param_data[7];
            SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
+          end
          32'h5:
            SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
        endcase
@@ -342,7 +353,9 @@ always @(posedge clk) begin
      8'hec: // release DSPx reset
        dspx_reset_out <= 1'b0;
      8'hed:
-        featurebits_out <= param_data[3:0];
+        featurebits_out <= param_data;
+      8'hee:
+        region_out <= param_data[0];
    endcase
  end
 end
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -16,55 +16,55 @@

  <files>
    <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
    </file>
    <file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
    </file>
    <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
    </file>
    <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
    </file>
    <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
    </file>
    <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
    </file>
    <file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
    </file>
    <file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    </file>
    <file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    </file>
    <file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    </file>
    <file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
    </file>
    <file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    </file>
    <file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    </file>
    <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
@@ -90,11 +90,11 @@
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
    </file>
    <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
    </file>
    <file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
    </file>
    <file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE">
@@ -349,8 +349,8 @@
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.main" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main/snes_dspx" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.upd77c25" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
@@ -372,13 +372,13 @@
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Search Directories for 'Include" xil_pn:value="../sd2snes" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.main" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.upd77c25" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="2" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -416,7 +416,7 @@
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/mnt/store/bin/Xilinx/13.2/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
@@ -433,7 +433,7 @@
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|upd77c25" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
--- a/verilog/sd2snes/sd_dma.v
+++ b/verilog/sd2snes/sd_dma.v
@@ -29,7 +29,9 @@ module sd_dma(
  output [7:0] SD_DMA_SRAM_DATA,
  input SD_DMA_PARTIAL,
  input [10:0] SD_DMA_PARTIAL_START,
-  input [10:0] SD_DMA_PARTIAL_END
+  input [10:0] SD_DMA_PARTIAL_END,
+  input SD_DMA_START_MID_BLOCK,
+  input SD_DMA_END_MID_BLOCK
 );

 reg [10:0] SD_DMA_STARTr;
@@ -85,7 +87,9 @@ always @(posedge CLK) begin
 end

 always @(posedge CLK) begin
-  if(cyclecnt == 1042) SD_DMA_DONEr <= 1;
+  if(cyclecnt == 1042
+     || ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END))
+    SD_DMA_DONEr <= 1;
  else SD_DMA_DONEr <= 0;
 end

@@ -100,8 +104,10 @@ always @(posedge CLK) begin
 end

 always @(posedge CLK) begin
-  if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0;
-  else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1;
+  if(SD_DMA_EN_rising) 
+    cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0;
+  else if(!SD_DMA_STATUSr) cyclecnt <= 0;
+  else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
 end

 // we have 8 clk cycles to complete one RAM write
--- a/verilog/sd2snes_cx4/address.v
+++ b/verilog/sd2snes_cx4/address.v
@@ -21,6 +21,7 @@ module address(
  input CLK,
  input [2:0] MAPPER,       // MCU detected mapper
  input [23:0] SNES_ADDR,   // requested address from SNES
+  input [7:0] SNES_PA,      // peripheral address from SNES
  input SNES_CS,            // SNES ROMSEL signal
  output [23:0] ROM_ADDR,   // Address to request from SRAM0
  output ROM_SEL,           // enable SRAM0 (active low)
@@ -32,7 +33,8 @@ module address(
  input use_msu1,
  output msu_enable,
  output cx4_enable,
-  output cx4_vect_enable
+  output cx4_vect_enable,
+  output r213f_enable
 );

 wire [23:0] SRAM_SNES_ADDR;
@@ -64,4 +66,11 @@ always @(posedge CLK) cx4_enable_r <= {cx4_enable_r[4:0], cx4_enable_w};
 assign cx4_enable = &cx4_enable_r[5:2];

 assign cx4_vect_enable = &SNES_ADDR[15:5];
+
+wire r213f_enable_w = (SNES_PA == 8'h3f);
+reg [5:0] r213f_enable_r;
+initial r213f_enable_r = 6'b000000;
+always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
+assign r213f_enable = &r213f_enable_r[5:2];
+
 endmodule
--- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise
+++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise
@@ -29,333 +29,27 @@
  </files>

  <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    <property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Module|cx4_mul" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top File" xil_pn:value="cx4_mul.ngc" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cx4_mul" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="cx4_mul" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="cx4_mul_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="cx4_mul_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="cx4_mul_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="cx4_mul_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_mul" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-30T21:22:43" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7C4ED2F86A69C26BC7F2AA5B611C709F" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
--- a/verilog/sd2snes_cx4/main.ucf
+++ b/verilog/sd2snes_cx4/main.ucf
--- a/verilog/sd2snes_cx4/main.v
+++ b/verilog/sd2snes_cx4/main.v
@@ -35,6 +35,10 @@ module main(
  output SNES_DATABUS_DIR,
  input SNES_SYSCLK,

+  input [7:0] SNES_PA,
+  input SNES_PARD,
+  input SNES_PAWR,
+
  /* SRAM signals */
  /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  inout [15:0] ROM_DATA,
@@ -121,7 +125,9 @@ sd_dma snes_sd_dma(
  .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
-  .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
+  .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
+  .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
+  .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
 );

 wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
@@ -211,6 +217,8 @@ mcu_cmd snes_mcu_cmd(
  .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
+  .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
+  .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
  .dac_addr_out(dac_addr),
  .DAC_STATUS(DAC_STATUS),
 //  .dac_volume_out(dac_volume),
@@ -234,7 +242,8 @@ mcu_cmd snes_mcu_cmd(
  .cx4_datrom_addr_out(cx4_datrom_addr), 
  .cx4_datrom_data_out(cx4_datrom_data), 
  .cx4_datrom_we_out(cx4_datrom_we), 
-  .cx4_reset_out(cx4_reset)
+  .cx4_reset_out(cx4_reset),
+  .region_out(mcu_region)
 );

 wire [7:0] DCM_STATUS;
@@ -247,17 +256,29 @@ my_dcm snes_dcm(
  .STATUS(DCM_STATUS)
 );

+my_dcm snes_dcm2(
+  .CLKIN(SNES_SYSCLK),
+  .CLKFX(SYSCLK2),
+  .RST(DCM_RST)
+);
+
 assign DCM_RST=0;

+reg [5:0] SNES_PARDr;
 reg [5:0] SNES_READr;
 reg [5:0] SNES_WRITEr;
 reg [5:0] SNES_CPU_CLKr;

+wire SNES_PARD_start = (SNES_PARDr == 6'b111110);
 wire SNES_RD_start = (SNES_READr == 6'b111110);
 wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
 wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
 wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);

+always @(posedge SYSCLK2) begin
+  SNES_PARDr <= {SNES_PARDr[4:0], SNES_PARD};
+end
+
 always @(posedge CLK2) begin
  SNES_READr <= {SNES_READr[4:0], SNES_READ};
  SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
@@ -268,6 +289,7 @@ address snes_addr(
  .CLK(CLK2),
  .MAPPER(MAPPER),
  .SNES_ADDR(SNES_ADDR), // requested address from SNES
+  .SNES_PA(SNES_PA),
  .SNES_CS(SNES_CS),
  .ROM_ADDR(MAPPED_SNES_ADDR),   // Address to request from SRAM (active low)
  .ROM_SEL(ROM_SEL),     // which SRAM unit to access
@@ -281,7 +303,8 @@ address snes_addr(
  .msu_enable(msu_enable),
  //CX4
  .cx4_enable(cx4_enable),
-  .cx4_vect_enable(cx4_vect_enable)
+  .cx4_vect_enable(cx4_vect_enable),
+  .r213f_enable(r213f_enable)
 );

 reg [7:0] CX4_DINr;
@@ -347,11 +370,21 @@ assign CX4_SNES_DATA_IN = SNES_DATA;
 reg [7:0] SNES_DINr;
 reg [7:0] ROM_DOUTr;

-assign SNES_DATA = (!SNES_READ) 
-                    ? (msu_enable ? MSU_SNES_DATA_OUT
+reg [7:0] r213fr;
+reg r213f_forceread;
+reg [2:0] r213f_delay;
+reg [1:0] r213f_state;
+initial r213fr = 8'h55;
+initial r213f_forceread = 0;
+initial r213f_state = 2'b01;
+initial r213f_delay = 3'b011;
+
+assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr
+                   :(!SNES_READ ^ r213f_forceread)
+                     ? (msu_enable ? MSU_SNES_DATA_OUT
                       :cx4_enable ? CX4_SNES_DATA_OUT
                       :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
-                       : SNES_DINr)
+                       :SNES_DINr)
                    : 8'bZ;

 reg [3:0] ST_MEM_DELAYr;
@@ -539,6 +572,21 @@ always @(posedge CLK2) begin
  end
 end

+always @(posedge SYSCLK2) begin
+  if(SNES_PARD_start & r213f_enable) begin
+    r213f_forceread <= 1'b1;
+    r213f_delay <= 3'b001;
+    r213f_state <= 2'b10;
+  end else if(r213f_state == 2'b10) begin
+    r213f_delay <= r213f_delay - 1;
+    if(r213f_delay == 3'b000) begin
+      r213f_forceread <= 1'b0;
+      r213f_state <= 2'b01;
+      r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
+    end
+  end
+end
+
 assign ROM_DATA[7:0] = ROM_ADDR0
                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
                                        : (!ROM_WE ? ROM_DOUTr : 8'bZ)
@@ -565,11 +613,14 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
 assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
                         cx4_enable ? 1'b0 :
                         (cx4_active & cx4_vect_enable) ? 1'b0 :
+                         r213f_enable & !SNES_PARD ? 1'b0 :
                         ((!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
                          |(SNES_READ & SNES_WRITE)
                         );

-assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
+assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & r213f_enable))
+                           ? 1'b1 ^ r213f_forceread
+                           : 1'b0;

 assign IRQ_DIR = 1'b0;
 assign SNES_IRQ = 1'bZ;
--- a/verilog/sd2snes_cx4/sd2snes_cx4.xise
+++ b/verilog/sd2snes_cx4/sd2snes_cx4.xise
@@ -284,7 +284,7 @@
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
@@ -366,8 +366,8 @@
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="5" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="5" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="4" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
--- a/verilog/sd2snes_cx4/sd_dma.v
+++ b/verilog/sd2snes_cx4/sd_dma.v
@@ -29,7 +29,9 @@ module sd_dma(
  output [7:0] SD_DMA_SRAM_DATA,
  input SD_DMA_PARTIAL,
  input [10:0] SD_DMA_PARTIAL_START,
-  input [10:0] SD_DMA_PARTIAL_END
+  input [10:0] SD_DMA_PARTIAL_END,
+  input SD_DMA_START_MID_BLOCK,
+  input SD_DMA_END_MID_BLOCK
 );

 reg [10:0] SD_DMA_STARTr;
@@ -85,7 +87,9 @@ always @(posedge CLK) begin
 end

 always @(posedge CLK) begin
-  if(cyclecnt == 1042) SD_DMA_DONEr <= 1;
+  if(cyclecnt == 1042
+     || ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END))
+    SD_DMA_DONEr <= 1;
  else SD_DMA_DONEr <= 0;
 end

@@ -100,8 +104,10 @@ always @(posedge CLK) begin
 end

 always @(posedge CLK) begin
-  if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0;
-  else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1;
+  if(SD_DMA_EN_rising) 
+    cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0;
+  else if(!SD_DMA_STATUSr) cyclecnt <= 0;
+  else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
 end

 // we have 8 clk cycles to complete one RAM write
Author	SHA1	Message	Date
ikari	8c0ca0ea05	PCB: update Rev.E assembly diagrams	2012-01-14 23:35:14 +01:00
ikari	f0a2e85c65	FPGA: updated project files	2012-01-14 23:16:57 +01:00
ikari	86a81bfa82	PCB: Rev.E2 WIP	2012-01-14 23:13:38 +01:00
ikari	cb859f3bfb	Firmware: add SD debugging message	2012-01-14 23:12:45 +01:00
ikari	a79a538560	update changelog	2012-01-14 23:08:12 +01:00
ikari	da2386e453	Firmware/MSU1: stop DAC at end of audio file	2012-01-14 12:18:13 +01:00
ikari	b8f4c9b584	Firmware: optimize non-sector-aligned SD DMA reads (bugfix)	2012-01-14 11:58:20 +01:00
ikari	d7ad740843	FPGA/Cx4: add missing file main.ucf	2012-01-14 02:25:34 +01:00
ikari	2d89eb8000	SNES menu: swap A and B buttons	2012-01-14 02:23:43 +01:00
ikari	d139fdb40c	SNES menu: helper script for map creation	2012-01-14 02:22:42 +01:00
ikari	059966f06a	FPGA/Cx4: optimize non-sector-aligned SD DMA reads	2012-01-14 02:21:01 +01:00
ikari	3243143c39	FPGA/Cx4: region override (patch register $213f)	2012-01-14 02:19:39 +01:00
ikari	a50522b4e9	FPGA: optimize non-sector-aligned SD DMA reads	2012-01-14 01:22:38 +01:00
ikari	eefcc712ca	FPGA: add RAM1 pinout to user constraints	2012-01-14 01:21:40 +01:00
ikari	5a3e935a3e	FPGA: region override (patch register $213f)	2012-01-14 01:21:21 +01:00
ikari	5f87768a14	Firmware: remove unnecessary crc16.c from Makefile	2012-01-14 01:17:59 +01:00
ikari	3436ccf46a	Firmware: improve map detection	2012-01-14 01:17:20 +01:00
ikari	03ee71a626	Firmware/MSU1: add debug macros before logging statements	2012-01-14 01:14:37 +01:00
ikari	b272a6fc1c	Firmware: optimize non-sector-aligned SD DMA reads	2012-01-14 01:13:36 +01:00
ikari	afc26397b1	Firmware: region override (patch register $213f)	2012-01-14 01:10:13 +01:00
ikari	3506cb0ba2	Firmware/bootldr: size reduction and stability measures	2012-01-14 01:05:15 +01:00
ikari	52d5fc9e92	PCB Rev.E: update BOM (RA103, RA104 final)	2012-01-13 13:39:24 +01:00
ikari	cbe30cb388	PCB Rev.E: update BOM (-> RA103, RA104 pending)	2012-01-10 23:59:33 +01:00
ikari	a52638b4be	Firmware: update version number to 0.1.2	2012-01-02 23:36:42 +01:00
ikari	22fe28c624	SNES: insert debug marker	2012-01-02 23:34:45 +01:00
ikari	2c14c3f925	SNES: fix crash on empty database	2012-01-02 23:34:31 +01:00
ikari	fec9004dc1	SNES: display system information (new menu entry)	2012-01-02 23:33:24 +01:00
ikari	97aef4a2d3	Firmware: gather+display system information	2012-01-02 23:31:40 +01:00
ikari	6d28f3fb51	PCB: very basic solder paste pad reduction script	2011-12-27 10:31:39 +01:00
ikari	1585032c5a	PCB: Rev.E2 (replace elusive Micrel regulator)	2011-12-27 01:56:24 +01:00