revyos_defconfig: enable nfs kernel server support

This version update involves a lot of content, so the previous version
has been deleted and the new version has been re-merged into the kernel.

The configuration file for the GPU driver originates from a previous
version.

Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>

.github/workflows/kernel.yml

@@ -0,0 +1,103 @@
+name: revyos-kernel-build
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+  schedule:
+    - cron: "0 2 * * *"
+
+env:
+  xuetie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1663142514282
+  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.6.1-20220906.tar.gz
+  ARCH: riscv
+  board: lpi4a
+
+jobs:
+  kernel:
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          - name: thead-gcc
+            toolchain_tripe: riscv64-unknown-linux-gnu-
+          - name: gcc-12
+            toolchain_tripe: riscv64-linux-gnu-
+
+    runs-on: ubuntu-22.04
+    env:
+      CROSS_COMPILE: ${{ matrix.toolchain_tripe }}
+
+    steps:
+      - name: Install software
+        run: |
+              sudo apt update && \
+              sudo apt install -y gdisk dosfstools g++-12-riscv64-linux-gnu build-essential \
+                                  libncurses-dev gawk flex bison openssl libssl-dev tree \
+                                  dkms libelf-dev libudev-dev libpci-dev libiberty-dev autoconf device-tree-compiler \
+                                  devscripts
+              sudo update-alternatives --install \
+                  /usr/bin/riscv64-linux-gnu-gcc riscv64-gcc /usr/bin/riscv64-linux-gnu-gcc-12 10
+              sudo update-alternatives --install \
+                  /usr/bin/riscv64-linux-gnu-g++ riscv64-g++ /usr/bin/riscv64-linux-gnu-g++-12 10
+
+      - name: Checkout kernel
+        uses: actions/checkout@v3
+        with:
+            path: 'kernel'
+
+      - name: Configure toolchains
+        run: |
+              mkdir rootfs && mkdir rootfs/boot
+              if [ x"${{ matrix.name }}" = x"thead-gcc" ]; then
+                wget ${xuetie_toolchain}/${toolchain_file_name}
+                tar -xvf ${toolchain_file_name} -C /opt
+              fi
+
+      - name: Compile Kernel && Install
+        run: |
+              export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.6.1/bin:$PATH"
+
+              pushd kernel
+                make revyos_defconfig
+                export KDEB_PKGVERSION="$(date "+%Y.%m.%d.%H.%M")+$(git rev-parse --short HEAD)"
+                if [ x"${{ matrix.name }}" = x"gcc-12" ]; then
+                  echo "CONFIG_THEAD_ISA=n" >> .config
+                elif [ x"${{ matrix.name }}" = x"thead-gcc" ]; then
+                  echo "CONFIG_THEAD_ISA=y" >> .config
+                fi
+                make -j$(nproc) bindeb-pkg LOCALVERSION="-${board}"
+                make -j$(nproc) dtbs
+                # if [ x"$(cat .config | grep CONFIG_MODULES=y)" = x"CONFIG_MODULES=y" ]; then
+                #   sudo make INSTALL_MOD_PATH=${GITHUB_WORKSPACE}/rootfs/ modules_install -j$(nproc)
+                # fi
+                # sudo make INSTALL_PATH=${GITHUB_WORKSPACE}/rootfs/boot install -j$(nproc)
+
+                # Copy deb
+                sudo dcmd cp -v ../*.changes ${GITHUB_WORKSPACE}/rootfs/
+
+                # build perf & install
+                # make LDFLAGS=-static NO_LIBELF=1 NO_JVMTI=1 VF=1 -C tools/perf/
+                # sudo mkdir -p ${GITHUB_WORKSPACE}/rootfs/sbin/
+                # sudo cp -v tools/perf/perf ${GITHUB_WORKSPACE}/rootfs/sbin/perf-thead
+
+                # Install Kernel
+                # sudo cp -v arch/riscv/boot/Image ${GITHUB_WORKSPACE}/rootfs/boot/
+
+                # record commit-id
+                git rev-parse HEAD > kernel-commitid
+                sudo cp -v kernel-commitid ${GITHUB_WORKSPACE}/rootfs/boot/
+
+                # Install DTB
+                sudo cp -v arch/riscv/boot/dts/thead/{light-lpi4a.dtb,light-lpi4a-16gb.dtb} ${GITHUB_WORKSPACE}/rootfs/boot/
+              popd
+
+      - name: compress
+        run: tar -zcvf thead-kernel-${{ matrix.name }}.tar.gz rootfs
+
+      - name: 'Upload Artifact'
+        uses: actions/upload-artifact@v3
+        with:
+          name: thead-kernel-${{ matrix.name }}.tar.gz
+          path: thead-kernel-${{ matrix.name }}.tar.gz
+          retention-days: 30

Makefile

@@ -480,6 +480,8 @@ LZ4		= lz4
 XZ		= xz
 ZSTD		= zstd
 
+PAHOLE_FLAGS	= $(shell PAHOLE=$(PAHOLE) $(srctree)/scripts/pahole-flags.sh)
+
 CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
 		  -Wbitwise -Wno-return-void -Wno-unknown-attribute $(CF)
 NOSTDINC_FLAGS :=
@@ -534,6 +536,7 @@ export KBUILD_CFLAGS CFLAGS_KERNEL CFLAGS_MODULE
 export KBUILD_AFLAGS AFLAGS_KERNEL AFLAGS_MODULE
 export KBUILD_AFLAGS_MODULE KBUILD_CFLAGS_MODULE KBUILD_LDFLAGS_MODULE
 export KBUILD_AFLAGS_KERNEL KBUILD_CFLAGS_KERNEL
+export PAHOLE_FLAGS
 
 # Files to ignore in find ... statements
 

arch/riscv/Kconfig

@@ -21,7 +21,6 @@ config RISCV
 	select ARCH_HAS_GCOV_PROFILE_ALL
 	select ARCH_HAS_GIGANTIC_PAGE
 	select ARCH_HAS_KCOV
-	select ARCH_HAS_MMIOWB
 	select ARCH_HAS_PTE_SPECIAL
 	select ARCH_HAS_SET_DIRECT_MAP
 	select ARCH_HAS_SET_MEMORY
@@ -35,6 +34,7 @@ config RISCV
 	select ARCH_KEEP_MEMBLOCK
 	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
 	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
+	select ARCH_USE_QUEUED_SPINLOCKS
 	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
 	select ARCH_WANT_FRAME_POINTERS
@@ -393,42 +393,14 @@ config FPU
 	  If you don't know what to do here, say Y.
 
 config VECTOR
-	bool "VECTOR support"
-	default n
-
-choice VECTOR_VERSION
-	prompt "Vector Version"
-	depends on VECTOR
-	default VECTOR_1_0
-
-config VECTOR_1_0
-	bool "VECTOR 1.0 support"
-	help
-	  Say N here if you want to disable all vector 1.0 related procedure
-	  in the kernel.
-
-	  If you don't know what to do here, say Y.
-
-config VECTOR_0_7
 	bool "VECTOR 0.7 support"
+	default y
 	help
 	  Say N here if you want to disable all vector 0.7 related procedure
 	  in the kernel.
 
 	  If you don't know what to do here, say Y.
 
-endchoice
-
-config VLEN_256
-	bool "VECTOR VLEN 256"
-	depends on VECTOR
-	default n
-
-config VECTOR_EMU
-	bool "VECTOR e64 emulate for c906 v1"
-	depends on VECTOR
-	default n
-
 config THEAD_ISA
 	bool "T-HEAD extension ISA in AFLAGS with -march=_xtheadc"
 	default n

arch/riscv/Makefile

@@ -48,25 +48,20 @@ endif
 endif
 
 # ISA string setting
+riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
+riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
+riscv-march-$(CONFIG_FPU)			:= $(riscv-march-y)fd
+riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
+riscv-march-$(CONFIG_VECTOR)		:= $(riscv-march-y)v0p7
+riscv-march-$(CONFIG_THEAD_ISA)		:= $(riscv-march-y)_xtheadc
+
 # Newer binutils versions default to ISA spec version 20191213 which moves some
 # instructions from the I extension to the Zicsr and Zifencei extensions.
 toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
 riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
 
-riscv-march-cflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
-riscv-march-cflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
-riscv-march-cflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-cflags-y)c
-
-riscv-march-aflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
-riscv-march-aflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
-riscv-march-aflags-$(CONFIG_FPU)		:= $(riscv-march-aflags-y)fd
-riscv-march-aflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-aflags-y)c
-riscv-march-aflags-$(CONFIG_VECTOR_1_0)		:= $(riscv-march-aflags-y)v
-riscv-march-aflags-$(CONFIG_VECTOR_0_7)		:= $(riscv-march-aflags-y)v0p7
-riscv-march-aflags-$(CONFIG_THEAD_ISA)		:= $(riscv-march-aflags-y)_xtheadc
-
-KBUILD_CFLAGS += -march=$(riscv-march-cflags-y) -Wa,-march=$(riscv-march-aflags-y)
-KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
+KBUILD_CFLAGS += -march=$(subst _xtheadc,,$(subst v0p7,,$(subst fd,,$(riscv-march-y))))
+KBUILD_AFLAGS += -march=$(riscv-march-y)
 
 KBUILD_CFLAGS += -mno-save-restore
 KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
@@ -124,7 +119,7 @@ endif
 ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_KENDRYTE),yy)
 KBUILD_IMAGE := $(boot)/loader.bin
 else
-KBUILD_IMAGE := $(boot)/Image.gz
+KBUILD_IMAGE := $(boot)/Image
 endif
 BOOT_TARGETS := Image Image.gz loader loader.bin
 

arch/riscv/boot/dts/thead/Makefile

@@ -12,22 +12,25 @@ dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G.dtb light-a-val-ddr1G.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb light-a-val-audio-i2s-8ch.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-tdm.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-spdif.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dsi0-hdmi-audio.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-gpio-keys.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-product.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb light-b-product-sec.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-b-product-miniapp-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-ant-ref.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-lpi4a.dtb light-lpi4a-ddr2G.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-lpi4a.dtb light-lpi4a-ddr2G.dtb light-lpi4a-16gb.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-lpi4a-cluster.dtb light-lpi4a-cluster-16gb.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb
@@ -37,3 +40,5 @@ dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb
 
 dtb-$(CONFIG_SOC_THEAD) += fire-emu.dtb fire-emu-crash.dtb
 dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb
+dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base-sec.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-lpi4a-laptop.dtb

arch/riscv/boot/dts/thead/fire-crash.dts

@@ -523,7 +523,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238

arch/riscv/boot/dts/thead/fire-emu-soc-base-sec.dts

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+/* #include "fire-emu.dts" */
+#include "fire-emu-soc-base.dts"
+
+&light_iopmp {
+        status = "disabled";
+};

arch/riscv/boot/dts/thead/fire-emu.dts

@@ -338,16 +338,18 @@
         clock-frequency = <100000>;
         status = "disabled";
 
-       es8156_audio_codec: es8156@8 {
+        es8156_audio_codec: es8156@8 {
                #sound-dai-cells = <0>;
                compatible = "everest,es8156";
                reg = <0x08>;
-       };
+               status = "disabled";
+        };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                status = "disabled";
         };
 };
 
@@ -488,7 +490,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238

arch/riscv/boot/dts/thead/fire.dtsi

@@ -373,7 +373,7 @@
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
 			control-val = <0x1c>;
-			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
 		};
 
 		clint0: clint@ffdc000000 {
@@ -1335,8 +1335,7 @@
 
 		emmc: sdhci@ffe7080000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7080000 0x0 0x10000
-			       0xff 0xef014060 0x0 0x4>;
+			reg = <0xff 0xe7080000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <62>;
 			interrupt-names = "sdhciirq";
@@ -1346,8 +1345,7 @@
 
 		sdhci0: sd@ffe7090000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7090000 0x0 0x10000
-			       0xff 0xef014064 0x0 0x4>;
+			reg = <0xff 0xe7090000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <64>;
 			interrupt-names = "sdhci0irq";
@@ -1357,8 +1355,7 @@
 
 		sdhci1: sd@ffe70a0000 {
 		        compatible = "snps,dwcmshc-sdhci";
-		        reg = <0xff 0xe70a0000 0x0 0x10000
-		               0xff 0xef014064 0x0 0x4>;
+		        reg = <0xff 0xe70a0000 0x0 0x10000>;
 		        interrupt-parent = <&intc>;
 		        interrupts = <71>;
 		        interrupt-names = "sdhci1irq";
@@ -1433,7 +1430,7 @@
 			compatible = "light,light-i2s";
 			reg = <0xff 0xe7034000 0x0 0x4000>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_audio_i2s0>;
+			pinctrl-0 = <&pinctrl_light_i2s0>;
 			light,mode = "i2s-master";
 			light,sel = "ap_i2s";
 			interrupt-parent = <&intc>;

arch/riscv/boot/dts/thead/light-a-product.dts

@@ -687,6 +687,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -729,7 +730,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238

arch/riscv/boot/dts/thead/light-a-val-android.dts

@@ -63,7 +63,7 @@
                         sound-dai = <&light_i2s 1>;
                 };
                 codec {
-                        sound-dai = <&dummy_codec 2>;
+                        sound-dai = <&dummy_codec>;
                 };
     };
 };

arch/riscv/boot/dts/thead/light-a-val-audio-hdmi.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "light-a-val.dts"
+#include "light-a-val-audio.dts"
 
 / {
 	display-subsystem {
@@ -40,28 +40,6 @@
 
 &lightsound {
 	status = "okay";
-
-        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
-                reg = <0>;
-                format = "i2s";
-                cpu {
-                        sound-dai = <&i2s0 0>;
-                };
-                codec {
-                        sound-dai = <&es8156_audio_codec>;
-                };
-        };
-
-        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
-                reg = <1>;
-                format = "i2s";
-                cpu {
-                        sound-dai = <&i2s3 0>;
-                };
-                codec {
-                        sound-dai = <&es7210_audio_codec>;
-                };
-        };
 	
 	simple-audio-card,dai-link@2 {          /* I2S - HDMI */
 		reg = <2>;
@@ -70,7 +48,7 @@
 			sound-dai = <&light_i2s 1>;
 		};
 		codec {
-			sound-dai = <&dummy_codec 2>;
+			sound-dai = <&dummy_codec>;
 		};
 	};
 };
@@ -78,12 +56,3 @@
 &light_i2s {
         status = "okay";
 };
-
-&i2s0 {
-        status = "okay";
-};
-
-&i2s3 {
-        status = "okay";
-};
-

arch/riscv/boot/dts/thead/light-a-val-audio-i2s-8ch.dts

@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "light-a-val-audio.dts"
+
+/ {
+	model = "T-HEAD Light FM Audio VAL board";
+	compatible = "thead,light-val-audio-i2s-8ch", "thead,light";
+};
+
+
+&lightsound {
+        status = "okay";
+
+	simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd2 2>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
+                };
+        };
+
+	simple-audio-card,dai-link@2 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <2>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd3 3>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
+                };
+        };
+
+        simple-audio-card,dai-link@3 {          /* I2S - AUDIO SYS CODEC 7210_1*/
+                reg = <3>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd0 0>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc1>;
+                };
+        };
+
+        simple-audio-card,dai-link@4 {          /* I2S - AUDIO SYS CODEC 7210_1*/
+                reg = <4>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd1 1>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc1>;
+                };
+        };
+};
+
+&i2s_8ch_sd0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa4>,
+                    <&pinctrl_audio_i2s_8ch_sd0>,
+                    <&pinctrl_audiopa2>,
+                    <&pinctrl_audiopa3>,
+                    <&pinctrl_audiopa8>,
+                    <&pinctrl_audio_i2s_8ch_bus>;
+};
+
+&i2s_8ch_sd1 {
+        status = "okay";
+};
+
+&i2s_8ch_sd2 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa0>,
+                    <&pinctrl_audio_i2s_8ch_sd2>;
+};
+
+&i2s_8ch_sd3 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
+        status = "okay";
+        channels-max = <8>;
+};
+
+&es7210_audio_codec_adc1 {
+        status = "okay";
+        channels-max = <8>;
+};

arch/riscv/boot/dts/thead/light-a-val-audio-spdif.dts

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "light-a-val.dts"
+
+&spdif0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audio_spdif0>;
+	status = "okay";
+};
+
+&spdif1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audio_spdif1>;
+	status = "okay";
+};
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,dai-link@0 {          /* SPDIF0 */
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&spdif0>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
+        simple-audio-card,dai-link@1 {          /* SPDIF1 */
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&spdif1>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
+};

arch/riscv/boot/dts/thead/light-a-val-audio-tdm.dts

@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "light-a-val.dts"
+
+&tdm_slot1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audio_tdm>;
+	status = "okay";
+};
+
+&tdm_slot2 {
+	status = "okay";
+};
+
+&tdm_slot3 {
+	status = "okay";
+};
+
+&tdm_slot4 {
+	status = "okay";
+};
+
+&tdm_slot5 {
+	status = "okay";
+};
+
+&tdm_slot6 {
+	status = "okay";
+};
+
+&tdm_slot7 {
+	status = "okay";
+};
+
+&tdm_slot8 {
+	status = "okay";
+};
+
+&audio_i2c0 {
+        clock-frequency = <100000>;
+        status = "okay";
+
+        es7210_adc2: es7210@42 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_0";
+                reg = <0x42>;
+                work-mode = "ES7210_TDM_1LRCK_DSPB";
+                channels-max = <8>;
+                sound-name-prefix = "ES7210_ADC2";
+                MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                DVDD-supply = <&soc_dvdd18_aon_reg>;
+                PVDD-supply = <&soc_dvdd18_aon_reg>;
+        };
+
+        es7210_adc3: es7210@43 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_1";
+                reg = <0x43>;
+                work-mode = "ES7210_TDM_1LRCK_DSPB";
+                channels-max = <8>;
+                sound-name-prefix = "ES7210_ADC3";
+                MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                DVDD-supply = <&soc_dvdd18_aon_reg>;
+                PVDD-supply = <&soc_dvdd18_aon_reg>;
+        };
+};
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"AW87519 IN", "ES8156 ROUT",
+        	"Speaker", "AW87519 VO";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
+        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
+                reg = <0>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+                codec {
+                        sound-dai = <&es8156_audio_codec>;
+                };
+        };
+
+        simple-audio-card,dai-link@1 {          /* TDM - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot1>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@2 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot2>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@3 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot3>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@4 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot4>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@5 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot5>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@6 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot6>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@7 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot7>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@8 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot8>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+};
+
+&i2s0 {
+        status = "okay";
+};

arch/riscv/boot/dts/thead/light-a-val-audio.dts

@@ -11,8 +11,12 @@
 };
 
 &lightsound {
-	status = "okay";
-
+        status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -28,22 +32,24 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
-                        sound-dai = <&es7210_audio_codec>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
                 };
         };
 };
 
-&light_i2s {
-	status = "okay";
-};
-
 &i2s0 {
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
 };
+
+&es7210_audio_codec_adc0 {
+        status = "okay";
+};
+
+

arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts

@@ -11,7 +11,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x40000000>;
+		reg = <0x0 0x200000 0x0 0x3fe00000>;
 	};
 };
 

arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts

@@ -11,7 +11,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 };
 

arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-audio.dts

@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "light-a-val-dsi0-hdmi.dts"
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
+        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
+                reg = <0>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+                codec {
+                        sound-dai = <&es8156_audio_codec>;
+                };
+        };
+
+        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd2 2>;
+                };
+                codec {
+                        sound-dai = <&es7210_audio_codec_adc0>;
+                };
+        };
+        simple-audio-card,dai-link@2 {          /* I2S - HDMI */
+                reg = <2>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&light_i2s 1>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
+};
+
+&light_i2s {
+	status = "okay";
+};
+
+&i2s0 {
+        status = "okay";
+};
+
+&i2s_8ch_sd2 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
+        status = "okay";
+};

arch/riscv/boot/dts/thead/light-a-val-full.dts

@@ -95,7 +95,11 @@
 
 &lightsound {
         status = "okay";
-
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -111,23 +115,27 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
-                        sound-dai = <&es7210_audio_codec>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
                 };
         };
 };
 
 &light_i2s {
-        status = "okay";
+	status = "okay";
 };
 
 &i2s0 {
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
+        status = "okay";
+};
+ 
+&es7210_audio_codec_adc0 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-a-val-hdmi.dts

@@ -48,7 +48,7 @@
 			sound-dai = <&light_i2s 1>;
 		};
 		codec {
-			sound-dai = <&dummy_codec 2>;
+			sound-dai = <&dummy_codec>;
 		};
 	};
 };

arch/riscv/boot/dts/thead/light-a-val-miniapp-dsi0.dts

@@ -74,6 +74,26 @@
 	};
 };
 
+&padctrl_audiosys {
+	status = "okay";
+
+	light-audio-padctrl {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+
+			pinctrl_audio_i2s_8ch: audio_i2s_8ch_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA0	  0x2 0x008
+					FM_AUDIO_IO_PA2	  0x2 0x008
+					FM_AUDIO_IO_PA3   0x2 0x008
+					FM_AUDIO_IO_PA8   0x2 0x008
+				>;
+			};
+	};
+};
+
 &lightsound {
 	status = "okay";
 
@@ -92,15 +112,14 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
-                        sound-dai = <&es7210_audio_codec>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
                 };
         };
 };
 
-
 &light_i2s {
 	status = "okay";
 };
@@ -109,7 +128,11 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi.dts

@@ -56,10 +56,10 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
-                        sound-dai = <&es7210_audio_codec>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
                 };
         };
 };
@@ -73,7 +73,11 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-a-val-sec.dts

@@ -5,9 +5,13 @@
 
 /dts-v1/;
 
-#include "light-a-val-dsi0-hdmi.dts"
+#include "light-a-val-audio-hdmi.dts"
 
 
 &light_iopmp {
         status = "disabled";
 };
+&qspi1 {
+        status = "disabled";
+};
+

arch/riscv/boot/dts/thead/light-a-val.dts

@@ -179,7 +179,8 @@
 		compatible = "thead,light-mbox-client";
 		mbox-names = "906";
 		mboxes = <&mbox_910t 2 0>;
-		status = "disabled";
+		audio-mbox-regmap = <&audio_mbox>;
+		status = "okay";
 	};
 
 	lightsound: lightsound@1 {
@@ -192,9 +193,24 @@
 		status = "disabled";
 	};
 
+	light_rpmsg: light_rpmsg {
+		compatible = "light,rpmsg-bus", "simple-bus";
+		memory-region = <&rpmsgmem>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		rpmsg: rpmsg{
+			vdev-nums = <1>;
+            reg = <0x0 0x1E000000 0 0x10000>;
+			compatible = "light,light-rpmsg";
+			status = "okay";
+		};
+	};
+
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
-		compatible = "linux,bt-sco";
+		#sound-dai-cells = <0>;
+		compatible = "thead,light-dummy-pcm";
+		sound-name-prefix = "DUMMY";
 		status = "okay";
 	};
 
@@ -262,6 +278,24 @@
 		enable-active-high;
 	};
 
+	soc_aud_adc_3v3_en_reg: soc-aud-adc-3v3-en {
+		compatible = "regulator-fixed";
+		regulator-name = "soc_aud_adc_3v3_en";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pcal6408ahk_b 1 1>;
+		enable-active-high;
+	};
+
+	soc_aud_dac_3v3_en_reg: soc-aud-dac-3v3-en {
+		compatible = "regulator-fixed";
+		regulator-name = "soc_aud_dac_3v3_en";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pcal6408ahk_b 2 1>;
+		enable-active-high;
+	};
+
 	wcn_wifi: wireless-wlan {
 		compatible = "wlan-platdata";
 		clock-names = "clk_wifi";
@@ -512,7 +546,14 @@
 		reg = <0x0 0x22000000 0x0 0x10000000>;
 		no-map;
 	};
-
+    audio_mem: memory@32000000 {
+		reg = <0x0 0x32000000 0x0 0x6400000>;
+		no-map;
+    };
+	rpmsgmem: memory@1E000000 {
+		reg = <0x0 0x1E000000 0x0 0x10000>;
+		no-map;
+	};
 };
 
 &adc {
@@ -556,17 +597,74 @@
 &audio_i2c0 {
         clock-frequency = <100000>;
         status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_audiopa6>,
+					<&pinctrl_audiopa7>,
+					<&pinctrl_audio_i2c0>;
 
-       es8156_audio_codec: es8156@8 {
-               #sound-dai-cells = <0>;
-               compatible = "everest,es8156";
-               reg = <0x08>;
-       };
+        es8156_audio_codec: es8156@8 {
+                #sound-dai-cells = <0>;
+                compatible = "everest,es8156";
+                reg = <0x08>;
+                sound-name-prefix = "ES8156";
+                AVDD-supply = <&soc_aud_dac_3v3_en_reg>;
+                DVDD-supply = <&soc_dvdd18_aon_reg>;
+                PVDD-supply = <&soc_dvdd18_aon_reg>;
+				mclk-sclk-ratio = <4>;
+        };
 
-        es7210_audio_codec: es7210@40 {
+        es7210_audio_codec_adc0: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                status = "disabled";
+                work-mode = "ES7210_NORMAL_I2S";
+                channels-max = <2>;
+                mclk-sclk-ratio = <4>;
+                sound-name-prefix = "ES7210_ADC0";
+                MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                DVDD-supply = <&soc_dvdd18_aon_reg>;
+                PVDD-supply = <&soc_dvdd18_aon_reg>;
+        };
+
+        es7210_audio_codec_adc1: es7210@41 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_1";
+                reg = <0x41>;
+                status = "disabled";
+                work-mode = "ES7210_NORMAL_I2S";
+                channels-max = <2>;
+                mclk-sclk-ratio = <4>;
+                sound-name-prefix = "ES7210_ADC1";
+                MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                DVDD-supply = <&soc_dvdd18_aon_reg>;
+                PVDD-supply = <&soc_dvdd18_aon_reg>;
+        };
+
+        audio_aw87519_pa: amp@58 {
+                compatible = "awinic,aw87519_pa";
+                reg = <0x58>;
+                reset-gpio = <&pcal6408ahk_b 3 0x1>;
+                sound-name-prefix = "AW87519";
+                status = "okay";
+        };
+};
+
+&audio_i2c1 {
+        clock-frequency = <100000>;
+        status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_audiopa13>,
+					<&pinctrl_audiopa16>,
+					<&pinctrl_audio_i2c1>;
+
+        pcal6408ahk_b: gpio@20 {
+                compatible = "nxp,pcal9554b";
+                reg = <0x20>;
+                gpio-controller;
+                #gpio-cells = <2>;
         };
 };
 
@@ -717,6 +815,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -759,7 +858,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -834,22 +933,151 @@
 			 * Format: <pin_id mux_node config>
 			 */
 
-			pinctrl_audiopa1: audiopa1_grp {
-				thead,pins = <
-					FM_AUDIO_PA1	0x3	0x72
-				>;
+			pinctrl_audiopa0: audiopa0 {
+				thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >;
 			};
-
-			pinctrl_audiopa2: audiopa2_grp {
-				thead,pins = <
-					FM_AUDIO_PA2	0x0	0x72
-				>;
+			pinctrl_audiopa1: audiopa1 {
+				thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa2: audiopa2 {
+				thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa3: audiopa3 {
+				thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa4: audiopa4 {
+				thead,pins = < FM_AUDIO_PA4 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa5: audiopa5 {
+				thead,pins = < FM_AUDIO_PA5 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa6: audiopa6 {
+				thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa7: audiopa7 {
+				thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa8: audiopa8 {
+				thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa9: audiopa9 {
+				thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa10: audiopa10 {
+				thead,pins = < FM_AUDIO_PA10 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa11: audiopa11 {
+				thead,pins = < FM_AUDIO_PA11 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa12: audiopa12 {
+				thead,pins = < FM_AUDIO_PA12 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa13: audiopa13 {
+				thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa14: audiopa14 {
+				thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa15: audiopa15 {
+				thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa16: audiopa16 {
+				thead,pins = < FM_AUDIO_PA16 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa17: audiopa17 {
+				thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >;
 			};
 
 			pinctrl_volume: volume_grp {
 				thead,pins = <
-					FM_CPU_JTG_TDI  0x3     0x208
-					FM_CPU_JTG_TDO  0x3     0x208
+					FM_CPU_JTG_TDI  0x3     0x238
+					FM_CPU_JTG_TDO  0x3     0x238
+				>;
+			};
+	};
+};
+
+&padctrl_audiosys {
+
+	status = "okay";
+
+	light-audio-padctrl {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+
+			pinctrl_audio_i2c0: audio_i2c0_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA6		LIGHT_PIN_FUNC_0 0x004
+					FM_AUDIO_IO_PA7		LIGHT_PIN_FUNC_0 0x004
+				>;
+			};
+			pinctrl_audio_i2c1: audio_i2c1_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA13	LIGHT_PIN_FUNC_1 0x004
+					FM_AUDIO_IO_PA16	LIGHT_PIN_FUNC_3 0x004
+				>;
+			};
+			pinctrl_audio_i2s0: audio_i2s0_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA9	  LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA10   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA11   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA12   LIGHT_PIN_FUNC_0 0x008
+				>;
+			};
+			pinctrl_audio_i2s1: audio_i2s1_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA14   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA15   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA17   LIGHT_PIN_FUNC_0 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA2	  LIGHT_PIN_FUNC_3 0x008
+					FM_AUDIO_IO_PA3   LIGHT_PIN_FUNC_3 0x008
+					FM_AUDIO_IO_PA8   LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_sd0: audio_i2s_8ch_sd0_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA4	  LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_sd1: audio_i2s_8ch_sd1_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA5   LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA0	  LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA1   LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+			pinctrl_audio_tdm: audio_tdm_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA27   LIGHT_PIN_FUNC_1 0x007
+					FM_AUDIO_IO_PA28   LIGHT_PIN_FUNC_1 0x007
+					FM_AUDIO_IO_PA29   LIGHT_PIN_FUNC_1 0x000
+				>;
+			};
+			pinctrl_audio_spdif0: audio_spdif0_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA21   LIGHT_PIN_FUNC_1 0x000
+					FM_AUDIO_IO_PA22   LIGHT_PIN_FUNC_1 0x007
+				>;
+			};
+			pinctrl_audio_spdif1: audio_spdif1_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA23   LIGHT_PIN_FUNC_1 0x007
+					FM_AUDIO_IO_PA24   LIGHT_PIN_FUNC_1 0x000
 				>;
 			};
 	};
@@ -989,6 +1217,24 @@
 	status = "disabled";
 };
 
+
+&vvcam_sensor1 {
+	sensor_name = "OV5693";
+	sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+	sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
+	sensor_regulator_timing_us = <70 50 20>;
+	sensor_rst = <&gpio1_porta 16 0>;
+	sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
+	DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+	DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+	AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+    i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x36>;
+	i2c_bus = /bits/ 8 <3>;
+	status = "okay";
+};
+
 &vvcam_sensor2 {
 	sensor_name = "GC5035";
 	sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
@@ -1073,6 +1319,22 @@
 	status = "okay";
 };
 
+&vvcam_sensor7 {
+    sensor_name = "IMX334";
+    sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+    sensor_regulator_timing_us = <70 50 20>;
+    sensor_rst = <&gpio1_porta 16 0>;
+    sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
+    DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+    DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+    AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+	i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x1a>;
+    i2c_bus = /bits/ 8 <3>;
+    status = "okay";
+};
+
 &video0{
 	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
 	channel0 {
@@ -1279,13 +1541,20 @@
 			mode_idx = <0>;
 			path_type = "SENSOR_1600x1200_RAW10_LINER";
 		};
+		sensor2 {
+			subdev_name = "vivcam";
+			idx = <7>; //imx334
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_3840x2180_RAW12_LINER";
+		};
 		isp {
 			subdev_name = "isp";
 			idx = <1>;
 			path_type = "ISP_MI_PATH_MP";
 			output {
-				max_width = <1920>;
-				max_height = <1088>;
+				max_width = <3840>;
+				max_height = <2180>;
 				bit_per_pixel = <16>;
 				frame_count = <3>;
 			};
@@ -2138,6 +2407,44 @@
 	status = "okay";
 };
 
+&i2s0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa9>,
+                    <&pinctrl_audiopa10>,
+                    <&pinctrl_audiopa11>,
+                    <&pinctrl_audiopa12>,
+                    <&pinctrl_audio_i2s0>;
+};
+
+&i2s_8ch_sd0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa4>,
+                    <&pinctrl_audio_i2s_8ch_sd0>;
+};
+
+&i2s_8ch_sd1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa5>,
+                    <&pinctrl_audio_i2s_8ch_sd1>;
+};
+
+&i2s_8ch_sd2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa0>,
+                    <&pinctrl_audio_i2s_8ch_sd2>,
+                    <&pinctrl_audiopa2>,
+                    <&pinctrl_audiopa3>,
+                    <&pinctrl_audiopa8>,
+                    <&pinctrl_audio_i2s_8ch_bus>;
+};
+
+&i2s_8ch_sd3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa1>,
+                    <&pinctrl_audio_i2s_8ch_sd3>;
+};
+
+
 &cpus {
 	c910_0: cpu@0 {
 		operating-points = <

arch/riscv/boot/dts/thead/light-ant-discrete.dts

@@ -15,7 +15,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 
 	chosen {
@@ -194,9 +194,10 @@
 	};
 
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
-		compatible = "linux,bt-sco";
+		#sound-dai-cells = <0>;
+		compatible = "thead,light-dummy-pcm";
 		status = "okay";
+		sound-name-prefix = "DUMMY";
 	};
 
 	reg_vref_1v8: regulator-adc-verf {
@@ -581,24 +582,31 @@
         clock-frequency = <100000>;
         status = "okay";
 
-       es8156_audio_codec: es8156@8 {
-               #sound-dai-cells = <0>;
-               compatible = "everest,es8156";
-               reg = <0x08>;
-       };
+        es8156_audio_codec: es8156@8 {
+                #sound-dai-cells = <0>;
+                compatible = "everest,es8156";
+                reg = <0x08>;
+                sound-name-prefix = "ES8156";
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
+        };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                sound-name-prefix = "ES7210";
+                status = "disabled";
         };
 
-	audio_aw87519_pa@58 {
-		compatible = "awinic,aw87519_pa";
-		reg = <0x58>;
-		reset-gpio = <&ao_gpio4_porta 9 0x1>;
-		status = "okay";
-	};
+        audio_aw87519_pa: amp@58 {
+                compatible = "awinic,aw87519_pa";
+                reg = <0x58>;
+                reset-gpio = <&ao_gpio4_porta 9 0x1>;
+                sound-name-prefix = "AW87519";
+                status = "okay";
+        };
 };
 
 &i2c1 {
@@ -731,6 +739,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -773,7 +782,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -2091,6 +2100,11 @@
 
 &lightsound {
         status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -2105,7 +2119,7 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
                         sound-dai = <&es7210_audio_codec>;
@@ -2118,7 +2132,7 @@
                         sound-dai = <&light_i2s 1>;
                 };
                 codec {
-                        sound-dai = <&dummy_codec 2>;
+                        sound-dai = <&dummy_codec>;
                 };
         };
 };
@@ -2135,7 +2149,7 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-ant-ref.dts

@@ -15,7 +15,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 
 	chosen {
@@ -194,9 +194,10 @@
 	};
 
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
-		compatible = "linux,bt-sco";
+		#sound-dai-cells = <0>;
+		compatible = "thead,light-dummy-pcm";
 		status = "okay";
+		sound-name-prefix = "DUMMY";
 	};
 
 	reg_vref_1v8: regulator-adc-verf {
@@ -238,7 +239,8 @@
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		pinctrl-0 = <&pinctrl_volume>;
+		pinctrl-0 = <&pinctrl_volume_up
+				&pinctrl_volume_down>;
 		pinctrl-names = "default";
 		key-volumedown {
 			label = "Volume Down Key";
@@ -588,24 +590,31 @@
         clock-frequency = <100000>;
         status = "okay";
 
-       es8156_audio_codec: es8156@8 {
-               #sound-dai-cells = <0>;
-               compatible = "everest,es8156";
-               reg = <0x08>;
-       };
+        es8156_audio_codec: es8156@8 {
+                #sound-dai-cells = <0>;
+                compatible = "everest,es8156";
+                reg = <0x08>;
+                sound-name-prefix = "ES8156";
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
+        };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                sound-name-prefix = "ES7210";
+                status = "disabled";
         };
 
-	audio_aw87519_pa@58 {
-		compatible = "awinic,aw87519_pa";
-		reg = <0x58>;
-		reset-gpio = <&ao_gpio4_porta 9 0x1>;
-		status = "okay";
-	};
+        audio_aw87519_pa: amp@58 {
+                compatible = "awinic,aw87519_pa";
+                reg = <0x58>;
+                reset-gpio = <&ao_gpio4_porta 9 0x1>;
+                sound-name-prefix = "AW87519";
+                status = "okay";
+        };
 };
 
 &i2c1 {
@@ -738,6 +747,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -780,7 +790,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -797,6 +807,12 @@
 					FM_GPIO3_2	0x1	0x208	/* pwm0 */
 				>;
 			};
+
+			pinctrl_volume_up: volume_up_grp {
+				thead,pins = <
+					FM_GPIO2_25   0x0     0x238
+				>;
+			};
 		};
 };
 
@@ -842,9 +858,9 @@
 				>;
 			};
 
-			pinctrl_volume: volume_grp {
+			pinctrl_volume_down: volume_down_grp {
 				thead,pins = <
-					FM_CLK_OUT_2  0x3     0x208
+					FM_CLK_OUT_2  0x3     0x238
 				>;
 			};
 		};
@@ -2265,6 +2281,11 @@
 
 &lightsound {
         status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -2279,7 +2300,7 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
                         sound-dai = <&es7210_audio_codec>;
@@ -2292,7 +2313,7 @@
                         sound-dai = <&light_i2s 1>;
                 };
                 codec {
-                        sound-dai = <&dummy_codec 2>;
+                        sound-dai = <&dummy_codec>;
                 };
         };
 };
@@ -2309,7 +2330,7 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts

@@ -11,7 +11,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x40000000>;
+		reg = <0x0 0x200000 0x0 0x3fe00000>;
 	};
 };
 

arch/riscv/boot/dts/thead/light-b-product-sec.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "light-b-product.dts"
+#include "light-b-audio-hdmi.dts"
 
 
 

arch/riscv/boot/dts/thead/light-b-product.dts

@@ -15,7 +15,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 
 	chosen {
@@ -180,7 +180,8 @@
 		compatible = "thead,light-mbox-client";
 		mbox-names = "906";
 		mboxes = <&mbox_910t 2 0>;
-		status = "disabled";
+		audio-mbox-regmap = <&audio_mbox>;
+        status = "okay";
 	};
 
 	lightsound: lightsound@1 {
@@ -193,10 +194,25 @@
 		status = "disabled";
 	};
 
+	light_rpmsg: light_rpmsg {
+		compatible = "light,rpmsg-bus", "simple-bus";
+		memory-region = <&rpmsgmem>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		rpmsg: rpmsg{
+			vdev-nums = <1>;
+            reg = <0x0 0x1E000000 0 0x10000>;
+			compatible = "light,light-rpmsg";
+			status = "okay";
+		};
+	};
+
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
-		compatible = "linux,bt-sco";
+		#sound-dai-cells = <0>;
+		compatible = "thead,light-dummy-pcm";
 		status = "okay";
+		sound-name-prefix = "DUMMY";
 	};
 
 	reg_vref_1v8: regulator-adc-verf {
@@ -270,6 +286,8 @@
 			regulator-name = "soc_aud_3v3_en";
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_audio_3v3_en>;
 			gpio = <&ao_gpio_porta 7 1>;
 			enable-active-high;
 			regulator-always-on;
@@ -280,6 +298,8 @@
 			regulator-name = "soc_aud_1v8_en";
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_audio_1v8_en>;
 			gpio = <&ao_gpio_porta 8 1>;
 			enable-active-high;
 			regulator-always-on;
@@ -569,7 +589,14 @@
 		reg = <0x0 0x17000000 0 0x02000000>;
 		no-map;
 	};
-
+	audio_mem: memory@32000000 {
+		reg = <0x0 0x32000000 0x0 0x6400000>;
+		no-map;
+    };
+	rpmsgmem: memory@1E000000 {
+		reg = <0x0 0x1E000000 0x0 0x10000>;
+		no-map;
+	};
 
 };
 
@@ -600,23 +627,43 @@
 &audio_i2c0 {
         clock-frequency = <100000>;
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa6>,
+                    <&pinctrl_audiopa7>,
+                    <&pinctrl_audio_i2c0>;
 
-       es8156_audio_codec: es8156@8 {
-               #sound-dai-cells = <0>;
-               compatible = "everest,es8156";
-               reg = <0x08>;
-       };
+        es8156_audio_codec: es8156@8 {
+                #sound-dai-cells = <0>;
+                compatible = "everest,es8156";
+                reg = <0x08>;
+                sound-name-prefix = "ES8156";
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
+                mclk-sclk-ratio = <4>;
+        };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                work-mode = "ES7210_NORMAL_I2S";
+                channels-max = <2>;
+				mclk-sclk-ratio = <4>;
+                sound-name-prefix = "ES7210_ADC0";
+                MVDD-supply = <&soc_aud_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
         };
 
-	audio_aw87519_pa@58 {
+	audio_aw87519_pa: amp@58 {
 		compatible = "awinic,aw87519_pa";
 		reg = <0x58>;
+		pingctrl-names = "default";
+		pinctrl-0 = <&pinctrl_audio_pa_rst0>;
 		reset-gpio = <&ao_gpio4_porta 9 0x1>;
+		sound-name-prefix = "AW87519";
 		status = "okay";
 	};
 };
@@ -750,6 +797,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -792,7 +840,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -866,27 +914,103 @@
 			 * Format: <pin_id mux_node config>
 			 */
 
-			pinctrl_audiopa1: audiopa1_grp {
-				thead,pins = <
-					FM_AUDIO_PA1	0x3	0x72
-				>;
+			pinctrl_audiopa0: audiopa0 {
+				thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >;
 			};
-
-			pinctrl_audiopa2: audiopa2_grp {
-				thead,pins = <
-					FM_AUDIO_PA2	0x0	0x72
-				>;
+			pinctrl_audiopa1: audiopa1 {
+				thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa2: audiopa2 {
+				thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa3: audiopa3 {
+				thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa6: audiopa6 {
+				thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa7: audiopa7 {
+				thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa8: audiopa8 {
+				thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audio_pa_rst0: audio_pa_rst0 {
+				thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_3 0x000 >;
+			};
+			pinctrl_audiopa13: audiopa13 {
+				thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa14: audiopa14 {
+				thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa15: audiopa15 {
+				thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa17: audiopa17 {
+				thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audio_3v3_en: audio_3v3_en {
+				thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_3 0x008 >;
+			};
+			pinctrl_audio_1v8_en: audio_1v8_en {
+				thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_3 0x008 >;
 			};
 
 			pinctrl_volume: volume_grp {
 				thead,pins = <
-					FM_AOGPIO_11  0x0     0x208
-					FM_AOGPIO_10  0x3     0x208
+					FM_AOGPIO_11  0x0     0x238
+					FM_AOGPIO_10  0x3     0x238
 				>;
 			};
 	};
 };
 
+&padctrl_audiosys {
+
+	status = "okay";
+
+	light-audio-padctrl {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+
+			pinctrl_audio_i2c0: audio_i2c0_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA6		LIGHT_PIN_FUNC_0 0x004
+					FM_AUDIO_IO_PA7		LIGHT_PIN_FUNC_0 0x004
+				>;
+			};
+			pinctrl_audio_i2s1: audio_i2s1_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA13   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA14   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA15   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA17   LIGHT_PIN_FUNC_0 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA2	  LIGHT_PIN_FUNC_3 0x008
+					FM_AUDIO_IO_PA3   LIGHT_PIN_FUNC_3 0x008
+					FM_AUDIO_IO_PA8   LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA0	  LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA1   LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+	};
+};
+
+
 &i2c0 {
 	clock-frequency = <400000>;
 	status = "okay";
@@ -1000,30 +1124,21 @@
 	status = "okay";
 };
 
-/*
-&vvcam_sensor0 {
-	sensor_name = "IMX334";
-	sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
-	sensor_regulator_timing_us = <70 50 20>;
-	sensor_rst = <&gpio1_porta 16 0>;
-	sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
-	DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
-	DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
-	AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+&vvcam_sensor1 {
+       sensor_name = "OV5693";
+       sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+       sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
+       sensor_regulator_timing_us = <70 50 20>;
+       sensor_rst = <&gpio1_porta 16 0>;
+       sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
+       DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+       DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+       AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
     i2c_reg_width = /bits/ 8 <2>;
     i2c_data_width = /bits/ 8 <1>;
-    i2c_addr = /bits/ 8 <0x1a>;
-	i2c_bus = /bits/ 8 <3>;
-	status = "okay";
-};
-*/
-
-&vvcam_sensor1 {
-	sensor_name = "OV5693";
-	i2c_bus = /bits/ 8 <3>;
-	i2c_reg_width = /bits/ 8 <1>;
-	i2c_data_width = /bits/ 8 <1>;
-	status = "disabled";
+    i2c_addr = /bits/ 8 <0x36>;
+       i2c_bus = /bits/ 8 <3>;
+       status = "okay";
 };
 
 &vvcam_sensor2 {
@@ -1108,6 +1223,22 @@
 	status = "okay";
 };
 
+&vvcam_sensor7 {
+    sensor_name = "IMX334";
+    sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+    sensor_regulator_timing_us = <70 50 20>;
+    sensor_rst = <&gpio1_porta 16 0>;
+    sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
+    DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+    DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+    AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+	i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x1a>;
+    i2c_bus = /bits/ 8 <3>;
+    status = "okay";
+};
+
 &video0{
 	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
 	channel0 {
@@ -1314,13 +1445,20 @@
 			mode_idx = <0>;
 			path_type = "SENSOR_1600x1200_RAW10_LINER";
 		};
+		sensor2 {
+			subdev_name = "vivcam";
+			idx = <7>; //imx334
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_3840x2180_RAW12_LINER";
+		};
 		isp {
 			subdev_name = "isp";
 			idx = <1>;
 			path_type = "ISP_MI_PATH_MP";
 			output {
-				max_width = <1920>;
-				max_height = <1088>;
+				max_width = <3840>;
+				max_height = <2180>;
 				bit_per_pixel = <16>;
 				frame_count = <3>;
 			};
@@ -2313,6 +2451,11 @@
 
 &lightsound {
         status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -2327,7 +2470,7 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
                         sound-dai = <&es7210_audio_codec>;
@@ -2340,7 +2483,7 @@
                         sound-dai = <&light_i2s 1>;
                 };
                 codec {
-                        sound-dai = <&dummy_codec 2>;
+                        sound-dai = <&dummy_codec>;
                 };
         };
 };
@@ -2355,10 +2498,29 @@
 
 &i2s1 {
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa13>,
+                    <&pinctrl_audiopa14>,
+                    <&pinctrl_audiopa15>,
+                    <&pinctrl_audiopa17>,
+                    <&pinctrl_audio_i2s1>;
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa0>,
+                    <&pinctrl_audio_i2s_8ch_sd2>,
+                    <&pinctrl_audiopa2>,
+                    <&pinctrl_audiopa3>,
+                    <&pinctrl_audiopa8>,
+                    <&pinctrl_audio_i2s_8ch_bus>;
+};
+
+&i2s_8ch_sd3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa1>,
+                    <&pinctrl_audio_i2s_8ch_sd3>;
 };
 
 &cpus {

arch/riscv/boot/dts/thead/light-beagle-ref.dts

@@ -15,7 +15,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 
 	chosen {
@@ -194,9 +194,10 @@
 	};
 
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
-		compatible = "linux,bt-sco";
+		#sound-dai-cells = <0>;
+		compatible = "thead,light-dummy-pcm";
 		status = "okay";
+		sound-name-prefix = "DUMMY";
 	};
 
 	reg_vref_1v8: regulator-adc-verf {
@@ -569,24 +570,34 @@
         clock-frequency = <100000>;
         status = "okay";
 
-       es8156_audio_codec: es8156@8 {
-               #sound-dai-cells = <0>;
-               compatible = "everest,es8156";
-               reg = <0x08>;
-       };
+        es8156_audio_codec: es8156@8 {
+                #sound-dai-cells = <0>;
+                compatible = "everest,es8156";
+                reg = <0x08>;
+                sound-name-prefix = "ES8156";
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
+        };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                sound-name-prefix = "ES7210";
+                MVDD-supply = <&soc_aud_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
         };
 
-	audio_aw87519_pa@58 {
-		compatible = "awinic,aw87519_pa";
-		reg = <0x58>;
-		reset-gpio = <&ao_gpio4_porta 9 0x1>;
-		status = "okay";
-	};
+        audio_aw87519_pa: amp@58 {
+                compatible = "awinic,aw87519_pa";
+                reg = <0x58>;
+                reset-gpio = <&ao_gpio4_porta 9 0x1>;
+                sound-name-prefix = "AW87519";
+                status = "okay";
+        };
 };
 
 &i2c1 {
@@ -719,6 +730,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -761,7 +773,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -2249,6 +2261,11 @@
 
 &lightsound {
         status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -2263,7 +2280,7 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
                         sound-dai = <&es7210_audio_codec>;
@@ -2276,7 +2293,7 @@
                         sound-dai = <&light_i2s 1>;
                 };
                 codec {
-                        sound-dai = <&dummy_codec 2>;
+                        sound-dai = <&dummy_codec>;
                 };
         };
 };
@@ -2293,7 +2310,7 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-crash.dts

@@ -191,8 +191,9 @@
 	};
 
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
-		compatible = "linux,bt-sco";
+		#sound-dai-cells = <0>;
+		compatible = "thead,light-dummy-pcm";
+		sound-name-prefix = "DUMMY";
 		status = "okay";
 	};
 
@@ -341,18 +342,23 @@
                #sound-dai-cells = <0>;
                compatible = "everest,es8156";
                reg = <0x08>;
+               sound-name-prefix = "ES8156";
+               status = "disabled";
        };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                sound-name-prefix = "ES7210";
+                status = "disabled";
         };
 
-	audio_aw87519_pa@58 {
+	audio_aw87519_pa: amp@58 {
 		compatible = "awinic,aw87519_pa";
 		reg = <0x58>;
 		reset-gpio = <&ao_gpio4_porta 9 0x1>;
+		sound-name-prefix = "AW87519";
 		status = "okay";
 	};
 };
@@ -488,6 +494,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -530,7 +537,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -862,22 +869,6 @@
         status = "disabled";
 };
 
-&light_i2s {
-        status = "okay";
-};
-
-&i2s0 {
-        status = "okay";
-};
-
-&i2s1 {
-        status = "okay";
-};
-
-&i2s3 {
-        status = "okay";
-};
-
 &khvhost {
 	status = "disabled";
 };

arch/riscv/boot/dts/thead/light-emu.dtsi

@@ -309,7 +309,7 @@
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
 			control-val = <0x1c>;
-			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
 		};
 
 		clint0: clint@ffdc000000 {

arch/riscv/boot/dts/thead/light-evb.dtsi

@@ -318,7 +318,7 @@
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
 			control-val = <0x1c>;
-			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
 		};
 
 		clint0: clint@ffdc000000 {
@@ -1193,8 +1193,7 @@
 
 		emmc: sdhci@ffe7080000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7080000 0x0 0x10000
-			       0xff 0xef014060 0x0 0x4>;
+			reg = <0xff 0xe7080000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <62>;
 			interrupt-names = "sdhciirq";
@@ -1204,8 +1203,7 @@
 
 		sdhci0: sd@ffe7090000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7090000 0x0 0x10000
-			       0xff 0xef014064 0x0 0x4>;
+			reg = <0xff 0xe7090000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <64>;
 			interrupt-names = "sdhci0irq";
@@ -1215,8 +1213,7 @@
 
 		sdhci1: sd@ffe70a0000 {
 		        compatible = "snps,dwcmshc-sdhci";
-		        reg = <0xff 0xe70a0000 0x0 0x10000
-		               0xff 0xef014064 0x0 0x4>;
+		        reg = <0xff 0xe70a0000 0x0 0x10000>;
 		        interrupt-parent = <&intc>;
 		        interrupts = <71>;
 		        interrupt-names = "sdhci1irq";
@@ -1302,7 +1299,7 @@
 			compatible = "light,light-i2s";
 			reg = <0xff 0xe7034000 0x0 0x4000>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_audio_i2s0>;
+			pinctrl-0 = <&pinctrl_light_i2s0>;
 			light,mode = "i2s-master";
 			interrupt-parent = <&intc>;
 			interrupts = <70>;

arch/riscv/boot/dts/thead/light-fm-emu.dts

@@ -185,7 +185,7 @@
 				sound-dai = <&light_i2s 0>;
 			};
 			codec {
-				sound-dai = <&dummy_codec 2>;
+				sound-dai = <&dummy_codec>;
 			};
 		};
 
@@ -196,7 +196,7 @@
 				sound-dai = <&light_i2s 1>;
 			};
 			codec {
-				sound-dai = <&dummy_codec 2>;
+				sound-dai = <&dummy_codec>;
 			};
 		};
 	};

arch/riscv/boot/dts/thead/light-lpi4a-16gb.dts

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 Alibaba Group Holding Limited.
+ */
+
+#include "light-lpi4a-ref.dts"
+
+/ {
+	model = "T-HEAD Light Lichee Pi 4A configuration for 16GB DDR board";
+	compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x200000 0x3 0xffe00000>;
+	};
+};
+
+&cmamem {
+	alloc-ranges = <0x3 0xe4000000 0 0x14000000>; // [0x3E400_0000 ~ 0x3F800_0000]
+};

arch/riscv/boot/dts/thead/light-lpi4a-cluster-16gb.dts

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Sipeed.
+ */
+
+#include "light-lpi4a-16gb.dts"
+
+/ {
+	model = "T-HEAD Light Lichee Pi 4A configuration for 16GB DDR board on Cluster";
+};
+
+&audio_i2c0 {
+	status = "disabled";
+};
+
+&audio_i2c1 {
+	status = "disabled";
+};
+
+&lightsound {
+	status = "disabled";
+};
+
+&reg_usb_hub_vdd1v2 {
+	/delete-property/ gpio;
+};

arch/riscv/boot/dts/thead/light-lpi4a-cluster.dts

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Sipeed.
+ */
+
+#include "light-lpi4a.dts"
+
+/ {
+	model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board on Cluster";
+};
+
+&audio_i2c0 {
+	status = "disabled";
+};
+
+&audio_i2c1 {
+	status = "disabled";
+};
+
+&lightsound {
+	status = "disabled";
+};
+
+&reg_usb_hub_vdd1v2 {
+	/delete-property/ gpio;
+};

arch/riscv/boot/dts/thead/light-lpi4a-ddr2G.dts

@@ -11,7 +11,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 };
 

arch/riscv/boot/dts/thead/light-lpi4a-laptop.dts

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Sipeed.
+ */
+
+#include "light-lpi4a.dts"
+
+/ {
+	model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board use on laptop";
+
+	power-keys {
+                compatible = "gpio-keys";
+		key-lid {
+			label = "lid status";
+			linux,code = <KEY_DISPLAY_OFF>;
+			debounce-interval = <1>;
+			gpios = <&gpio1_porta 5 0x1>;
+		};
+	};
+};

arch/riscv/boot/dts/thead/light-lpi4a-ref.dts

@@ -172,7 +172,8 @@
 		compatible = "thead,light-mbox-client";
 		mbox-names = "906";
 		mboxes = <&mbox_910t 2 0>;
-		status = "disabled";
+		audio-mbox-regmap = <&audio_mbox>;
+		status = "okay";
 	};
 
 	lightsound: lightsound@1 {
@@ -185,10 +186,32 @@
 		status = "disabled";
 	};
 
+	light_rpmsg: light_rpmsg {
+		compatible = "light,rpmsg-bus", "simple-bus";
+		memory-region = <&rpmsgmem>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		rpmsg: rpmsg{
+			vdev-nums = <1>;
+            reg = <0x0 0x1E000000 0 0x10000>;
+			compatible = "light,light-rpmsg";
+			status = "okay";
+		};
+	};
+
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
-		compatible = "linux,bt-sco";
+		#sound-dai-cells = <0>;
+		compatible = "thead,light-dummy-pcm";
 		status = "okay";
+		sound-name-prefix = "DUMMY";
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		pwms = <&pwm 1 10000000 0>;
+		cooling-levels = <0 64 192 255>;
 	};
 
 	reg_vref_1v8: regulator-adc-verf {
@@ -196,7 +219,7 @@
 			regulator-name = "vref-1v8";
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
-	status = "okay";
+			status = "okay";
 	};
 
         reg_tp_pwr_en: regulator-pwr-en {
@@ -281,7 +304,6 @@
 			regulator-name = "soc_aud_3v3_en";
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
-			gpio = <&pcal6408ahk_a 1 1>;
 			enable-active-high;
 			regulator-always-on;
 		};
@@ -291,7 +313,6 @@
 			regulator-name = "soc_aud_1v8_en";
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
-			gpio = <&pcal6408ahk_a 0 1>;
 			enable-active-high;
 			regulator-always-on;
 		};
@@ -361,6 +382,7 @@
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			gpio = <&pcal6408ahk_b 1 1>;
+			regulator-always-on;
 			enable-active-high;
 		};
 
@@ -370,6 +392,7 @@
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			gpio = <&pcal6408ahk_b 2 1>;
+			regulator-always-on;
 			enable-active-high;
 		};
 
@@ -379,6 +402,7 @@
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			gpio = <&pcal6408ahk_b 0 1>;
+			regulator-always-on;
 			enable-active-high;
 		};
 
@@ -558,6 +582,48 @@
 		};
 	};
 
+	thermal-zones {
+		cpu-thermal-zone {
+			trips {
+				fan_config0: fan-trip0 {
+					temperature = <40000>;
+					hysteresis = <5000>;
+					type = "active";
+				};
+
+				fan_config1: fan-trip1 {
+					temperature = <50000>;
+					hysteresis = <5000>;
+					type = "active";
+				};
+
+				fan_config2: fan-trip2 {
+					temperature = <60000>;
+					hysteresis = <5000>;
+					type = "active";
+				};
+			};
+
+			cooling-maps {
+				fan-on {
+					trip = <&fan_config0>;
+					cooling-device =
+						<&fan 1 1>;
+				};
+				fan-faster {
+					trip = <&fan_config1>;
+					cooling-device =
+						<&fan 2 2>;
+				};
+				fan-full {
+					trip = <&fan_config2>;
+					cooling-device =
+						<&fan 3 3>;
+				};
+			};
+		};
+	};
+
 };
 
 &resmem {
@@ -594,6 +660,14 @@
 		reg = <0x0 0x17000000 0 0x02000000>;
 		no-map;
 	};
+    audio_mem: memory@32000000 {
+		reg = <0x0 0x32000000 0x0 0x6400000>;
+		no-map;
+    };
+	rpmsgmem: memory@1E000000 {
+		reg = <0x0 0x1E000000 0x0 0x10000>;
+		no-map;
+	};
 
 };
 
@@ -606,44 +680,53 @@
 &audio_i2c0 {
 	clock-frequency = <100000>;
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audiopa29>,
+				<&pinctrl_audiopa30>,
+				<&pinctrl_audio_i2c0>;
 
 	es8156_audio_codec: es8156@8 {
 		#sound-dai-cells = <0>;
 		compatible = "everest,es8156";
 		reg = <0x08>;
+		sound-name-prefix = "ES8156";
+		AVDD-supply = <&soc_aud_3v3_en_reg>;
+		DVDD-supply = <&soc_aud_1v8_en_reg>;
+		PVDD-supply = <&soc_aud_1v8_en_reg>;
 	};
 
 	es7210_audio_codec: es7210@40 {
 		#sound-dai-cells = <0>;
 		compatible = "MicArray_0";
 		reg = <0x40>;
+		sound-name-prefix = "ES7210";
+		MVDD-supply = <&soc_aud_3v3_en_reg>;
+		AVDD-supply = <&soc_aud_3v3_en_reg>;
+		DVDD-supply = <&soc_aud_1v8_en_reg>;
+		PVDD-supply = <&soc_aud_1v8_en_reg>;
 	};
 
-	audio_aw87519_pa@58 {
+	audio_aw87519_pa: amp@58 {
 		compatible = "awinic,aw87519_pa";
 		reg = <0x58>;
-		reset-gpio = <&pcal6408ahk_a 2 0x1>;
-		status = "okay";
+		sound-name-prefix = "AW87519";
+		status = "disabled";
 	};
 
 	audio_aw87519_pa1@5b {
 		compatible = "awinic,aw87519_pa";
 		reg = <0x5b>;
-		reset-gpio = <&pcal6408ahk_a 3 0x1>;
 		status = "disabled";
 	};
 
-	pcal6408ahk_a: gpio@20 {
-		compatible = "nxp,pcal9554b";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
 };
 
 &audio_i2c1 {
 	clock-frequency = <100000>;
 	status = "okay";
+	pinctrl-0 = <&pinctrl_audiopa6>,
+				<&pinctrl_audiopa7>,
+				<&pinctrl_audio_i2c1>;
 
 	es8156_audio_codec_1: es8156@8 {
 		#sound-dai-cells = <0>;
@@ -662,14 +745,12 @@
 	audio_aw87519_pa2@58 {
 		compatible = "awinic,aw87519_pa";
 		reg = <0x58>;
-		reset-gpio = <&pcal6408ahk_a 4 0x1>;
 		status = "disabled";
 	};
 
 	audio_aw87519_pa3@5b {
 		compatible = "awinic,aw87519_pa";
 		reg = <0x5b>;
-		reset-gpio = <&pcal6408ahk_a 5 0x1>;
 		status = "disabled";
 	};
 };
@@ -706,7 +787,7 @@
 	num-cs = <1>;
 	cs-gpios = <&gpio2_porta 3 0>;
 	rx-sample-dly = <4>;
-	status = "okay";
+	status = "disabled";
 
 	spi-flash@0 {
 		#address-cells = <1>;
@@ -841,7 +922,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -929,17 +1010,94 @@
 					FM_AUDIO_PA2	0x0	0x72
 				>;
 			};
+			pinctrl_audiopa6: audiopa6 {
+				thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa7: audiopa7 {
+				thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa14: audiopa14 {
+				thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa15: audiopa15 {
+				thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa16: audiopa16 {
+				thead,pins = < FM_AUDIO_PA16 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa17: audiopa17 {
+				thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa18: audiopa18 {
+				thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_1 0x000 >;
+			};
+			pinctrl_audiopa19: audiopa19 {
+				thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_1 0x000 >;
+			};
+			pinctrl_audiopa21: audiopa21 {
+				thead,pins = < FM_AOGPIO_10 LIGHT_PIN_FUNC_1 0x000 >;
+			};
+			pinctrl_audiopa22: audiopa22 {
+				thead,pins = < FM_AOGPIO_11 LIGHT_PIN_FUNC_1 0x000 >;
+			};
+			pinctrl_audiopa29: audiopa29 {
+				thead,pins = < FM_AUDIO_PA29 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa30: audiopa30 {
+				thead,pins = < FM_AUDIO_PA30 LIGHT_PIN_FUNC_0 0x000 >;
+			};
 
 	};
 };
 
+&padctrl_audiosys {
+
+	status = "okay";
+
+	light-audio-padctrl {
+		/*
+		 * Pin Configuration Node:
+		 * Format: <pin_id mux_node config>
+		 */
+
+		pinctrl_audio_i2c0: audio_i2c0_grp {
+			thead,pins = <
+				FM_AUDIO_IO_PA29     LIGHT_PIN_FUNC_2 0x004
+				FM_AUDIO_IO_PA30     LIGHT_PIN_FUNC_2 0x004
+			>;
+		};
+		pinctrl_audio_i2c1: audio_i2c1_grp {
+			thead,pins = <
+				FM_AUDIO_IO_PA6     LIGHT_PIN_FUNC_2 0x004
+				FM_AUDIO_IO_PA7     LIGHT_PIN_FUNC_2 0x004
+			>;
+		};
+		pinctrl_audio_i2s1: audio_i2s1_grp {
+			thead,pins = <
+				FM_AUDIO_IO_PA14   LIGHT_PIN_FUNC_0 0x008
+				FM_AUDIO_IO_PA15   LIGHT_PIN_FUNC_0 0x008
+				FM_AUDIO_IO_PA16   LIGHT_PIN_FUNC_0 0x008
+				FM_AUDIO_IO_PA17   LIGHT_PIN_FUNC_0 0x008
+			>;
+		};
+		pinctrl_audio_i2s2: audio_i2s2_grp {
+			thead,pins = <
+				FM_AUDIO_IO_PA18   LIGHT_PIN_FUNC_0 0x008
+				FM_AUDIO_IO_PA19   LIGHT_PIN_FUNC_0 0x008
+				FM_AUDIO_IO_PA21   LIGHT_PIN_FUNC_0 0x008
+				FM_AUDIO_IO_PA22   LIGHT_PIN_FUNC_0 0x008
+			>;
+		};
+	};
+};
+
 &i2c0 {
     clock-frequency = <400000>;
 	status = "okay";
 
 	pcal6408ahk_b: gpio@20 {
-		compatible = "nxp,pcal9554b";
-		reg = <0x20>;
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
 		gpio-controller;
 		#gpio-cells = <2>;
 	};
@@ -950,8 +1108,8 @@
 	status = "okay";
 
 	pcal6408ahk_c: gpio@20 {
-		compatible = "nxp,pcal9554b";
-		reg = <0x20>;
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
 		gpio-controller;
 		#gpio-cells = <2>;
 	};
@@ -967,8 +1125,8 @@
 	status = "okay";
 
 	pcal6408ahk_d: gpio@20 {
-		compatible = "nxp,pcal9554b";
-		reg = <0x20>;
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
 		gpio-controller;
 		#gpio-cells = <2>;
 	};
@@ -1093,6 +1251,24 @@
     status = "okay";
 };
 
+&vvcam_sensor3 {//cam3 csi0 modified
+	sensor_name = "OV5693";
+	sensor_regulators = "soc_dovdd18_rgb", "soc_dvdd12_rgb", "soc_avdd28_rgb";
+	sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
+	sensor_regulator_timing_us = <70 50 20>;
+	sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin 
+	sensor_rst 	= <&pcal6408ahk_c 1 0>;
+	sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
+	DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+	DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+	AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+	i2c_reg_width = /bits/ 8 <2>;
+	i2c_data_width = /bits/ 8 <1>;
+	i2c_addr = /bits/ 8 <0x36>;
+	i2c_bus = /bits/ 8 <0>;
+	status = "okay";
+};
+
 &video2 {
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
 	status = "okay";
@@ -1101,11 +1277,18 @@
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
-			idx = <0>; 
+			idx = <0>;
 			csi_idx = <0>;
 			mode_idx = <0>;
 			path_type = "SENSOR_VGA_RAW12_LINER";
 		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>;
+			csi_idx = <0>;
+			mode_idx = <1>;
+			path_type = "SENSOR_2592x1944_LINER";
+		};
 		dma {
 			subdev_name = "vipre";
 			idx = <0>;
@@ -1116,8 +1299,8 @@
 			idx = <1>;
 			path_type = "ISP_MI_PATH_MP";
             output {
-				max_width = <1920>;
-				max_height = <1088>;
+				max_width = <2600>;
+				max_height = <2000>;
 				bit_per_pixel = <12>;
 				frame_count = <3>;
 			};
@@ -1138,6 +1321,13 @@
 			path_type = "SENSOR_VGA_RAW12_LINER";
 
 		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>;
+			csi_idx = <0>;
+			mode_idx = <1>;
+			path_type = "SENSOR_2592x1944_LINER";
+		};
         dma {
             subdev_name = "vipre";
 			idx = <0>;
@@ -1275,15 +1465,22 @@
         status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
-			idx = <2>;
-			csi_idx = <1>; //csi_b
+			idx = <0>;
+			csi_idx = <0>;
 			mode_idx = <0>;
-			path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+			path_type = "SENSOR_VGA_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>;
+			csi_idx = <0>;
+			mode_idx = <1>;
+			path_type = "SENSOR_2592x1944_LINER";
 		};
 		dma {
 			subdev_name = "vipre";
 			idx = <0>;
-            path_type = "VIPRE_CSI1_DDR";
+			path_type = "VIPRE_CSI0_DDR";
 		};
     };
 };
@@ -1327,21 +1524,6 @@
 	status = "okay";
 };
 
-&dpu_enc0 {
-	status = "okay";
-
-	ports {
-		/* output */
-		port@1 {
-			reg = <1>;
-
-			enc0_out: endpoint {
-				remote-endpoint = <&dsi0_in>;
-			};
-		};
-	};
-};
-
 &dpu_enc1 {
         ports {
                 /delete-node/ port@0;
@@ -1352,48 +1534,6 @@
         status = "okay";
 };
 
-&dsi0 {
-        status = "okay";
-};
-
-&dhost_0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-
-			dsi0_in: endpoint {
-				remote-endpoint = <&enc0_out>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			dsi0_out: endpoint {
-				remote-endpoint = <&panel0_in>;
-			};
-		};
-	};
-
-	panel0@0 {
-		compatible = "himax,hx8394";
-		reg = <0>;
-		backlight = <&lcd0_backlight>;
-		reset-gpio = <&pcal6408ahk_d 7 1>; /* active low */
-		hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
-		vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
-
-		port {
-			panel0_in: endpoint {
-				remote-endpoint = <&dsi0_out>;
-			};
-		};
-	};
-};
-
 &disp1_out {
 	remote-endpoint = <&hdmi_tx_in>;
 };
@@ -1425,12 +1565,22 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s1 1>;
+                        sound-dai = <&i2s1 0>;
                 };
                 codec {
                         sound-dai = <&es7210_audio_codec>;
                 };
         };
+        simple-audio-card,dai-link@2 {          /* I2S - HDMI*/
+                reg = <2>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&light_i2s 1>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
 };
 
 &light_i2s {
@@ -1444,14 +1594,29 @@
 &i2s1 {
         status = "okay";
         dmas = <&dmac2 11>, <&dmac2 10>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa14>,
+                    <&pinctrl_audiopa15>,
+                    <&pinctrl_audiopa16>,
+                    <&pinctrl_audiopa17>,
+                    <&pinctrl_audio_i2s1>;
 };
 
 &i2s2 {
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa18>,
+                    <&pinctrl_audiopa19>,
+                    <&pinctrl_audiopa21>,
+                    <&pinctrl_audiopa22>,
+                    <&pinctrl_audio_i2s2>;
 };
 
-&i2s3 {
-        status = "okay";
+&usb_1 {
+	hubswitch-gpio = <&ao_gpio_porta 4 0>;
+	vbus-supply = <&soc_vbus_en_reg>;
+	hub1v2-supply = <&reg_usb_hub_vdd1v2>;
+	hub5v-supply = <&reg_usb_hub_vcc5v>;
 };
 
 &cpus {
@@ -1461,12 +1626,14 @@
 			300000	650000
 			800000	700000
 			1500000	800000
+			1848000 1000000
 		>;
 		light,dvddm-operating-points = <
 			/* kHz   uV */
 			300000	800000
 			800000	800000
 			1500000	800000
+			1848000 1000000
 		>;
 	};
 	c910_1: cpu@1 {
@@ -1475,12 +1642,14 @@
 			300000	650000
 			800000	700000
 			1500000	800000
+			1848000 1000000
 		>;
 		light,dvddm-operating-points = <
 			/* kHz   uV */
 			300000	800000
 			800000	800000
 			1500000	800000
+			1848000 1000000
 		>;
 	};
 	c910_2: cpu@2 {
@@ -1490,12 +1659,14 @@
 			300000	650000
 			800000	700000
 			1500000	800000
+			1848000 1000000
 		>;
 		light,dvddm-operating-points = <
 			/* kHz   uV */
 			300000	800000
 			800000	800000
 			1500000	800000
+			1848000 1000000
 		>;
 	};
 	c910_3: cpu@3 {
@@ -1505,12 +1676,14 @@
 			300000	650000
 			800000	700000
 			1500000	800000
+			1848000 1000000
 		>;
 		light,dvddm-operating-points = <
 			/* kHz   uV */
 			300000	800000
 			800000	800000
 			1500000	800000
+			1848000 1000000
 		>;
 	};
 };

arch/riscv/boot/dts/thead/light-lpi4a-sec.dts

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "light-lpi4a.dts"
+
+
+&light_iopmp {
+        status = "disabled";
+};
+
+&qspi1 {
+        status = "disabled";
+};
+

arch/riscv/boot/dts/thead/light-lpi4a.dts

@@ -6,22 +6,15 @@
 #include "light-lpi4a-ref.dts"
 
 / {
-	model = "T-HEAD Light Lichee Pi 4A configuration for 4GB DDR board";
+	model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
 	compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x1 0x00000000>;
+		reg = <0x0 0x200000 0x1 0xffe00000>;
 	};
 };
 
 &cmamem {
-	alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000]
-};
-
-&usb_1 {
-	hubswitch-gpio = <&ao_gpio_porta 4 0>;
-	vbus-supply = <&soc_vbus_en_reg>;
-	hub1v2-supply = <&reg_usb_hub_vdd1v2>;
-	hub5v-supply = <&reg_usb_hub_vcc5v>;
+	alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0x0E400_0000 ~ 0x0F800_0000]
 };

arch/riscv/boot/dts/thead/light-vi-devices.dtsi

@@ -199,6 +199,12 @@
 			csi_idx = <0xff>;
 			path_type = "SENSOR_VGA_RAW10_LINER";
 		};
+		sensor2 {
+			subdev_name = "vivcam";
+			idx = <0xff>; // invalid
+			csi_idx = <0xff>;
+			path_type = "SENSOR_VGA_RAW10_LINER";
+		};
 		dma {
 			subdev_name = "vipre";
 			idx = <0>;

arch/riscv/boot/dts/thead/light.dtsi

@@ -6,11 +6,14 @@
 #include <dt-bindings/pinctrl/light-fm-left-pinctrl.h>
 #include <dt-bindings/pinctrl/light-fm-right-pinctrl.h>
 #include <dt-bindings/pinctrl/light-fm-aon-pinctrl.h>
+#include <dt-bindings/pinctrl/light-fm-audio-pinctrl.h>
+#include <dt-bindings/pinctrl/light-fm-pinctrl-def.h>
 #include <dt-bindings/clock/light-fm-ap-clock.h>
 #include <dt-bindings/clock/light-vpsys.h>
 #include <dt-bindings/clock/light-vosys.h>
 #include <dt-bindings/clock/light-visys.h>
 #include <dt-bindings/clock/light-dspsys.h>
+#include <dt-bindings/clock/light-audiosys.h>
 #include <dt-bindings/firmware/thead/rsrc.h>
 #include <dt-bindings/soc/thead,light-iopmp.h>
 #include <dt-bindings/thermal/thermal.h>
@@ -34,7 +37,7 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		audio_i2c0 = &audio_i2c0;
-		audio_i2c1 = &audio_i2c1;
+        audio_i2c1 = &audio_i2c1;
 		mmc0 = &emmc;
 		mmc1 = &sdhci0;
 		serial0 = &uart0;
@@ -55,6 +58,7 @@
 		vivcam4 = &vvcam_sensor4;
 		vivcam5 = &vvcam_sensor5;
         vivcam6 = &vvcam_sensor6;
+        vivcam7 = &vvcam_sensor7;
 
         viv_video0 =  &video0;
         viv_video1 =  &video1;
@@ -94,6 +98,11 @@
 		};
 	};
 
+    aon_iram: aon-iram@ffffef8000 {
+            compatible = "syscon";
+            reg = <0xff 0xffef8000 0x0 0x10000>;
+    };
+
 	thermal-zones {
 		cpu-thermal-zone {
 			polling-delay-passive = <250>;
@@ -383,7 +392,7 @@
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
 			control-val = <0x1c>;
-			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
 		};
 
 		clint0: clint@ffdc000000 {
@@ -634,6 +643,12 @@
 			status = "okay";
 		};
 
+		audio_mbox: audio_mbox@0xffefc48000 {
+			compatible = "thead,light-audio-mbox-reg", "syscon";
+			reg = <0xff 0xefc48000 0x0 0x1000>;
+			status = "okay";
+		};
+
 		nvmem_controller: efuse@ffff210000 {
 			compatible = "thead,light-fm-efuse", "syscon";
 			reg = <0xff 0xff210000 0x0 0x10000>;
@@ -855,6 +870,12 @@
 			status = "okay";
 		};
 
+		padctrl_audiosys: padctrl-audiosys@ffcb01d000 {
+			compatible = "thead,light-fm-audio-pinctrl";
+			reg = <0xff 0xcb01d000 0x0 0x1000>;
+			status = "disabled";
+		};
+
 		timer4: timer@ffffc33000 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0xff 0xffc33000 0x0 0x14>;
@@ -1248,6 +1269,13 @@
 			status = "okay";
 		};
 
+		vpsys_rst: vpsys-reset-controller@ffecc30000 {
+			compatible = "thead,light-vpsys-reset-src","syscon";
+			reg = <0xff 0xecc30000 0x0 0x1000>;
+			#reset-cells = <1>;
+			status = "okay";
+		};
+
 		sys_reg: sys_reg@ffef010100 {
 			compatible = "thead,light_sys_reg";
 			reg = <0xff 0xef010100 0x0 0x100>;
@@ -1301,7 +1329,7 @@
                                           65536 65536 65536 65536
                                           65536 65536 65536 65536
                                           65536 65536 65536 65536>;
-                        snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+                        snps,priority = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; // <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
                         snps,dma-masters = <1>;
                         snps,data-width = <4>;
                         snps,axi-max-burst-len = <16>;
@@ -1354,8 +1382,7 @@
 
 		emmc: sdhci@ffe7080000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7080000 0x0 0x10000
-			       0xff 0xef014060 0x0 0x4>;
+			reg = <0xff 0xe7080000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <62>;
 			interrupt-names = "sdhciirq";
@@ -1365,8 +1392,7 @@
 
 		sdhci0: sd@ffe7090000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7090000 0x0 0x10000
-			       0xff 0xef014064 0x0 0x4>;
+			reg = <0xff 0xe7090000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <64>;
 			interrupt-names = "sdhci0irq";
@@ -1376,8 +1402,7 @@
 
 		sdhci1: sd@ffe70a0000 {
 		        compatible = "snps,dwcmshc-sdhci";
-		        reg = <0xff 0xe70a0000 0x0 0x10000
-		               0xff 0xef014064 0x0 0x4>;
+		        reg = <0xff 0xe70a0000 0x0 0x10000>;
 		        interrupt-parent = <&intc>;
 		        interrupts = <71>;
 		        interrupt-names = "sdhci1irq";
@@ -1403,7 +1428,8 @@
 			clock-names = "pclk", "aclk";
 			vha_clk_rate = <1000000000>;
 			ldo_vha-supply = <&npu>;
-			dma-mask = <0xf 0xffffffff>;
+			dma-mask = <0xff 0xffffffff>;
+			resets = <&rst LIGHT_RESET_NPU>;
 			status = "disabled";
 		};
 
@@ -1432,6 +1458,7 @@
 			clocks = <&vpsys_clk_gate LIGHT_VPSYS_FCE_ACLK>,
 				<&vpsys_clk_gate LIGHT_VPSYS_FCE_PCLK>;
 			clock-names = "aclk", "pclk";
+			resets = <&vpsys_rst LIGHT_RESET_FCE>;
 			dma-mask = <0xf 0xffffffff>;
 			status = "disabled";
 		};
@@ -1481,7 +1508,7 @@
 			compatible = "light,light-i2s";
 			reg = <0xff 0xe7034000 0x0 0x4000>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_audio_i2s0>;
+			pinctrl-0 = <&pinctrl_light_i2s0>;
 			light,mode = "i2s-master";
 			light,sel = "ap_i2s";
 			interrupt-parent = <&intc>;
@@ -1506,7 +1533,7 @@
 			light,sel = "i2s0";
 			interrupt-parent = <&intc>;
 			interrupts = <174>;
-			dmas = <&dmac2 9>, <&dmac2 16>;
+			dmas = <&dmac2 9>, <&dmac2 8>;
 			dma-names = "tx", "rx";
 			light,dma_maxburst = <4>;
 			#dma-cells = <1>;
@@ -1555,16 +1582,17 @@
 			status = "disabled";
 		};
 
-		i2s3: audio_i2s3@0xffcb017000 {
+		i2s_8ch_sd0: audio_i2s_8ch_sd0@0xffcb017000 {
 			#sound-dai-cells = <1>;
-			compatible = "light,light-i2s";
+			compatible = "light,light-i2s-8ch";
 			reg = <0xff 0xcb017000 0x0 0x1000>;
+			audio-cpr-regmap = <&audio_cpr>;
 			pinctrl-names = "default";
 			light,mode = "i2s-master";
-			light,sel = "i2s3";
+			light,sel = "i2s_8ch_sd0";
 			interrupt-parent = <&intc>;
 			interrupts = <177>;
-			dmas = <&dmac2 14>, <&dmac2 16>;
+			dmas = <&dmac2 36>, <&dmac2 14>;
 			dma-names = "tx", "rx";
 			light,dma_maxburst = <4>;
 			#dma-cells = <1>;
@@ -1573,6 +1601,267 @@
 			status = "disabled";
 		};
 
+		i2s_8ch_sd1: audio_i2s_8ch_sd1@0xffcb017000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s-8ch";
+			reg = <0xff 0xcb017000 0x0 0x1000>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s_8ch_sd1";
+			interrupt-parent = <&intc>;
+			interrupts = <177>;
+			dmas = <&dmac2 37>, <&dmac2 15>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		i2s_8ch_sd2: audio_i2s_8ch_sd2@0xffcb017000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s-8ch";
+			reg = <0xff 0xcb017000 0x0 0x1000>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s_8ch_sd2";
+			interrupt-parent = <&intc>;
+			interrupts = <177>;
+			dmas = <&dmac2 38>, <&dmac2 16>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		i2s_8ch_sd3: audio_i2s_8ch_sd3@0xffcb017000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s-8ch";
+			reg = <0xff 0xcb017000 0x0 0x1000>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s_8ch_sd3";
+			interrupt-parent = <&intc>;
+			interrupts = <177>;
+			dmas = <&dmac2 39>, <&dmac2 17>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot1: audio_tdm_slot1@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <1>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 28>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot2: audio_tdm_slot2@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 29>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot3: audio_tdm_slot3@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <3>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 30>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot4: audio_tdm_slot4@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <4>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 31>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot5: audio_tdm_slot5@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <5>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 32>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot6: audio_tdm_slot6@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <6>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 33>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot7: audio_tdm_slot7@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <7>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 34>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot8: audio_tdm_slot8@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <8>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 35>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		spdif0: audio_spdif0@0xffcb018000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-spdif";
+			reg = <0xff 0xcb018000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			interrupt-parent = <&intc>;
+			interrupts = <179>;
+			dmas = <&dmac2 25>, <&dmac2 24>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF0>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		spdif1: audio_spdif1@0xffcb019000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-spdif";
+			reg = <0xff 0xcb019000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			interrupt-parent = <&intc>;
+			interrupts = <180>;
+			dmas = <&dmac2 27>, <&dmac2 26>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF1>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
 		pvt: pvt@fffff4e000 {
 		    compatible = "moortec,mr75203";
 		    reg = <0xff 0xfff4e000 0x0 0x80>,
@@ -1592,6 +1881,10 @@
 			interrupts = <44>;
 			clocks = <&dummy_clock_apb>;
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 12>, <&dmac0 13>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1611,6 +1904,10 @@
 			interrupts = <45>;
 			clocks = <&dummy_clock_apb>;
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 14>, <&dmac0 15>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1630,6 +1927,10 @@
 			interrupts = <46>;
 			clocks = <&dummy_clock_apb>;
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 16>, <&dmac0 17>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1651,6 +1952,10 @@
 			interrupts = <47>;
 			clocks = <&dummy_clock_apb>;
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 18>, <&dmac0 19>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1672,6 +1977,10 @@
 			interrupts = <48>;
 			clocks = <&dummy_clock_apb>;
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 20>, <&dmac0 21>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1693,6 +2002,10 @@
 			interrupts = <182>;
 			clocks = <&dummy_clock_apb>;
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac2 21>, <&dmac2 20>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x82>;
 			ss_lcnt = /bits/ 16 <0x78>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1705,26 +2018,30 @@
 			#size-cells = <0>;
 		};
 
-		audio_i2c1: i2c@0xffcb01b000 {
-			compatible = "snps,designware-i2c";
-			reg = <0xff 0xcb01b000 0x0 0x1000>;
-			interrupt-parent = <&intc>;
-			interrupts = <183>;
-			clocks = <&dummy_clock_apb>;
-			clock-frequency = <100000>;
-			ss_hcnt = /bits/ 16 <0x82>;
-			ss_lcnt = /bits/ 16 <0x78>;
-			fs_hcnt = /bits/ 16 <0x37>;
-			fs_lcnt = /bits/ 16 <0x42>;
-			fp_hcnt = /bits/ 16 <0x14>;
-			fp_lcnt = /bits/ 16 <0x1a>;
-			hs_hcnt = /bits/ 16 <0x5>;
-			hs_lcnt = /bits/ 16 <0x15>;
-			status = "disabled";
+        audio_i2c1: i2c@0xffcb01b000 {
+                compatible = "snps,designware-i2c";
+                reg = <0xff 0xcb01b000 0x0 0x1000>;
+                interrupt-parent = <&intc>;
+                interrupts = <183>;
+                clocks = <&dummy_clock_apb>;
+                clock-frequency = <100000>;
+                i2c_mode = "dma";
+			    dmas = <&dmac2 23>, <&dmac2 22>;
+			    dma-names = "tx", "rx";
+			    #dma-cells = <1>;
+                ss_hcnt = /bits/ 16 <0x82>;
+                ss_lcnt = /bits/ 16 <0x78>;
+                fs_hcnt = /bits/ 16 <0x37>;
+                fs_lcnt = /bits/ 16 <0x42>;
+                fp_hcnt = /bits/ 16 <0x14>;
+                fp_lcnt = /bits/ 16 <0x1a>;
+                hs_hcnt = /bits/ 16 <0x5>;
+                hs_lcnt = /bits/ 16 <0x15>;
+                status = "disabled";
 
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
 
 		isp0: isp@ffe4100000 {
 			compatible = "thead,light-isp";
@@ -2005,6 +2322,11 @@
 			status = "disabled";
 		};
 
+		vvcam_sensor7: vvcam_sensor@7 {
+			compatible = "thead,light-vvcam-sensor";
+			status = "disabled";
+		};
+
 		xtensa_dsp: dsp@01{
 			compatible = "thead,dsp-hw-common";
 			reg = <0xff 0xef040000 0x0 0x001000 >;   /*DSP_SYSREG(0x0000-0xFFF) */
@@ -2154,6 +2476,12 @@
 			interrupts = <215>; /* TEE INT SRC_7 */
 		};
 
+        light_event: light-event {
+                compatible = "thead,light-event";
+                aon-iram-regmap = <&aon_iram>;
+                status = "okay";
+        };
+
 		visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */
 			compatible = "thead,visys-gate-controller";
 			visys-regmap = <&visys_reg>;
@@ -2181,6 +2509,13 @@
 			#clock-cells = <1>;
 			status = "okay";
 		};
+
+		audiosys_clk_gate: audiosys-clk-gate {
+			compatible = "thead,audiosys-gate-controller";
+			audiosys-regmap = <&audio_cpr>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
 	};
 
 };

arch/riscv/configs/fire_defconfig

@@ -251,6 +251,7 @@ CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_LIGHT=y
 CONFIG_HWSPINLOCK_LIGHT_TEST=m
 CONFIG_MAILBOX=y
+CONFIG_EXTCON=y
 CONFIG_IIO=y
 CONFIG_IIO_SW_DEVICE=y
 CONFIG_PWM=y

arch/riscv/configs/fire_emu_defconfig

@@ -252,6 +252,7 @@ CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_LIGHT=y
 CONFIG_HWSPINLOCK_LIGHT_TEST=m
 CONFIG_MAILBOX=y
+CONFIG_EXTCON=y
 CONFIG_IIO=y
 CONFIG_IIO_SW_DEVICE=y
 CONFIG_PWM=y

arch/riscv/configs/light_defconfig

@@ -91,6 +91,7 @@ CONFIG_TUN=y
 CONFIG_VIRTIO_NET=y
 CONFIG_MACB=y
 CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_RX_ZERO_COPY=y
 CONFIG_DWMAC_LIGHT=y
 CONFIG_MICROSEMI_PHY=y
 CONFIG_REALTEK_PHY=y
@@ -265,6 +266,11 @@ CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_LIGHT=y
 CONFIG_HWSPINLOCK_LIGHT_TEST=m
 CONFIG_MAILBOX=y
+CONFIG_RPMSG=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_VIRTIO=y
+CONFIG_RPMSG_THEAD_LIGHT=y
+CONFIG_EXTCON=y
 CONFIG_IIO=y
 CONFIG_IIO_SW_DEVICE=y
 CONFIG_PWM=y
@@ -298,13 +304,21 @@ CONFIG_CRYPTO_AUTHENC=y
 CONFIG_CRYPTO_DH=y
 CONFIG_CRYPTO_CURVE25519=y
 CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
 CONFIG_CRYPTO_OFB=y
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_SHA512=y
 CONFIG_CRYPTO_SHA3=y
 CONFIG_CRYPTO_SM3=y
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_USER=y
 CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=y
+# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
+CONFIG_CRYPTO_USER_API_AEAD=y
 CONFIG_DMA_CMA=y
 CONFIG_DMA_PERNUMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=32

arch/riscv/configs/revyos_defconfig

@@ -0,0 +1,454 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_MEMCG=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_BPF=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+# CONFIG_BUG is not set
+CONFIG_BPF_SYSCALL=y
+CONFIG_PERF_EVENTS=y
+CONFIG_FORCE_MAX_ZONEORDER=15
+CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_THEAD=y
+CONFIG_SMP=y
+CONFIG_VECTOR=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_RISV_THEAD_LIGHT_CPUFREQ=y
+# CONFIG_SUSPEND is not set
+CONFIG_PM=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_LIGHT_AON_PD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BINFMT_MISC=m
+CONFIG_CMA=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_CMA_AREAS=16
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPVTI=y
+CONFIG_INET_ESP=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_IPVS=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_BBR=m
+CONFIG_IP_VS=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_NFCT=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_NAT=y
+CONFIG_BRIDGE=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_CLS_CGROUP=y
+CONFIG_VSOCKETS=y
+# CONFIG_VSOCKETS_LOOPBACK is not set
+CONFIG_VIRTIO_VSOCKETS=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_RTL3WIRE=y
+CONFIG_CFG80211=y
+CONFIG_RFKILL=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_PCI=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_LIGHT_DSMART_CARD=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_THIN_PROVISIONING=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_MACVLAN=y
+CONFIG_IPVLAN=y
+CONFIG_VXLAN=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+CONFIG_VIRTIO_NET=y
+CONFIG_MACB=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_RX_ZERO_COPY=y
+CONFIG_DWMAC_LIGHT=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_USB_USBNET=m
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_AX88179_178A is not set
+# CONFIG_USB_NET_NET1080 is not set
+CONFIG_RTL8723DS=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_GOODIX=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_DW_QUAD=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PINCTRL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_MR75203=y
+CONFIG_SENSORS_PWM_FAN=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=32
+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
+CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_LIGHT_PMIC_WATCHDOG=y
+CONFIG_ABX500_CORE=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_MEDIA_SUPPORT=y
+# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
+# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_ASPEED=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18250 is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MSI001 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2063 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_FC0011 is not set
+# CONFIG_MEDIA_TUNER_FC0012 is not set
+# CONFIG_MEDIA_TUNER_FC0013 is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_E4000 is not set
+# CONFIG_MEDIA_TUNER_FC2580 is not set
+# CONFIG_MEDIA_TUNER_M88RS6000T is not set
+# CONFIG_MEDIA_TUNER_TUA9001 is not set
+# CONFIG_MEDIA_TUNER_SI2157 is not set
+# CONFIG_MEDIA_TUNER_IT913X is not set
+# CONFIG_MEDIA_TUNER_R820T is not set
+# CONFIG_MEDIA_TUNER_MXL301RF is not set
+# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
+# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
+CONFIG_DRM_PANEL_ILI9881D=y
+CONFIG_DRM_PANEL_HX8394=y
+CONFIG_DRM_VERISILICON=y
+CONFIG_DRM_POWERVR_ROGUE=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_THEAD_LIGHT=y
+CONFIG_SND_SOC_AW87519=y
+CONFIG_SND_SOC_BT_SCO=y
+CONFIG_SND_SOC_ES7210=y
+CONFIG_SND_SOC_ES8156=y
+CONFIG_SND_SOC_WM8960=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_UHID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ACM=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_DWC3=m
+CONFIG_USB_DWC3_HOST=y
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_F8153X=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_METRO=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MXUPORT=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_XSENS_MT=m
+CONFIG_USB_SERIAL_WISHBONE=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_QT2=m
+CONFIG_USB_SERIAL_UPD78F0730=m
+CONFIG_USB_SERIAL_DEBUG=m
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_ROLE_SWITCH=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_XGENE=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_AXI_DMAC=y
+CONFIG_DMATEST=y
+CONFIG_SW_SYNC=y
+CONFIG_UDMABUF=y
+CONFIG_DMABUF_SELFTESTS=m
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_KHV_MMIO=y
+CONFIG_VHOST_NET=y
+CONFIG_VHOST_VSOCK=y
+CONFIG_STAGING=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_CLK_LIGHT_FM=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_LIGHT=y
+CONFIG_HWSPINLOCK_LIGHT_TEST=m
+CONFIG_MAILBOX=y
+CONFIG_RPMSG=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_VIRTIO=y
+CONFIG_RPMSG_THEAD_LIGHT=y
+CONFIG_EXTCON=y
+CONFIG_IIO=y
+CONFIG_IIO_SW_DEVICE=y
+CONFIG_PWM=y
+CONFIG_PWM_LIGHT=y
+CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_BENCHMARK=y
+CONFIG_LIGHT_GPU_VIV=m
+# CONFIG_LIGHT_NET is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_BTRFS_FS=y
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_OVERLAY_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_EXFAT_FS=m
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_APPARMOR=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_CURVE25519=y
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_OFB=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=y
+CONFIG_CRYPTO_USER_API_AEAD=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_RCU_TRACE is not set

arch/riscv/include/asm/Kbuild

@@ -3,7 +3,8 @@ generic-y += early_ioremap.h
 generic-y += extable.h
 generic-y += flat.h
 generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
+generic-y += qspinlock.h
 generic-y += qrwlock.h
-generic-y += qrwlock_types.h
 generic-y += user.h
 generic-y += vmlinux.lds.h

arch/riscv/include/asm/cmpxchg.h

@@ -11,12 +11,36 @@
 #include <asm/barrier.h>
 #include <asm/fence.h>
 
+static inline ulong __xchg16_relaxed(ulong new, void *ptr)
+{
+       ulong ret, tmp;
+       ulong shif = ((ulong)ptr & 2) ? 16 : 0;
+       ulong mask = 0xffff << shif;
+       ulong *__ptr = (ulong *)((ulong)ptr & ~2);
+
+       __asm__ __volatile__ (
+               "0:     lr.w %0, %2\n"
+               "       and  %1, %0, %z3\n"
+               "       or   %1, %1, %z4\n"
+               "       sc.w %1, %1, %2\n"
+               "       bnez %1, 0b\n"
+               : "=&r" (ret), "=&r" (tmp), "+A" (*__ptr)
+               : "rJ" (~mask), "rJ" (new << shif)
+               : "memory");
+
+       return (ulong)((ret & mask) >> shif);
+}
+
 #define __xchg_relaxed(ptr, new, size)					\
 ({									\
 	__typeof__(ptr) __ptr = (ptr);					\
 	__typeof__(new) __new = (new);					\
 	__typeof__(*(ptr)) __ret;					\
 	switch (size) {							\
+        case 2: {                                                       \
+                __ret = (__typeof__(*(ptr)))                            \
+                         __xchg16_relaxed((ulong)__new, __ptr);         \
+                break;}                                                 \
 	case 4:								\
 		__asm__ __volatile__ (					\
 			"	amoswap.w %0, %2, %1\n"			\

arch/riscv/include/asm/csr.h

@@ -26,19 +26,11 @@
 
 #define SR_VS_OFF	_AC(0x00000000, UL)
 
-#if (defined(CONFIG_VECTOR_1_0) && defined(__THEAD_VERSION__))
-#define SR_VS		_AC(0x00000600, UL) /* Vector Status */
-#define SR_VS_INITIAL	_AC(0x00000200, UL)
-#define SR_VS_CLEAN	_AC(0x00000400, UL)
-#define SR_VS_DIRTY	_AC(0x00000600, UL)
-#else
 #define SR_VS		_AC(0x01800000, UL) /* Vector Status */
 #define SR_VS_INITIAL	_AC(0x00800000, UL)
 #define SR_VS_CLEAN	_AC(0x01000000, UL)
 #define SR_VS_DIRTY	_AC(0x01800000, UL)
 
-#endif
-
 #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
 #define SR_XS_OFF	_AC(0x00000000, UL)
 #define SR_XS_INITIAL	_AC(0x00008000, UL)

arch/riscv/include/asm/io.h

@@ -13,7 +13,6 @@
 
 #include <linux/types.h>
 #include <linux/pgtable.h>
-#include <asm/mmiowb.h>
 #include <asm/early_ioremap.h>
 
 /*

arch/riscv/include/asm/mmio.h

@@ -133,7 +133,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
 #define __io_br()	do {} while (0)
 #define __io_ar(v)	__asm__ __volatile__ ("fence i,r" : : : "memory")
 #define __io_bw()	__asm__ __volatile__ ("fence w,o" : : : "memory")
-#define __io_aw()	mmiowb_set_pending()
+#define __io_aw()	__asm__ __volatile__ ("fence o,w" : : : "memory")
 
 #define readb(c)	({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
 #define readw(c)	({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })

arch/riscv/include/asm/mmiowb.h

@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef _ASM_RISCV_MMIOWB_H
-#define _ASM_RISCV_MMIOWB_H
-
-/*
- * "o,w" is sufficient to ensure that all writes to the device have completed
- * before the write to the spinlock is allowed to commit.
- */
-#define mmiowb()	__asm__ __volatile__ ("fence o,w" : : : "memory");
-
-#include <linux/smp.h>
-#include <asm-generic/mmiowb.h>
-
-#endif	/* _ASM_RISCV_MMIOWB_H */

arch/riscv/include/asm/spinlock.h

@@ -1,92 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 
-/*
- * 'Generic' ticket-lock implementation.
- *
- * It relies on atomic_fetch_add() having well defined forward progress
- * guarantees under contention. If your architecture cannot provide this, stick
- * to a test-and-set lock.
- *
- * It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
- * sub-word of the value. This is generally true for anything LL/SC although
- * you'd be hard pressed to find anything useful in architecture specifications
- * about this. If your architecture cannot do this you might be better off with
- * a test-and-set.
- *
- * It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
- * uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
- * a full fence after the spin to upgrade the otherwise-RCpc
- * atomic_cond_read_acquire().
- *
- * The implementation uses smp_cond_load_acquire() to spin, so if the
- * architecture has WFE like instructions to sleep instead of poll for word
- * modifications be sure to implement that (see ARM64 for example).
- *
- */
-
 #ifndef __ASM_GENERIC_SPINLOCK_H
 #define __ASM_GENERIC_SPINLOCK_H
 
-#include <linux/atomic.h>
-#include <asm/spinlock_types.h>
-
-static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
-{
-	u32 val = atomic_fetch_add(1<<16, lock);
-	u16 ticket = val >> 16;
-
-	if (ticket == (u16)val)
-		return;
-
-	/*
-	 * atomic_cond_read_acquire() is RCpc, but rather than defining a
-	 * custom cond_read_rcsc() here we just emit a full fence.  We only
-	 * need the prior reads before subsequent writes ordering from
-	 * smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
-	 * have no outstanding writes due to the atomic_fetch_add() the extra
-	 * orderings are free.
-	 */
-	atomic_cond_read_acquire(lock, ticket == (u16)VAL);
-	smp_mb();
-}
-
-static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
-{
-	u32 old = atomic_read(lock);
-
-	if ((old >> 16) != (old & 0xffff))
-		return false;
-
-	return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
-}
-
-static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
-	u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
-	u32 val = atomic_read(lock);
-
-	smp_store_release(ptr, (u16)val + 1);
-}
-
-static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
-	u32 val = atomic_read(lock);
-
-	return ((val >> 16) != (val & 0xffff));
-}
-
-static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
-{
-	u32 val = atomic_read(lock);
-
-	return (s16)((val >> 16) - (val & 0xffff)) > 1;
-}
-
-static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
-{
-	return !arch_spin_is_locked(&lock);
-}
-
+#include <asm-generic/qspinlock.h>
 #include <asm/qrwlock.h>
 
 #endif /* __ASM_GENERIC_SPINLOCK_H */

arch/riscv/include/asm/spinlock_types.h

@@ -3,15 +3,7 @@
 #ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
 #define __ASM_GENERIC_SPINLOCK_TYPES_H
 
-#include <linux/types.h>
-typedef atomic_t arch_spinlock_t;
-
-/*
- * qrwlock_types depends on arch_spinlock_t, so we must typedef that before the
- * include.
- */
-#include <asm/qrwlock_types.h>
-
-#define __ARCH_SPIN_LOCK_UNLOCKED	ATOMIC_INIT(0)
+#include <asm-generic/qspinlock_types.h>
+#include <asm-generic/qrwlock_types.h>
 
 #endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */

arch/riscv/kernel/probes/decode-insn.c

@@ -38,11 +38,10 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)
 	RISCV_INSN_REJECTED(c_ebreak,		insn);
 #endif
 
-	RISCV_INSN_REJECTED(auipc,		insn);
-	RISCV_INSN_REJECTED(branch,		insn);
-
 	RISCV_INSN_SET_SIMULATE(jal,		insn);
 	RISCV_INSN_SET_SIMULATE(jalr,		insn);
+	RISCV_INSN_SET_SIMULATE(auipc,		insn);
+	RISCV_INSN_SET_SIMULATE(branch,		insn);
 
 	return INSN_GOOD;
 }

arch/riscv/kernel/probes/simulate-insn.c

@@ -83,3 +83,115 @@ bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *reg
 
 	return ret;
 }
+
+#define auipc_rd_idx(opcode) \
+	((opcode >> 7) & 0x1f)
+
+#define auipc_imm(opcode) \
+	((((opcode) >> 12) & 0xfffff) << 12)
+
+#if __riscv_xlen == 64
+#define auipc_offset(opcode)	sign_extend64(auipc_imm(opcode), 31)
+#elif __riscv_xlen == 32
+#define auipc_offset(opcode)	auipc_imm(opcode)
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs)
+{
+	/*
+	 * auipc instruction:
+	 *  31        12 11 7 6      0
+	 * | imm[31:12] | rd | opcode |
+	 *        20       5     7
+	 */
+
+	u32 rd_idx = auipc_rd_idx(opcode);
+	unsigned long rd_val = addr + auipc_offset(opcode);
+
+	if (!rv_insn_reg_set_val(regs, rd_idx, rd_val))
+		return false;
+
+	instruction_pointer_set(regs, addr + 4);
+
+	return true;
+}
+
+#define branch_rs1_idx(opcode) \
+	(((opcode) >> 15) & 0x1f)
+
+#define branch_rs2_idx(opcode) \
+	(((opcode) >> 20) & 0x1f)
+
+#define branch_funct3(opcode) \
+	(((opcode) >> 12) & 0x7)
+
+#define branch_imm(opcode) \
+	(((((opcode) >>  8) & 0xf ) <<  1) | \
+	 ((((opcode) >> 25) & 0x3f) <<  5) | \
+	 ((((opcode) >>  7) & 0x1 ) << 11) | \
+	 ((((opcode) >> 31) & 0x1 ) << 12))
+
+#define branch_offset(opcode) \
+	sign_extend32((branch_imm(opcode)), 12)
+
+#define BRANCH_BEQ	0x0
+#define BRANCH_BNE	0x1
+#define BRANCH_BLT	0x4
+#define BRANCH_BGE	0x5
+#define BRANCH_BLTU	0x6
+#define BRANCH_BGEU	0x7
+
+bool __kprobes simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs)
+{
+	/*
+	 * branch instructions:
+	 *      31    30       25 24 20 19 15 14    12 11       8    7      6      0
+	 * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |
+	 *     1           6        5     5      3         4         1         7
+	 *     imm[12|10:5]        rs2   rs1    000       imm[4:1|11]       1100011  BEQ
+	 *     imm[12|10:5]        rs2   rs1    001       imm[4:1|11]       1100011  BNE
+	 *     imm[12|10:5]        rs2   rs1    100       imm[4:1|11]       1100011  BLT
+	 *     imm[12|10:5]        rs2   rs1    101       imm[4:1|11]       1100011  BGE
+	 *     imm[12|10:5]        rs2   rs1    110       imm[4:1|11]       1100011  BLTU
+	 *     imm[12|10:5]        rs2   rs1    111       imm[4:1|11]       1100011  BGEU
+	 */
+
+	s32 offset;
+	s32 offset_tmp;
+	unsigned long rs1_val;
+	unsigned long rs2_val;
+
+	if (!rv_insn_reg_get_val(regs, branch_rs1_idx(opcode), &rs1_val) ||
+	    !rv_insn_reg_get_val(regs, branch_rs2_idx(opcode), &rs2_val))
+		return false;
+
+	offset_tmp = branch_offset(opcode);
+	switch (branch_funct3(opcode)) {
+	case BRANCH_BEQ:
+		offset = (rs1_val == rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BNE:
+		offset = (rs1_val != rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BLT:
+		offset = ((long)rs1_val < (long)rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BGE:
+		offset = ((long)rs1_val >= (long)rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BLTU:
+		offset = (rs1_val < rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BGEU:
+		offset = (rs1_val >= rs2_val) ? offset_tmp : 4;
+		break;
+	default:
+		return false;
+	}
+
+	instruction_pointer_set(regs, addr + offset);
+
+	return true;
+}

arch/riscv/kernel/vector.S

@@ -20,14 +20,6 @@
 #include <asm/csr.h>
 #include <asm/asm-offsets.h>
 
-#if (defined(CONFIG_VECTOR_1_0) && defined(__THEAD_VERSION__))
-#define V_ST	vse8.v
-#define V_LD	vle8.v
-#else
-#define V_ST	vsb.v
-#define V_LD	vlb.v
-#endif
-
 ENTRY(__vstate_save)
 	li	a2,  TASK_THREAD_V0
 	add	a0,  a0, a2
@@ -46,81 +38,14 @@ ENTRY(__vstate_save)
 	csrr	t0,  CSR_VTYPE
 	sd	t0,  TASK_THREAD_VTYPE_V0(a0)
 
-#ifdef CONFIG_VLEN_256
-	vsetvli	t0, x0, e8,m1
-	V_ST	v0,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v1,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v2,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v3,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v4,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v5,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v6,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v7,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v8,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v9,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v10, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v11, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v12, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v13, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v14, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v15, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v16, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v17, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v18, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v19, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v20, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v21, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v22, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v23, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v24, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v25, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v26, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v27, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v28, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v29, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v30, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_ST	v31, (a0)
-#else
-	vsetvli	t0, x0, e8,m8
-	V_ST	v0,  (a0)
+	.word 0x003072d7 	/* vsetvli	t0, x0, e8,m8 	*/
+	.word 0x02050027 	/* vsb.v	v0,  (a0)	*/
 	addi	a0, a0, RISCV_VECTOR_VLENB*8
-	V_ST	v8,  (a0)
+	.word 0x02050427 	/* vsb.v	v8,  (a0) 	*/
 	addi	a0, a0, RISCV_VECTOR_VLENB*8
-	V_ST	v16, (a0)
+	.word 0x02050827 	/* vsb.v	v16, (a0) 	*/
 	addi	a0, a0, RISCV_VECTOR_VLENB*8
-	V_ST	v24, (a0)
-#endif
+	.word 0x02050c27 	/* vsb.v	v24, (a0) 	*/
 
 	csrc	sstatus, t1
 	ret
@@ -134,81 +59,14 @@ ENTRY(__vstate_restore)
 	li	t1, (SR_VS | SR_FS)
 	csrs	sstatus, t1
 
-#ifdef CONFIG_VLEN_256
-	vsetvli	t0, x0, e8,m1
-	V_LD	v0,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v1,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v2,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v3,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v4,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v5,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v6,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v7,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v8,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v9,  (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v10, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v11, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v12, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v13, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v14, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v15, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v16, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v17, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v18, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v19, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v20, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v21, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v22, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v23, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v24, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v25, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v26, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v27, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v28, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v29, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v30, (a0)
-	addi	a0, a0, RISCV_VECTOR_VLENB
-	V_LD	v31, (a0)
-#else
-	vsetvli	t0, x0, e8,m8
-	V_LD	v0,  (a0)
+	.word 0x003072d7	/* vsetvli	t0, x0, e8,m8 	*/
+	.word 0x12050007	/* vlb.v	v0,  (a0) 	*/
 	addi	a0, a0, RISCV_VECTOR_VLENB*8
-	V_LD	v8,  (a0)
+	.word 0x12050407	/* vlb.v	v8,  (a0)	*/
 	addi	a0, a0, RISCV_VECTOR_VLENB*8
-	V_LD	v16, (a0)
+	.word 0x12050807 	/* vlb.v	v16, (a0)	*/
 	addi	a0, a0, RISCV_VECTOR_VLENB*8
-	V_LD	v24, (a0)
-#endif
+	.word 0x12050c07	/* vlb.v	v24, (a0)	*/
 
 	mv	a0,  t2
 	ld	t0,  TASK_THREAD_VSTART_V0(a0)
@@ -219,16 +77,9 @@ ENTRY(__vstate_restore)
 	csrw	CSR_VXRM, t0
 	ld	t0,  TASK_THREAD_VL_V0(a0)
 	ld	t2,  TASK_THREAD_VTYPE_V0(a0)
-#ifdef CONFIG_VECTOR_EMU
-	srli	t3, t2, 63
-	bne	t3,zero,1f
-#endif
-	vsetvl	t3, t0, t2
-#ifdef CONFIG_VECTOR_EMU
-	j	2f
-1:	vsetvli zero,zero,e64,m2,d1
-2:
-#endif
+
+	.word 0x8072fe57 	/* vsetvl	t3, t0, t2	*/
+
 	csrc	sstatus, t1
 	ret
 ENDPROC(__vstate_restore)

drivers/Kconfig

@@ -8,6 +8,7 @@ source "drivers/eisa/Kconfig"
 source "drivers/pci/Kconfig"
 source "drivers/pcmcia/Kconfig"
 source "drivers/rapidio/Kconfig"
+source "drivers/nna/Kconfig"
 
 
 source "drivers/base/Kconfig"

drivers/Makefile

@@ -45,6 +45,9 @@ obj-$(CONFIG_VIRTIO)		+= virtio/
 obj-$(CONFIG_VDPA)		+= vdpa/
 obj-$(CONFIG_XEN)		+= xen/
 
+# npu-ax3386-gpl driver
+obj-y				+= nna/
+
 # regulators early, since some subsystems rely on them to initialize
 obj-$(CONFIG_REGULATOR)		+= regulator/
 

drivers/clk/thead/gate/Makefile

@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 
-obj-$(CONFIG_CLK_LIGHT_FM) += thead-gate.o visys-gate.o vpsys-gate.o vosys-gate.o dspsys-gate.o
+obj-$(CONFIG_CLK_LIGHT_FM) += thead-gate.o visys-gate.o vpsys-gate.o vosys-gate.o dspsys-gate.o audiosys-gate.o

drivers/clk/thead/gate/audiosys-gate.c

@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 Alibaba Group Holding Limited.
+ */
+
+#include <dt-bindings/clock/light-fm-ap-clock.h>
+#include <dt-bindings/clock/light-audiosys.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include "clk-gate.h"
+#include "../clk.h"
+
+static struct clk *gates[LIGHT_CLKGEN_AUDIO_CLK_END];
+static struct clk_onecell_data clk_gate_data;
+
+static int light_audiosys_clk_probe(struct platform_device *pdev)
+{
+	struct regmap *audiosys_regmap;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	audiosys_regmap = syscon_regmap_lookup_by_phandle(np, "audiosys-regmap");
+	if (IS_ERR(audiosys_regmap)) {
+		dev_err(&pdev->dev, "cannot find regmap for vi system register\n");
+		return PTR_ERR(audiosys_regmap);
+	}
+
+	printk("%s audiosys_regmap=0x%px\n", __func__, audiosys_regmap);
+
+	/* we assume that the gate clock is a root clock  */
+	gates[LIGHT_CLKGEN_AUDIO_CPU] = thead_gate_clk_register("clkgen_audiosys_cpu_clk", NULL,
+									audiosys_regmap, 0x10, 0, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_SRAM0] = thead_gate_clk_register("clkgen_audiosys_sram0_clk", NULL,
+									audiosys_regmap, 0x10, 1, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_SRAM1] = thead_gate_clk_register("clkgen_audiosys_sram1_clk", NULL,
+									audiosys_regmap, 0x10, 2, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_DMA] = thead_gate_clk_register("clkgen_audiosys_dma_clk", NULL,
+									audiosys_regmap, 0x10, 3, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_BSM] = thead_gate_clk_register("clkgen_audiosys_bsm_clk", NULL,
+									audiosys_regmap, 0x10, 4, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_TIMER] = thead_gate_clk_register("clkgen_audiosys_timer_clk", NULL,
+									audiosys_regmap, 0x10, 8, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_TIMER_CNT1] = thead_gate_clk_register("clkgen_audiosys_timer_cnt1_clk", NULL,
+									audiosys_regmap, 0x10, 9, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_TIMER_CNT2] = thead_gate_clk_register("clkgen_audiosys_timer_cnt2_clk", NULL,
+									audiosys_regmap, 0x10, 10, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_TIMER_CNT3] = thead_gate_clk_register("clkgen_audiosys_timer_cnt3_clk", NULL,
+									audiosys_regmap, 0x10, 11, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_TIMER_CNT4] = thead_gate_clk_register("clkgen_audiosys_timer_cnt4_clk", NULL,
+									audiosys_regmap, 0x10, 12, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_WDR] = thead_gate_clk_register("clkgen_audiosys_wdr_clk", NULL,
+									audiosys_regmap, 0x10, 13, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_I2C0] = thead_gate_clk_register("clkgen_audiosys_i2c0_clk", NULL,
+									audiosys_regmap, 0x10, 14, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_I2C1] = thead_gate_clk_register("clkgen_audiosys_i2c1_clk", NULL,
+									audiosys_regmap, 0x10, 15, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_UART] = thead_gate_clk_register("clkgen_audiosys_uart_clk", NULL,
+									audiosys_regmap, 0x10, 16, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_I2S0] = thead_gate_clk_register("clkgen_audiosys_i2s0_clk", NULL,
+									audiosys_regmap, 0x10, 17, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_I2S1] = thead_gate_clk_register("clkgen_audiosys_i2s1_clk", NULL,
+									audiosys_regmap, 0x10, 18, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_I2S2] = thead_gate_clk_register("clkgen_audiosys_i2s2_clk", NULL,
+									audiosys_regmap, 0x10, 19, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_I2S8CH] = thead_gate_clk_register("clkgen_audiosys_i2s8ch_clk", NULL,
+									audiosys_regmap, 0x10, 20, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_TDM] = thead_gate_clk_register("clkgen_audiosys_tdm_clk", NULL,
+									audiosys_regmap, 0x10, 21, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_GPIO] = thead_gate_clk_register("clkgen_audiosys_gpio_clk", NULL,
+									audiosys_regmap, 0x10, 22, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_SPDIF0] = thead_gate_clk_register("clkgen_audiosys_spdif0_clk", NULL,
+									audiosys_regmap, 0x10, 23, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_SPDIF1] = thead_gate_clk_register("clkgen_audiosys_spdif1_clk", NULL,
+									audiosys_regmap, 0x10, 24, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_VAD] = thead_gate_clk_register("clkgen_audiosys_vad_clk", NULL,
+									audiosys_regmap, 0x10, 25, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_AUDIO_IOMUX] = thead_gate_clk_register("clkgen_audiosys_iomux_clk", NULL,
+									audiosys_regmap, 0x10, 26, GATE_NOT_SHARED, NULL, dev);
+
+	clk_gate_data.clks = gates;
+	clk_gate_data.clk_num = ARRAY_SIZE(gates);
+
+	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_gate_data);
+	if (ret < 0) {
+		dev_err(dev, "failed to register gate clks for light audiosys\n");
+		goto unregister_clks;
+	}
+
+	dev_info(dev, "succeed to register audiosys gate clock provider\n");
+
+	return 0;
+
+unregister_clks:
+	thead_unregister_clocks(gates, ARRAY_SIZE(gates));
+	return ret;
+}
+
+static const struct of_device_id audiosys_clk_gate_of_match[] = {
+	{ .compatible = "thead,audiosys-gate-controller" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, audiosys_clk_gate_of_match);
+
+static struct platform_driver light_audiosys_clk_driver = {
+	.probe = light_audiosys_clk_probe,
+	.driver = {
+		.name = "audiosys-clk-gate-provider",
+		.of_match_table = of_match_ptr(audiosys_clk_gate_of_match),
+	},
+};
+
+module_platform_driver(light_audiosys_clk_driver);
+MODULE_AUTHOR("nanli.yd <nanli.yd@linux.alibaba.com>");
+MODULE_DESCRIPTION("Thead Light Fullmask audiosys clock gate provider");
+MODULE_LICENSE("GPL v2");

drivers/cpufreq/light-mpw-cpufreq.c

@@ -34,7 +34,7 @@ enum LIGHT_MPW_CPUFREQ_CLKS {
 };
 
 #define LIGHT_MPW_CPUFREQ_CLK_NUM	4
-#define LIGHT_CPUFREQ_THRE		1500000
+#define LIGHT_CPUFREQ_THRE		2000000
 #define LIGHT_C910_BUS_CLK_SYNC		BIT(11)
 #define LIGHT_C910_BUS_CLK_RATIO_MASK	0x700
 #define LIGHT_C910_BUS_CLK_DIV_RATIO_2	0x100

drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h

@@ -335,7 +335,7 @@ _ConvertLogical2Physical(
     OUT gctPHYS_ADDR_T * Physical
     );
 
-gctBOOL
+gceSTATUS
 _QuerySignal(
     IN gckOS Os,
     IN gctSIGNAL Signal

drivers/gpu/drm/Kconfig

@@ -394,6 +394,8 @@ source "drivers/gpu/drm/xlnx/Kconfig"
 
 source "drivers/gpu/drm/verisilicon/Kconfig"
 
+source "drivers/gpu/drm/img-rogue/Kconfig"
+
 # Keep legacy drivers last
 
 menuconfig DRM_LEGACY

drivers/gpu/drm/Makefile

@@ -57,6 +57,8 @@ drm_kms_helper-$(CONFIG_DRM_DP_CEC) += drm_dp_cec.o
 obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o
 obj-$(CONFIG_DRM_DEBUG_SELFTEST) += selftests/
 
+obj-$(CONFIG_DRM_POWERVR_ROGUE) += img-rogue/
+
 obj-$(CONFIG_DRM)	+= drm.o
 obj-$(CONFIG_DRM_MIPI_DBI) += drm_mipi_dbi.o
 obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

@@ -6,6 +6,7 @@
  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  */
+#include <linux/extcon-provider.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/err.h>
@@ -103,6 +104,11 @@ static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
 	{ 0x0000, 0x0000, 0x1b7c, 0x0020 }
 };
 
+static const unsigned int hdmi_extcon_cable[] = {
+	EXTCON_DISP_HDMI,
+	EXTCON_NONE,
+};
+
 struct hdmi_vmode {
 	bool mdataenablepolarity;
 
@@ -160,6 +166,7 @@ struct dw_hdmi {
 	struct clk *pix_clk;
 	struct clk *i2s_clk;
 	struct dw_hdmi_i2c *i2c;
+	struct extcon_dev *edev;
 
 	struct hdmi_data_info hdmi_data;
 	const struct dw_hdmi_plat_data *plat_data;
@@ -3117,6 +3124,10 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
 		dev_dbg(hdmi->dev, "EVENT=%s\n",
 			status == connector_status_connected ?
 			"plugin" : "plugout");
+		if (status == connector_status_connected)
+			extcon_set_state_sync(hdmi->edev, EXTCON_DISP_HDMI, true);
+		else
+			extcon_set_state_sync(hdmi->edev, EXTCON_DISP_HDMI, false);
 
 		if (hdmi->bridge.dev) {
 			drm_helper_hpd_irq_event(hdmi->bridge.dev);
@@ -3423,6 +3434,19 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
 
 	dw_hdmi_init_hw(hdmi);
 
+	hdmi->edev = devm_extcon_dev_allocate(dev, hdmi_extcon_cable);
+	if (IS_ERR(hdmi->edev)) {
+		dev_err(dev, "failed to allocate extcon device\n");
+		ret = -ENOMEM;
+		goto err_res;
+	}
+
+	ret = devm_extcon_dev_register(dev, hdmi->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to register extcon device\n");
+		goto err_res;
+	}
+
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
 		ret = irq;

drivers/gpu/drm/img-rogue/Kconfig

@@ -0,0 +1,24 @@
+config DRM_POWERVR_ROGUE
+	tristate "PowerVR Rogue"
+	depends on HAS_IOMEM
+	depends on DRM
+	select DRM_KMS_HELPER
+	select PM_DEVFREQ
+	select DEVFREQ_GOV_SIMPLE_ONDEMAND
+	select PM_OPP
+	select DEVFREQ_THERMAL
+	select SYNC_FILE
+	help
+	  Driver for PowerVR Rogue graphics hardware.
+
+	  Say Y here if your SoC contains a PowerVR Rogue GPU. For more
+	  information, see <http://www.imgtec.com/powervr/>.
+
+config DRM_POWERVR_ROGUE_DEBUG
+	bool "Enable PowerVR Rogue debug features"
+	depends on DRM_POWERVR_ROGUE
+	default n
+	help
+	  Add additional debug features to the PowerVR Rogue driver.
+	  To build a matching userspace, enable the following build options:
+	  BUILD=debug SUPPORT_PAGE_FAULT_DEBUG=1 PVRSRV_ENABLE_GPU_MEMORY_INFO=1

drivers/gpu/drm/img-rogue/Makefile

@@ -0,0 +1,19 @@
+img_basedir := drivers/gpu/drm/img-rogue
+include $(img_basedir)/config_kernel.mk
+
+obj-$(CONFIG_DRM_POWERVR_ROGUE) += pvrsrvkm.o
+
+ccflags-y += \
+ -include config_kernel.h \
+ -I$(img_basedir)/include/drm \
+ -I$(img_basedir) \
+ -I$(img_basedir)/include \
+ -I$(img_basedir)/km \
+ -I$(img_basedir)/system \
+ -D__linux__
+
+include $(img_basedir)/pvrsrvkm.mk
+
+obj-$(CONFIG_DRM_POWERVR_ROGUE)	+= drm_nulldisp.o
+
+drm_nulldisp-y	+= drm_nulldisp_drv.o drm_nulldisp_netlink.o drm_netlink_gem.o drm_nulldisp_gem.o

drivers/gpu/drm/img-rogue/allocmem.c

@@ -0,0 +1,422 @@
+/*************************************************************************/ /*!
+@File
+@Title          Host memory management implementation for Linux
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/ /**************************************************************************/
+
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/mm.h>
+#include <linux/string.h>
+
+#include "img_defs.h"
+#include "allocmem.h"
+#include "pvr_debug.h"
+#include "process_stats.h"
+#if defined(DEBUG) && defined(SUPPORT_VALIDATION)
+#include "pvrsrv.h"
+#endif
+#include "osfunc.h"
+
+
+/*
+ * When memory statistics are disabled, memory records are used instead.
+ * In order for these to work, the PID of the process that requested the
+ * allocation needs to be stored at the end of the kmalloc'd memory, making
+ * sure 4 extra bytes are allocated to fit the PID.
+ *
+ * There is no need for this extra allocation when memory statistics are
+ * enabled, since all allocations are tracked in DebugFS mem_area files.
+ */
+#if defined(PVRSRV_ENABLE_PROCESS_STATS) && !defined(PVRSRV_ENABLE_MEMORY_STATS)
+#define ALLOCMEM_MEMSTATS_PADDING sizeof(IMG_UINT32)
+#else
+#define ALLOCMEM_MEMSTATS_PADDING 0UL
+#endif
+
+/* How many times kmalloc can fail before the allocation threshold is reduced */
+static const IMG_UINT32 g_ui32kmallocFailLimit = 10;
+/* How many kmalloc failures happened since the last allocation threshold change */
+static IMG_UINT32 g_ui32kmallocFailCount = 0;
+/* Current kmalloc threshold value in bytes */
+static IMG_UINT32 g_ui32kmallocThreshold = PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD;
+/* Spinlock used so that the global variables above may not be modified by more than 1 thread at a time */
+static DEFINE_SPINLOCK(kmalloc_lock);
+
+#if defined(DEBUG) && defined(SUPPORT_VALIDATION)
+static DEFINE_SPINLOCK(kmalloc_leak_lock);
+static IMG_UINT32 g_ui32kmallocLeakCounter = 0;
+#endif
+
+static inline void OSTryDecreaseKmallocThreshold(void)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&kmalloc_lock, flags);
+
+	g_ui32kmallocFailCount++;
+
+	if (g_ui32kmallocFailCount >= g_ui32kmallocFailLimit)
+	{
+		g_ui32kmallocFailCount = 0;
+		if (g_ui32kmallocThreshold > PAGE_SIZE)
+		{
+			g_ui32kmallocThreshold >>= 1;
+			printk(KERN_INFO "Threshold is now set to %d\n", g_ui32kmallocThreshold);
+		}
+	}
+
+	spin_unlock_irqrestore(&kmalloc_lock, flags);
+}
+
+static inline void OSResetKmallocFailCount(void)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&kmalloc_lock, flags);
+
+	g_ui32kmallocFailCount = 0;
+
+	spin_unlock_irqrestore(&kmalloc_lock, flags);
+}
+
+static inline void _pvr_vfree(const void* pvAddr)
+{
+#if defined(DEBUG)
+	/* Size harder to come by for vmalloc and since vmalloc allocates
+	 * a whole number of pages, poison the minimum size known to have
+	 * been allocated.
+	 */
+	OSCachedMemSet((void*)pvAddr, PVRSRV_POISON_ON_ALLOC_VALUE,
+	               PAGE_SIZE);
+#endif
+	vfree(pvAddr);
+}
+
+static inline void _pvr_kfree(const void* pvAddr)
+{
+#if defined(DEBUG)
+	/* Poison whole memory block */
+	OSCachedMemSet((void*)pvAddr, PVRSRV_POISON_ON_ALLOC_VALUE,
+	               ksize(pvAddr));
+#endif
+	kfree(pvAddr);
+}
+
+static inline void _pvr_alloc_stats_add(void *pvAddr, IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS)
+{
+#if !defined(PVRSRV_ENABLE_PROCESS_STATS)
+	PVR_UNREFERENCED_PARAMETER(pvAddr);
+#else
+	if (!is_vmalloc_addr(pvAddr))
+	{
+#if defined(PVRSRV_ENABLE_MEMORY_STATS)
+		IMG_CPU_PHYADDR sCpuPAddr;
+		sCpuPAddr.uiAddr = 0;
+
+		PVRSRVStatsAddMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_KMALLOC,
+									  pvAddr,
+									  sCpuPAddr,
+									  ksize(pvAddr),
+									  NULL,
+									  OSGetCurrentClientProcessIDKM()
+									  DEBUG_MEMSTATS_ARGS);
+#else
+		{
+			/* Store the PID in the final additional 4 bytes allocated */
+			IMG_UINT32 *puiTemp = IMG_OFFSET_ADDR(pvAddr, ksize(pvAddr) - ALLOCMEM_MEMSTATS_PADDING);
+			*puiTemp = OSGetCurrentClientProcessIDKM();
+		}
+		PVRSRVStatsIncrMemAllocStat(PVRSRV_MEM_ALLOC_TYPE_KMALLOC, ksize(pvAddr), OSGetCurrentClientProcessIDKM());
+#endif /* defined(PVRSRV_ENABLE_MEMORY_STATS) */
+	}
+	else
+	{
+#if defined(PVRSRV_ENABLE_MEMORY_STATS)
+		IMG_CPU_PHYADDR sCpuPAddr;
+		sCpuPAddr.uiAddr = 0;
+
+		PVRSRVStatsAddMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_VMALLOC,
+									  pvAddr,
+									  sCpuPAddr,
+									  ((ui32Size + PAGE_SIZE-1) & ~(PAGE_SIZE-1)),
+									  NULL,
+									  OSGetCurrentClientProcessIDKM()
+									  DEBUG_MEMSTATS_ARGS);
+#else
+		PVRSRVStatsIncrMemAllocStatAndTrack(PVRSRV_MEM_ALLOC_TYPE_VMALLOC,
+		                                    ((ui32Size + PAGE_SIZE-1) & ~(PAGE_SIZE-1)),
+		                                    (IMG_UINT64)(uintptr_t) pvAddr,
+		                                    OSGetCurrentClientProcessIDKM());
+#endif /* defined(PVRSRV_ENABLE_MEMORY_STATS) */
+	}
+#endif /* !defined(PVRSRV_ENABLE_PROCESS_STATS) */
+}
+
+static inline void _pvr_alloc_stats_remove(void *pvAddr)
+{
+#if !defined(PVRSRV_ENABLE_PROCESS_STATS)
+	PVR_UNREFERENCED_PARAMETER(pvAddr);
+#else
+	if (!is_vmalloc_addr(pvAddr))
+	{
+#if !defined(PVRSRV_ENABLE_MEMORY_STATS)
+		{
+			IMG_UINT32 *puiTemp = IMG_OFFSET_ADDR(pvAddr, ksize(pvAddr) - ALLOCMEM_MEMSTATS_PADDING);
+			PVRSRVStatsDecrMemKAllocStat(ksize(pvAddr), *puiTemp);
+		}
+#else
+		PVRSRVStatsRemoveMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_KMALLOC,
+		                                (IMG_UINT64)(uintptr_t) pvAddr,
+		                                OSGetCurrentClientProcessIDKM());
+#endif
+	}
+	else
+	{
+#if !defined(PVRSRV_ENABLE_MEMORY_STATS)
+		PVRSRVStatsDecrMemAllocStatAndUntrack(PVRSRV_MEM_ALLOC_TYPE_VMALLOC,
+		                                      (IMG_UINT64)(uintptr_t) pvAddr);
+#else
+		PVRSRVStatsRemoveMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_VMALLOC,
+		                                (IMG_UINT64)(uintptr_t) pvAddr,
+		                                OSGetCurrentClientProcessIDKM());
+#endif
+	}
+#endif /* !defined(PVRSRV_ENABLE_PROCESS_STATS) */
+}
+
+void *(OSAllocMem)(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS)
+{
+	void *pvRet = NULL;
+
+	if ((ui32Size + ALLOCMEM_MEMSTATS_PADDING) <= g_ui32kmallocThreshold)
+	{
+		pvRet = kmalloc(ui32Size + ALLOCMEM_MEMSTATS_PADDING, GFP_KERNEL);
+		if (pvRet == NULL)
+		{
+			OSTryDecreaseKmallocThreshold();
+		}
+		else
+		{
+			OSResetKmallocFailCount();
+		}
+	}
+
+	if (pvRet == NULL)
+	{
+		pvRet = vmalloc(ui32Size);
+	}
+
+	if (pvRet != NULL)
+	{
+		_pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ARGS);
+	}
+
+	return pvRet;
+}
+
+void *(OSAllocZMem)(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS)
+{
+	void *pvRet = NULL;
+
+	if ((ui32Size + ALLOCMEM_MEMSTATS_PADDING) <= g_ui32kmallocThreshold)
+	{
+		pvRet = kzalloc(ui32Size + ALLOCMEM_MEMSTATS_PADDING, GFP_KERNEL);
+		if (pvRet == NULL)
+		{
+			OSTryDecreaseKmallocThreshold();
+		}
+		else
+		{
+			OSResetKmallocFailCount();
+		}
+	}
+
+	if (pvRet == NULL)
+	{
+		pvRet = vzalloc(ui32Size);
+	}
+
+	if (pvRet != NULL)
+	{
+		_pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ARGS);
+	}
+
+	return pvRet;
+}
+
+/*
+ * The parentheses around OSFreeMem prevent the macro in allocmem.h from
+ * applying, as it would break the function's definition.
+ */
+void (OSFreeMem)(void *pvMem)
+{
+#if defined(DEBUG) && defined(SUPPORT_VALIDATION)
+	unsigned long flags;
+	PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData();
+
+	if (psPVRSRVData)
+	{
+		IMG_UINT32 ui32kmallocLeakMax = psPVRSRVData->sMemLeakIntervals.ui32OSAlloc;
+
+		spin_lock_irqsave(&kmalloc_leak_lock, flags);
+
+		g_ui32kmallocLeakCounter++;
+		if (ui32kmallocLeakMax && (g_ui32kmallocLeakCounter >= ui32kmallocLeakMax))
+		{
+			g_ui32kmallocLeakCounter = 0;
+			spin_unlock_irqrestore(&kmalloc_leak_lock, flags);
+
+			PVR_DPF((PVR_DBG_WARNING,
+			         "%s: Skipped freeing of pointer 0x%p to trigger memory leak.",
+			         __func__,
+			         pvMem));
+			return;
+		}
+
+		spin_unlock_irqrestore(&kmalloc_leak_lock, flags);
+	}
+#endif
+	if (pvMem != NULL)
+	{
+		_pvr_alloc_stats_remove(pvMem);
+
+		if (!is_vmalloc_addr(pvMem))
+		{
+			_pvr_kfree(pvMem);
+		}
+		else
+		{
+			_pvr_vfree(pvMem);
+		}
+	}
+}
+
+void *OSAllocMemNoStats(IMG_UINT32 ui32Size)
+{
+	void *pvRet = NULL;
+
+	if (ui32Size <= g_ui32kmallocThreshold)
+	{
+		pvRet = kmalloc(ui32Size, GFP_KERNEL);
+		if (pvRet == NULL)
+		{
+			OSTryDecreaseKmallocThreshold();
+		}
+		else
+		{
+			OSResetKmallocFailCount();
+		}
+	}
+
+	if (pvRet == NULL)
+	{
+		pvRet = vmalloc(ui32Size);
+	}
+
+	return pvRet;
+}
+
+void *OSAllocZMemNoStats(IMG_UINT32 ui32Size)
+{
+	void *pvRet = NULL;
+
+	if (ui32Size <= g_ui32kmallocThreshold)
+	{
+		pvRet = kzalloc(ui32Size, GFP_KERNEL);
+		if (pvRet == NULL)
+		{
+			OSTryDecreaseKmallocThreshold();
+		}
+		else
+		{
+			OSResetKmallocFailCount();
+		}
+	}
+
+	if (pvRet == NULL)
+	{
+		pvRet = vzalloc(ui32Size);
+	}
+
+	return pvRet;
+}
+
+/*
+ * The parentheses around OSFreeMemNoStats prevent the macro in allocmem.h from
+ * applying, as it would break the function's definition.
+ */
+void (OSFreeMemNoStats)(void *pvMem)
+{
+#if defined(DEBUG) && defined(SUPPORT_VALIDATION)
+	unsigned long flags;
+	PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData();
+
+	if (psPVRSRVData)
+	{
+		IMG_UINT32 ui32kmallocLeakMax = psPVRSRVData->sMemLeakIntervals.ui32OSAlloc;
+
+		spin_lock_irqsave(&kmalloc_leak_lock, flags);
+
+		g_ui32kmallocLeakCounter++;
+		if (ui32kmallocLeakMax && (g_ui32kmallocLeakCounter >= ui32kmallocLeakMax))
+		{
+			g_ui32kmallocLeakCounter = 0;
+			spin_unlock_irqrestore(&kmalloc_leak_lock, flags);
+
+			PVR_DPF((PVR_DBG_WARNING,
+			         "%s: Skipped freeing of pointer 0x%p to trigger memory leak.",
+			         __func__,
+			         pvMem));
+			return;
+		}
+
+		spin_unlock_irqrestore(&kmalloc_leak_lock, flags);
+	}
+#endif
+	if (pvMem != NULL)
+	{
+		if (!is_vmalloc_addr(pvMem))
+		{
+			_pvr_kfree(pvMem);
+		}
+		else
+		{
+			_pvr_vfree(pvMem);
+		}
+	}
+}

drivers/gpu/drm/img-rogue/allocmem.h

@@ -0,0 +1,224 @@
+/*************************************************************************/ /*!
+@File           allocmem.h
+@Title          memory allocation header
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Memory-Allocation API definitions
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/ /**************************************************************************/
+
+#ifndef ALLOCMEM_H
+#define ALLOCMEM_H
+
+#include "img_types.h"
+#include "pvr_debug.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*
+ * PVRSRV_ENABLE_PROCESS_STATS enables process statistics regarding events,
+ *     resources and memory across all processes
+ * PVRSRV_ENABLE_MEMORY_STATS enables recording of Linux kernel memory
+ *     allocations, provided that PVRSRV_ENABLE_PROCESS_STATS is enabled
+ *   - Output can be found in:
+ *     /(sys/kernel/debug|proc)/pvr/proc_stats/[live|retired]_pids_stats/mem_area
+ * PVRSRV_DEBUG_LINUX_MEMORY_STATS provides more details about memory
+ *     statistics in conjunction with PVRSRV_ENABLE_MEMORY_STATS
+ * PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON is defined to encompass both memory
+ *     allocation statistics functionalities described above in a single macro
+ */
+#if defined(PVRSRV_ENABLE_PROCESS_STATS) && defined(PVRSRV_ENABLE_MEMORY_STATS) && defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS) && defined(DEBUG)
+#define PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
+#endif
+
+/*
+ * When using detailed memory allocation statistics, the line number and
+ * file name where the allocation happened are also provided.
+ * When this feature is not used, these parameters are not needed.
+ */
+#if defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON)
+#define DEBUG_MEMSTATS_PARAMS ,void *pvAllocFromFile, IMG_UINT32 ui32AllocFromLine
+#define DEBUG_MEMSTATS_ARGS   ,pvAllocFromFile, ui32AllocFromLine
+#define DEBUG_MEMSTATS_UNREF  (void)pvAllocFromFile; (void)ui32AllocFromLine;
+#define DEBUG_MEMSTATS_VALUES ,__FILE__, __LINE__
+#else
+#define DEBUG_MEMSTATS_PARAMS /*!<
+                                 * Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
+                                 * build option. */
+#define DEBUG_MEMSTATS_ARGS   /*!<
+                                 * Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
+                                 * build option. */
+#define DEBUG_MEMSTATS_UNREF  /*!<
+                                 * Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
+                                 * build option. */
+#define DEBUG_MEMSTATS_VALUES  /*!<
+                                 * Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
+                                 * build option. */
+#endif
+
+
+/**************************************************************************/ /*!
+@Function       OSAllocMem
+@Description    Allocates CPU memory. Contents are uninitialized.
+                If passed a size of zero, function should not assert,
+                but just return a NULL pointer.
+@Input          ui32Size        Size of required allocation (in bytes)
+@Return         Pointer to allocated memory on success.
+                Otherwise NULL.
+ */ /**************************************************************************/
+#if defined(DOXYGEN)
+void *OSAllocMem(IMG_UINT32 ui32Size);
+#else
+void *OSAllocMem(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS);
+#define OSAllocMem(_size)	(OSAllocMem)((_size) DEBUG_MEMSTATS_VALUES)
+#endif
+
+/**************************************************************************/ /*!
+@Function       OSAllocZMem
+@Description    Allocates CPU memory and initializes the contents to zero.
+                If passed a size of zero, function should not assert,
+                but just return a NULL pointer.
+@Input          ui32Size        Size of required allocation (in bytes)
+@Return         Pointer to allocated memory on success.
+                Otherwise NULL.
+ */ /**************************************************************************/
+#if defined(DOXYGEN)
+void *OSAllocZMem(IMG_UINT32 ui32Size);
+#else
+void *OSAllocZMem(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS);
+#define OSAllocZMem(_size)	(OSAllocZMem)((_size) DEBUG_MEMSTATS_VALUES)
+#endif
+
+
+/**************************************************************************/ /*!
+@Function       OSAllocMemNoStats
+@Description    Allocates CPU memory. Contents are uninitialized.
+                 If passed a size of zero, function should not assert,
+                 but just return a NULL pointer.
+                 The allocated memory is not accounted for by process stats.
+                 Process stats are an optional feature (enabled only when
+                 PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount
+                 of memory allocated to help in debugging. Where this is not
+                 required, OSAllocMem() and OSAllocMemNoStats() equate to
+                 the same operation.
+@Input          ui32Size        Size of required allocation (in bytes)
+@Return         Pointer to allocated memory on success.
+                Otherwise NULL.
+ */ /**************************************************************************/
+void *OSAllocMemNoStats(IMG_UINT32 ui32Size);
+
+/**************************************************************************/ /*!
+@Function       OSAllocZMemNoStats
+@Description    Allocates CPU memory and initializes the contents to zero.
+                 If passed a size of zero, function should not assert,
+                 but just return a NULL pointer.
+                 The allocated memory is not accounted for by process stats.
+                 Process stats are an optional feature (enabled only when
+                 PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount
+                 of memory allocated to help in debugging. Where this is not
+                 required, OSAllocZMem() and OSAllocZMemNoStats() equate to
+                 the same operation.
+@Input          ui32Size        Size of required allocation (in bytes)
+@Return         Pointer to allocated memory on success.
+                Otherwise NULL.
+ */ /**************************************************************************/
+void *OSAllocZMemNoStats(IMG_UINT32 ui32Size);
+
+/**************************************************************************/ /*!
+@Function       OSFreeMem
+@Description    Frees previously allocated CPU memory.
+@Input          pvCpuVAddr       Pointer to the memory to be freed.
+@Return         None.
+ */ /**************************************************************************/
+void OSFreeMem(void *pvCpuVAddr);
+
+/**************************************************************************/ /*!
+@Function       OSFreeMemNoStats
+@Description    Frees previously allocated CPU memory.
+                 The freed memory does not update the figures in process stats.
+                 Process stats are an optional feature (enabled only when
+                 PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount
+                 of memory allocated to help in debugging. Where this is not
+                 required, OSFreeMem() and OSFreeMemNoStats() equate to the
+                 same operation.
+@Input          pvCpuVAddr       Pointer to the memory to be freed.
+@Return         None.
+ */ /**************************************************************************/
+void OSFreeMemNoStats(void *pvCpuVAddr);
+
+/*
+ * These macros allow us to catch double-free bugs on DEBUG builds and
+ * prevent crashes on RELEASE builds.
+ */
+
+/*! @cond Doxygen_Suppress */
+#if defined(DEBUG)
+#define double_free_sentinel ((void *)&OSFreeMem)
+#define ALLOCMEM_ASSERT(exp) PVR_ASSERT(exp)
+#else
+#define double_free_sentinel NULL
+#define ALLOCMEM_ASSERT(exp) do {} while (0)
+#endif
+/*! @endcond */
+
+/*! Frees memory allocated by OSAllocMem(). */
+#define OSFreeMem(_ptr) do { \
+		ALLOCMEM_ASSERT((_ptr) != double_free_sentinel); \
+		(OSFreeMem)(_ptr); \
+		(_ptr) = double_free_sentinel; \
+		MSC_SUPPRESS_4127 \
+	} while (0)
+
+/*! Frees memory allocated by OSAllocMemNoStats(). */
+#define OSFreeMemNoStats(_ptr) do { \
+		ALLOCMEM_ASSERT((_ptr) != double_free_sentinel); \
+		(OSFreeMemNoStats)(_ptr); \
+		(_ptr) = double_free_sentinel; \
+		MSC_SUPPRESS_4127 \
+	} while (0)
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* ALLOCMEM_H */
+
+/******************************************************************************
+ End of file (allocmem.h)
+******************************************************************************/

drivers/gpu/drm/img-rogue/cache_km.h

@@ -0,0 +1,151 @@
+/*************************************************************************/ /*!
+@File           cache_km.h
+@Title          CPU cache management header
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/ /**************************************************************************/
+
+#ifndef CACHE_KM_H
+#define CACHE_KM_H
+
+#if defined(__linux__)
+#include <linux/version.h>
+#else
+#define KERNEL_VERSION
+#endif
+
+#include "pvrsrv_error.h"
+#include "os_cpu_cache.h"
+#include "img_types.h"
+#include "cache_ops.h"
+#include "device.h"
+#include "pmr.h"
+
+typedef IMG_UINT32 PVRSRV_CACHE_OP_ADDR_TYPE;	/*!< Represents CPU address type required for CPU d-cache maintenance */
+#define PVRSRV_CACHE_OP_ADDR_TYPE_VIRTUAL	0x1	/*!< Operation requires CPU virtual address only */
+#define PVRSRV_CACHE_OP_ADDR_TYPE_PHYSICAL	0x2	/*!< Operation requires CPU physical address only */
+#define PVRSRV_CACHE_OP_ADDR_TYPE_BOTH		0x3	/*!< Operation requires both CPU virtual & physical addresses */
+
+#include "connection_server.h"
+
+/*
+ * CacheOpInit() & CacheOpDeInit()
+ *
+ * This must be called to initialise the KM cache maintenance framework.
+ * This is called early during the driver/module (un)loading phase.
+ */
+PVRSRV_ERROR CacheOpInit(void);
+void CacheOpDeInit(void);
+
+/*
+ * CacheOpInit2() & CacheOpDeInit2()
+ *
+ * This must be called to initialise the UM cache maintenance framework.
+ * This is called when the driver is loaded/unloaded from the kernel.
+ */
+PVRSRV_ERROR CacheOpInit2(void);
+void CacheOpDeInit2(void);
+
+/*
+ * CacheOpExec()
+ *
+ * This is the primary CPU data-cache maintenance interface and it is
+ * always guaranteed to be synchronous; the arguments supplied must be
+ * pre-validated for performance reasons else the d-cache maintenance
+ * operation might cause the underlying OS kernel to fault.
+ */
+PVRSRV_ERROR CacheOpExec(PPVRSRV_DEVICE_NODE psDevNode,
+						void *pvVirtStart,
+						void *pvVirtEnd,
+						IMG_CPU_PHYADDR sCPUPhysStart,
+						IMG_CPU_PHYADDR sCPUPhysEnd,
+						PVRSRV_CACHE_OP uiCacheOp);
+
+/*
+ * CacheOpValExec()
+ *
+ * Same as CacheOpExec(), except arguments are _Validated_ before being
+ * presented to the underlying OS kernel for CPU data-cache maintenance.
+ * The uiAddress is the start CPU virtual address for the to-be d-cache
+ * maintained PMR, it can be NULL in which case a remap will be performed
+ * internally, if required for cache maintenance. This is primarily used
+ * as the services client bridge call handler for synchronous user-mode
+ * cache maintenance requests.
+ */
+PVRSRV_ERROR CacheOpValExec(PMR *psPMR,
+							IMG_UINT64 uiAddress,
+							IMG_DEVMEM_OFFSET_T uiOffset,
+							IMG_DEVMEM_SIZE_T uiSize,
+							PVRSRV_CACHE_OP uiCacheOp);
+
+/*
+ * CacheOpQueue()
+ *
+ * This is the secondary cache maintenance interface and it is not
+ * guaranteed to be synchronous in that requests could be deferred
+ * and executed asynchronously. This interface is primarily meant
+ * as services client bridge call handler. Both uiInfoPgGFSeqNum
+ * and ui32[Current,Next]FenceSeqNum implements an internal client
+ * server queueing protocol so making use of this interface outside
+ * of services client is not recommended and should not be done.
+ */
+PVRSRV_ERROR CacheOpQueue(CONNECTION_DATA *psConnection,
+						PPVRSRV_DEVICE_NODE psDevNode,
+						IMG_UINT32 ui32OpCount,
+						PMR **ppsPMR,
+						IMG_UINT64 *puiAddress,
+						IMG_DEVMEM_OFFSET_T *puiOffset,
+						IMG_DEVMEM_SIZE_T *puiSize,
+						PVRSRV_CACHE_OP *puiCacheOp,
+						IMG_UINT32 ui32OpTimeline);
+
+/*
+ * CacheOpLog()
+ *
+ * This is used for logging client cache maintenance operations that
+ * was executed in user-space.
+ */
+PVRSRV_ERROR CacheOpLog(PMR *psPMR,
+						IMG_UINT64 uiAddress,
+						IMG_DEVMEM_OFFSET_T uiOffset,
+						IMG_DEVMEM_SIZE_T uiSize,
+						IMG_UINT64 ui64StartTime,
+						IMG_UINT64 ui64EndTime,
+						PVRSRV_CACHE_OP uiCacheOp);
+
+#endif	/* CACHE_KM_H */

drivers/gpu/drm/img-rogue/cache_ops.h

@@ -0,0 +1,61 @@
+/*************************************************************************/ /*!
+@File
+@Title          Services cache management header
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Defines for cache management which are visible internally
+                and externally
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/ /**************************************************************************/
+
+#ifndef CACHE_OPS_H
+#define CACHE_OPS_H
+#include "img_types.h"
+/*!
+* @Defgroup CPUCacheAPIs
+* @{
+*/
+#define CACHE_BATCH_MAX (8U)
+#define MAX_DMA_OPS (34)
+typedef IMG_UINT32 PVRSRV_CACHE_OP;				/*!< Type represents cache maintenance operation */
+#define PVRSRV_CACHE_OP_NONE				0x0U	/*!< No operation */
+#define PVRSRV_CACHE_OP_CLEAN				0x1U	/*!< Flush w/o invalidate */
+#define PVRSRV_CACHE_OP_INVALIDATE			0x2U	/*!< Invalidate w/o flush */
+#define PVRSRV_CACHE_OP_FLUSH				0x3U	/*!< Flush w/ invalidate */
+/*! @} End of Defgroup CPUCacheAPIs */
+
+#endif	/* CACHE_OPS_H */

drivers/gpu/drm/img-rogue/client_cache_bridge.h

@@ -0,0 +1,80 @@
+/*******************************************************************************
+@File
+@Title          Client bridge header for cache
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Exports the client bridge functions for cache
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef CLIENT_CACHE_BRIDGE_H
+#define CLIENT_CACHE_BRIDGE_H
+
+#include "img_defs.h"
+#include "pvrsrv_error.h"
+
+#if defined(PVR_INDIRECT_BRIDGE_CLIENTS)
+#include "pvr_bridge_client.h"
+#include "pvr_bridge.h"
+#endif
+
+#include "common_cache_bridge.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpQueue(IMG_HANDLE hBridge,
+					     IMG_UINT32 ui32NumCacheOps,
+					     IMG_HANDLE * phPMR,
+					     IMG_UINT64 * pui64Address,
+					     IMG_DEVMEM_OFFSET_T * puiOffset,
+					     IMG_DEVMEM_SIZE_T * puiSize,
+					     PVRSRV_CACHE_OP * piuCacheOp,
+					     IMG_UINT32 ui32OpTimeline);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpExec(IMG_HANDLE hBridge,
+					    IMG_HANDLE hPMR,
+					    IMG_UINT64 ui64Address,
+					    IMG_DEVMEM_OFFSET_T uiOffset,
+					    IMG_DEVMEM_SIZE_T uiSize, PVRSRV_CACHE_OP iuCacheOp);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpLog(IMG_HANDLE hBridge,
+					   IMG_HANDLE hPMR,
+					   IMG_UINT64 ui64Address,
+					   IMG_DEVMEM_OFFSET_T uiOffset,
+					   IMG_DEVMEM_SIZE_T uiSize,
+					   IMG_INT64 i64StartTime,
+					   IMG_INT64 i64EndTime, PVRSRV_CACHE_OP iuCacheOp);
+
+#endif /* CLIENT_CACHE_BRIDGE_H */

drivers/gpu/drm/img-rogue/client_cache_direct_bridge.c

@@ -0,0 +1,112 @@
+/*******************************************************************************
+@File
+@Title          Direct client bridge for cache
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Implements the client side of the bridge for cache
+                which is used in calls from Server context.
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#include "client_cache_bridge.h"
+#include "img_defs.h"
+#include "pvr_debug.h"
+
+/* Module specific includes */
+#include "cache_ops.h"
+
+#include "cache_km.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpQueue(IMG_HANDLE hBridge,
+					     IMG_UINT32 ui32NumCacheOps,
+					     IMG_HANDLE * phPMR,
+					     IMG_UINT64 * pui64Address,
+					     IMG_DEVMEM_OFFSET_T * puiOffset,
+					     IMG_DEVMEM_SIZE_T * puiSize,
+					     PVRSRV_CACHE_OP * piuCacheOp,
+					     IMG_UINT32 ui32OpTimeline)
+{
+	PVRSRV_ERROR eError;
+	PMR **psPMRInt;
+
+	psPMRInt = (PMR **) phPMR;
+
+	eError =
+	    CacheOpQueue(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+			 ui32NumCacheOps,
+			 psPMRInt, pui64Address, puiOffset, puiSize, piuCacheOp, ui32OpTimeline);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpExec(IMG_HANDLE hBridge,
+					    IMG_HANDLE hPMR,
+					    IMG_UINT64 ui64Address,
+					    IMG_DEVMEM_OFFSET_T uiOffset,
+					    IMG_DEVMEM_SIZE_T uiSize, PVRSRV_CACHE_OP iuCacheOp)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError = CacheOpValExec(psPMRInt, ui64Address, uiOffset, uiSize, iuCacheOp);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpLog(IMG_HANDLE hBridge,
+					   IMG_HANDLE hPMR,
+					   IMG_UINT64 ui64Address,
+					   IMG_DEVMEM_OFFSET_T uiOffset,
+					   IMG_DEVMEM_SIZE_T uiSize,
+					   IMG_INT64 i64StartTime,
+					   IMG_INT64 i64EndTime, PVRSRV_CACHE_OP iuCacheOp)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError =
+	    CacheOpLog(psPMRInt,
+		       ui64Address, uiOffset, uiSize, i64StartTime, i64EndTime, iuCacheOp);
+
+	return eError;
+}

drivers/gpu/drm/img-rogue/client_devicememhistory_bridge.h

@@ -0,0 +1,111 @@
+/*******************************************************************************
+@File
+@Title          Client bridge header for devicememhistory
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Exports the client bridge functions for devicememhistory
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef CLIENT_DEVICEMEMHISTORY_BRIDGE_H
+#define CLIENT_DEVICEMEMHISTORY_BRIDGE_H
+
+#include "img_defs.h"
+#include "pvrsrv_error.h"
+
+#if defined(PVR_INDIRECT_BRIDGE_CLIENTS)
+#include "pvr_bridge_client.h"
+#include "pvr_bridge.h"
+#endif
+
+#include "common_devicememhistory_bridge.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistoryMap(IMG_HANDLE hBridge,
+						    IMG_HANDLE hPMR,
+						    IMG_DEVMEM_SIZE_T uiOffset,
+						    IMG_DEV_VIRTADDR sDevVAddr,
+						    IMG_DEVMEM_SIZE_T uiSize,
+						    const IMG_CHAR * puiText,
+						    IMG_UINT32 ui32Log2PageSize,
+						    IMG_UINT32 ui32AllocationIndex,
+						    IMG_UINT32 * pui32AllocationIndexOut);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistoryUnmap(IMG_HANDLE hBridge,
+						      IMG_HANDLE hPMR,
+						      IMG_DEVMEM_SIZE_T uiOffset,
+						      IMG_DEV_VIRTADDR sDevVAddr,
+						      IMG_DEVMEM_SIZE_T uiSize,
+						      const IMG_CHAR * puiText,
+						      IMG_UINT32 ui32Log2PageSize,
+						      IMG_UINT32 ui32AllocationIndex,
+						      IMG_UINT32 * pui32AllocationIndexOut);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistoryMapVRange(IMG_HANDLE hBridge,
+							  IMG_DEV_VIRTADDR sBaseDevVAddr,
+							  IMG_UINT32 ui32ui32StartPage,
+							  IMG_UINT32 ui32NumPages,
+							  IMG_DEVMEM_SIZE_T uiAllocSize,
+							  const IMG_CHAR * puiText,
+							  IMG_UINT32 ui32Log2PageSize,
+							  IMG_UINT32 ui32AllocationIndex,
+							  IMG_UINT32 * pui32AllocationIndexOut);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistoryUnmapVRange(IMG_HANDLE hBridge,
+							    IMG_DEV_VIRTADDR sBaseDevVAddr,
+							    IMG_UINT32 ui32ui32StartPage,
+							    IMG_UINT32 ui32NumPages,
+							    IMG_DEVMEM_SIZE_T uiAllocSize,
+							    const IMG_CHAR * puiText,
+							    IMG_UINT32 ui32Log2PageSize,
+							    IMG_UINT32 ui32AllocationIndex,
+							    IMG_UINT32 * pui32AllocationIndexOut);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistorySparseChange(IMG_HANDLE hBridge,
+							     IMG_HANDLE hPMR,
+							     IMG_DEVMEM_SIZE_T uiOffset,
+							     IMG_DEV_VIRTADDR sDevVAddr,
+							     IMG_DEVMEM_SIZE_T uiSize,
+							     const IMG_CHAR * puiText,
+							     IMG_UINT32 ui32Log2PageSize,
+							     IMG_UINT32 ui32AllocPageCount,
+							     IMG_UINT32 * pui32AllocPageIndices,
+							     IMG_UINT32 ui32FreePageCount,
+							     IMG_UINT32 * pui32FreePageIndices,
+							     IMG_UINT32 ui32AllocationIndex,
+							     IMG_UINT32 * pui32AllocationIndexOut);
+
+#endif /* CLIENT_DEVICEMEMHISTORY_BRIDGE_H */

drivers/gpu/drm/img-rogue/client_devicememhistory_direct_bridge.c

@@ -0,0 +1,194 @@
+/*******************************************************************************
+@File
+@Title          Direct client bridge for devicememhistory
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Implements the client side of the bridge for devicememhistory
+                which is used in calls from Server context.
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#include "client_devicememhistory_bridge.h"
+#include "img_defs.h"
+#include "pvr_debug.h"
+
+/* Module specific includes */
+#include "img_types.h"
+#include "img_defs.h"
+#include "devicemem_typedefs.h"
+
+#include "devicemem_history_server.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistoryMap(IMG_HANDLE hBridge,
+						    IMG_HANDLE hPMR,
+						    IMG_DEVMEM_SIZE_T uiOffset,
+						    IMG_DEV_VIRTADDR sDevVAddr,
+						    IMG_DEVMEM_SIZE_T uiSize,
+						    const IMG_CHAR * puiText,
+						    IMG_UINT32 ui32Log2PageSize,
+						    IMG_UINT32 ui32AllocationIndex,
+						    IMG_UINT32 * pui32AllocationIndexOut)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError =
+	    DevicememHistoryMapKM(psPMRInt,
+				  uiOffset,
+				  sDevVAddr,
+				  uiSize,
+				  puiText,
+				  ui32Log2PageSize, ui32AllocationIndex, pui32AllocationIndexOut);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistoryUnmap(IMG_HANDLE hBridge,
+						      IMG_HANDLE hPMR,
+						      IMG_DEVMEM_SIZE_T uiOffset,
+						      IMG_DEV_VIRTADDR sDevVAddr,
+						      IMG_DEVMEM_SIZE_T uiSize,
+						      const IMG_CHAR * puiText,
+						      IMG_UINT32 ui32Log2PageSize,
+						      IMG_UINT32 ui32AllocationIndex,
+						      IMG_UINT32 * pui32AllocationIndexOut)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError =
+	    DevicememHistoryUnmapKM(psPMRInt,
+				    uiOffset,
+				    sDevVAddr,
+				    uiSize,
+				    puiText,
+				    ui32Log2PageSize, ui32AllocationIndex, pui32AllocationIndexOut);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistoryMapVRange(IMG_HANDLE hBridge,
+							  IMG_DEV_VIRTADDR sBaseDevVAddr,
+							  IMG_UINT32 ui32ui32StartPage,
+							  IMG_UINT32 ui32NumPages,
+							  IMG_DEVMEM_SIZE_T uiAllocSize,
+							  const IMG_CHAR * puiText,
+							  IMG_UINT32 ui32Log2PageSize,
+							  IMG_UINT32 ui32AllocationIndex,
+							  IMG_UINT32 * pui32AllocationIndexOut)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    DevicememHistoryMapVRangeKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+					sBaseDevVAddr,
+					ui32ui32StartPage,
+					ui32NumPages,
+					uiAllocSize,
+					puiText,
+					ui32Log2PageSize,
+					ui32AllocationIndex, pui32AllocationIndexOut);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistoryUnmapVRange(IMG_HANDLE hBridge,
+							    IMG_DEV_VIRTADDR sBaseDevVAddr,
+							    IMG_UINT32 ui32ui32StartPage,
+							    IMG_UINT32 ui32NumPages,
+							    IMG_DEVMEM_SIZE_T uiAllocSize,
+							    const IMG_CHAR * puiText,
+							    IMG_UINT32 ui32Log2PageSize,
+							    IMG_UINT32 ui32AllocationIndex,
+							    IMG_UINT32 * pui32AllocationIndexOut)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    DevicememHistoryUnmapVRangeKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+					  sBaseDevVAddr,
+					  ui32ui32StartPage,
+					  ui32NumPages,
+					  uiAllocSize,
+					  puiText,
+					  ui32Log2PageSize,
+					  ui32AllocationIndex, pui32AllocationIndexOut);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevicememHistorySparseChange(IMG_HANDLE hBridge,
+							     IMG_HANDLE hPMR,
+							     IMG_DEVMEM_SIZE_T uiOffset,
+							     IMG_DEV_VIRTADDR sDevVAddr,
+							     IMG_DEVMEM_SIZE_T uiSize,
+							     const IMG_CHAR * puiText,
+							     IMG_UINT32 ui32Log2PageSize,
+							     IMG_UINT32 ui32AllocPageCount,
+							     IMG_UINT32 * pui32AllocPageIndices,
+							     IMG_UINT32 ui32FreePageCount,
+							     IMG_UINT32 * pui32FreePageIndices,
+							     IMG_UINT32 ui32AllocationIndex,
+							     IMG_UINT32 * pui32AllocationIndexOut)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError =
+	    DevicememHistorySparseChangeKM(psPMRInt,
+					   uiOffset,
+					   sDevVAddr,
+					   uiSize,
+					   puiText,
+					   ui32Log2PageSize,
+					   ui32AllocPageCount,
+					   pui32AllocPageIndices,
+					   ui32FreePageCount,
+					   pui32FreePageIndices,
+					   ui32AllocationIndex, pui32AllocationIndexOut);
+
+	return eError;
+}

drivers/gpu/drm/img-rogue/client_htbuffer_bridge.h

@@ -0,0 +1,71 @@
+/*******************************************************************************
+@File
+@Title          Client bridge header for htbuffer
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Exports the client bridge functions for htbuffer
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef CLIENT_HTBUFFER_BRIDGE_H
+#define CLIENT_HTBUFFER_BRIDGE_H
+
+#include "img_defs.h"
+#include "pvrsrv_error.h"
+
+#if defined(PVR_INDIRECT_BRIDGE_CLIENTS)
+#include "pvr_bridge_client.h"
+#include "pvr_bridge.h"
+#endif
+
+#include "common_htbuffer_bridge.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHTBControl(IMG_HANDLE hBridge,
+					   IMG_UINT32 ui32NumGroups,
+					   IMG_UINT32 * pui32GroupEnable,
+					   IMG_UINT32 ui32LogLevel,
+					   IMG_UINT32 ui32EnablePID,
+					   IMG_UINT32 ui32LogMode, IMG_UINT32 ui32OpMode);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHTBLog(IMG_HANDLE hBridge,
+				       IMG_UINT32 ui32PID,
+				       IMG_UINT32 ui32TID,
+				       IMG_UINT64 ui64TimeStamp,
+				       IMG_UINT32 ui32SF,
+				       IMG_UINT32 ui32NumArgs, IMG_UINT32 * pui32Args);
+
+#endif /* CLIENT_HTBUFFER_BRIDGE_H */

drivers/gpu/drm/img-rogue/client_htbuffer_direct_bridge.c

@@ -0,0 +1,85 @@
+/*******************************************************************************
+@File
+@Title          Direct client bridge for htbuffer
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Implements the client side of the bridge for htbuffer
+                which is used in calls from Server context.
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#include "client_htbuffer_bridge.h"
+#include "img_defs.h"
+#include "pvr_debug.h"
+
+/* Module specific includes */
+#include "devicemem_typedefs.h"
+#include "htbuffer_types.h"
+
+#include "htbserver.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHTBControl(IMG_HANDLE hBridge,
+					   IMG_UINT32 ui32NumGroups,
+					   IMG_UINT32 * pui32GroupEnable,
+					   IMG_UINT32 ui32LogLevel,
+					   IMG_UINT32 ui32EnablePID,
+					   IMG_UINT32 ui32LogMode, IMG_UINT32 ui32OpMode)
+{
+	PVRSRV_ERROR eError;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	eError =
+	    HTBControlKM(ui32NumGroups,
+			 pui32GroupEnable, ui32LogLevel, ui32EnablePID, ui32LogMode, ui32OpMode);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHTBLog(IMG_HANDLE hBridge,
+				       IMG_UINT32 ui32PID,
+				       IMG_UINT32 ui32TID,
+				       IMG_UINT64 ui64TimeStamp,
+				       IMG_UINT32 ui32SF,
+				       IMG_UINT32 ui32NumArgs, IMG_UINT32 * pui32Args)
+{
+	PVRSRV_ERROR eError;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	eError = HTBLogKM(ui32PID, ui32TID, ui64TimeStamp, ui32SF, ui32NumArgs, pui32Args);
+
+	return eError;
+}

drivers/gpu/drm/img-rogue/client_mm_bridge.h

@@ -0,0 +1,265 @@
+/*******************************************************************************
+@File
+@Title          Client bridge header for mm
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Exports the client bridge functions for mm
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef CLIENT_MM_BRIDGE_H
+#define CLIENT_MM_BRIDGE_H
+
+#include "img_defs.h"
+#include "pvrsrv_error.h"
+
+#if defined(PVR_INDIRECT_BRIDGE_CLIENTS)
+#include "pvr_bridge_client.h"
+#include "pvr_bridge.h"
+#endif
+
+#include "common_mm_bridge.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRExportPMR(IMG_HANDLE hBridge,
+					     IMG_HANDLE hPMR,
+					     IMG_HANDLE * phPMRExport,
+					     IMG_UINT64 * pui64Size,
+					     IMG_UINT32 * pui32Log2Contig,
+					     IMG_UINT64 * pui64Password);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRUnexportPMR(IMG_HANDLE hBridge, IMG_HANDLE hPMRExport);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRGetUID(IMG_HANDLE hBridge,
+					  IMG_HANDLE hPMR, IMG_UINT64 * pui64UID);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRMakeLocalImportHandle(IMG_HANDLE hBridge,
+							 IMG_HANDLE hBuffer, IMG_HANDLE * phExtMem);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRUnmakeLocalImportHandle(IMG_HANDLE hBridge, IMG_HANDLE hExtMem);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRImportPMR(IMG_HANDLE hBridge,
+					     IMG_HANDLE hPMRExport,
+					     IMG_UINT64 ui64uiPassword,
+					     IMG_UINT64 ui64uiSize,
+					     IMG_UINT32 ui32uiLog2Contig, IMG_HANDLE * phPMR);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRLocalImportPMR(IMG_HANDLE hBridge,
+						  IMG_HANDLE hExtHandle,
+						  IMG_HANDLE * phPMR,
+						  IMG_DEVMEM_SIZE_T * puiSize,
+						  IMG_DEVMEM_ALIGN_T * puiAlign);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRUnrefPMR(IMG_HANDLE hBridge, IMG_HANDLE hPMR);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRUnrefUnlockPMR(IMG_HANDLE hBridge, IMG_HANDLE hPMR);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePhysmemNewRamBackedPMR(IMG_HANDLE hBridge,
+						       IMG_DEVMEM_SIZE_T uiSize,
+						       IMG_DEVMEM_SIZE_T uiChunkSize,
+						       IMG_UINT32 ui32NumPhysChunks,
+						       IMG_UINT32 ui32NumVirtChunks,
+						       IMG_UINT32 * pui32MappingTable,
+						       IMG_UINT32 ui32Log2PageSize,
+						       PVRSRV_MEMALLOCFLAGS_T uiFlags,
+						       IMG_UINT32 ui32AnnotationLength,
+						       const IMG_CHAR * puiAnnotation,
+						       IMG_PID ui32PID,
+						       IMG_HANDLE * phPMRPtr,
+						       IMG_UINT32 ui32PDumpFlags,
+						       PVRSRV_MEMALLOCFLAGS_T * puiOutFlags);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePhysmemNewRamBackedLockedPMR(IMG_HANDLE hBridge,
+							     IMG_DEVMEM_SIZE_T uiSize,
+							     IMG_DEVMEM_SIZE_T uiChunkSize,
+							     IMG_UINT32 ui32NumPhysChunks,
+							     IMG_UINT32 ui32NumVirtChunks,
+							     IMG_UINT32 * pui32MappingTable,
+							     IMG_UINT32 ui32Log2PageSize,
+							     PVRSRV_MEMALLOCFLAGS_T uiFlags,
+							     IMG_UINT32 ui32AnnotationLength,
+							     const IMG_CHAR * puiAnnotation,
+							     IMG_PID ui32PID,
+							     IMG_HANDLE * phPMRPtr,
+							     IMG_UINT32 ui32PDumpFlags,
+							     PVRSRV_MEMALLOCFLAGS_T * puiOutFlags);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntPin(IMG_HANDLE hBridge, IMG_HANDLE hPMR);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnpin(IMG_HANDLE hBridge, IMG_HANDLE hPMR);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntPinValidate(IMG_HANDLE hBridge,
+						     IMG_HANDLE hMapping, IMG_HANDLE hPMR);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnpinInvalidate(IMG_HANDLE hBridge,
+							 IMG_HANDLE hMapping, IMG_HANDLE hPMR);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntCtxCreate(IMG_HANDLE hBridge,
+						   IMG_BOOL bbKernelMemoryCtx,
+						   IMG_HANDLE * phDevMemServerContext,
+						   IMG_HANDLE * phPrivData,
+						   IMG_UINT32 * pui32CPUCacheLineSize);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntCtxDestroy(IMG_HANDLE hBridge,
+						    IMG_HANDLE hDevmemServerContext);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntHeapCreate(IMG_HANDLE hBridge,
+						    IMG_HANDLE hDevmemCtx,
+						    IMG_DEV_VIRTADDR sHeapBaseAddr,
+						    IMG_DEVMEM_SIZE_T uiHeapLength,
+						    IMG_UINT32 ui32Log2DataPageSize,
+						    IMG_HANDLE * phDevmemHeapPtr);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntHeapDestroy(IMG_HANDLE hBridge, IMG_HANDLE hDevmemHeap);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntMapPMR(IMG_HANDLE hBridge,
+						IMG_HANDLE hDevmemServerHeap,
+						IMG_HANDLE hReservation,
+						IMG_HANDLE hPMR,
+						PVRSRV_MEMALLOCFLAGS_T uiMapFlags,
+						IMG_HANDLE * phMapping);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnmapPMR(IMG_HANDLE hBridge, IMG_HANDLE hMapping);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntReserveRange(IMG_HANDLE hBridge,
+						      IMG_HANDLE hDevmemServerHeap,
+						      IMG_DEV_VIRTADDR sAddress,
+						      IMG_DEVMEM_SIZE_T uiLength,
+						      IMG_HANDLE * phReservation);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnreserveRange(IMG_HANDLE hBridge,
+							IMG_HANDLE hReservation);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeChangeSparseMem(IMG_HANDLE hBridge,
+						IMG_HANDLE hSrvDevMemHeap,
+						IMG_HANDLE hPMR,
+						IMG_UINT32 ui32AllocPageCount,
+						IMG_UINT32 * pui32AllocPageIndices,
+						IMG_UINT32 ui32FreePageCount,
+						IMG_UINT32 * pui32FreePageIndices,
+						IMG_UINT32 ui32SparseFlags,
+						PVRSRV_MEMALLOCFLAGS_T uiFlags,
+						IMG_DEV_VIRTADDR sDevVAddr,
+						IMG_UINT64 ui64CPUVAddr);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntMapPages(IMG_HANDLE hBridge,
+						  IMG_HANDLE hReservation,
+						  IMG_HANDLE hPMR,
+						  IMG_UINT32 ui32PageCount,
+						  IMG_UINT32 ui32PhysicalPgOffset,
+						  PVRSRV_MEMALLOCFLAGS_T uiFlags,
+						  IMG_DEV_VIRTADDR sDevVAddr);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnmapPages(IMG_HANDLE hBridge,
+						    IMG_HANDLE hReservation,
+						    IMG_DEV_VIRTADDR sDevVAddr,
+						    IMG_UINT32 ui32PageCount);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIsVDevAddrValid(IMG_HANDLE hBridge,
+						      IMG_HANDLE hDevmemCtx,
+						      IMG_DEV_VIRTADDR sAddress);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemFlushDevSLCRange(IMG_HANDLE hBridge,
+						       IMG_HANDLE hDevmemCtx,
+						       IMG_DEV_VIRTADDR sAddress,
+						       IMG_DEVMEM_SIZE_T uiSize,
+						       IMG_BOOL bInvalidate);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemInvalidateFBSCTable(IMG_HANDLE hBridge,
+							  IMG_HANDLE hDevmemCtx,
+							  IMG_UINT64 ui64FBSCEntries);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHeapCfgHeapConfigCount(IMG_HANDLE hBridge,
+						       IMG_UINT32 * pui32NumHeapConfigs);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHeapCfgHeapCount(IMG_HANDLE hBridge,
+						 IMG_UINT32 ui32HeapConfigIndex,
+						 IMG_UINT32 * pui32NumHeaps);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHeapCfgHeapConfigName(IMG_HANDLE hBridge,
+						      IMG_UINT32 ui32HeapConfigIndex,
+						      IMG_UINT32 ui32HeapConfigNameBufSz,
+						      IMG_CHAR * puiHeapConfigName);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHeapCfgHeapDetails(IMG_HANDLE hBridge,
+						   IMG_UINT32 ui32HeapConfigIndex,
+						   IMG_UINT32 ui32HeapIndex,
+						   IMG_UINT32 ui32HeapNameBufSz,
+						   IMG_CHAR * puiHeapNameOut,
+						   IMG_DEV_VIRTADDR * psDevVAddrBase,
+						   IMG_DEVMEM_SIZE_T * puiHeapLength,
+						   IMG_DEVMEM_SIZE_T * puiReservedRegionLength,
+						   IMG_UINT32 * pui32Log2DataPageSizeOut,
+						   IMG_UINT32 * pui32Log2ImportAlignmentOut);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntRegisterPFNotifyKM(IMG_HANDLE hBridge,
+							    IMG_HANDLE hDevm,
+							    IMG_UINT32 ui32PID, IMG_BOOL bRegister);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeGetMaxPhysHeapCount(IMG_HANDLE hBridge,
+						    IMG_UINT32 * pui32PhysHeapCount);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePhysHeapGetMemInfo(IMG_HANDLE hBridge,
+						   IMG_UINT32 ui32PhysHeapCount,
+						   PVRSRV_PHYS_HEAP * peaPhysHeapID,
+						   PHYS_HEAP_MEM_STATS * pasapPhysHeapMemStats);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeGetDefaultPhysicalHeap(IMG_HANDLE hBridge,
+						       PVRSRV_PHYS_HEAP * peHeap);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeGetHeapPhysMemUsage(IMG_HANDLE hBridge,
+						    IMG_UINT32 ui32PhysHeapCount,
+						    PHYS_HEAP_MEM_STATS * pasapPhysHeapMemStats);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemGetFaultAddress(IMG_HANDLE hBridge,
+						      IMG_HANDLE hDevmemCtx,
+						      IMG_DEV_VIRTADDR * psFaultAddress);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePVRSRVUpdateOOMStats(IMG_HANDLE hBridge,
+						     IMG_UINT32 ui32ui32StatType, IMG_PID ui32pid);
+
+IMG_INTERNAL PVRSRV_ERROR BridgePhysHeapGetMemInfoPkd(IMG_HANDLE hBridge,
+						      IMG_UINT32 ui32PhysHeapCount,
+						      PVRSRV_PHYS_HEAP * peaPhysHeapID,
+						      PHYS_HEAP_MEM_STATS_PKD *
+						      psapPhysHeapMemStats);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeGetHeapPhysMemUsagePkd(IMG_HANDLE hBridge,
+						       IMG_UINT32 ui32PhysHeapCount,
+						       PHYS_HEAP_MEM_STATS_PKD *
+						       psapPhysHeapMemStats);
+
+#endif /* CLIENT_MM_BRIDGE_H */

drivers/gpu/drm/img-rogue/client_mm_direct_bridge.c

@@ -0,0 +1,804 @@
+/*******************************************************************************
+@File
+@Title          Direct client bridge for mm
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Implements the client side of the bridge for mm
+                which is used in calls from Server context.
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#include "client_mm_bridge.h"
+#include "img_defs.h"
+#include "pvr_debug.h"
+
+/* Module specific includes */
+#include "pvrsrv_memallocflags.h"
+#include "pvrsrv_memalloc_physheap.h"
+#include "devicemem_typedefs.h"
+
+#include "pvrsrv_memalloc_physheap.h"
+#include "devicemem.h"
+#include "devicemem_server.h"
+#include "pmr.h"
+#include "devicemem_heapcfg.h"
+#include "physmem.h"
+#include "devicemem_utils.h"
+#include "process_stats.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRExportPMR(IMG_HANDLE hBridge,
+					     IMG_HANDLE hPMR,
+					     IMG_HANDLE * phPMRExport,
+					     IMG_UINT64 * pui64Size,
+					     IMG_UINT32 * pui32Log2Contig,
+					     IMG_UINT64 * pui64Password)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PMR_EXPORT *psPMRExportInt = NULL;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError = PMRExportPMR(psPMRInt, &psPMRExportInt, pui64Size, pui32Log2Contig, pui64Password);
+
+	*phPMRExport = psPMRExportInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRUnexportPMR(IMG_HANDLE hBridge, IMG_HANDLE hPMRExport)
+{
+	PVRSRV_ERROR eError;
+	PMR_EXPORT *psPMRExportInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRExportInt = (PMR_EXPORT *) hPMRExport;
+
+	eError = PMRUnexportPMR(psPMRExportInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRGetUID(IMG_HANDLE hBridge,
+					  IMG_HANDLE hPMR, IMG_UINT64 * pui64UID)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError = PMRGetUID(psPMRInt, pui64UID);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRMakeLocalImportHandle(IMG_HANDLE hBridge,
+							 IMG_HANDLE hBuffer, IMG_HANDLE * phExtMem)
+{
+	PVRSRV_ERROR eError;
+	PMR *psBufferInt;
+	PMR *psExtMemInt = NULL;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psBufferInt = (PMR *) hBuffer;
+
+	eError = PMRMakeLocalImportHandle(psBufferInt, &psExtMemInt);
+
+	*phExtMem = psExtMemInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRUnmakeLocalImportHandle(IMG_HANDLE hBridge, IMG_HANDLE hExtMem)
+{
+	PVRSRV_ERROR eError;
+	PMR *psExtMemInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psExtMemInt = (PMR *) hExtMem;
+
+	eError = PMRUnmakeLocalImportHandle(psExtMemInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRImportPMR(IMG_HANDLE hBridge,
+					     IMG_HANDLE hPMRExport,
+					     IMG_UINT64 ui64uiPassword,
+					     IMG_UINT64 ui64uiSize,
+					     IMG_UINT32 ui32uiLog2Contig, IMG_HANDLE * phPMR)
+{
+	PVRSRV_ERROR eError;
+	PMR_EXPORT *psPMRExportInt;
+	PMR *psPMRInt = NULL;
+
+	psPMRExportInt = (PMR_EXPORT *) hPMRExport;
+
+	eError =
+	    PhysmemImportPMR(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+			     psPMRExportInt,
+			     ui64uiPassword, ui64uiSize, ui32uiLog2Contig, &psPMRInt);
+
+	*phPMR = psPMRInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRLocalImportPMR(IMG_HANDLE hBridge,
+						  IMG_HANDLE hExtHandle,
+						  IMG_HANDLE * phPMR,
+						  IMG_DEVMEM_SIZE_T * puiSize,
+						  IMG_DEVMEM_ALIGN_T * puiAlign)
+{
+	PVRSRV_ERROR eError;
+	PMR *psExtHandleInt;
+	PMR *psPMRInt = NULL;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psExtHandleInt = (PMR *) hExtHandle;
+
+	eError = PMRLocalImportPMR(psExtHandleInt, &psPMRInt, puiSize, puiAlign);
+
+	*phPMR = psPMRInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRUnrefPMR(IMG_HANDLE hBridge, IMG_HANDLE hPMR)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError = PMRUnrefPMR(psPMRInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePMRUnrefUnlockPMR(IMG_HANDLE hBridge, IMG_HANDLE hPMR)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError = PMRUnrefUnlockPMR(psPMRInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePhysmemNewRamBackedPMR(IMG_HANDLE hBridge,
+						       IMG_DEVMEM_SIZE_T uiSize,
+						       IMG_DEVMEM_SIZE_T uiChunkSize,
+						       IMG_UINT32 ui32NumPhysChunks,
+						       IMG_UINT32 ui32NumVirtChunks,
+						       IMG_UINT32 * pui32MappingTable,
+						       IMG_UINT32 ui32Log2PageSize,
+						       PVRSRV_MEMALLOCFLAGS_T uiFlags,
+						       IMG_UINT32 ui32AnnotationLength,
+						       const IMG_CHAR * puiAnnotation,
+						       IMG_PID ui32PID,
+						       IMG_HANDLE * phPMRPtr,
+						       IMG_UINT32 ui32PDumpFlags,
+						       PVRSRV_MEMALLOCFLAGS_T * puiOutFlags)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRPtrInt = NULL;
+
+	eError =
+	    PhysmemNewRamBackedPMR_direct(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+					  uiSize,
+					  uiChunkSize,
+					  ui32NumPhysChunks,
+					  ui32NumVirtChunks,
+					  pui32MappingTable,
+					  ui32Log2PageSize,
+					  uiFlags,
+					  ui32AnnotationLength,
+					  puiAnnotation,
+					  ui32PID, &psPMRPtrInt, ui32PDumpFlags, puiOutFlags);
+
+	*phPMRPtr = psPMRPtrInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePhysmemNewRamBackedLockedPMR(IMG_HANDLE hBridge,
+							     IMG_DEVMEM_SIZE_T uiSize,
+							     IMG_DEVMEM_SIZE_T uiChunkSize,
+							     IMG_UINT32 ui32NumPhysChunks,
+							     IMG_UINT32 ui32NumVirtChunks,
+							     IMG_UINT32 * pui32MappingTable,
+							     IMG_UINT32 ui32Log2PageSize,
+							     PVRSRV_MEMALLOCFLAGS_T uiFlags,
+							     IMG_UINT32 ui32AnnotationLength,
+							     const IMG_CHAR * puiAnnotation,
+							     IMG_PID ui32PID,
+							     IMG_HANDLE * phPMRPtr,
+							     IMG_UINT32 ui32PDumpFlags,
+							     PVRSRV_MEMALLOCFLAGS_T * puiOutFlags)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRPtrInt = NULL;
+
+	eError =
+	    PhysmemNewRamBackedLockedPMR(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+					 uiSize,
+					 uiChunkSize,
+					 ui32NumPhysChunks,
+					 ui32NumVirtChunks,
+					 pui32MappingTable,
+					 ui32Log2PageSize,
+					 uiFlags,
+					 ui32AnnotationLength,
+					 puiAnnotation,
+					 ui32PID, &psPMRPtrInt, ui32PDumpFlags, puiOutFlags);
+
+	*phPMRPtr = psPMRPtrInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntPin(IMG_HANDLE hBridge, IMG_HANDLE hPMR)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError = DevmemIntPin(psPMRInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnpin(IMG_HANDLE hBridge, IMG_HANDLE hPMR)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRInt = (PMR *) hPMR;
+
+	eError = DevmemIntUnpin(psPMRInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntPinValidate(IMG_HANDLE hBridge,
+						     IMG_HANDLE hMapping, IMG_HANDLE hPMR)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_MAPPING *psMappingInt;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psMappingInt = (DEVMEMINT_MAPPING *) hMapping;
+	psPMRInt = (PMR *) hPMR;
+
+	eError = DevmemIntPinValidate(psMappingInt, psPMRInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnpinInvalidate(IMG_HANDLE hBridge,
+							 IMG_HANDLE hMapping, IMG_HANDLE hPMR)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_MAPPING *psMappingInt;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psMappingInt = (DEVMEMINT_MAPPING *) hMapping;
+	psPMRInt = (PMR *) hPMR;
+
+	eError = DevmemIntUnpinInvalidate(psMappingInt, psPMRInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntCtxCreate(IMG_HANDLE hBridge,
+						   IMG_BOOL bbKernelMemoryCtx,
+						   IMG_HANDLE * phDevMemServerContext,
+						   IMG_HANDLE * phPrivData,
+						   IMG_UINT32 * pui32CPUCacheLineSize)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_CTX *psDevMemServerContextInt = NULL;
+	IMG_HANDLE hPrivDataInt = NULL;
+
+	eError =
+	    DevmemIntCtxCreate(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+			       bbKernelMemoryCtx,
+			       &psDevMemServerContextInt, &hPrivDataInt, pui32CPUCacheLineSize);
+
+	*phDevMemServerContext = psDevMemServerContextInt;
+	*phPrivData = hPrivDataInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntCtxDestroy(IMG_HANDLE hBridge,
+						    IMG_HANDLE hDevmemServerContext)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_CTX *psDevmemServerContextInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psDevmemServerContextInt = (DEVMEMINT_CTX *) hDevmemServerContext;
+
+	eError = DevmemIntCtxDestroy(psDevmemServerContextInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntHeapCreate(IMG_HANDLE hBridge,
+						    IMG_HANDLE hDevmemCtx,
+						    IMG_DEV_VIRTADDR sHeapBaseAddr,
+						    IMG_DEVMEM_SIZE_T uiHeapLength,
+						    IMG_UINT32 ui32Log2DataPageSize,
+						    IMG_HANDLE * phDevmemHeapPtr)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_CTX *psDevmemCtxInt;
+	DEVMEMINT_HEAP *psDevmemHeapPtrInt = NULL;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psDevmemCtxInt = (DEVMEMINT_CTX *) hDevmemCtx;
+
+	eError =
+	    DevmemIntHeapCreate(psDevmemCtxInt,
+				sHeapBaseAddr,
+				uiHeapLength, ui32Log2DataPageSize, &psDevmemHeapPtrInt);
+
+	*phDevmemHeapPtr = psDevmemHeapPtrInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntHeapDestroy(IMG_HANDLE hBridge, IMG_HANDLE hDevmemHeap)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_HEAP *psDevmemHeapInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psDevmemHeapInt = (DEVMEMINT_HEAP *) hDevmemHeap;
+
+	eError = DevmemIntHeapDestroy(psDevmemHeapInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntMapPMR(IMG_HANDLE hBridge,
+						IMG_HANDLE hDevmemServerHeap,
+						IMG_HANDLE hReservation,
+						IMG_HANDLE hPMR,
+						PVRSRV_MEMALLOCFLAGS_T uiMapFlags,
+						IMG_HANDLE * phMapping)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_HEAP *psDevmemServerHeapInt;
+	DEVMEMINT_RESERVATION *psReservationInt;
+	PMR *psPMRInt;
+	DEVMEMINT_MAPPING *psMappingInt = NULL;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psDevmemServerHeapInt = (DEVMEMINT_HEAP *) hDevmemServerHeap;
+	psReservationInt = (DEVMEMINT_RESERVATION *) hReservation;
+	psPMRInt = (PMR *) hPMR;
+
+	eError =
+	    DevmemIntMapPMR(psDevmemServerHeapInt,
+			    psReservationInt, psPMRInt, uiMapFlags, &psMappingInt);
+
+	*phMapping = psMappingInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnmapPMR(IMG_HANDLE hBridge, IMG_HANDLE hMapping)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_MAPPING *psMappingInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psMappingInt = (DEVMEMINT_MAPPING *) hMapping;
+
+	eError = DevmemIntUnmapPMR(psMappingInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntReserveRange(IMG_HANDLE hBridge,
+						      IMG_HANDLE hDevmemServerHeap,
+						      IMG_DEV_VIRTADDR sAddress,
+						      IMG_DEVMEM_SIZE_T uiLength,
+						      IMG_HANDLE * phReservation)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_HEAP *psDevmemServerHeapInt;
+	DEVMEMINT_RESERVATION *psReservationInt = NULL;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psDevmemServerHeapInt = (DEVMEMINT_HEAP *) hDevmemServerHeap;
+
+	eError =
+	    DevmemIntReserveRange(psDevmemServerHeapInt, sAddress, uiLength, &psReservationInt);
+
+	*phReservation = psReservationInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnreserveRange(IMG_HANDLE hBridge, IMG_HANDLE hReservation)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_RESERVATION *psReservationInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psReservationInt = (DEVMEMINT_RESERVATION *) hReservation;
+
+	eError = DevmemIntUnreserveRange(psReservationInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeChangeSparseMem(IMG_HANDLE hBridge,
+						IMG_HANDLE hSrvDevMemHeap,
+						IMG_HANDLE hPMR,
+						IMG_UINT32 ui32AllocPageCount,
+						IMG_UINT32 * pui32AllocPageIndices,
+						IMG_UINT32 ui32FreePageCount,
+						IMG_UINT32 * pui32FreePageIndices,
+						IMG_UINT32 ui32SparseFlags,
+						PVRSRV_MEMALLOCFLAGS_T uiFlags,
+						IMG_DEV_VIRTADDR sDevVAddr, IMG_UINT64 ui64CPUVAddr)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_HEAP *psSrvDevMemHeapInt;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSrvDevMemHeapInt = (DEVMEMINT_HEAP *) hSrvDevMemHeap;
+	psPMRInt = (PMR *) hPMR;
+
+	eError =
+	    DevmemIntChangeSparse(psSrvDevMemHeapInt,
+				  psPMRInt,
+				  ui32AllocPageCount,
+				  pui32AllocPageIndices,
+				  ui32FreePageCount,
+				  pui32FreePageIndices,
+				  ui32SparseFlags, uiFlags, sDevVAddr, ui64CPUVAddr);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntMapPages(IMG_HANDLE hBridge,
+						  IMG_HANDLE hReservation,
+						  IMG_HANDLE hPMR,
+						  IMG_UINT32 ui32PageCount,
+						  IMG_UINT32 ui32PhysicalPgOffset,
+						  PVRSRV_MEMALLOCFLAGS_T uiFlags,
+						  IMG_DEV_VIRTADDR sDevVAddr)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_RESERVATION *psReservationInt;
+	PMR *psPMRInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psReservationInt = (DEVMEMINT_RESERVATION *) hReservation;
+	psPMRInt = (PMR *) hPMR;
+
+	eError =
+	    DevmemIntMapPages(psReservationInt,
+			      psPMRInt, ui32PageCount, ui32PhysicalPgOffset, uiFlags, sDevVAddr);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntUnmapPages(IMG_HANDLE hBridge,
+						    IMG_HANDLE hReservation,
+						    IMG_DEV_VIRTADDR sDevVAddr,
+						    IMG_UINT32 ui32PageCount)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_RESERVATION *psReservationInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psReservationInt = (DEVMEMINT_RESERVATION *) hReservation;
+
+	eError = DevmemIntUnmapPages(psReservationInt, sDevVAddr, ui32PageCount);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIsVDevAddrValid(IMG_HANDLE hBridge,
+						      IMG_HANDLE hDevmemCtx,
+						      IMG_DEV_VIRTADDR sAddress)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_CTX *psDevmemCtxInt;
+
+	psDevmemCtxInt = (DEVMEMINT_CTX *) hDevmemCtx;
+
+	eError =
+	    DevmemIntIsVDevAddrValid(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+				     psDevmemCtxInt, sAddress);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemFlushDevSLCRange(IMG_HANDLE hBridge,
+						       IMG_HANDLE hDevmemCtx,
+						       IMG_DEV_VIRTADDR sAddress,
+						       IMG_DEVMEM_SIZE_T uiSize,
+						       IMG_BOOL bInvalidate)
+{
+#if defined(RGX_SRV_SLC_RANGEBASED_CFI_SUPPORTED)
+	PVRSRV_ERROR eError;
+	DEVMEMINT_CTX *psDevmemCtxInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psDevmemCtxInt = (DEVMEMINT_CTX *) hDevmemCtx;
+
+	eError = DevmemIntFlushDevSLCRange(psDevmemCtxInt, sAddress, uiSize, bInvalidate);
+
+	return eError;
+#else
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+	PVR_UNREFERENCED_PARAMETER(hDevmemCtx);
+	PVR_UNREFERENCED_PARAMETER(sAddress);
+	PVR_UNREFERENCED_PARAMETER(uiSize);
+	PVR_UNREFERENCED_PARAMETER(bInvalidate);
+
+	return PVRSRV_ERROR_NOT_IMPLEMENTED;
+#endif
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemInvalidateFBSCTable(IMG_HANDLE hBridge,
+							  IMG_HANDLE hDevmemCtx,
+							  IMG_UINT64 ui64FBSCEntries)
+{
+#if defined(RGX_FEATURE_FBCDC)
+	PVRSRV_ERROR eError;
+	DEVMEMINT_CTX *psDevmemCtxInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psDevmemCtxInt = (DEVMEMINT_CTX *) hDevmemCtx;
+
+	eError = DevmemIntInvalidateFBSCTable(psDevmemCtxInt, ui64FBSCEntries);
+
+	return eError;
+#else
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+	PVR_UNREFERENCED_PARAMETER(hDevmemCtx);
+	PVR_UNREFERENCED_PARAMETER(ui64FBSCEntries);
+
+	return PVRSRV_ERROR_NOT_IMPLEMENTED;
+#endif
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHeapCfgHeapConfigCount(IMG_HANDLE hBridge,
+						       IMG_UINT32 * pui32NumHeapConfigs)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    HeapCfgHeapConfigCount(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+				   pui32NumHeapConfigs);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHeapCfgHeapCount(IMG_HANDLE hBridge,
+						 IMG_UINT32 ui32HeapConfigIndex,
+						 IMG_UINT32 * pui32NumHeaps)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    HeapCfgHeapCount(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+			     ui32HeapConfigIndex, pui32NumHeaps);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHeapCfgHeapConfigName(IMG_HANDLE hBridge,
+						      IMG_UINT32 ui32HeapConfigIndex,
+						      IMG_UINT32 ui32HeapConfigNameBufSz,
+						      IMG_CHAR * puiHeapConfigName)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    HeapCfgHeapConfigName(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+				  ui32HeapConfigIndex, ui32HeapConfigNameBufSz, puiHeapConfigName);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeHeapCfgHeapDetails(IMG_HANDLE hBridge,
+						   IMG_UINT32 ui32HeapConfigIndex,
+						   IMG_UINT32 ui32HeapIndex,
+						   IMG_UINT32 ui32HeapNameBufSz,
+						   IMG_CHAR * puiHeapNameOut,
+						   IMG_DEV_VIRTADDR * psDevVAddrBase,
+						   IMG_DEVMEM_SIZE_T * puiHeapLength,
+						   IMG_DEVMEM_SIZE_T * puiReservedRegionLength,
+						   IMG_UINT32 * pui32Log2DataPageSizeOut,
+						   IMG_UINT32 * pui32Log2ImportAlignmentOut)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    HeapCfgHeapDetails(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+			       ui32HeapConfigIndex,
+			       ui32HeapIndex,
+			       ui32HeapNameBufSz,
+			       puiHeapNameOut,
+			       psDevVAddrBase,
+			       puiHeapLength,
+			       puiReservedRegionLength,
+			       pui32Log2DataPageSizeOut, pui32Log2ImportAlignmentOut);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemIntRegisterPFNotifyKM(IMG_HANDLE hBridge,
+							    IMG_HANDLE hDevm,
+							    IMG_UINT32 ui32PID, IMG_BOOL bRegister)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_CTX *psDevmInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psDevmInt = (DEVMEMINT_CTX *) hDevm;
+
+	eError = DevmemIntRegisterPFNotifyKM(psDevmInt, ui32PID, bRegister);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeGetMaxPhysHeapCount(IMG_HANDLE hBridge,
+						    IMG_UINT32 * pui32PhysHeapCount)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    PVRSRVGetMaxPhysHeapCountKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+					pui32PhysHeapCount);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePhysHeapGetMemInfo(IMG_HANDLE hBridge,
+						   IMG_UINT32 ui32PhysHeapCount,
+						   PVRSRV_PHYS_HEAP * peaPhysHeapID,
+						   PHYS_HEAP_MEM_STATS * pasapPhysHeapMemStats)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    PVRSRVPhysHeapGetMemInfoKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+				       ui32PhysHeapCount, peaPhysHeapID, pasapPhysHeapMemStats);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeGetDefaultPhysicalHeap(IMG_HANDLE hBridge,
+						       PVRSRV_PHYS_HEAP * peHeap)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    PVRSRVGetDefaultPhysicalHeapKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge), peHeap);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeGetHeapPhysMemUsage(IMG_HANDLE hBridge,
+						    IMG_UINT32 ui32PhysHeapCount,
+						    PHYS_HEAP_MEM_STATS * pasapPhysHeapMemStats)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    PVRSRVGetHeapPhysMemUsageKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+					ui32PhysHeapCount, pasapPhysHeapMemStats);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeDevmemGetFaultAddress(IMG_HANDLE hBridge,
+						      IMG_HANDLE hDevmemCtx,
+						      IMG_DEV_VIRTADDR * psFaultAddress)
+{
+	PVRSRV_ERROR eError;
+	DEVMEMINT_CTX *psDevmemCtxInt;
+
+	psDevmemCtxInt = (DEVMEMINT_CTX *) hDevmemCtx;
+
+	eError =
+	    DevmemIntGetFaultAddress(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+				     psDevmemCtxInt, psFaultAddress);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePVRSRVUpdateOOMStats(IMG_HANDLE hBridge,
+						     IMG_UINT32 ui32ui32StatType, IMG_PID ui32pid)
+{
+#if defined(PVRSRV_ENABLE_PROCESS_STATS)
+	PVRSRV_ERROR eError;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	eError = PVRSRVServerUpdateOOMStats(ui32ui32StatType, ui32pid);
+
+	return eError;
+#else
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+	PVR_UNREFERENCED_PARAMETER(ui32ui32StatType);
+	PVR_UNREFERENCED_PARAMETER(ui32pid);
+
+	return PVRSRV_ERROR_NOT_IMPLEMENTED;
+#endif
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgePhysHeapGetMemInfoPkd(IMG_HANDLE hBridge,
+						      IMG_UINT32 ui32PhysHeapCount,
+						      PVRSRV_PHYS_HEAP * peaPhysHeapID,
+						      PHYS_HEAP_MEM_STATS_PKD *
+						      psapPhysHeapMemStats)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    PVRSRVPhysHeapGetMemInfoPkdKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+					  ui32PhysHeapCount, peaPhysHeapID, psapPhysHeapMemStats);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeGetHeapPhysMemUsagePkd(IMG_HANDLE hBridge,
+						       IMG_UINT32 ui32PhysHeapCount,
+						       PHYS_HEAP_MEM_STATS_PKD *
+						       psapPhysHeapMemStats)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    PVRSRVGetHeapPhysMemUsagePkdKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+					   ui32PhysHeapCount, psapPhysHeapMemStats);
+
+	return eError;
+}

drivers/gpu/drm/img-rogue/client_pvrtl_bridge.h

@@ -0,0 +1,93 @@
+/*******************************************************************************
+@File
+@Title          Client bridge header for pvrtl
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Exports the client bridge functions for pvrtl
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef CLIENT_PVRTL_BRIDGE_H
+#define CLIENT_PVRTL_BRIDGE_H
+
+#include "img_defs.h"
+#include "pvrsrv_error.h"
+
+#if defined(PVR_INDIRECT_BRIDGE_CLIENTS)
+#include "pvr_bridge_client.h"
+#include "pvr_bridge.h"
+#endif
+
+#include "common_pvrtl_bridge.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLOpenStream(IMG_HANDLE hBridge,
+					     const IMG_CHAR * puiName,
+					     IMG_UINT32 ui32Mode,
+					     IMG_HANDLE * phSD, IMG_HANDLE * phTLPMR);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLCloseStream(IMG_HANDLE hBridge, IMG_HANDLE hSD);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLAcquireData(IMG_HANDLE hBridge,
+					      IMG_HANDLE hSD,
+					      IMG_UINT32 * pui32ReadOffset,
+					      IMG_UINT32 * pui32ReadLen);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLReleaseData(IMG_HANDLE hBridge,
+					      IMG_HANDLE hSD,
+					      IMG_UINT32 ui32ReadOffset, IMG_UINT32 ui32ReadLen);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLDiscoverStreams(IMG_HANDLE hBridge,
+						  const IMG_CHAR * puiNamePattern,
+						  IMG_UINT32 ui32Size,
+						  IMG_CHAR * puiStreams,
+						  IMG_UINT32 * pui32NumFound);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLReserveStream(IMG_HANDLE hBridge,
+						IMG_HANDLE hSD,
+						IMG_UINT32 * pui32BufferOffset,
+						IMG_UINT32 ui32Size,
+						IMG_UINT32 ui32SizeMin,
+						IMG_UINT32 * pui32Available);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLCommitStream(IMG_HANDLE hBridge,
+					       IMG_HANDLE hSD, IMG_UINT32 ui32ReqSize);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLWriteData(IMG_HANDLE hBridge,
+					    IMG_HANDLE hSD,
+					    IMG_UINT32 ui32Size, IMG_BYTE * pui8Data);
+
+#endif /* CLIENT_PVRTL_BRIDGE_H */

drivers/gpu/drm/img-rogue/client_pvrtl_direct_bridge.c

@@ -0,0 +1,175 @@
+/*******************************************************************************
+@File
+@Title          Direct client bridge for pvrtl
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Implements the client side of the bridge for pvrtl
+                which is used in calls from Server context.
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#include "client_pvrtl_bridge.h"
+#include "img_defs.h"
+#include "pvr_debug.h"
+
+/* Module specific includes */
+#include "devicemem_typedefs.h"
+#include "pvrsrv_tlcommon.h"
+
+#include "tlserver.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLOpenStream(IMG_HANDLE hBridge,
+					     const IMG_CHAR * puiName,
+					     IMG_UINT32 ui32Mode,
+					     IMG_HANDLE * phSD, IMG_HANDLE * phTLPMR)
+{
+	PVRSRV_ERROR eError;
+	TL_STREAM_DESC *psSDInt = NULL;
+	PMR *psTLPMRInt = NULL;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	eError = TLServerOpenStreamKM(puiName, ui32Mode, &psSDInt, &psTLPMRInt);
+
+	*phSD = psSDInt;
+	*phTLPMR = psTLPMRInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLCloseStream(IMG_HANDLE hBridge, IMG_HANDLE hSD)
+{
+	PVRSRV_ERROR eError;
+	TL_STREAM_DESC *psSDInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSDInt = (TL_STREAM_DESC *) hSD;
+
+	eError = TLServerCloseStreamKM(psSDInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLAcquireData(IMG_HANDLE hBridge,
+					      IMG_HANDLE hSD,
+					      IMG_UINT32 * pui32ReadOffset,
+					      IMG_UINT32 * pui32ReadLen)
+{
+	PVRSRV_ERROR eError;
+	TL_STREAM_DESC *psSDInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSDInt = (TL_STREAM_DESC *) hSD;
+
+	eError = TLServerAcquireDataKM(psSDInt, pui32ReadOffset, pui32ReadLen);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLReleaseData(IMG_HANDLE hBridge,
+					      IMG_HANDLE hSD,
+					      IMG_UINT32 ui32ReadOffset, IMG_UINT32 ui32ReadLen)
+{
+	PVRSRV_ERROR eError;
+	TL_STREAM_DESC *psSDInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSDInt = (TL_STREAM_DESC *) hSD;
+
+	eError = TLServerReleaseDataKM(psSDInt, ui32ReadOffset, ui32ReadLen);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLDiscoverStreams(IMG_HANDLE hBridge,
+						  const IMG_CHAR * puiNamePattern,
+						  IMG_UINT32 ui32Size,
+						  IMG_CHAR * puiStreams, IMG_UINT32 * pui32NumFound)
+{
+	PVRSRV_ERROR eError;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	eError = TLServerDiscoverStreamsKM(puiNamePattern, ui32Size, puiStreams, pui32NumFound);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLReserveStream(IMG_HANDLE hBridge,
+						IMG_HANDLE hSD,
+						IMG_UINT32 * pui32BufferOffset,
+						IMG_UINT32 ui32Size,
+						IMG_UINT32 ui32SizeMin, IMG_UINT32 * pui32Available)
+{
+	PVRSRV_ERROR eError;
+	TL_STREAM_DESC *psSDInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSDInt = (TL_STREAM_DESC *) hSD;
+
+	eError =
+	    TLServerReserveStreamKM(psSDInt,
+				    pui32BufferOffset, ui32Size, ui32SizeMin, pui32Available);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLCommitStream(IMG_HANDLE hBridge,
+					       IMG_HANDLE hSD, IMG_UINT32 ui32ReqSize)
+{
+	PVRSRV_ERROR eError;
+	TL_STREAM_DESC *psSDInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSDInt = (TL_STREAM_DESC *) hSD;
+
+	eError = TLServerCommitStreamKM(psSDInt, ui32ReqSize);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeTLWriteData(IMG_HANDLE hBridge,
+					    IMG_HANDLE hSD,
+					    IMG_UINT32 ui32Size, IMG_BYTE * pui8Data)
+{
+	PVRSRV_ERROR eError;
+	TL_STREAM_DESC *psSDInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSDInt = (TL_STREAM_DESC *) hSD;
+
+	eError = TLServerWriteDataKM(psSDInt, ui32Size, pui8Data);
+
+	return eError;
+}

drivers/gpu/drm/img-rogue/client_ri_bridge.h

@@ -0,0 +1,89 @@
+/*******************************************************************************
+@File
+@Title          Client bridge header for ri
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Exports the client bridge functions for ri
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef CLIENT_RI_BRIDGE_H
+#define CLIENT_RI_BRIDGE_H
+
+#include "img_defs.h"
+#include "pvrsrv_error.h"
+
+#if defined(PVR_INDIRECT_BRIDGE_CLIENTS)
+#include "pvr_bridge_client.h"
+#include "pvr_bridge.h"
+#endif
+
+#include "common_ri_bridge.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIWritePMREntry(IMG_HANDLE hBridge, IMG_HANDLE hPMRHandle);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIWriteMEMDESCEntry(IMG_HANDLE hBridge,
+						    IMG_HANDLE hPMRHandle,
+						    IMG_UINT32 ui32TextBSize,
+						    const IMG_CHAR * puiTextB,
+						    IMG_UINT64 ui64Offset,
+						    IMG_UINT64 ui64Size,
+						    IMG_BOOL bIsImport,
+						    IMG_BOOL bIsSuballoc, IMG_HANDLE * phRIHandle);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIWriteProcListEntry(IMG_HANDLE hBridge,
+						     IMG_UINT32 ui32TextBSize,
+						     const IMG_CHAR * puiTextB,
+						     IMG_UINT64 ui64Size,
+						     IMG_UINT64 ui64DevVAddr,
+						     IMG_HANDLE * phRIHandle);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIUpdateMEMDESCAddr(IMG_HANDLE hBridge,
+						    IMG_HANDLE hRIHandle, IMG_DEV_VIRTADDR sAddr);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIDeleteMEMDESCEntry(IMG_HANDLE hBridge, IMG_HANDLE hRIHandle);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIDumpList(IMG_HANDLE hBridge, IMG_HANDLE hPMRHandle);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIDumpAll(IMG_HANDLE hBridge);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIDumpProcess(IMG_HANDLE hBridge, IMG_PID ui32Pid);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIWritePMREntryWithOwner(IMG_HANDLE hBridge,
+							 IMG_HANDLE hPMRHandle, IMG_PID ui32Owner);
+
+#endif /* CLIENT_RI_BRIDGE_H */

drivers/gpu/drm/img-rogue/client_ri_direct_bridge.c

@@ -0,0 +1,182 @@
+/*******************************************************************************
+@File
+@Title          Direct client bridge for ri
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Implements the client side of the bridge for ri
+                which is used in calls from Server context.
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#include "client_ri_bridge.h"
+#include "img_defs.h"
+#include "pvr_debug.h"
+
+/* Module specific includes */
+#include "ri_typedefs.h"
+
+#include "ri_server.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIWritePMREntry(IMG_HANDLE hBridge, IMG_HANDLE hPMRHandle)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRHandleInt = (PMR *) hPMRHandle;
+
+	eError = RIWritePMREntryKM(psPMRHandleInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIWriteMEMDESCEntry(IMG_HANDLE hBridge,
+						    IMG_HANDLE hPMRHandle,
+						    IMG_UINT32 ui32TextBSize,
+						    const IMG_CHAR * puiTextB,
+						    IMG_UINT64 ui64Offset,
+						    IMG_UINT64 ui64Size,
+						    IMG_BOOL bIsImport,
+						    IMG_BOOL bIsSuballoc, IMG_HANDLE * phRIHandle)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRHandleInt;
+	RI_HANDLE psRIHandleInt = NULL;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRHandleInt = (PMR *) hPMRHandle;
+
+	eError =
+	    RIWriteMEMDESCEntryKM(psPMRHandleInt,
+				  ui32TextBSize,
+				  puiTextB,
+				  ui64Offset, ui64Size, bIsImport, bIsSuballoc, &psRIHandleInt);
+
+	*phRIHandle = psRIHandleInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIWriteProcListEntry(IMG_HANDLE hBridge,
+						     IMG_UINT32 ui32TextBSize,
+						     const IMG_CHAR * puiTextB,
+						     IMG_UINT64 ui64Size,
+						     IMG_UINT64 ui64DevVAddr,
+						     IMG_HANDLE * phRIHandle)
+{
+	PVRSRV_ERROR eError;
+	RI_HANDLE psRIHandleInt = NULL;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	eError =
+	    RIWriteProcListEntryKM(ui32TextBSize, puiTextB, ui64Size, ui64DevVAddr, &psRIHandleInt);
+
+	*phRIHandle = psRIHandleInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIUpdateMEMDESCAddr(IMG_HANDLE hBridge,
+						    IMG_HANDLE hRIHandle, IMG_DEV_VIRTADDR sAddr)
+{
+	PVRSRV_ERROR eError;
+	RI_HANDLE psRIHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psRIHandleInt = (RI_HANDLE) hRIHandle;
+
+	eError = RIUpdateMEMDESCAddrKM(psRIHandleInt, sAddr);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIDeleteMEMDESCEntry(IMG_HANDLE hBridge, IMG_HANDLE hRIHandle)
+{
+	PVRSRV_ERROR eError;
+	RI_HANDLE psRIHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psRIHandleInt = (RI_HANDLE) hRIHandle;
+
+	eError = RIDeleteMEMDESCEntryKM(psRIHandleInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIDumpList(IMG_HANDLE hBridge, IMG_HANDLE hPMRHandle)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRHandleInt = (PMR *) hPMRHandle;
+
+	eError = RIDumpListKM(psPMRHandleInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIDumpAll(IMG_HANDLE hBridge)
+{
+	PVRSRV_ERROR eError;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	eError = RIDumpAllKM();
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIDumpProcess(IMG_HANDLE hBridge, IMG_PID ui32Pid)
+{
+	PVRSRV_ERROR eError;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	eError = RIDumpProcessKM(ui32Pid);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeRIWritePMREntryWithOwner(IMG_HANDLE hBridge,
+							 IMG_HANDLE hPMRHandle, IMG_PID ui32Owner)
+{
+	PVRSRV_ERROR eError;
+	PMR *psPMRHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psPMRHandleInt = (PMR *) hPMRHandle;
+
+	eError = RIWritePMREntryWithOwnerKM(psPMRHandleInt, ui32Owner);
+
+	return eError;
+}

drivers/gpu/drm/img-rogue/client_sync_bridge.h

@@ -0,0 +1,102 @@
+/*******************************************************************************
+@File
+@Title          Client bridge header for sync
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Exports the client bridge functions for sync
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef CLIENT_SYNC_BRIDGE_H
+#define CLIENT_SYNC_BRIDGE_H
+
+#include "img_defs.h"
+#include "pvrsrv_error.h"
+
+#if defined(PVR_INDIRECT_BRIDGE_CLIENTS)
+#include "pvr_bridge_client.h"
+#include "pvr_bridge.h"
+#endif
+
+#include "common_sync_bridge.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeAllocSyncPrimitiveBlock(IMG_HANDLE hBridge,
+							IMG_HANDLE * phSyncHandle,
+							IMG_UINT32 * pui32SyncPrimVAddr,
+							IMG_UINT32 * pui32SyncPrimBlockSize,
+							IMG_HANDLE * phhSyncPMR);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeFreeSyncPrimitiveBlock(IMG_HANDLE hBridge, IMG_HANDLE hSyncHandle);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimSet(IMG_HANDLE hBridge,
+					    IMG_HANDLE hSyncHandle,
+					    IMG_UINT32 ui32Index, IMG_UINT32 ui32Value);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimPDump(IMG_HANDLE hBridge,
+					      IMG_HANDLE hSyncHandle, IMG_UINT32 ui32Offset);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimPDumpValue(IMG_HANDLE hBridge,
+						   IMG_HANDLE hSyncHandle,
+						   IMG_UINT32 ui32Offset, IMG_UINT32 ui32Value);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimPDumpPol(IMG_HANDLE hBridge,
+						 IMG_HANDLE hSyncHandle,
+						 IMG_UINT32 ui32Offset,
+						 IMG_UINT32 ui32Value,
+						 IMG_UINT32 ui32Mask,
+						 PDUMP_POLL_OPERATOR eOperator,
+						 PDUMP_FLAGS_T uiPDumpFlags);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimPDumpCBP(IMG_HANDLE hBridge,
+						 IMG_HANDLE hSyncHandle,
+						 IMG_UINT32 ui32Offset,
+						 IMG_DEVMEM_OFFSET_T uiWriteOffset,
+						 IMG_DEVMEM_SIZE_T uiPacketSize,
+						 IMG_DEVMEM_SIZE_T uiBufferSize);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncAllocEvent(IMG_HANDLE hBridge,
+					       IMG_BOOL bServerSync,
+					       IMG_UINT32 ui32FWAddr,
+					       IMG_UINT32 ui32ClassNameSize,
+					       const IMG_CHAR * puiClassName);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncFreeEvent(IMG_HANDLE hBridge, IMG_UINT32 ui32FWAddr);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncCheckpointSignalledPDumpPol(IMG_HANDLE hBridge,
+								PVRSRV_FENCE hFence);
+
+#endif /* CLIENT_SYNC_BRIDGE_H */

drivers/gpu/drm/img-rogue/client_sync_direct_bridge.c

@@ -0,0 +1,262 @@
+/*******************************************************************************
+@File
+@Title          Direct client bridge for sync
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Implements the client side of the bridge for sync
+                which is used in calls from Server context.
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#include "client_sync_bridge.h"
+#include "img_defs.h"
+#include "pvr_debug.h"
+
+/* Module specific includes */
+#include "pdump.h"
+#include "pdumpdefs.h"
+#include "devicemem_typedefs.h"
+#include "pvrsrv_sync_km.h"
+#include <powervr/pvrsrv_sync_ext.h>
+
+#include "sync.h"
+#include "sync_server.h"
+#include "pdump.h"
+#include "pvrsrv_sync_km.h"
+#include "sync_fallback_server.h"
+#include "sync_checkpoint.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeAllocSyncPrimitiveBlock(IMG_HANDLE hBridge,
+							IMG_HANDLE * phSyncHandle,
+							IMG_UINT32 * pui32SyncPrimVAddr,
+							IMG_UINT32 * pui32SyncPrimBlockSize,
+							IMG_HANDLE * phhSyncPMR)
+{
+	PVRSRV_ERROR eError;
+	SYNC_PRIMITIVE_BLOCK *psSyncHandleInt = NULL;
+	PMR *pshSyncPMRInt = NULL;
+
+	eError =
+	    PVRSRVAllocSyncPrimitiveBlockKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+					    &psSyncHandleInt,
+					    pui32SyncPrimVAddr,
+					    pui32SyncPrimBlockSize, &pshSyncPMRInt);
+
+	*phSyncHandle = psSyncHandleInt;
+	*phhSyncPMR = pshSyncPMRInt;
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeFreeSyncPrimitiveBlock(IMG_HANDLE hBridge, IMG_HANDLE hSyncHandle)
+{
+	PVRSRV_ERROR eError;
+	SYNC_PRIMITIVE_BLOCK *psSyncHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSyncHandleInt = (SYNC_PRIMITIVE_BLOCK *) hSyncHandle;
+
+	eError = PVRSRVFreeSyncPrimitiveBlockKM(psSyncHandleInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimSet(IMG_HANDLE hBridge,
+					    IMG_HANDLE hSyncHandle,
+					    IMG_UINT32 ui32Index, IMG_UINT32 ui32Value)
+{
+	PVRSRV_ERROR eError;
+	SYNC_PRIMITIVE_BLOCK *psSyncHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSyncHandleInt = (SYNC_PRIMITIVE_BLOCK *) hSyncHandle;
+
+	eError = PVRSRVSyncPrimSetKM(psSyncHandleInt, ui32Index, ui32Value);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimPDump(IMG_HANDLE hBridge,
+					      IMG_HANDLE hSyncHandle, IMG_UINT32 ui32Offset)
+{
+#if defined(PDUMP)
+	PVRSRV_ERROR eError;
+	SYNC_PRIMITIVE_BLOCK *psSyncHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSyncHandleInt = (SYNC_PRIMITIVE_BLOCK *) hSyncHandle;
+
+	eError = PVRSRVSyncPrimPDumpKM(psSyncHandleInt, ui32Offset);
+
+	return eError;
+#else
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+	PVR_UNREFERENCED_PARAMETER(hSyncHandle);
+	PVR_UNREFERENCED_PARAMETER(ui32Offset);
+
+	return PVRSRV_ERROR_NOT_IMPLEMENTED;
+#endif
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimPDumpValue(IMG_HANDLE hBridge,
+						   IMG_HANDLE hSyncHandle,
+						   IMG_UINT32 ui32Offset, IMG_UINT32 ui32Value)
+{
+#if defined(PDUMP)
+	PVRSRV_ERROR eError;
+	SYNC_PRIMITIVE_BLOCK *psSyncHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSyncHandleInt = (SYNC_PRIMITIVE_BLOCK *) hSyncHandle;
+
+	eError = PVRSRVSyncPrimPDumpValueKM(psSyncHandleInt, ui32Offset, ui32Value);
+
+	return eError;
+#else
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+	PVR_UNREFERENCED_PARAMETER(hSyncHandle);
+	PVR_UNREFERENCED_PARAMETER(ui32Offset);
+	PVR_UNREFERENCED_PARAMETER(ui32Value);
+
+	return PVRSRV_ERROR_NOT_IMPLEMENTED;
+#endif
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimPDumpPol(IMG_HANDLE hBridge,
+						 IMG_HANDLE hSyncHandle,
+						 IMG_UINT32 ui32Offset,
+						 IMG_UINT32 ui32Value,
+						 IMG_UINT32 ui32Mask,
+						 PDUMP_POLL_OPERATOR eOperator,
+						 PDUMP_FLAGS_T uiPDumpFlags)
+{
+#if defined(PDUMP)
+	PVRSRV_ERROR eError;
+	SYNC_PRIMITIVE_BLOCK *psSyncHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSyncHandleInt = (SYNC_PRIMITIVE_BLOCK *) hSyncHandle;
+
+	eError =
+	    PVRSRVSyncPrimPDumpPolKM(psSyncHandleInt,
+				     ui32Offset, ui32Value, ui32Mask, eOperator, uiPDumpFlags);
+
+	return eError;
+#else
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+	PVR_UNREFERENCED_PARAMETER(hSyncHandle);
+	PVR_UNREFERENCED_PARAMETER(ui32Offset);
+	PVR_UNREFERENCED_PARAMETER(ui32Value);
+	PVR_UNREFERENCED_PARAMETER(ui32Mask);
+	PVR_UNREFERENCED_PARAMETER(eOperator);
+	PVR_UNREFERENCED_PARAMETER(uiPDumpFlags);
+
+	return PVRSRV_ERROR_NOT_IMPLEMENTED;
+#endif
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncPrimPDumpCBP(IMG_HANDLE hBridge,
+						 IMG_HANDLE hSyncHandle,
+						 IMG_UINT32 ui32Offset,
+						 IMG_DEVMEM_OFFSET_T uiWriteOffset,
+						 IMG_DEVMEM_SIZE_T uiPacketSize,
+						 IMG_DEVMEM_SIZE_T uiBufferSize)
+{
+#if defined(PDUMP)
+	PVRSRV_ERROR eError;
+	SYNC_PRIMITIVE_BLOCK *psSyncHandleInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	psSyncHandleInt = (SYNC_PRIMITIVE_BLOCK *) hSyncHandle;
+
+	eError =
+	    PVRSRVSyncPrimPDumpCBPKM(psSyncHandleInt,
+				     ui32Offset, uiWriteOffset, uiPacketSize, uiBufferSize);
+
+	return eError;
+#else
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+	PVR_UNREFERENCED_PARAMETER(hSyncHandle);
+	PVR_UNREFERENCED_PARAMETER(ui32Offset);
+	PVR_UNREFERENCED_PARAMETER(uiWriteOffset);
+	PVR_UNREFERENCED_PARAMETER(uiPacketSize);
+	PVR_UNREFERENCED_PARAMETER(uiBufferSize);
+
+	return PVRSRV_ERROR_NOT_IMPLEMENTED;
+#endif
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncAllocEvent(IMG_HANDLE hBridge,
+					       IMG_BOOL bServerSync,
+					       IMG_UINT32 ui32FWAddr,
+					       IMG_UINT32 ui32ClassNameSize,
+					       const IMG_CHAR * puiClassName)
+{
+	PVRSRV_ERROR eError;
+
+	eError =
+	    PVRSRVSyncAllocEventKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+				   bServerSync, ui32FWAddr, ui32ClassNameSize, puiClassName);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncFreeEvent(IMG_HANDLE hBridge, IMG_UINT32 ui32FWAddr)
+{
+	PVRSRV_ERROR eError;
+
+	eError = PVRSRVSyncFreeEventKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge), ui32FWAddr);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncCheckpointSignalledPDumpPol(IMG_HANDLE hBridge,
+								PVRSRV_FENCE hFence)
+{
+#if defined(PDUMP)
+	PVRSRV_ERROR eError;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	eError = PVRSRVSyncCheckpointSignalledPDumpPolKM(hFence);
+
+	return eError;
+#else
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+	PVR_UNREFERENCED_PARAMETER(hFence);
+
+	return PVRSRV_ERROR_NOT_IMPLEMENTED;
+#endif
+}

drivers/gpu/drm/img-rogue/client_synctracking_bridge.h

@@ -0,0 +1,68 @@
+/*******************************************************************************
+@File
+@Title          Client bridge header for synctracking
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Exports the client bridge functions for synctracking
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef CLIENT_SYNCTRACKING_BRIDGE_H
+#define CLIENT_SYNCTRACKING_BRIDGE_H
+
+#include "img_defs.h"
+#include "pvrsrv_error.h"
+
+#if defined(PVR_INDIRECT_BRIDGE_CLIENTS)
+#include "pvr_bridge_client.h"
+#include "pvr_bridge.h"
+#endif
+
+#include "common_synctracking_bridge.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncRecordRemoveByHandle(IMG_HANDLE hBridge, IMG_HANDLE hhRecord);
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncRecordAdd(IMG_HANDLE hBridge,
+					      IMG_HANDLE * phhRecord,
+					      IMG_HANDLE hhServerSyncPrimBlock,
+					      IMG_UINT32 ui32ui32FwBlockAddr,
+					      IMG_UINT32 ui32ui32SyncOffset,
+					      IMG_BOOL bbServerSync,
+					      IMG_UINT32 ui32ClassNameSize,
+					      const IMG_CHAR * puiClassName);
+
+#endif /* CLIENT_SYNCTRACKING_BRIDGE_H */

drivers/gpu/drm/img-rogue/client_synctracking_direct_bridge.c

@@ -0,0 +1,92 @@
+/*******************************************************************************
+@File
+@Title          Direct client bridge for synctracking
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Implements the client side of the bridge for synctracking
+                which is used in calls from Server context.
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#include "client_synctracking_bridge.h"
+#include "img_defs.h"
+#include "pvr_debug.h"
+
+/* Module specific includes */
+
+#include "sync.h"
+#include "sync_server.h"
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncRecordRemoveByHandle(IMG_HANDLE hBridge, IMG_HANDLE hhRecord)
+{
+	PVRSRV_ERROR eError;
+	SYNC_RECORD_HANDLE pshRecordInt;
+	PVR_UNREFERENCED_PARAMETER(hBridge);
+
+	pshRecordInt = (SYNC_RECORD_HANDLE) hhRecord;
+
+	eError = PVRSRVSyncRecordRemoveByHandleKM(pshRecordInt);
+
+	return eError;
+}
+
+IMG_INTERNAL PVRSRV_ERROR BridgeSyncRecordAdd(IMG_HANDLE hBridge,
+					      IMG_HANDLE * phhRecord,
+					      IMG_HANDLE hhServerSyncPrimBlock,
+					      IMG_UINT32 ui32ui32FwBlockAddr,
+					      IMG_UINT32 ui32ui32SyncOffset,
+					      IMG_BOOL bbServerSync,
+					      IMG_UINT32 ui32ClassNameSize,
+					      const IMG_CHAR * puiClassName)
+{
+	PVRSRV_ERROR eError;
+	SYNC_RECORD_HANDLE pshRecordInt = NULL;
+	SYNC_PRIMITIVE_BLOCK *pshServerSyncPrimBlockInt;
+
+	pshServerSyncPrimBlockInt = (SYNC_PRIMITIVE_BLOCK *) hhServerSyncPrimBlock;
+
+	eError =
+	    PVRSRVSyncRecordAddKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
+				  &pshRecordInt,
+				  pshServerSyncPrimBlockInt,
+				  ui32ui32FwBlockAddr,
+				  ui32ui32SyncOffset,
+				  bbServerSync, ui32ClassNameSize, puiClassName);
+
+	*phhRecord = pshRecordInt;
+	return eError;
+}

drivers/gpu/drm/img-rogue/common_cache_bridge.h

@@ -0,0 +1,126 @@
+/*******************************************************************************
+@File
+@Title          Common bridge header for cache
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Declares common defines and structures used by both the client
+                and server side of the bridge for cache
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef COMMON_CACHE_BRIDGE_H
+#define COMMON_CACHE_BRIDGE_H
+
+#include <powervr/mem_types.h>
+
+#include "img_defs.h"
+#include "img_types.h"
+#include "pvrsrv_error.h"
+
+#include "cache_ops.h"
+
+#define PVRSRV_BRIDGE_CACHE_CMD_FIRST			0
+#define PVRSRV_BRIDGE_CACHE_CACHEOPQUEUE			PVRSRV_BRIDGE_CACHE_CMD_FIRST+0
+#define PVRSRV_BRIDGE_CACHE_CACHEOPEXEC			PVRSRV_BRIDGE_CACHE_CMD_FIRST+1
+#define PVRSRV_BRIDGE_CACHE_CACHEOPLOG			PVRSRV_BRIDGE_CACHE_CMD_FIRST+2
+#define PVRSRV_BRIDGE_CACHE_CMD_LAST			(PVRSRV_BRIDGE_CACHE_CMD_FIRST+2)
+
+/*******************************************
+            CacheOpQueue
+ *******************************************/
+
+/* Bridge in structure for CacheOpQueue */
+typedef struct PVRSRV_BRIDGE_IN_CACHEOPQUEUE_TAG
+{
+	PVRSRV_CACHE_OP *piuCacheOp;
+	IMG_UINT64 *pui64Address;
+	IMG_DEVMEM_OFFSET_T *puiOffset;
+	IMG_DEVMEM_SIZE_T *puiSize;
+	IMG_HANDLE *phPMR;
+	IMG_UINT32 ui32NumCacheOps;
+	IMG_UINT32 ui32OpTimeline;
+} __packed PVRSRV_BRIDGE_IN_CACHEOPQUEUE;
+
+/* Bridge out structure for CacheOpQueue */
+typedef struct PVRSRV_BRIDGE_OUT_CACHEOPQUEUE_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_CACHEOPQUEUE;
+
+/*******************************************
+            CacheOpExec
+ *******************************************/
+
+/* Bridge in structure for CacheOpExec */
+typedef struct PVRSRV_BRIDGE_IN_CACHEOPEXEC_TAG
+{
+	IMG_UINT64 ui64Address;
+	IMG_DEVMEM_OFFSET_T uiOffset;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hPMR;
+	PVRSRV_CACHE_OP iuCacheOp;
+} __packed PVRSRV_BRIDGE_IN_CACHEOPEXEC;
+
+/* Bridge out structure for CacheOpExec */
+typedef struct PVRSRV_BRIDGE_OUT_CACHEOPEXEC_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_CACHEOPEXEC;
+
+/*******************************************
+            CacheOpLog
+ *******************************************/
+
+/* Bridge in structure for CacheOpLog */
+typedef struct PVRSRV_BRIDGE_IN_CACHEOPLOG_TAG
+{
+	IMG_INT64 i64EndTime;
+	IMG_INT64 i64StartTime;
+	IMG_UINT64 ui64Address;
+	IMG_DEVMEM_OFFSET_T uiOffset;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hPMR;
+	PVRSRV_CACHE_OP iuCacheOp;
+} __packed PVRSRV_BRIDGE_IN_CACHEOPLOG;
+
+/* Bridge out structure for CacheOpLog */
+typedef struct PVRSRV_BRIDGE_OUT_CACHEOPLOG_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_CACHEOPLOG;
+
+#endif /* COMMON_CACHE_BRIDGE_H */

drivers/gpu/drm/img-rogue/common_cmm_bridge.h

@@ -0,0 +1,114 @@
+/*******************************************************************************
+@File
+@Title          Common bridge header for cmm
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Declares common defines and structures used by both the client
+                and server side of the bridge for cmm
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef COMMON_CMM_BRIDGE_H
+#define COMMON_CMM_BRIDGE_H
+
+#include <powervr/mem_types.h>
+
+#include "img_defs.h"
+#include "img_types.h"
+#include "pvrsrv_error.h"
+
+#include "devicemem_typedefs.h"
+
+#define PVRSRV_BRIDGE_CMM_CMD_FIRST			0
+#define PVRSRV_BRIDGE_CMM_DEVMEMINTEXPORTCTX			PVRSRV_BRIDGE_CMM_CMD_FIRST+0
+#define PVRSRV_BRIDGE_CMM_DEVMEMINTUNEXPORTCTX			PVRSRV_BRIDGE_CMM_CMD_FIRST+1
+#define PVRSRV_BRIDGE_CMM_DEVMEMINTACQUIREREMOTECTX			PVRSRV_BRIDGE_CMM_CMD_FIRST+2
+#define PVRSRV_BRIDGE_CMM_CMD_LAST			(PVRSRV_BRIDGE_CMM_CMD_FIRST+2)
+
+/*******************************************
+            DevmemIntExportCtx
+ *******************************************/
+
+/* Bridge in structure for DevmemIntExportCtx */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTEXPORTCTX_TAG
+{
+	IMG_HANDLE hContext;
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTEXPORTCTX;
+
+/* Bridge out structure for DevmemIntExportCtx */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTEXPORTCTX_TAG
+{
+	IMG_HANDLE hContextExport;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTEXPORTCTX;
+
+/*******************************************
+            DevmemIntUnexportCtx
+ *******************************************/
+
+/* Bridge in structure for DevmemIntUnexportCtx */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTUNEXPORTCTX_TAG
+{
+	IMG_HANDLE hContextExport;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTUNEXPORTCTX;
+
+/* Bridge out structure for DevmemIntUnexportCtx */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTUNEXPORTCTX_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTUNEXPORTCTX;
+
+/*******************************************
+            DevmemIntAcquireRemoteCtx
+ *******************************************/
+
+/* Bridge in structure for DevmemIntAcquireRemoteCtx */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTACQUIREREMOTECTX_TAG
+{
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTACQUIREREMOTECTX;
+
+/* Bridge out structure for DevmemIntAcquireRemoteCtx */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTACQUIREREMOTECTX_TAG
+{
+	IMG_HANDLE hContext;
+	IMG_HANDLE hPrivData;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTACQUIREREMOTECTX;
+
+#endif /* COMMON_CMM_BRIDGE_H */

drivers/gpu/drm/img-rogue/common_devicememhistory_bridge.h

@@ -0,0 +1,185 @@
+/*******************************************************************************
+@File
+@Title          Common bridge header for devicememhistory
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Declares common defines and structures used by both the client
+                and server side of the bridge for devicememhistory
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef COMMON_DEVICEMEMHISTORY_BRIDGE_H
+#define COMMON_DEVICEMEMHISTORY_BRIDGE_H
+
+#include <powervr/mem_types.h>
+
+#include "img_defs.h"
+#include "img_types.h"
+#include "pvrsrv_error.h"
+
+#include "img_types.h"
+#include "img_defs.h"
+#include "devicemem_typedefs.h"
+
+#define PVRSRV_BRIDGE_DEVICEMEMHISTORY_CMD_FIRST			0
+#define PVRSRV_BRIDGE_DEVICEMEMHISTORY_DEVICEMEMHISTORYMAP			PVRSRV_BRIDGE_DEVICEMEMHISTORY_CMD_FIRST+0
+#define PVRSRV_BRIDGE_DEVICEMEMHISTORY_DEVICEMEMHISTORYUNMAP			PVRSRV_BRIDGE_DEVICEMEMHISTORY_CMD_FIRST+1
+#define PVRSRV_BRIDGE_DEVICEMEMHISTORY_DEVICEMEMHISTORYMAPVRANGE			PVRSRV_BRIDGE_DEVICEMEMHISTORY_CMD_FIRST+2
+#define PVRSRV_BRIDGE_DEVICEMEMHISTORY_DEVICEMEMHISTORYUNMAPVRANGE			PVRSRV_BRIDGE_DEVICEMEMHISTORY_CMD_FIRST+3
+#define PVRSRV_BRIDGE_DEVICEMEMHISTORY_DEVICEMEMHISTORYSPARSECHANGE			PVRSRV_BRIDGE_DEVICEMEMHISTORY_CMD_FIRST+4
+#define PVRSRV_BRIDGE_DEVICEMEMHISTORY_CMD_LAST			(PVRSRV_BRIDGE_DEVICEMEMHISTORY_CMD_FIRST+4)
+
+/*******************************************
+            DevicememHistoryMap
+ *******************************************/
+
+/* Bridge in structure for DevicememHistoryMap */
+typedef struct PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYMAP_TAG
+{
+	IMG_DEV_VIRTADDR sDevVAddr;
+	IMG_DEVMEM_SIZE_T uiOffset;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hPMR;
+	const IMG_CHAR *puiText;
+	IMG_UINT32 ui32AllocationIndex;
+	IMG_UINT32 ui32Log2PageSize;
+} __packed PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYMAP;
+
+/* Bridge out structure for DevicememHistoryMap */
+typedef struct PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYMAP_TAG
+{
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32AllocationIndexOut;
+} __packed PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYMAP;
+
+/*******************************************
+            DevicememHistoryUnmap
+ *******************************************/
+
+/* Bridge in structure for DevicememHistoryUnmap */
+typedef struct PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYUNMAP_TAG
+{
+	IMG_DEV_VIRTADDR sDevVAddr;
+	IMG_DEVMEM_SIZE_T uiOffset;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hPMR;
+	const IMG_CHAR *puiText;
+	IMG_UINT32 ui32AllocationIndex;
+	IMG_UINT32 ui32Log2PageSize;
+} __packed PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYUNMAP;
+
+/* Bridge out structure for DevicememHistoryUnmap */
+typedef struct PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYUNMAP_TAG
+{
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32AllocationIndexOut;
+} __packed PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYUNMAP;
+
+/*******************************************
+            DevicememHistoryMapVRange
+ *******************************************/
+
+/* Bridge in structure for DevicememHistoryMapVRange */
+typedef struct PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYMAPVRANGE_TAG
+{
+	IMG_DEV_VIRTADDR sBaseDevVAddr;
+	IMG_DEVMEM_SIZE_T uiAllocSize;
+	const IMG_CHAR *puiText;
+	IMG_UINT32 ui32AllocationIndex;
+	IMG_UINT32 ui32Log2PageSize;
+	IMG_UINT32 ui32NumPages;
+	IMG_UINT32 ui32ui32StartPage;
+} __packed PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYMAPVRANGE;
+
+/* Bridge out structure for DevicememHistoryMapVRange */
+typedef struct PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYMAPVRANGE_TAG
+{
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32AllocationIndexOut;
+} __packed PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYMAPVRANGE;
+
+/*******************************************
+            DevicememHistoryUnmapVRange
+ *******************************************/
+
+/* Bridge in structure for DevicememHistoryUnmapVRange */
+typedef struct PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYUNMAPVRANGE_TAG
+{
+	IMG_DEV_VIRTADDR sBaseDevVAddr;
+	IMG_DEVMEM_SIZE_T uiAllocSize;
+	const IMG_CHAR *puiText;
+	IMG_UINT32 ui32AllocationIndex;
+	IMG_UINT32 ui32Log2PageSize;
+	IMG_UINT32 ui32NumPages;
+	IMG_UINT32 ui32ui32StartPage;
+} __packed PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYUNMAPVRANGE;
+
+/* Bridge out structure for DevicememHistoryUnmapVRange */
+typedef struct PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYUNMAPVRANGE_TAG
+{
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32AllocationIndexOut;
+} __packed PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYUNMAPVRANGE;
+
+/*******************************************
+            DevicememHistorySparseChange
+ *******************************************/
+
+/* Bridge in structure for DevicememHistorySparseChange */
+typedef struct PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYSPARSECHANGE_TAG
+{
+	IMG_DEV_VIRTADDR sDevVAddr;
+	IMG_DEVMEM_SIZE_T uiOffset;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hPMR;
+	IMG_UINT32 *pui32AllocPageIndices;
+	IMG_UINT32 *pui32FreePageIndices;
+	const IMG_CHAR *puiText;
+	IMG_UINT32 ui32AllocPageCount;
+	IMG_UINT32 ui32AllocationIndex;
+	IMG_UINT32 ui32FreePageCount;
+	IMG_UINT32 ui32Log2PageSize;
+} __packed PVRSRV_BRIDGE_IN_DEVICEMEMHISTORYSPARSECHANGE;
+
+/* Bridge out structure for DevicememHistorySparseChange */
+typedef struct PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYSPARSECHANGE_TAG
+{
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32AllocationIndexOut;
+} __packed PVRSRV_BRIDGE_OUT_DEVICEMEMHISTORYSPARSECHANGE;
+
+#endif /* COMMON_DEVICEMEMHISTORY_BRIDGE_H */

drivers/gpu/drm/img-rogue/common_di_bridge.h

@@ -0,0 +1,153 @@
+/*******************************************************************************
+@File
+@Title          Common bridge header for di
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Declares common defines and structures used by both the client
+                and server side of the bridge for di
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef COMMON_DI_BRIDGE_H
+#define COMMON_DI_BRIDGE_H
+
+#include <powervr/mem_types.h>
+
+#include "img_defs.h"
+#include "img_types.h"
+#include "pvrsrv_error.h"
+
+#include "pvrsrv_tlcommon.h"
+#include "pvr_dicommon.h"
+
+#define PVRSRV_BRIDGE_DI_CMD_FIRST			0
+#define PVRSRV_BRIDGE_DI_DICREATECONTEXT			PVRSRV_BRIDGE_DI_CMD_FIRST+0
+#define PVRSRV_BRIDGE_DI_DIDESTROYCONTEXT			PVRSRV_BRIDGE_DI_CMD_FIRST+1
+#define PVRSRV_BRIDGE_DI_DIREADENTRY			PVRSRV_BRIDGE_DI_CMD_FIRST+2
+#define PVRSRV_BRIDGE_DI_DIWRITEENTRY			PVRSRV_BRIDGE_DI_CMD_FIRST+3
+#define PVRSRV_BRIDGE_DI_DILISTALLENTRIES			PVRSRV_BRIDGE_DI_CMD_FIRST+4
+#define PVRSRV_BRIDGE_DI_CMD_LAST			(PVRSRV_BRIDGE_DI_CMD_FIRST+4)
+
+/*******************************************
+            DICreateContext
+ *******************************************/
+
+/* Bridge in structure for DICreateContext */
+typedef struct PVRSRV_BRIDGE_IN_DICREATECONTEXT_TAG
+{
+	IMG_CHAR *puiStreamName;
+} __packed PVRSRV_BRIDGE_IN_DICREATECONTEXT;
+
+/* Bridge out structure for DICreateContext */
+typedef struct PVRSRV_BRIDGE_OUT_DICREATECONTEXT_TAG
+{
+	IMG_HANDLE hContext;
+	IMG_CHAR *puiStreamName;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DICREATECONTEXT;
+
+/*******************************************
+            DIDestroyContext
+ *******************************************/
+
+/* Bridge in structure for DIDestroyContext */
+typedef struct PVRSRV_BRIDGE_IN_DIDESTROYCONTEXT_TAG
+{
+	IMG_HANDLE hContext;
+} __packed PVRSRV_BRIDGE_IN_DIDESTROYCONTEXT;
+
+/* Bridge out structure for DIDestroyContext */
+typedef struct PVRSRV_BRIDGE_OUT_DIDESTROYCONTEXT_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DIDESTROYCONTEXT;
+
+/*******************************************
+            DIReadEntry
+ *******************************************/
+
+/* Bridge in structure for DIReadEntry */
+typedef struct PVRSRV_BRIDGE_IN_DIREADENTRY_TAG
+{
+	IMG_UINT64 ui64Offset;
+	IMG_UINT64 ui64Size;
+	IMG_HANDLE hContext;
+	const IMG_CHAR *puiEntryPath;
+} __packed PVRSRV_BRIDGE_IN_DIREADENTRY;
+
+/* Bridge out structure for DIReadEntry */
+typedef struct PVRSRV_BRIDGE_OUT_DIREADENTRY_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DIREADENTRY;
+
+/*******************************************
+            DIWriteEntry
+ *******************************************/
+
+/* Bridge in structure for DIWriteEntry */
+typedef struct PVRSRV_BRIDGE_IN_DIWRITEENTRY_TAG
+{
+	IMG_HANDLE hContext;
+	const IMG_CHAR *puiEntryPath;
+	const IMG_CHAR *puiValue;
+	IMG_UINT32 ui32ValueSize;
+} __packed PVRSRV_BRIDGE_IN_DIWRITEENTRY;
+
+/* Bridge out structure for DIWriteEntry */
+typedef struct PVRSRV_BRIDGE_OUT_DIWRITEENTRY_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DIWRITEENTRY;
+
+/*******************************************
+            DIListAllEntries
+ *******************************************/
+
+/* Bridge in structure for DIListAllEntries */
+typedef struct PVRSRV_BRIDGE_IN_DILISTALLENTRIES_TAG
+{
+	IMG_HANDLE hContext;
+} __packed PVRSRV_BRIDGE_IN_DILISTALLENTRIES;
+
+/* Bridge out structure for DIListAllEntries */
+typedef struct PVRSRV_BRIDGE_OUT_DILISTALLENTRIES_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DILISTALLENTRIES;
+
+#endif /* COMMON_DI_BRIDGE_H */

drivers/gpu/drm/img-rogue/common_dmabuf_bridge.h

@@ -0,0 +1,150 @@
+/*******************************************************************************
+@File
+@Title          Common bridge header for dmabuf
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Declares common defines and structures used by both the client
+                and server side of the bridge for dmabuf
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef COMMON_DMABUF_BRIDGE_H
+#define COMMON_DMABUF_BRIDGE_H
+
+#include <powervr/mem_types.h>
+
+#include "img_defs.h"
+#include "img_types.h"
+#include "pvrsrv_error.h"
+
+#include "pvrsrv_memallocflags.h"
+
+#define PVRSRV_BRIDGE_DMABUF_CMD_FIRST			0
+#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUF			PVRSRV_BRIDGE_DMABUF_CMD_FIRST+0
+#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUFLOCKED			PVRSRV_BRIDGE_DMABUF_CMD_FIRST+1
+#define PVRSRV_BRIDGE_DMABUF_PHYSMEMEXPORTDMABUF			PVRSRV_BRIDGE_DMABUF_CMD_FIRST+2
+#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTSPARSEDMABUF			PVRSRV_BRIDGE_DMABUF_CMD_FIRST+3
+#define PVRSRV_BRIDGE_DMABUF_CMD_LAST			(PVRSRV_BRIDGE_DMABUF_CMD_FIRST+3)
+
+/*******************************************
+            PhysmemImportDmaBuf
+ *******************************************/
+
+/* Bridge in structure for PhysmemImportDmaBuf */
+typedef struct PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUF_TAG
+{
+	const IMG_CHAR *puiName;
+	IMG_INT ifd;
+	IMG_UINT32 ui32NameSize;
+	PVRSRV_MEMALLOCFLAGS_T uiFlags;
+} __packed PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUF;
+
+/* Bridge out structure for PhysmemImportDmaBuf */
+typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUF_TAG
+{
+	IMG_DEVMEM_ALIGN_T uiAlign;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hPMRPtr;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUF;
+
+/*******************************************
+            PhysmemImportDmaBufLocked
+ *******************************************/
+
+/* Bridge in structure for PhysmemImportDmaBufLocked */
+typedef struct PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED_TAG
+{
+	const IMG_CHAR *puiName;
+	IMG_INT ifd;
+	IMG_UINT32 ui32NameSize;
+	PVRSRV_MEMALLOCFLAGS_T uiFlags;
+} __packed PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED;
+
+/* Bridge out structure for PhysmemImportDmaBufLocked */
+typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED_TAG
+{
+	IMG_DEVMEM_ALIGN_T uiAlign;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hPMRPtr;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED;
+
+/*******************************************
+            PhysmemExportDmaBuf
+ *******************************************/
+
+/* Bridge in structure for PhysmemExportDmaBuf */
+typedef struct PVRSRV_BRIDGE_IN_PHYSMEMEXPORTDMABUF_TAG
+{
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_PHYSMEMEXPORTDMABUF;
+
+/* Bridge out structure for PhysmemExportDmaBuf */
+typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMEXPORTDMABUF_TAG
+{
+	PVRSRV_ERROR eError;
+	IMG_INT iFd;
+} __packed PVRSRV_BRIDGE_OUT_PHYSMEMEXPORTDMABUF;
+
+/*******************************************
+            PhysmemImportSparseDmaBuf
+ *******************************************/
+
+/* Bridge in structure for PhysmemImportSparseDmaBuf */
+typedef struct PVRSRV_BRIDGE_IN_PHYSMEMIMPORTSPARSEDMABUF_TAG
+{
+	IMG_DEVMEM_SIZE_T uiChunkSize;
+	IMG_UINT32 *pui32MappingTable;
+	const IMG_CHAR *puiName;
+	IMG_INT ifd;
+	IMG_UINT32 ui32NameSize;
+	IMG_UINT32 ui32NumPhysChunks;
+	IMG_UINT32 ui32NumVirtChunks;
+	PVRSRV_MEMALLOCFLAGS_T uiFlags;
+} __packed PVRSRV_BRIDGE_IN_PHYSMEMIMPORTSPARSEDMABUF;
+
+/* Bridge out structure for PhysmemImportSparseDmaBuf */
+typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTSPARSEDMABUF_TAG
+{
+	IMG_DEVMEM_ALIGN_T uiAlign;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hPMRPtr;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTSPARSEDMABUF;
+
+#endif /* COMMON_DMABUF_BRIDGE_H */

drivers/gpu/drm/img-rogue/common_htbuffer_bridge.h

@@ -0,0 +1,104 @@
+/*******************************************************************************
+@File
+@Title          Common bridge header for htbuffer
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Declares common defines and structures used by both the client
+                and server side of the bridge for htbuffer
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef COMMON_HTBUFFER_BRIDGE_H
+#define COMMON_HTBUFFER_BRIDGE_H
+
+#include <powervr/mem_types.h>
+
+#include "img_defs.h"
+#include "img_types.h"
+#include "pvrsrv_error.h"
+
+#include "devicemem_typedefs.h"
+#include "htbuffer_types.h"
+
+#define PVRSRV_BRIDGE_HTBUFFER_CMD_FIRST			0
+#define PVRSRV_BRIDGE_HTBUFFER_HTBCONTROL			PVRSRV_BRIDGE_HTBUFFER_CMD_FIRST+0
+#define PVRSRV_BRIDGE_HTBUFFER_HTBLOG			PVRSRV_BRIDGE_HTBUFFER_CMD_FIRST+1
+#define PVRSRV_BRIDGE_HTBUFFER_CMD_LAST			(PVRSRV_BRIDGE_HTBUFFER_CMD_FIRST+1)
+
+/*******************************************
+            HTBControl
+ *******************************************/
+
+/* Bridge in structure for HTBControl */
+typedef struct PVRSRV_BRIDGE_IN_HTBCONTROL_TAG
+{
+	IMG_UINT32 *pui32GroupEnable;
+	IMG_UINT32 ui32EnablePID;
+	IMG_UINT32 ui32LogLevel;
+	IMG_UINT32 ui32LogMode;
+	IMG_UINT32 ui32NumGroups;
+	IMG_UINT32 ui32OpMode;
+} __packed PVRSRV_BRIDGE_IN_HTBCONTROL;
+
+/* Bridge out structure for HTBControl */
+typedef struct PVRSRV_BRIDGE_OUT_HTBCONTROL_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_HTBCONTROL;
+
+/*******************************************
+            HTBLog
+ *******************************************/
+
+/* Bridge in structure for HTBLog */
+typedef struct PVRSRV_BRIDGE_IN_HTBLOG_TAG
+{
+	IMG_UINT64 ui64TimeStamp;
+	IMG_UINT32 *pui32Args;
+	IMG_UINT32 ui32NumArgs;
+	IMG_UINT32 ui32PID;
+	IMG_UINT32 ui32SF;
+	IMG_UINT32 ui32TID;
+} __packed PVRSRV_BRIDGE_IN_HTBLOG;
+
+/* Bridge out structure for HTBLog */
+typedef struct PVRSRV_BRIDGE_OUT_HTBLOG_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_HTBLOG;
+
+#endif /* COMMON_HTBUFFER_BRIDGE_H */

drivers/gpu/drm/img-rogue/common_mm_bridge.h

@@ -0,0 +1,879 @@
+/*******************************************************************************
+@File
+@Title          Common bridge header for mm
+@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
+@Description    Declares common defines and structures used by both the client
+                and server side of the bridge for mm
+@License        Dual MIT/GPLv2
+
+The contents of this file are subject to the MIT license as set out below.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+Alternatively, the contents of this file may be used under the terms of
+the GNU General Public License Version 2 ("GPL") in which case the provisions
+of GPL are applicable instead of those above.
+
+If you wish to allow use of your version of this file only under the terms of
+GPL, and not to allow others to use your version of this file under the terms
+of the MIT license, indicate your decision by deleting the provisions above
+and replace them with the notice and other provisions required by GPL as set
+out in the file called "GPL-COPYING" included in this distribution. If you do
+not delete the provisions above, a recipient may use your version of this file
+under the terms of either the MIT license or GPL.
+
+This License is also included in this distribution in the file called
+"MIT-COPYING".
+
+EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
+#ifndef COMMON_MM_BRIDGE_H
+#define COMMON_MM_BRIDGE_H
+
+#include <powervr/mem_types.h>
+
+#include "img_defs.h"
+#include "img_types.h"
+#include "pvrsrv_error.h"
+
+#include "pvrsrv_memallocflags.h"
+#include "pvrsrv_memalloc_physheap.h"
+#include "devicemem_typedefs.h"
+
+#define PVRSRV_BRIDGE_MM_CMD_FIRST			0
+#define PVRSRV_BRIDGE_MM_PMREXPORTPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+0
+#define PVRSRV_BRIDGE_MM_PMRUNEXPORTPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+1
+#define PVRSRV_BRIDGE_MM_PMRGETUID			PVRSRV_BRIDGE_MM_CMD_FIRST+2
+#define PVRSRV_BRIDGE_MM_PMRMAKELOCALIMPORTHANDLE			PVRSRV_BRIDGE_MM_CMD_FIRST+3
+#define PVRSRV_BRIDGE_MM_PMRUNMAKELOCALIMPORTHANDLE			PVRSRV_BRIDGE_MM_CMD_FIRST+4
+#define PVRSRV_BRIDGE_MM_PMRIMPORTPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+5
+#define PVRSRV_BRIDGE_MM_PMRLOCALIMPORTPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+6
+#define PVRSRV_BRIDGE_MM_PMRUNREFPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+7
+#define PVRSRV_BRIDGE_MM_PMRUNREFUNLOCKPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+8
+#define PVRSRV_BRIDGE_MM_PHYSMEMNEWRAMBACKEDPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+9
+#define PVRSRV_BRIDGE_MM_PHYSMEMNEWRAMBACKEDLOCKEDPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+10
+#define PVRSRV_BRIDGE_MM_DEVMEMINTPIN			PVRSRV_BRIDGE_MM_CMD_FIRST+11
+#define PVRSRV_BRIDGE_MM_DEVMEMINTUNPIN			PVRSRV_BRIDGE_MM_CMD_FIRST+12
+#define PVRSRV_BRIDGE_MM_DEVMEMINTPINVALIDATE			PVRSRV_BRIDGE_MM_CMD_FIRST+13
+#define PVRSRV_BRIDGE_MM_DEVMEMINTUNPININVALIDATE			PVRSRV_BRIDGE_MM_CMD_FIRST+14
+#define PVRSRV_BRIDGE_MM_DEVMEMINTCTXCREATE			PVRSRV_BRIDGE_MM_CMD_FIRST+15
+#define PVRSRV_BRIDGE_MM_DEVMEMINTCTXDESTROY			PVRSRV_BRIDGE_MM_CMD_FIRST+16
+#define PVRSRV_BRIDGE_MM_DEVMEMINTHEAPCREATE			PVRSRV_BRIDGE_MM_CMD_FIRST+17
+#define PVRSRV_BRIDGE_MM_DEVMEMINTHEAPDESTROY			PVRSRV_BRIDGE_MM_CMD_FIRST+18
+#define PVRSRV_BRIDGE_MM_DEVMEMINTMAPPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+19
+#define PVRSRV_BRIDGE_MM_DEVMEMINTUNMAPPMR			PVRSRV_BRIDGE_MM_CMD_FIRST+20
+#define PVRSRV_BRIDGE_MM_DEVMEMINTRESERVERANGE			PVRSRV_BRIDGE_MM_CMD_FIRST+21
+#define PVRSRV_BRIDGE_MM_DEVMEMINTUNRESERVERANGE			PVRSRV_BRIDGE_MM_CMD_FIRST+22
+#define PVRSRV_BRIDGE_MM_CHANGESPARSEMEM			PVRSRV_BRIDGE_MM_CMD_FIRST+23
+#define PVRSRV_BRIDGE_MM_DEVMEMINTMAPPAGES			PVRSRV_BRIDGE_MM_CMD_FIRST+24
+#define PVRSRV_BRIDGE_MM_DEVMEMINTUNMAPPAGES			PVRSRV_BRIDGE_MM_CMD_FIRST+25
+#define PVRSRV_BRIDGE_MM_DEVMEMISVDEVADDRVALID			PVRSRV_BRIDGE_MM_CMD_FIRST+26
+#define PVRSRV_BRIDGE_MM_DEVMEMFLUSHDEVSLCRANGE			PVRSRV_BRIDGE_MM_CMD_FIRST+27
+#define PVRSRV_BRIDGE_MM_DEVMEMINVALIDATEFBSCTABLE			PVRSRV_BRIDGE_MM_CMD_FIRST+28
+#define PVRSRV_BRIDGE_MM_HEAPCFGHEAPCONFIGCOUNT			PVRSRV_BRIDGE_MM_CMD_FIRST+29
+#define PVRSRV_BRIDGE_MM_HEAPCFGHEAPCOUNT			PVRSRV_BRIDGE_MM_CMD_FIRST+30
+#define PVRSRV_BRIDGE_MM_HEAPCFGHEAPCONFIGNAME			PVRSRV_BRIDGE_MM_CMD_FIRST+31
+#define PVRSRV_BRIDGE_MM_HEAPCFGHEAPDETAILS			PVRSRV_BRIDGE_MM_CMD_FIRST+32
+#define PVRSRV_BRIDGE_MM_DEVMEMINTREGISTERPFNOTIFYKM			PVRSRV_BRIDGE_MM_CMD_FIRST+33
+#define PVRSRV_BRIDGE_MM_GETMAXPHYSHEAPCOUNT			PVRSRV_BRIDGE_MM_CMD_FIRST+34
+#define PVRSRV_BRIDGE_MM_PHYSHEAPGETMEMINFO			PVRSRV_BRIDGE_MM_CMD_FIRST+35
+#define PVRSRV_BRIDGE_MM_GETDEFAULTPHYSICALHEAP			PVRSRV_BRIDGE_MM_CMD_FIRST+36
+#define PVRSRV_BRIDGE_MM_GETHEAPPHYSMEMUSAGE			PVRSRV_BRIDGE_MM_CMD_FIRST+37
+#define PVRSRV_BRIDGE_MM_DEVMEMGETFAULTADDRESS			PVRSRV_BRIDGE_MM_CMD_FIRST+38
+#define PVRSRV_BRIDGE_MM_PVRSRVUPDATEOOMSTATS			PVRSRV_BRIDGE_MM_CMD_FIRST+39
+#define PVRSRV_BRIDGE_MM_PHYSHEAPGETMEMINFOPKD			PVRSRV_BRIDGE_MM_CMD_FIRST+40
+#define PVRSRV_BRIDGE_MM_GETHEAPPHYSMEMUSAGEPKD			PVRSRV_BRIDGE_MM_CMD_FIRST+41
+#define PVRSRV_BRIDGE_MM_CMD_LAST			(PVRSRV_BRIDGE_MM_CMD_FIRST+41)
+
+/*******************************************
+            PMRExportPMR
+ *******************************************/
+
+/* Bridge in structure for PMRExportPMR */
+typedef struct PVRSRV_BRIDGE_IN_PMREXPORTPMR_TAG
+{
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_PMREXPORTPMR;
+
+/* Bridge out structure for PMRExportPMR */
+typedef struct PVRSRV_BRIDGE_OUT_PMREXPORTPMR_TAG
+{
+	IMG_UINT64 ui64Password;
+	IMG_UINT64 ui64Size;
+	IMG_HANDLE hPMRExport;
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32Log2Contig;
+} __packed PVRSRV_BRIDGE_OUT_PMREXPORTPMR;
+
+/*******************************************
+            PMRUnexportPMR
+ *******************************************/
+
+/* Bridge in structure for PMRUnexportPMR */
+typedef struct PVRSRV_BRIDGE_IN_PMRUNEXPORTPMR_TAG
+{
+	IMG_HANDLE hPMRExport;
+} __packed PVRSRV_BRIDGE_IN_PMRUNEXPORTPMR;
+
+/* Bridge out structure for PMRUnexportPMR */
+typedef struct PVRSRV_BRIDGE_OUT_PMRUNEXPORTPMR_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PMRUNEXPORTPMR;
+
+/*******************************************
+            PMRGetUID
+ *******************************************/
+
+/* Bridge in structure for PMRGetUID */
+typedef struct PVRSRV_BRIDGE_IN_PMRGETUID_TAG
+{
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_PMRGETUID;
+
+/* Bridge out structure for PMRGetUID */
+typedef struct PVRSRV_BRIDGE_OUT_PMRGETUID_TAG
+{
+	IMG_UINT64 ui64UID;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PMRGETUID;
+
+/*******************************************
+            PMRMakeLocalImportHandle
+ *******************************************/
+
+/* Bridge in structure for PMRMakeLocalImportHandle */
+typedef struct PVRSRV_BRIDGE_IN_PMRMAKELOCALIMPORTHANDLE_TAG
+{
+	IMG_HANDLE hBuffer;
+} __packed PVRSRV_BRIDGE_IN_PMRMAKELOCALIMPORTHANDLE;
+
+/* Bridge out structure for PMRMakeLocalImportHandle */
+typedef struct PVRSRV_BRIDGE_OUT_PMRMAKELOCALIMPORTHANDLE_TAG
+{
+	IMG_HANDLE hExtMem;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PMRMAKELOCALIMPORTHANDLE;
+
+/*******************************************
+            PMRUnmakeLocalImportHandle
+ *******************************************/
+
+/* Bridge in structure for PMRUnmakeLocalImportHandle */
+typedef struct PVRSRV_BRIDGE_IN_PMRUNMAKELOCALIMPORTHANDLE_TAG
+{
+	IMG_HANDLE hExtMem;
+} __packed PVRSRV_BRIDGE_IN_PMRUNMAKELOCALIMPORTHANDLE;
+
+/* Bridge out structure for PMRUnmakeLocalImportHandle */
+typedef struct PVRSRV_BRIDGE_OUT_PMRUNMAKELOCALIMPORTHANDLE_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PMRUNMAKELOCALIMPORTHANDLE;
+
+/*******************************************
+            PMRImportPMR
+ *******************************************/
+
+/* Bridge in structure for PMRImportPMR */
+typedef struct PVRSRV_BRIDGE_IN_PMRIMPORTPMR_TAG
+{
+	IMG_UINT64 ui64uiPassword;
+	IMG_UINT64 ui64uiSize;
+	IMG_HANDLE hPMRExport;
+	IMG_UINT32 ui32uiLog2Contig;
+} __packed PVRSRV_BRIDGE_IN_PMRIMPORTPMR;
+
+/* Bridge out structure for PMRImportPMR */
+typedef struct PVRSRV_BRIDGE_OUT_PMRIMPORTPMR_TAG
+{
+	IMG_HANDLE hPMR;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PMRIMPORTPMR;
+
+/*******************************************
+            PMRLocalImportPMR
+ *******************************************/
+
+/* Bridge in structure for PMRLocalImportPMR */
+typedef struct PVRSRV_BRIDGE_IN_PMRLOCALIMPORTPMR_TAG
+{
+	IMG_HANDLE hExtHandle;
+} __packed PVRSRV_BRIDGE_IN_PMRLOCALIMPORTPMR;
+
+/* Bridge out structure for PMRLocalImportPMR */
+typedef struct PVRSRV_BRIDGE_OUT_PMRLOCALIMPORTPMR_TAG
+{
+	IMG_DEVMEM_ALIGN_T uiAlign;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hPMR;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PMRLOCALIMPORTPMR;
+
+/*******************************************
+            PMRUnrefPMR
+ *******************************************/
+
+/* Bridge in structure for PMRUnrefPMR */
+typedef struct PVRSRV_BRIDGE_IN_PMRUNREFPMR_TAG
+{
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_PMRUNREFPMR;
+
+/* Bridge out structure for PMRUnrefPMR */
+typedef struct PVRSRV_BRIDGE_OUT_PMRUNREFPMR_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PMRUNREFPMR;
+
+/*******************************************
+            PMRUnrefUnlockPMR
+ *******************************************/
+
+/* Bridge in structure for PMRUnrefUnlockPMR */
+typedef struct PVRSRV_BRIDGE_IN_PMRUNREFUNLOCKPMR_TAG
+{
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_PMRUNREFUNLOCKPMR;
+
+/* Bridge out structure for PMRUnrefUnlockPMR */
+typedef struct PVRSRV_BRIDGE_OUT_PMRUNREFUNLOCKPMR_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PMRUNREFUNLOCKPMR;
+
+/*******************************************
+            PhysmemNewRamBackedPMR
+ *******************************************/
+
+/* Bridge in structure for PhysmemNewRamBackedPMR */
+typedef struct PVRSRV_BRIDGE_IN_PHYSMEMNEWRAMBACKEDPMR_TAG
+{
+	IMG_DEVMEM_SIZE_T uiChunkSize;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_UINT32 *pui32MappingTable;
+	const IMG_CHAR *puiAnnotation;
+	IMG_UINT32 ui32AnnotationLength;
+	IMG_UINT32 ui32Log2PageSize;
+	IMG_UINT32 ui32NumPhysChunks;
+	IMG_UINT32 ui32NumVirtChunks;
+	IMG_UINT32 ui32PDumpFlags;
+	IMG_PID ui32PID;
+	PVRSRV_MEMALLOCFLAGS_T uiFlags;
+} __packed PVRSRV_BRIDGE_IN_PHYSMEMNEWRAMBACKEDPMR;
+
+/* Bridge out structure for PhysmemNewRamBackedPMR */
+typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMNEWRAMBACKEDPMR_TAG
+{
+	IMG_HANDLE hPMRPtr;
+	PVRSRV_ERROR eError;
+	PVRSRV_MEMALLOCFLAGS_T uiOutFlags;
+} __packed PVRSRV_BRIDGE_OUT_PHYSMEMNEWRAMBACKEDPMR;
+
+/*******************************************
+            PhysmemNewRamBackedLockedPMR
+ *******************************************/
+
+/* Bridge in structure for PhysmemNewRamBackedLockedPMR */
+typedef struct PVRSRV_BRIDGE_IN_PHYSMEMNEWRAMBACKEDLOCKEDPMR_TAG
+{
+	IMG_DEVMEM_SIZE_T uiChunkSize;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_UINT32 *pui32MappingTable;
+	const IMG_CHAR *puiAnnotation;
+	IMG_UINT32 ui32AnnotationLength;
+	IMG_UINT32 ui32Log2PageSize;
+	IMG_UINT32 ui32NumPhysChunks;
+	IMG_UINT32 ui32NumVirtChunks;
+	IMG_UINT32 ui32PDumpFlags;
+	IMG_PID ui32PID;
+	PVRSRV_MEMALLOCFLAGS_T uiFlags;
+} __packed PVRSRV_BRIDGE_IN_PHYSMEMNEWRAMBACKEDLOCKEDPMR;
+
+/* Bridge out structure for PhysmemNewRamBackedLockedPMR */
+typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMNEWRAMBACKEDLOCKEDPMR_TAG
+{
+	IMG_HANDLE hPMRPtr;
+	PVRSRV_ERROR eError;
+	PVRSRV_MEMALLOCFLAGS_T uiOutFlags;
+} __packed PVRSRV_BRIDGE_OUT_PHYSMEMNEWRAMBACKEDLOCKEDPMR;
+
+/*******************************************
+            DevmemIntPin
+ *******************************************/
+
+/* Bridge in structure for DevmemIntPin */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTPIN_TAG
+{
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTPIN;
+
+/* Bridge out structure for DevmemIntPin */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTPIN_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTPIN;
+
+/*******************************************
+            DevmemIntUnpin
+ *******************************************/
+
+/* Bridge in structure for DevmemIntUnpin */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTUNPIN_TAG
+{
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTUNPIN;
+
+/* Bridge out structure for DevmemIntUnpin */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTUNPIN_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTUNPIN;
+
+/*******************************************
+            DevmemIntPinValidate
+ *******************************************/
+
+/* Bridge in structure for DevmemIntPinValidate */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTPINVALIDATE_TAG
+{
+	IMG_HANDLE hMapping;
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTPINVALIDATE;
+
+/* Bridge out structure for DevmemIntPinValidate */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTPINVALIDATE_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTPINVALIDATE;
+
+/*******************************************
+            DevmemIntUnpinInvalidate
+ *******************************************/
+
+/* Bridge in structure for DevmemIntUnpinInvalidate */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTUNPININVALIDATE_TAG
+{
+	IMG_HANDLE hMapping;
+	IMG_HANDLE hPMR;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTUNPININVALIDATE;
+
+/* Bridge out structure for DevmemIntUnpinInvalidate */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTUNPININVALIDATE_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTUNPININVALIDATE;
+
+/*******************************************
+            DevmemIntCtxCreate
+ *******************************************/
+
+/* Bridge in structure for DevmemIntCtxCreate */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTCTXCREATE_TAG
+{
+	IMG_BOOL bbKernelMemoryCtx;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTCTXCREATE;
+
+/* Bridge out structure for DevmemIntCtxCreate */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTCTXCREATE_TAG
+{
+	IMG_HANDLE hDevMemServerContext;
+	IMG_HANDLE hPrivData;
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32CPUCacheLineSize;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTCTXCREATE;
+
+/*******************************************
+            DevmemIntCtxDestroy
+ *******************************************/
+
+/* Bridge in structure for DevmemIntCtxDestroy */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTCTXDESTROY_TAG
+{
+	IMG_HANDLE hDevmemServerContext;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTCTXDESTROY;
+
+/* Bridge out structure for DevmemIntCtxDestroy */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTCTXDESTROY_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTCTXDESTROY;
+
+/*******************************************
+            DevmemIntHeapCreate
+ *******************************************/
+
+/* Bridge in structure for DevmemIntHeapCreate */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTHEAPCREATE_TAG
+{
+	IMG_DEV_VIRTADDR sHeapBaseAddr;
+	IMG_DEVMEM_SIZE_T uiHeapLength;
+	IMG_HANDLE hDevmemCtx;
+	IMG_UINT32 ui32Log2DataPageSize;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTHEAPCREATE;
+
+/* Bridge out structure for DevmemIntHeapCreate */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTHEAPCREATE_TAG
+{
+	IMG_HANDLE hDevmemHeapPtr;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTHEAPCREATE;
+
+/*******************************************
+            DevmemIntHeapDestroy
+ *******************************************/
+
+/* Bridge in structure for DevmemIntHeapDestroy */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTHEAPDESTROY_TAG
+{
+	IMG_HANDLE hDevmemHeap;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTHEAPDESTROY;
+
+/* Bridge out structure for DevmemIntHeapDestroy */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTHEAPDESTROY_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTHEAPDESTROY;
+
+/*******************************************
+            DevmemIntMapPMR
+ *******************************************/
+
+/* Bridge in structure for DevmemIntMapPMR */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTMAPPMR_TAG
+{
+	IMG_HANDLE hDevmemServerHeap;
+	IMG_HANDLE hPMR;
+	IMG_HANDLE hReservation;
+	PVRSRV_MEMALLOCFLAGS_T uiMapFlags;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTMAPPMR;
+
+/* Bridge out structure for DevmemIntMapPMR */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTMAPPMR_TAG
+{
+	IMG_HANDLE hMapping;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTMAPPMR;
+
+/*******************************************
+            DevmemIntUnmapPMR
+ *******************************************/
+
+/* Bridge in structure for DevmemIntUnmapPMR */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTUNMAPPMR_TAG
+{
+	IMG_HANDLE hMapping;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTUNMAPPMR;
+
+/* Bridge out structure for DevmemIntUnmapPMR */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTUNMAPPMR_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTUNMAPPMR;
+
+/*******************************************
+            DevmemIntReserveRange
+ *******************************************/
+
+/* Bridge in structure for DevmemIntReserveRange */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTRESERVERANGE_TAG
+{
+	IMG_DEV_VIRTADDR sAddress;
+	IMG_DEVMEM_SIZE_T uiLength;
+	IMG_HANDLE hDevmemServerHeap;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTRESERVERANGE;
+
+/* Bridge out structure for DevmemIntReserveRange */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTRESERVERANGE_TAG
+{
+	IMG_HANDLE hReservation;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTRESERVERANGE;
+
+/*******************************************
+            DevmemIntUnreserveRange
+ *******************************************/
+
+/* Bridge in structure for DevmemIntUnreserveRange */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTUNRESERVERANGE_TAG
+{
+	IMG_HANDLE hReservation;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTUNRESERVERANGE;
+
+/* Bridge out structure for DevmemIntUnreserveRange */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTUNRESERVERANGE_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTUNRESERVERANGE;
+
+/*******************************************
+            ChangeSparseMem
+ *******************************************/
+
+/* Bridge in structure for ChangeSparseMem */
+typedef struct PVRSRV_BRIDGE_IN_CHANGESPARSEMEM_TAG
+{
+	IMG_DEV_VIRTADDR sDevVAddr;
+	IMG_UINT64 ui64CPUVAddr;
+	IMG_HANDLE hPMR;
+	IMG_HANDLE hSrvDevMemHeap;
+	IMG_UINT32 *pui32AllocPageIndices;
+	IMG_UINT32 *pui32FreePageIndices;
+	IMG_UINT32 ui32AllocPageCount;
+	IMG_UINT32 ui32FreePageCount;
+	IMG_UINT32 ui32SparseFlags;
+	PVRSRV_MEMALLOCFLAGS_T uiFlags;
+} __packed PVRSRV_BRIDGE_IN_CHANGESPARSEMEM;
+
+/* Bridge out structure for ChangeSparseMem */
+typedef struct PVRSRV_BRIDGE_OUT_CHANGESPARSEMEM_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_CHANGESPARSEMEM;
+
+/*******************************************
+            DevmemIntMapPages
+ *******************************************/
+
+/* Bridge in structure for DevmemIntMapPages */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTMAPPAGES_TAG
+{
+	IMG_DEV_VIRTADDR sDevVAddr;
+	IMG_HANDLE hPMR;
+	IMG_HANDLE hReservation;
+	IMG_UINT32 ui32PageCount;
+	IMG_UINT32 ui32PhysicalPgOffset;
+	PVRSRV_MEMALLOCFLAGS_T uiFlags;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTMAPPAGES;
+
+/* Bridge out structure for DevmemIntMapPages */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTMAPPAGES_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTMAPPAGES;
+
+/*******************************************
+            DevmemIntUnmapPages
+ *******************************************/
+
+/* Bridge in structure for DevmemIntUnmapPages */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTUNMAPPAGES_TAG
+{
+	IMG_DEV_VIRTADDR sDevVAddr;
+	IMG_HANDLE hReservation;
+	IMG_UINT32 ui32PageCount;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTUNMAPPAGES;
+
+/* Bridge out structure for DevmemIntUnmapPages */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTUNMAPPAGES_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTUNMAPPAGES;
+
+/*******************************************
+            DevmemIsVDevAddrValid
+ *******************************************/
+
+/* Bridge in structure for DevmemIsVDevAddrValid */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMISVDEVADDRVALID_TAG
+{
+	IMG_DEV_VIRTADDR sAddress;
+	IMG_HANDLE hDevmemCtx;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMISVDEVADDRVALID;
+
+/* Bridge out structure for DevmemIsVDevAddrValid */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMISVDEVADDRVALID_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMISVDEVADDRVALID;
+
+/*******************************************
+            DevmemFlushDevSLCRange
+ *******************************************/
+
+/* Bridge in structure for DevmemFlushDevSLCRange */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMFLUSHDEVSLCRANGE_TAG
+{
+	IMG_DEV_VIRTADDR sAddress;
+	IMG_DEVMEM_SIZE_T uiSize;
+	IMG_HANDLE hDevmemCtx;
+	IMG_BOOL bInvalidate;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMFLUSHDEVSLCRANGE;
+
+/* Bridge out structure for DevmemFlushDevSLCRange */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMFLUSHDEVSLCRANGE_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMFLUSHDEVSLCRANGE;
+
+/*******************************************
+            DevmemInvalidateFBSCTable
+ *******************************************/
+
+/* Bridge in structure for DevmemInvalidateFBSCTable */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINVALIDATEFBSCTABLE_TAG
+{
+	IMG_UINT64 ui64FBSCEntries;
+	IMG_HANDLE hDevmemCtx;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINVALIDATEFBSCTABLE;
+
+/* Bridge out structure for DevmemInvalidateFBSCTable */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINVALIDATEFBSCTABLE_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINVALIDATEFBSCTABLE;
+
+/*******************************************
+            HeapCfgHeapConfigCount
+ *******************************************/
+
+/* Bridge in structure for HeapCfgHeapConfigCount */
+typedef struct PVRSRV_BRIDGE_IN_HEAPCFGHEAPCONFIGCOUNT_TAG
+{
+	IMG_UINT32 ui32EmptyStructPlaceholder;
+} __packed PVRSRV_BRIDGE_IN_HEAPCFGHEAPCONFIGCOUNT;
+
+/* Bridge out structure for HeapCfgHeapConfigCount */
+typedef struct PVRSRV_BRIDGE_OUT_HEAPCFGHEAPCONFIGCOUNT_TAG
+{
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32NumHeapConfigs;
+} __packed PVRSRV_BRIDGE_OUT_HEAPCFGHEAPCONFIGCOUNT;
+
+/*******************************************
+            HeapCfgHeapCount
+ *******************************************/
+
+/* Bridge in structure for HeapCfgHeapCount */
+typedef struct PVRSRV_BRIDGE_IN_HEAPCFGHEAPCOUNT_TAG
+{
+	IMG_UINT32 ui32HeapConfigIndex;
+} __packed PVRSRV_BRIDGE_IN_HEAPCFGHEAPCOUNT;
+
+/* Bridge out structure for HeapCfgHeapCount */
+typedef struct PVRSRV_BRIDGE_OUT_HEAPCFGHEAPCOUNT_TAG
+{
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32NumHeaps;
+} __packed PVRSRV_BRIDGE_OUT_HEAPCFGHEAPCOUNT;
+
+/*******************************************
+            HeapCfgHeapConfigName
+ *******************************************/
+
+/* Bridge in structure for HeapCfgHeapConfigName */
+typedef struct PVRSRV_BRIDGE_IN_HEAPCFGHEAPCONFIGNAME_TAG
+{
+	IMG_CHAR *puiHeapConfigName;
+	IMG_UINT32 ui32HeapConfigIndex;
+	IMG_UINT32 ui32HeapConfigNameBufSz;
+} __packed PVRSRV_BRIDGE_IN_HEAPCFGHEAPCONFIGNAME;
+
+/* Bridge out structure for HeapCfgHeapConfigName */
+typedef struct PVRSRV_BRIDGE_OUT_HEAPCFGHEAPCONFIGNAME_TAG
+{
+	IMG_CHAR *puiHeapConfigName;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_HEAPCFGHEAPCONFIGNAME;
+
+/*******************************************
+            HeapCfgHeapDetails
+ *******************************************/
+
+/* Bridge in structure for HeapCfgHeapDetails */
+typedef struct PVRSRV_BRIDGE_IN_HEAPCFGHEAPDETAILS_TAG
+{
+	IMG_CHAR *puiHeapNameOut;
+	IMG_UINT32 ui32HeapConfigIndex;
+	IMG_UINT32 ui32HeapIndex;
+	IMG_UINT32 ui32HeapNameBufSz;
+} __packed PVRSRV_BRIDGE_IN_HEAPCFGHEAPDETAILS;
+
+/* Bridge out structure for HeapCfgHeapDetails */
+typedef struct PVRSRV_BRIDGE_OUT_HEAPCFGHEAPDETAILS_TAG
+{
+	IMG_DEV_VIRTADDR sDevVAddrBase;
+	IMG_DEVMEM_SIZE_T uiHeapLength;
+	IMG_DEVMEM_SIZE_T uiReservedRegionLength;
+	IMG_CHAR *puiHeapNameOut;
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32Log2DataPageSizeOut;
+	IMG_UINT32 ui32Log2ImportAlignmentOut;
+} __packed PVRSRV_BRIDGE_OUT_HEAPCFGHEAPDETAILS;
+
+/*******************************************
+            DevmemIntRegisterPFNotifyKM
+ *******************************************/
+
+/* Bridge in structure for DevmemIntRegisterPFNotifyKM */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMINTREGISTERPFNOTIFYKM_TAG
+{
+	IMG_HANDLE hDevm;
+	IMG_BOOL bRegister;
+	IMG_UINT32 ui32PID;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMINTREGISTERPFNOTIFYKM;
+
+/* Bridge out structure for DevmemIntRegisterPFNotifyKM */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMINTREGISTERPFNOTIFYKM_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMINTREGISTERPFNOTIFYKM;
+
+/*******************************************
+            GetMaxPhysHeapCount
+ *******************************************/
+
+/* Bridge in structure for GetMaxPhysHeapCount */
+typedef struct PVRSRV_BRIDGE_IN_GETMAXPHYSHEAPCOUNT_TAG
+{
+	IMG_UINT32 ui32EmptyStructPlaceholder;
+} __packed PVRSRV_BRIDGE_IN_GETMAXPHYSHEAPCOUNT;
+
+/* Bridge out structure for GetMaxPhysHeapCount */
+typedef struct PVRSRV_BRIDGE_OUT_GETMAXPHYSHEAPCOUNT_TAG
+{
+	PVRSRV_ERROR eError;
+	IMG_UINT32 ui32PhysHeapCount;
+} __packed PVRSRV_BRIDGE_OUT_GETMAXPHYSHEAPCOUNT;
+
+/*******************************************
+            PhysHeapGetMemInfo
+ *******************************************/
+
+/* Bridge in structure for PhysHeapGetMemInfo */
+typedef struct PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFO_TAG
+{
+	PHYS_HEAP_MEM_STATS *pasapPhysHeapMemStats;
+	PVRSRV_PHYS_HEAP *peaPhysHeapID;
+	IMG_UINT32 ui32PhysHeapCount;
+} __packed PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFO;
+
+/* Bridge out structure for PhysHeapGetMemInfo */
+typedef struct PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFO_TAG
+{
+	PHYS_HEAP_MEM_STATS *pasapPhysHeapMemStats;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFO;
+
+/*******************************************
+            GetDefaultPhysicalHeap
+ *******************************************/
+
+/* Bridge in structure for GetDefaultPhysicalHeap */
+typedef struct PVRSRV_BRIDGE_IN_GETDEFAULTPHYSICALHEAP_TAG
+{
+	IMG_UINT32 ui32EmptyStructPlaceholder;
+} __packed PVRSRV_BRIDGE_IN_GETDEFAULTPHYSICALHEAP;
+
+/* Bridge out structure for GetDefaultPhysicalHeap */
+typedef struct PVRSRV_BRIDGE_OUT_GETDEFAULTPHYSICALHEAP_TAG
+{
+	PVRSRV_ERROR eError;
+	PVRSRV_PHYS_HEAP eHeap;
+} __packed PVRSRV_BRIDGE_OUT_GETDEFAULTPHYSICALHEAP;
+
+/*******************************************
+            GetHeapPhysMemUsage
+ *******************************************/
+
+/* Bridge in structure for GetHeapPhysMemUsage */
+typedef struct PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGE_TAG
+{
+	PHYS_HEAP_MEM_STATS *pasapPhysHeapMemStats;
+	IMG_UINT32 ui32PhysHeapCount;
+} __packed PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGE;
+
+/* Bridge out structure for GetHeapPhysMemUsage */
+typedef struct PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGE_TAG
+{
+	PHYS_HEAP_MEM_STATS *pasapPhysHeapMemStats;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGE;
+
+/*******************************************
+            DevmemGetFaultAddress
+ *******************************************/
+
+/* Bridge in structure for DevmemGetFaultAddress */
+typedef struct PVRSRV_BRIDGE_IN_DEVMEMGETFAULTADDRESS_TAG
+{
+	IMG_HANDLE hDevmemCtx;
+} __packed PVRSRV_BRIDGE_IN_DEVMEMGETFAULTADDRESS;
+
+/* Bridge out structure for DevmemGetFaultAddress */
+typedef struct PVRSRV_BRIDGE_OUT_DEVMEMGETFAULTADDRESS_TAG
+{
+	IMG_DEV_VIRTADDR sFaultAddress;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_DEVMEMGETFAULTADDRESS;
+
+/*******************************************
+            PVRSRVUpdateOOMStats
+ *******************************************/
+
+/* Bridge in structure for PVRSRVUpdateOOMStats */
+typedef struct PVRSRV_BRIDGE_IN_PVRSRVUPDATEOOMSTATS_TAG
+{
+	IMG_PID ui32pid;
+	IMG_UINT32 ui32ui32StatType;
+} __packed PVRSRV_BRIDGE_IN_PVRSRVUPDATEOOMSTATS;
+
+/* Bridge out structure for PVRSRVUpdateOOMStats */
+typedef struct PVRSRV_BRIDGE_OUT_PVRSRVUPDATEOOMSTATS_TAG
+{
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PVRSRVUPDATEOOMSTATS;
+
+/*******************************************
+            PhysHeapGetMemInfoPkd
+ *******************************************/
+
+/* Bridge in structure for PhysHeapGetMemInfoPkd */
+typedef struct PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFOPKD_TAG
+{
+	PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats;
+	PVRSRV_PHYS_HEAP *peaPhysHeapID;
+	IMG_UINT32 ui32PhysHeapCount;
+} __packed PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFOPKD;
+
+/* Bridge out structure for PhysHeapGetMemInfoPkd */
+typedef struct PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFOPKD_TAG
+{
+	PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFOPKD;
+
+/*******************************************
+            GetHeapPhysMemUsagePkd
+ *******************************************/
+
+/* Bridge in structure for GetHeapPhysMemUsagePkd */
+typedef struct PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGEPKD_TAG
+{
+	PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats;
+	IMG_UINT32 ui32PhysHeapCount;
+} __packed PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGEPKD;
+
+/* Bridge out structure for GetHeapPhysMemUsagePkd */
+typedef struct PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGEPKD_TAG
+{
+	PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats;
+	PVRSRV_ERROR eError;
+} __packed PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGEPKD;
+
+#endif /* COMMON_MM_BRIDGE_H */