Merge branch 'develop' into merging

Conflicts:
	src/bootldr/fileops.h
	src/bootldr/iap.c
	src/fpga_spi.c
	src/memory.c
	src/smc.c
	verilog/sd2snes/address.v

CHANGELOG

@@ -79,3 +79,18 @@ v0.1.4a (bugfix release)
 
  * Fix DMA initialization in the menu (could cause sprite corruption in some games)
 
+
+v0.1.5
+======
+
+ * Sort directories by entire file name instead of first 20 characters only
+ * Correctly map SRAM larger than 8192 bytes (HiROM) / 32768 bytes (LoROM)
+   (fixes Dezaemon, Ongaku Tsukuuru - Kanadeeru)
+ * SPC player: fix soft fade-in (first note cut off) on S-APU consoles
+   (1CHIP / some Jr.)
+ * More accurate BS-X memory map
+ * Ignore input from non-standard controllers (Super Scope, Mouse etc.)
+ * Fixes:
+   - minor memory access timing tweaks
+     (should help with occasional glitches on some systems)
+

snes/Makefile

@@ -1,4 +1,4 @@
-OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 spc700.o65 spcplay.o65 # gfx.o65 # vars.o65
+OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 filesel.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 spc700.o65 spcplay.o65 # gfx.o65 # vars.o65
 
 all: clean menu.bin map
 

snes/boot/const.a65

@@ -2,7 +2,8 @@ version		.byt "                            v0.1",0
 zero		.word	0
 bg2tile		.byt $20
 
-space64	.byt $20, $20, $20, $20, $20, $20, $20, $20
+space64	
+    .byt $20, $20, $20, $20, $20, $20, $20, $20
 	.byt $20, $20, $20, $20, $20, $20, $20, $20
 	.byt $20, $20, $20, $20, $20, $20, $20, $20
 	.byt $20, $20, $20, $20, $20, $20, $20, $20

snes/boot/data.a65

@@ -1,41 +1,43 @@
 .data
 ;don't anger the stack!
 ;----------parameters for text output----------
-print_x	.byt 0		;x coordinate
+print_x         .byt  0  ; x coordinate
-	.byt 0
+                .byt  0
-print_y	.byt 0		;y coordinate
+print_y         .byt  0  ; y coordinate
-	.byt 0
+                .byt  0
-print_src	.word 0	;source data address
+print_src       .word 0  ; source data address
-print_bank	.byt 0	;source data bank
+print_bank      .byt  0  ; source data bank
-print_pal	.word 0	;palette number for text output
+print_pal       .word 0  ; palette number for text output
-print_temp	.word 0 ;work variable
+print_temp      .word 0  ; work variable
-print_count	.byt 0	;how many characters may be printed?
+print_count     .byt  0  ; how many characters may be printed?
-print_count_tmp .byt 0	;work variable
+print_count_tmp .byt  0  ; work variable
-print_done	.word 0  ;how many characters were printed?
+print_done      .word 0  ; how many characters were printed?
 ;----------parameters for dma----------
-dma_a_bank	.byt 0
+dma_a_bank      .byt  0
-dma_a_addr	.word 0
+dma_a_addr      .word 0
-dma_b_reg	.byt 0
+dma_b_reg       .byt  0
-dma_len		.word 0
+dma_len         .word 0
-dma_mode	.byt 0
+dma_mode        .byt  0
 
 ;----------state information----------
-isr_done	.byt 0  ; isr done flag
+isr_done        .byt  0  ; isr done flag
 ;----------menu layout/system constants (224/448)
-textdmasize	.word 0 ; number of bytes to copy each frame
+textdmasize     .word 0 ; number of bytes to copy each frame
 
-infloop		.byt 0,0  ; to be filled w/ 80 FE
+infloop         .byt 0,0  ; to be filled w/ 80 FE
 
-printloop_wram	.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+printloop_wram 
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
 
-loprint_wram	.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+loprint_wram 
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

snes/boot/palette.a65

@@ -1,4 +1,4 @@
 palette
 ;fonts
 	.byt  $42, $08, $ff, $7f, $00, $00, $9c, $73
-        .byt  $42, $08, $ff, $43, $00, $00, $18, $63
+    .byt  $42, $08, $ff, $43, $00, $00, $18, $63

snes/boot/reset.a65

@@ -11,24 +11,24 @@
 
 ; NMI - called on VBlank
 NMI_ROUTINE:
-        sep #$20 : .as
+    sep #$20 : .as
-	rep #$10 : .xl
+    rep #$10 : .xl
-	lda #$00
+    lda #$00
-	pha
+    pha
-	plb
+    plb
-        lda $4210
+    lda $4210
 
-	ldx #BG1_TILE_BASE
+    ldx #BG1_TILE_BASE
-	stx $2116
+    stx $2116
-	DMA0(#$01, #36*64, #^BG1_TILE_BUF, #!BG1_TILE_BUF, #$18)
+    DMA0(#$01, #36*64, #^BG1_TILE_BUF, #!BG1_TILE_BUF, #$18)
 
-	lda #$01
+    lda #$01
-	sta isr_done
+    sta isr_done
-        rtl
+    rtl
 
 ; IRQ - called when triggered
 IRQ_ROUTINE:
-        sep #$20 : .as
+    sep #$20 : .as
-        lda $4211  ;Acknowledge irq
+    lda $4211  ;Acknowledge irq
-        rtl
+    rtl
 

snes/data.a65

@@ -45,9 +45,9 @@ bar_x		.byt 0	; pixel x position of select bar
 bar_y		.byt 0	; pixel y position of select bar
 bar_w		.byt 0	; bar width
 bar_wl		.byt 0	; bar width
-menu_state	.byt 0	; menu state (0=file select)
+filesel_state	.byt 0	; menu state (0=file select)
-menu_dirty	.byt 0	; menu dirty (e.g. after state change or when redraw is needed)
+filesel_dirty	.byt 0	; menu dirty (e.g. after state change or when redraw is needed)
-menu_sel	.word 0 ; selected item #
+filesel_sel	.word 0 ; selected item #
 cursor_x	.byt 0	; current cursor position (x)
 cursor_y	.byt 0  ; current cursor position (y)
 fd_addr		.word 0	; address of current "file descriptor"
@@ -96,6 +96,8 @@ barstep		.byt 0  ; step size for bar
 
 ;-misc
 testvar		.word 0,0,0,0
+;menu system
+menu_stack	.word 0,0,0,0,0,0,0,0
 ;----------hdma tables in WRAM (must be stable when cartridge is cut off)
 hdma_pal	.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
 		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

snes/filesel.a65

@@ -1,7 +1,7 @@
 #include "memmap.i65"
 #include "dma.i65"
 
-menu_init:
+filesel_init:
 	sep #$20 : .as
 	rep #$10 : .xl
 	lda #^ROOT_DIR
@@ -10,7 +10,7 @@ menu_init:
 	stx dirptr_addr
 	sta dirstart_bank
 	stx dirstart_addr
-	stz menu_state
+	stz filesel_state
 	stz dirend_onscreen
 	lda #$02
 	sta cursor_x
@@ -22,11 +22,11 @@ menu_init:
 	sta bar_wl
 	ldx #$0000
 	stx dirptr_idx
-	stx menu_sel
+	stx filesel_sel
 	stx direntry_xscroll
 	stx direntry_xscroll_state
 	lda #$01
-	sta menu_dirty
+	sta filesel_dirty
 	rep #$20 : .al
 	lda #!dirlog
 	sta dirlog_idx
@@ -35,39 +35,39 @@ menu_init:
 	sta dirlog_idx+2
 	rts
 
-menuloop:
+fileselloop:
-menuloop_s1
+fileselloop_s1
 	sep #$20 : .as
 	rep #$10 : .xl
 	lda isr_done
 	lsr
-	bcc menuloop_s1
+	bcc fileselloop_s1
 	stz isr_done
 	jsr printtime
-	jsr menu_updates	;update stuff, check keys etc
+	jsr filesel_updates	;update stuff, check keys etc
-	lda menu_dirty		;is there ANY reason to redraw the menu?
+	lda filesel_dirty		;is there ANY reason to redraw the menu?
 	cmp #$01
-	beq menuloop_redraw 	;then do
+	beq fileselloop_redraw 	;then do
 	jsr scroll_direntry
-	bra menuloop_s1
+	bra fileselloop_s1
-menuloop_redraw
+fileselloop_redraw
-	stz menu_dirty
+	stz filesel_dirty
-	jsr menu_statusbar
+	jsr filesel_statusbar
-	jsr menu_redraw
+	jsr filesel_redraw
-	jsr menu_cleanup	;update phase 2
+	jsr filesel_cleanup	;update phase 2
-	bra menuloop_s1
+	bra fileselloop_s1
 	rts
 
-menu_cleanup:
+filesel_cleanup:
 	sep #$20 : .as
 	rep #$10 : .xl
 	lda dirend_onscreen     ;end of file list on screen?
-	beq menu_cleanup_out    ;
+	beq filesel_cleanup_out    ;
 	lda dirend_idx
 	lsr
 	lsr
 	pha
-menu_cleanup_loop               ;pad rest of screen with empty lines
+filesel_cleanup_loop               ;pad rest of screen with empty lines
 	cmp listdisp            ;end of screen reached?
 	beq +                   ;then leave
 	pha
@@ -86,24 +86,24 @@ menu_cleanup_loop               ;pad rest of screen with empty lines
 	jsr hiprint
 	pla
 	inc
-	bra menu_cleanup_loop
+	bra filesel_cleanup_loop
 +
 	pla
-	cmp menu_sel
+	cmp filesel_sel
-	beq menu_cleanup_out
+	beq filesel_cleanup_out
-	bpl menu_cleanup_out
+	bpl filesel_cleanup_out
-	sta menu_sel
+	sta filesel_sel
-menu_cleanup_out
+filesel_cleanup_out
 	rts
 
 
-menu_updates:
+filesel_updates:
 ;update selection, scroll etc
-	lda menu_sel
+	lda filesel_sel
 	asl
 	asl
 	sta dirptr_idx
-	lda menu_sel
+	lda filesel_sel
 	clc
 	adc #$08
 	sta bar_yl
@@ -140,47 +140,47 @@ menu_updates:
 	lda #$40
 	and pad1trig
 	bne key_x
-	bra menuupd_out
+	bra fileselupd_out
 key_down
-	jsr menu_key_down
+	jsr filesel_key_down
-	bra menuupd_out
+	bra fileselupd_out
 key_up
-	jsr menu_key_up
+	jsr filesel_key_up
-	bra menuupd_out
+	bra fileselupd_out
 key_right
-	jsr menu_key_right
+	jsr filesel_key_right
-	bra menuupd_out
+	bra fileselupd_out
 key_left
-	jsr menu_key_left
+	jsr filesel_key_left
-	bra menuupd_out
+	bra fileselupd_out
 key_b
-	jsr menu_key_b
+	jsr filesel_key_b
-	bra menuupd_out
+	bra fileselupd_out
 key_a
-	jsr menu_key_a
+	jsr filesel_key_a
-	bra menuupd_out
+	bra fileselupd_out
 key_x
-	jsr menu_key_x
+	jsr filesel_key_x
-	bra menuupd_out
+	bra fileselupd_out
 key_select
-	jsr menu_key_select
+	jsr filesel_key_select
-	bra menuupd_out
+	bra fileselupd_out
 key_start
-	jsr menu_key_start
+	jsr filesel_key_start
-	bra menuupd_out
+	bra fileselupd_out
 
-menuupd_out
+fileselupd_out
 	lda #$09
 	sta cursor_y
 	rts
 
 
-menu_redraw:
+filesel_redraw:
-	lda menu_state
+	lda filesel_state
 	beq redraw_filelist
 ;	cmp 1
 ;	beq redraw_main
-menu_redraw_out
+filesel_redraw_out
 	rts
 
 redraw_filelist
@@ -236,7 +236,7 @@ redraw_filelist_last	;check if next offscreen item is end of dir
 redraw_filelist_out
 	ldx #$0000
 	stx dirptr_idx
-	brl menu_redraw_out
+	brl filesel_redraw_out
 
 print_direntry:
         lda cursor_y
@@ -355,14 +355,14 @@ dirent_type_cont_2
 
 	rts
 
-menu_key_down:
+filesel_key_down:
 	jsr scroll_direntry_clean
 	lda listdisp
 	dec
-	cmp menu_sel
+	cmp filesel_sel
 	bne down_noscroll
 	lda #$01
-	sta menu_dirty
+	sta filesel_dirty
 	lda dirend_onscreen
 	bne down_out
 	rep #$20 : .al
@@ -380,21 +380,21 @@ down_noscroll
 	lda dirend_idx
 	lsr
 	lsr
-	cmp menu_sel
+	cmp filesel_sel
-	beq menuupd_lastcursor
+	beq fileselupd_lastcursor
-	bcc menuupd_lastcursor
+	bcc fileselupd_lastcursor
-+	lda menu_sel
++	lda filesel_sel
 	inc
-	sta menu_sel
+	sta filesel_sel
 down_out
 	rts
 
-menu_key_up:
+filesel_key_up:
 	jsr scroll_direntry_clean
-	lda menu_sel
+	lda filesel_sel
 	bne up_noscroll
 	lda #$01
-	sta menu_dirty
+	sta filesel_dirty
 	rep #$20 : .al
 	lda dirptr_addr
 	cmp dirstart_addr
@@ -407,25 +407,25 @@ menu_key_up:
 	bra up_out
 up_noscroll
 	dec
-	sta menu_sel
+	sta filesel_sel
 up_out
 	sep #$20 : .as
 	rts
 
-menuupd_lastcursor
+fileselupd_lastcursor
 	jsr scroll_direntry_clean
 	lda dirend_idx
 	lsr
 	lsr
-	sta menu_sel
+	sta filesel_sel
 	rts
 
 ; go back one page
-menu_key_left:
+filesel_key_left:
 	stz direntry_xscroll
 	stz direntry_xscroll_state
 	lda #$01            ; must redraw afterwards
-	sta menu_dirty
+	sta filesel_dirty
 	rep #$20 : .al
 	lda dirptr_addr     ; get current direntry pointer
 	beq +               ; special case: if 0, we are at the first entry in memory
@@ -444,18 +444,18 @@ menu_key_left:
 	sep #$20 : .as
 	rts
 +	lda dirstart_addr   ; reset pointer to start of directory
-	stz menu_sel        ; reset the selection cursor too
+	stz filesel_sel        ; reset the selection cursor too
 	bra -
 
 ; go forth one page
-menu_key_right:
+filesel_key_right:
 	stz direntry_xscroll
 	stz direntry_xscroll_state
 	sep #$20 : .as
 	lda dirend_onscreen
-	bne menuupd_lastcursor
+	bne fileselupd_lastcursor
 	lda #$01
-	sta menu_dirty
+	sta filesel_dirty
 	rep #$20 : .al
 	lda listdisp
 	asl
@@ -466,18 +466,18 @@ menu_key_right:
 	sep #$20 : .as
 	rts
 
-menu_key_a:
+filesel_key_a:
 	jsr select_item
 	rts
 
-menu_key_select:
+filesel_key_select:
 	rts
 
-menu_key_start:
+filesel_key_start:
 	jsr select_last_file
 	rts
 
-menu_key_b:
+filesel_key_b:
 	stz direntry_xscroll
 	stz direntry_xscroll_state
 	rep #$20 : .al
@@ -485,7 +485,7 @@ menu_key_b:
 	beq skip_key_b
 	sta dirptr_addr
 	lda #$0000
-	sta menu_sel
+	sta filesel_sel
 	bra select_item
 skip_key_b
 	sep #$20 : .as
@@ -493,7 +493,7 @@ skip_key_b
 
 select_item:
 	rep #$20 : .al
-	lda menu_sel
+	lda filesel_sel
 	and #$00ff
 	asl
 	asl
@@ -568,7 +568,7 @@ select_dir:
 	lda @dirptr_bank
 	sta [dirlog_idx], y
 	iny
-	lda @menu_sel
+	lda @filesel_sel
 	sta [dirlog_idx], y
 	lda @dirlog_idx
 	clc
@@ -604,12 +604,12 @@ select_dir:
 	sta @dirptr_addr
 	sta @dirstart_addr
 	lda #$0000
-	sta @menu_sel
+	sta @filesel_sel
 	sta @direntry_xscroll
 	sta @direntry_xscroll_state
 	sep #$20 : .as
 	lda #$01
-	sta @menu_dirty
+	sta @filesel_dirty
 	plb
 	rts
 
@@ -638,11 +638,11 @@ select_parent:
 	sta @dirptr_bank
 	iny
 	rep #$20 : .al
-	lda [dirlog_idx], y ; load menu_sel
+	lda [dirlog_idx], y ; load filesel_sel
-	sta @menu_sel
+	sta @filesel_sel
 	sep #$20 : .as
 	lda #$01
-	sta @menu_dirty
+	sta @filesel_dirty
 	rts
 
 select_spc:
@@ -666,7 +666,7 @@ wait_spc:
 	jsr restore_screen
 	rts
 
-menu_key_x:
+filesel_key_x:
 	jsr mainmenu
 	rts
 
@@ -676,11 +676,11 @@ setup_224:
 	lda #18
 	sta listdisp
 	dec
-	cmp menu_sel
+	cmp filesel_sel
 	bmi setup_224_adjsel
 	bra +
 setup_224_adjsel
-	sta menu_sel
+	sta filesel_sel
 +
 	lda #18*64
 	sta textdmasize
@@ -699,7 +699,7 @@ setup_224_adjsel
 	sta hdma_math_selection
 	stz vidmode
 	lda #$01
-	sta menu_dirty
+	sta filesel_dirty
 	lda #^space64
 	ldx #!space64
 	sta print_bank
@@ -719,7 +719,7 @@ setup_224_adjsel
 	plp
 	rts
 
-menu_statusbar
+filesel_statusbar
 	pha
 	phx
 	php
@@ -822,7 +822,7 @@ scroll_direntry_clean:
 	rts
 
 scroll_direntry:
-	ldy menu_sel
+	ldy filesel_sel
 	lda direntry_xscroll_state
 	bne +
 	lda direntry_fits, y
@@ -852,7 +852,7 @@ scroll_direntry_scrollfast
 	lda #$02
 	sta cursor_x
 	rep #$20 : .al
-	lda menu_sel
+	lda filesel_sel
 	asl
 	asl
 	tay
@@ -869,7 +869,7 @@ scroll_direntry_scrollfast
 	lda [dirptr_addr], y
 	iny
 	sta @dirent_type
-	ldy menu_sel
+	ldy filesel_sel
 	sty direntry_fits_idx
 	phy
 	jsr print_direntry

snes/main.a65

@@ -21,15 +21,15 @@ GAME_MAIN:
 	tcs
 	sep #$20 : .as
 
-	jsr killdma		; The following initialization processes must not touch memory
+;	jsr killdma		; The following initialization processes must not touch memory
-	jsr waitblank		; structures used by the main menu !
+	jsr waitblank		; structures used by the file selector !
 	jsr snes_init
 	cli
 	lda #$01
 	sta $420d 		; fast cpu
 	jsr setup_gfx
 	jsr colortest
-	jsr tests
+	jsr video_init
 	jsr setup_hdma
 	lda #$0f
 	sta cur_bright
@@ -43,15 +43,15 @@ set_bank:
 
 coldboot:							; Regular, cold-start init
 	sep #$20 : .as
-	jsr killdma
+;	jsr killdma
 	jsr waitblank
 	jsr snes_init
 	lda #$01
 	sta $420d ; fast cpu
 	jsr setup_gfx
 	jsr colortest
-	jsr menu_init
+	jsr filesel_init
-	jsr tests
+	jsr video_init
 	jsr setup_hdma
 	jsr screen_on
 
@@ -60,7 +60,7 @@ coldboot:							; Regular, cold-start init
 	beq +
 	jsl time_init
 +
-	jsr menuloop
+	jsr fileselloop
 	cli
 	stz $4200
 	jmp @infloop	;infinite loop in WRAM
@@ -138,6 +138,30 @@ killdma:
 	stz $4359
 	stz $435a
 	stz $435b
+	stz $4360
+	stz $4361
+	stz $4362
+	stz $4363
+	stz $4364
+	stz $4365
+	stz $4366
+	stz $4367
+	stz $4368
+	stz $4369
+	stz $436a
+	stz $436b
+	stz $4370
+	stz $4371
+	stz $4372
+	stz $4373
+	stz $4374
+	stz $4375
+	stz $4376
+	stz $4377
+	stz $4378
+	stz $4379
+	stz $437a
+	stz $437b
 
 	stz $420b
 	stz $420c
@@ -190,7 +214,7 @@ setup_gfx:
 ;clear OAM tables
 	ldx #$0000
 	stx $2102
-	DMA0(#$08, #$544, #^zero, #!zero, #$04)
+	DMA0(#$08, #$220, #^zero, #!zero, #$04)
 
 ;copy logo tiles
 	ldx #$2000
@@ -273,7 +297,7 @@ setup_gfx:
 	DMA0(#$00, #$6C, #^fadeloop, #!fadeloop, #$80);
 	rts
 
-tests:
+video_init:
 	sep #$20 : .as		;8-bit accumulator
 	rep #$10 : .xl		;16-bit index
 	lda #$03		;mode 3, mode 5 via HDMA

snes/mainmenu.a65

@@ -80,15 +80,12 @@ mm_entloop
 	plb
 	phx
 	jsr hiprint
-	plx
+	rep #$20 : .al
-	inx
+	pla
-	inx
+	clc
-	inx
+	adc #$08
-	inx
+	tax
-	inx
+	sep #$20 : .as
-	inx
-	inx
-	inx
 	inc mm_tmp
 	lda mm_tmp
 	cmp @main_entries

snes/pad.a65

@@ -4,7 +4,15 @@ read_pad:
 read_pad1
 	ldx pad1mem 	;byetUDLRaxlriiii
 	lda $4218
-	ora $421a
+	and #$000f
+	bne +
+	lda $4218
++	sta pad1mem
+	lda $421a
+	and #$000f
+	bne +
+	lda $421a
++	ora pad1mem
 	sta pad1mem
 	and #$0f00
 	bne read_pad1_count

snes/spcplay.a65

@@ -261,7 +261,19 @@ upload_dsp_regs:
 
 	ldx #$0000
 -
+; initialize FLG and KON ($6c/$4c) to avoid artifacts
+	cpx #$4C
+	bne +
+	lda #$00
+	bra upload_skip_load
++
+	cpx #$6C
+	bne +
+	lda #$E0
+	bra upload_skip_load
++
 	lda @SPC_DSP_REGS,x
+upload_skip_load
 	jsr spc_upload_byte
 	inx
 	cpx #128
@@ -439,6 +451,14 @@ restore_final:
 	ldx #$f3C4	; MOV $f3,A -> $f2 has been set-up before by SPC700 loader
 	jsr exec_instr
 
+; ---- wait a bit (the newer S-APU takes its time to ramp up the volume)
+	lda #$10
+-	pha
+	jsr waitblank
+	pla
+	dec
+	bne -
+
 ; ---- Restore DSP KON register
 
 	lda #$4C

src/Makefile

@@ -75,7 +75,7 @@ ASRC = startup.S crc.S
 #     (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
 # Use s -mcall-prologues when you really need size...
 #OPT = 2
-OPT = 2
+OPT = s
 
 # Debugging format.
 DEBUG = dwarf-2
@@ -124,7 +124,8 @@ NM = $(ARCH)-nm
 REMOVE = rm -f
 COPY = cp
 AWK = awk
-
+RLE = ../utils/rle
+BIN2H = utils/bin2h
 
 #---------------- Compiler Options ----------------
 #  -g*:          generate debugging information
@@ -197,7 +198,7 @@ ALL_ASFLAGS = -I. -x assembler-with-cpp $(ASFLAGS) $(CDEFS)
 # Default target.
 all: build
 
-build: elf bin hex
+build: elf bin hex cfgware.h
 	$(E) "  SIZE   $(TARGET).elf"
 	$(Q)$(ELFSIZE)|grep -v debug
 	cp $(TARGET).bin $(OBJDIR)/firmware.img
@@ -230,6 +231,13 @@ HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex
 ELFSIZE = $(SIZE) -A $(TARGET).elf
 
 
+# Generate cfgware.h
+cfgware.h: $(OBJDIR)/fpga_rle.bit
+	$(E) "  BIN2H  $@"
+	$(Q) $(BIN2H) $< $@
+$(OBJDIR)/fpga_rle.bit: sd2sneslite.bit
+	$(E) "  RLE    $@"
+	$(Q) $(RLE) $< $@
 
 # Generate autoconf.h from config
 .PRECIOUS : $(OBJDIR)/autoconf.h
@@ -302,6 +310,7 @@ clean_list :
 	$(Q)$(REMOVE) $(TARGET).sym
 	$(Q)$(REMOVE) $(TARGET).lss
 	$(Q)$(REMOVE) $(OBJ)
+	$(Q)$(REMOVE) cfgware.h
 	$(Q)$(REMOVE) $(OBJDIR)/autoconf.h
 	$(Q)$(REMOVE) $(OBJDIR)/*.bin
 	$(Q)$(REMOVE) $(LST)

src/README

@@ -17,6 +17,7 @@ b) Cortex M3 toolchain
     - texinfo
     - libmpfr-dev
     - libgmp3-dev
+    - libmpc-dev
     - gawk
     - bison
     - recode

src/bootldr/config.h

@@ -55,8 +55,8 @@
 //#define CONFIG_CPU_FREQUENCY      46000000
 #define CONFIG_UART_PCLKDIV       1
 #define CONFIG_UART_TX_BUF_SHIFT  8
-#define CONFIG_UART_BAUDRATE      921600
+//#define CONFIG_UART_BAUDRATE      921600
-//#define CONFIG_UART_BAUDRATE      115200
+#define CONFIG_UART_BAUDRATE      115200
 #define CONFIG_UART_DEADLOCKABLE
 
 #define SSP_CLK_DIVISOR_FAST 2

src/bootldr/fileops.h

@@ -31,7 +31,7 @@
 
 enum filestates { FILE_OK=0, FILE_ERR, FILE_EOF };
 
-BYTE file_buf[512];
+BYTE file_buf[512] __attribute__((aligned(4)));
 FATFS fatfs;
 FIL file_handle;
 FRESULT file_res;

src/bootldr/iap.c

@@ -189,7 +189,7 @@ FLASH_RES flash_file(uint8_t *filename) {
       }
       DBG_UART uart_putc('w');
       if((res = iap_ram2flash(flash_addr, file_buf, 512)) != CMD_SUCCESS) {
-        DBG_BL printf("error %ld while writing to address %08lx (sector %d)\n", res, flash_addr, current_sec);
+        DBG_BL printf("error %ld while writing from %08lX to address %08lx (sector %d)\n", res, (uint32_t)file_buf, flash_addr, current_sec);
         DBG_UART uart_putc('X');
         return ERR_FLASH;
       }

src/bootldr/lpc1754.cfg

@@ -27,9 +27,9 @@ if { [info exists CPUTAPID ] } {
 
 #delays on reset lines
 #if your OpenOCD version rejects "jtag_nsrst_delay" replace it with:
-#adapter_nsrst_delay 200
+adapter_nsrst_delay 200
-jtag_nsrst_delay 200
+#jtag_nsrst_delay 200
-jtag_ntrst_delay 200
+#jtag_ntrst_delay 200
 
 # LPC2000 & LPC1700 -> SRST causes TRST
 #reset_config srst_pulls_trst
@@ -56,7 +56,7 @@ flash bank $_FLASHNAME lpc2000 0x0 0x20000 0 0 $_TARGETNAME \
 # Run with *real slow* clock by default since the
 # boot rom could have been playing with the PLL, so
 # we have no idea what clock the target is running at.
-jtag_khz 1000
+adapter_khz 1000
 
 $_TARGETNAME configure -event reset-init {
 	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select

src/bootldr/main.c

@@ -52,8 +52,12 @@ int main(void) {
   clock_init();
 //  LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
   sdn_init();
+
+  for(i = 0; i < 20; i++) uart_putc('-');
+  uart_putc('\n');
+
   DBG_BL printf("chksum=%08lx\n", *(uint32_t*)28);
-  DBG_BL printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY);
+  /*DBG_BL*/ printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY);
 DBG_BL printf("PCONP=%lx\n", LPC_SC->PCONP);
 /* setup timer (fpga clk) */
   LPC_TIM3->CTCR=0;

src/bootldr/openocd-usb.cfg

@@ -5,8 +5,14 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x0403 0x6010
+ft2232_vid_pid 0x15ba 0x0003
-ft2232_device_desc "Dual RS232"
+ft2232_device_desc "Olimex OpenOCD JTAG"
-ft2232_layout "oocdlink"
+ft2232_layout "olimex-jtag"
-ft2232_latency 2
+
+
+#interface ft2232
+#ft2232_vid_pid 0x0403 0x6010
+#ft2232_device_desc "Dual RS232"
+#ft2232_layout "oocdlink"
+#ft2232_latency 2
 #adapter_khz 10

src/cli.c

@@ -58,8 +58,8 @@ static char *curchar;
 
 /* Word lists */
 static char command_words[] =
-  "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0rm\0mkdir\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0";
+  "cd\0reset\0sreset\0dir\0ls\0test\0exit\0loadrom\0loadraw\0saveraw\0put\0rm\0mkdir\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0memset\0";
-enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_MKDIR, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16 };
+enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_EXIT, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_MKDIR, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16, CMD_MEMSET };
 
 /* ------------------------------------------------------------------------- */
 /*   Parse functions                                                         */
@@ -104,11 +104,11 @@ static int32_t parse_unsigned(uint32_t lower, uint32_t upper, uint8_t base) {
 /* Parse the string starting with curchar for a word in wordlist */
 static int8_t parse_wordlist(char *wordlist) {
   uint8_t i, matched;
-  char *cur, *ptr;
+  unsigned char *cur, *ptr;
-  char c;
+  unsigned char c;
 
   i = 0;
-  ptr = wordlist;
+  ptr = (unsigned char *)wordlist;
 
   // Command list on "?"
   if (strlen(curchar) == 1 && *curchar == '?') {
@@ -128,7 +128,7 @@ static int8_t parse_wordlist(char *wordlist) {
   }
 
   while (1) {
-    cur = curchar;
+    cur = (unsigned char *)curchar;
     matched = 1;
     c = *ptr;
     do {
@@ -138,9 +138,9 @@ static int8_t parse_wordlist(char *wordlist) {
         return -1;
       }
 
-      if (tolower(c) != tolower(*cur)) {
+      if (tolower((int)c) != tolower((int)*cur)) {
         // Check for end-of-word
-        if (cur != curchar && (*cur == ' ' || *cur == 0)) {
+        if (cur != (unsigned char*)curchar && (*cur == ' ' || *cur == 0)) {
           // Partial match found, return that
           break;
         } else {
@@ -156,7 +156,7 @@ static int8_t parse_wordlist(char *wordlist) {
     if (matched) {
       char *tmp = curchar;
 
-      curchar = cur;
+      curchar = (char *)cur;
       // Return match only if whitespace or end-of-string follows
       // (avoids mismatching partial words)
       if (skip_spaces()) {
@@ -269,7 +269,7 @@ static void cmd_show_directory(void) {
       strlwr((char *)name);
     }
 
-    printf("%s",name);
+    printf("%s [%s] (%ld)",finfo.lfname, finfo.fname, finfo.fsize);
 
     /* Directory indicator (Unix-style) */
     if (finfo.fattrib & AM_DIR)
@@ -420,6 +420,13 @@ void cmd_w16(void) {
   sram_writeshort(val, offset);
 }
 
+void cmd_memset(void) {
+  uint32_t offset = parse_unsigned(0, 16777215, 16);
+  uint32_t len = parse_unsigned(0, 16777216, 16);
+  uint8_t val = parse_unsigned(0, 255, 16);
+  sram_memset(offset, len, val);
+}
+
 /* ------------------------------------------------------------------------- */
 /*   CLI interface functions                                                 */
 /* ------------------------------------------------------------------------- */
@@ -502,7 +509,7 @@ void cli_loop(void) {
       cmd_show_directory();
       break;
 
-    case CMD_RESUME:
+    case CMD_EXIT:
       return;
       break;
 
@@ -569,7 +576,11 @@ void cli_loop(void) {
     case CMD_W16:
       cmd_w16();
       break;
-    }
 
+    case CMD_MEMSET:
+      cmd_memset();
+      break;
+
+    }
   }
 }

src/clock.c

@@ -27,7 +27,7 @@ void clock_init() {
    -> FPGA freq = 11289473.7Hz
    First, disable and disconnect PLL0.
 */
-//  clock_disconnect();
+  clock_disconnect();
 
 /* PLL is disabled and disconnected. setup PCLK NOW as it cannot be changed
    reliably with PLL0 connected.
@@ -52,6 +52,15 @@ void clock_init() {
   enablePLL0();
   setCCLKDiv(6);
   connectPLL0();
+
+
+/* configure PLL1 for USB operation */
+  disconnectPLL1();
+  disablePLL1();
+  LPC_SC->PLL1CFG = 0x23;
+  enablePLL1();
+  connectPLL1();
+
 }
 
 void setFlashAccessTime(uint8_t clocks) {
@@ -74,7 +83,7 @@ void disablePLL0() {
 }
 
 void connectPLL0() {
-  while(!(LPC_SC->PLL0STAT&PLOCK0));
+  while(!(LPC_SC->PLL0STAT & PLOCK0));
   LPC_SC->PLL0CON |= PLLC0;
   PLL0feed();
 }
@@ -84,6 +93,32 @@ void disconnectPLL0() {
   PLL0feed();
 }
 
+void setPLL1MultPrediv(uint16_t mult, uint8_t prediv) {
+  LPC_SC->PLL1CFG=PLL_MULT(mult) | PLL_PREDIV(prediv);
+  PLL1feed();
+}
+
+void enablePLL1() {
+  LPC_SC->PLL1CON |= PLLE1;
+  PLL1feed();
+}
+
+void disablePLL1() {
+  LPC_SC->PLL1CON &= ~PLLE1;
+  PLL1feed();
+}
+
+void connectPLL1() {
+  while(!(LPC_SC->PLL1STAT & PLOCK1));
+  LPC_SC->PLL1CON |= PLLC1;
+  PLL1feed();
+}
+
+void disconnectPLL1() {
+  LPC_SC->PLL1CON &= ~PLLC1;
+  PLL1feed();
+}
+
 void setCCLKDiv(uint8_t div) {
   LPC_SC->CCLKCFG=CCLK_DIV(div);
 }
@@ -102,6 +137,11 @@ void PLL0feed() {
   LPC_SC->PLL0FEED=0x55;
 }
 
+void PLL1feed() {
+  LPC_SC->PLL1FEED=0xaa;
+  LPC_SC->PLL1FEED=0x55;
+}
+
 void setClkSrc(uint8_t src) {
   LPC_SC->CLKSRCSEL=src;
 }

src/clock.h

@@ -8,6 +8,9 @@
 #define PLLE0           (1<<0)
 #define PLLC0           (1<<1)
 #define PLOCK0          (1<<26)
+#define PLLE1           (1<<0)
+#define PLLC1           (1<<1)
+#define PLOCK1          (1<<10)
 #define OSCEN           (1<<5)
 #define OSCSTAT         (1<<6)
 #define FLASHTIM(x)     (((x-1)<<12)|0x3A)
@@ -56,14 +59,18 @@ void clock_init(void);
 void setFlashAccessTime(uint8_t clocks);
 
 void setPLL0MultPrediv(uint16_t mult, uint8_t prediv);
-
 void enablePLL0(void);
-
 void disablePLL0(void);
-
 void connectPLL0(void);
-
 void disconnectPLL0(void);
+void PLL0feed(void);
+
+void setPLL1MultPrediv(uint16_t mult, uint8_t prediv);
+void enablePLL1(void);
+void disablePLL1(void);
+void connectPLL1(void);
+void disconnectPLL1(void);
+void PLL1feed(void);
 
 void setCCLKDiv(uint8_t div);
 
@@ -71,9 +78,5 @@ void enableMainOsc(void);
 
 void disableMainOsc(void);
 
-void PLL0feed(void);
-
 void setClkSrc(uint8_t src);
-
-
 #endif

src/config

@@ -1,4 +1,4 @@
-CONFIG_VERSION="0.1.4a"
+CONFIG_VERSION="0.1.5"
 #FWVER=00010300
-CONFIG_FWVER=0x01010400
+CONFIG_FWVER=0x00010500
 CONFIG_MCU_FOSC=12000000

src/config.h

@@ -64,6 +64,7 @@
 #define FPGA_MCU_RDY_BIT          9
 
 #define QSORT_MAXELEM             2048
+#define SORT_STRLEN               256
 #define CLTBL_SIZE		  100
 
 #define DIR_FILE_MAX              16380
@@ -95,4 +96,7 @@
 
 #define SD_DAT (LPC_GPIO2->FIOPIN0)
 
+#define USB_CONNREG LPC_GPIO4
+#define USB_CONNBIT 28
+
 #endif

src/filetypes.c

@@ -65,7 +65,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
   static uint32_t next_subdir_tgt;
   static uint32_t parent_tgt;
   static uint32_t dir_end = 0;
-  static uint8_t was_empty = 0;
+/*  static uint8_t was_empty = 0;*/
   static uint16_t num_files_total = 0;
   static uint16_t num_dirs_total = 0;
   uint32_t dir_tgt;
@@ -147,12 +147,12 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
         res = f_readdir(&dir, &fno);
         if (res != FR_OK || fno.fname[0] == 0) {
           if(pass) {
-            if(!numentries) was_empty=1;
+/*            if(!numentries) was_empty=1;*/
           }
           break;
         }
         fn = *fno.lfname ? fno.lfname : fno.fname;
-        if ((*fn == '.') || !(strncasecmp(fn, SYS_DIR_NAME, sizeof(SYS_DIR_NAME)))) continue;
+        if ((*fn == '.') || !(strncasecmp(fn, SYS_DIR_NAME, strlen(SYS_DIR_NAME)+1))) continue;
         if (fno.fattrib & AM_DIR) {
           depth++;
           if(depth < FS_MAX_DEPTH) {
@@ -194,7 +194,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
                 sram_writeblock("/\0", old_db_tgt + sizeof(next_subdir_tgt) + sizeof(len) + pathlen, 2);
               }
               dir_tgt += 4;
-              was_empty = 0;
+/*              was_empty = 0;*/
             } else if(!mkdb) {
               path[len]='/';
               strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
@@ -275,6 +275,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
   sram_writeshort(num_dirs_total, SRAM_DB_ADDR+14);
   if(depth==0) return crc;
   else return switched_dir_tgt;
+  return was_empty; // tricky!
 }
 
 

src/fpga.c

@@ -98,37 +98,43 @@ void fpga_pgm(uint8_t* filename) {
   uint8_t data;
   int i;
   tick_t timeout;
+  /* open configware file */
+  file_open(filename, FA_READ);
+  if(file_res) {
+    uart_putc('?');
+    uart_putc(0x30+file_res);
+    return;
+  }
+
   do {
     i=0;
-    timeout = getticks() + 100;
+    timeout = getticks() + 1;
     fpga_set_prog_b(0);
-if(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) {
+    while(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) {
-  printf("PROGB is stuck high!\n");
+      if(getticks() > timeout) {
-  led_panic();
+        printf("PROGB is stuck high!\n");
-}
+        led_panic(LED_PANIC_FPGA_PROGB_STUCK);
+      }
+    }
+    timeout = getticks() + 100;
     uart_putc('P');
     fpga_set_prog_b(1);
     while(!fpga_get_initb()){
       if(getticks() > timeout) {
         printf("no response from FPGA trying to initiate configuration!\n");
-        led_panic();
+        led_panic(LED_PANIC_FPGA_NO_INITB);
       }
     };
-    if(fpga_get_done()) {
+    timeout = getticks() + 100;
-      printf("DONE is stuck high!\n");
+    while(fpga_get_done()) {
-      led_panic();
+      if(getticks() > timeout) {
+        printf("DONE is stuck high!\n");
+        led_panic(LED_PANIC_FPGA_DONE_STUCK);
+      }
     }
     LPC_GPIO2->FIOMASK1 = ~(BV(0));
     uart_putc('p');
 
-
-    /* open configware file */
-    file_open(filename, FA_READ);
-    if(file_res) {
-      uart_putc('?');
-      uart_putc(0x30+file_res);
-      return;
-    }
     uart_putc('C');
 
     for (;;) {
@@ -144,7 +150,7 @@ if(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) {
   } while (!fpga_get_done() && retries--);
   if(!fpga_get_done()) {
     printf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
-    led_panic();
+    led_panic(LED_PANIC_FPGA_NOCONF);
   }
   printf("FPGA configured\n");
   fpga_postinit();
@@ -165,12 +171,15 @@ void fpga_rompgm() {
     while(!fpga_get_initb()){
       if(getticks() > timeout) {
         printf("no response from FPGA trying to initiate configuration!\n");
-        led_panic();
+        led_panic(LED_PANIC_FPGA_NO_INITB);
       }
     };
-    if(fpga_get_done()) {
+    timeout = getticks() + 100;
-      printf("DONE is stuck high!\n");
+    while(fpga_get_done()) {
-      led_panic();
+      if(getticks() > timeout) {
+        printf("DONE is stuck high!\n");
+        led_panic(LED_PANIC_FPGA_DONE_STUCK);
+      }
     }
     LPC_GPIO2->FIOMASK1 = ~(BV(0));
     uart_putc('p');
@@ -190,7 +199,7 @@ void fpga_rompgm() {
   } while (!fpga_get_done() && retries--);
   if(!fpga_get_done()) {
     printf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
-    led_panic();
+    led_panic(LED_PANIC_FPGA_NOCONF);
   }
   printf("FPGA configured\n");
   fpga_postinit();

src/fpga_spi.c

@@ -1,6 +1,6 @@
 /* sd2snes - SD card based universal cartridge for the SNES
-   Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
+   Copyright (C) 2009-2012 Maximilian Rehkopf <otakon@gmx.net>
-   AVR firmware portion
+   uC firmware portion
 
    Inspired by and based on code from sd2iec, written by Ingo Korb et al.
    See sdcard.c|h, config.h.
@@ -149,7 +149,7 @@ void fpga_spi_init(void) {
 
 void set_msu_addr(uint16_t address) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0x02);
+  FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_MSUBUF);
   FPGA_TX_BYTE((address>>8)&0xff);
   FPGA_TX_BYTE((address)&0xff);
   FPGA_DESELECT();
@@ -157,7 +157,7 @@ void set_msu_addr(uint16_t address) {
 
 void set_dac_addr(uint16_t address) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0x01);
+  FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_DACBUF);
   FPGA_TX_BYTE((address>>8)&0xff);
   FPGA_TX_BYTE((address)&0xff);
   FPGA_DESELECT();
@@ -165,7 +165,7 @@ void set_dac_addr(uint16_t address) {
 
 void set_mcu_addr(uint32_t address) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0x00);
+  FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_MEM);
   FPGA_TX_BYTE((address>>16)&0xff);
   FPGA_TX_BYTE((address>>8)&0xff);
   FPGA_TX_BYTE((address)&0xff);
@@ -174,7 +174,7 @@ void set_mcu_addr(uint32_t address) {
 
 void set_saveram_mask(uint32_t mask) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0x20);
+  FPGA_TX_BYTE(FPGA_CMD_SETRAMMASK);
   FPGA_TX_BYTE((mask>>16)&0xff);
   FPGA_TX_BYTE((mask>>8)&0xff);
   FPGA_TX_BYTE((mask)&0xff);
@@ -183,7 +183,7 @@ void set_saveram_mask(uint32_t mask) {
 
 void set_rom_mask(uint32_t mask) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0x10);
+  FPGA_TX_BYTE(FPGA_CMD_SETROMMASK);
   FPGA_TX_BYTE((mask>>16)&0xff);
   FPGA_TX_BYTE((mask>>8)&0xff);
   FPGA_TX_BYTE((mask)&0xff);
@@ -192,13 +192,13 @@ void set_rom_mask(uint32_t mask) {
 
 void set_mapper(uint8_t val) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0x30 | (val & 0x0f));
+  FPGA_TX_BYTE(FPGA_CMD_SETMAPPER(val));
   FPGA_DESELECT();
 }
 
 uint8_t fpga_test() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xF0); /* TEST */
+  FPGA_TX_BYTE(FPGA_CMD_TEST);
   uint8_t result = FPGA_RX_BYTE();
   FPGA_DESELECT();
   return result;
@@ -206,7 +206,7 @@ uint8_t fpga_test() {
 
 uint16_t fpga_status() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xF1); /* STATUS */
+  FPGA_TX_BYTE(FPGA_CMD_GETSTATUS);
   uint16_t result = (FPGA_RX_BYTE()) << 8;
   result |= FPGA_RX_BYTE();
   FPGA_DESELECT();
@@ -214,65 +214,50 @@ uint16_t fpga_status() {
 }
 
 void fpga_set_sddma_range(uint16_t start, uint16_t end) {
+  printf("%s %08X -> %08X\n", __func__, start, end);
   FPGA_SELECT();
-  FPGA_TX_BYTE(0x60); /* DMA_RANGE */
+  FPGA_TX_BYTE(FPGA_CMD_SDDMA_RANGE);
   FPGA_TX_BYTE(start>>8);
   FPGA_TX_BYTE(start&0xff);
   FPGA_TX_BYTE(end>>8);
   FPGA_TX_BYTE(end&0xff);
-//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
   FPGA_DESELECT();
 }
 
 void fpga_sddma(uint8_t tgt, uint8_t partial) {
-  uint32_t test = 0;
-  uint8_t status = 0;
   BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 0;
   FPGA_SELECT();
-  FPGA_TX_BYTE(0x40 | (tgt & 0x3) | ((partial & 1) << 2) ); /* DO DMA */
+  FPGA_TX_BYTE(FPGA_CMD_SDDMA | (tgt & 3) | (partial ? FPGA_SDDMA_PARTIAL : 0));
   FPGA_TX_BYTE(0x00); /* dummy for falling DMA_EN edge */
-//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
   FPGA_DESELECT();
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xF1); /* STATUS */
+  FPGA_TX_BYTE(FPGA_CMD_GETSTATUS);
   DBG_SD printf("FPGA DMA request sent, wait for completion...");
-  while((status=FPGA_RX_BYTE()) & 0x80) {
+  while(FPGA_RX_BYTE() & 0x80) {
     FPGA_RX_BYTE(); /* eat the 2nd status byte */
-    test++;
   }
-
   DBG_SD printf("...complete\n");
   FPGA_DESELECT();
-//  if(test<5)printf("loopy: %ld %02x\n", test, status);
   BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
 }
 
-void set_dac_vol(uint8_t volume) {
-  FPGA_SELECT();
-  FPGA_TX_BYTE(0x50);
-  FPGA_TX_BYTE(volume);
-  FPGA_TX_BYTE(0x00); /* latch rise */
-  FPGA_TX_BYTE(0x00); /* latch fall */
-  FPGA_DESELECT();
-}
-
 void dac_play() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe2);
+  FPGA_TX_BYTE(FPGA_CMD_DACPLAY);
   FPGA_TX_BYTE(0x00); /* latch reset */
   FPGA_DESELECT();
 }
 
 void dac_pause() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe1);
+  FPGA_TX_BYTE(FPGA_CMD_DACPAUSE);
   FPGA_TX_BYTE(0x00); /* latch reset */
   FPGA_DESELECT();
 }
 
 void dac_reset() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe3);
+  FPGA_TX_BYTE(FPGA_CMD_DACRESETPTR);
   FPGA_TX_BYTE(0x00); /* latch reset */
   FPGA_TX_BYTE(0x00); /* latch reset */
   FPGA_DESELECT();
@@ -280,7 +265,7 @@ void dac_reset() {
 
 void msu_reset(uint16_t address) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe4);
+  FPGA_TX_BYTE(FPGA_CMD_MSUSETPTR);
   FPGA_TX_BYTE((address>>8) & 0xff); /* address hi */
   FPGA_TX_BYTE(address & 0xff);      /* address lo */
   FPGA_TX_BYTE(0x00);                /* latch reset */
@@ -290,24 +275,16 @@ void msu_reset(uint16_t address) {
 
 void set_msu_status(uint8_t set, uint8_t reset) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe0);
+  FPGA_TX_BYTE(FPGA_CMD_MSUSETBITS);
   FPGA_TX_BYTE(set);
   FPGA_TX_BYTE(reset);
   FPGA_TX_BYTE(0x00); /* latch reset */
   FPGA_DESELECT();
 }
 
-uint8_t get_msu_volume() {
-  FPGA_SELECT();
-  FPGA_TX_BYTE(0xF4); /* MSU_VOLUME */
-  uint8_t result = FPGA_RX_BYTE();
-  FPGA_DESELECT();
-  return result;
-}
-
 uint16_t get_msu_track() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xF3); /* MSU_TRACK */
+  FPGA_TX_BYTE(FPGA_CMD_MSUGETTRACK);
   uint16_t result = (FPGA_RX_BYTE()) << 8;
   result |= FPGA_RX_BYTE();
   FPGA_DESELECT();
@@ -316,7 +293,7 @@ uint16_t get_msu_track() {
 
 uint32_t get_msu_offset() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xF2); /* MSU_OFFSET */
+  FPGA_TX_BYTE(FPGA_CMD_MSUGETADDR);
   uint32_t result = (FPGA_RX_BYTE()) << 24;
   result |= (FPGA_RX_BYTE()) << 16;
   result |= (FPGA_RX_BYTE()) << 8;
@@ -327,7 +304,7 @@ uint32_t get_msu_offset() {
 
 uint32_t get_snes_sysclk() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xFE); /* GET_SYSCLK */
+  FPGA_TX_BYTE(FPGA_CMD_GETSYSCLK);
   FPGA_TX_BYTE(0x00); /* dummy (copy current sysclk count to register) */
   uint32_t result = (FPGA_RX_BYTE()) << 24;
   result |= (FPGA_RX_BYTE()) << 16;
@@ -339,7 +316,7 @@ uint32_t get_snes_sysclk() {
 
 void set_bsx_regs(uint8_t set, uint8_t reset) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe6);
+  FPGA_TX_BYTE(FPGA_CMD_BSXSETBITS);
   FPGA_TX_BYTE(set);
   FPGA_TX_BYTE(reset);
   FPGA_TX_BYTE(0x00); /* latch reset */
@@ -348,7 +325,7 @@ void set_bsx_regs(uint8_t set, uint8_t reset) {
 
 void set_fpga_time(uint64_t time) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe5);
+  FPGA_TX_BYTE(FPGA_CMD_RTCSET);
   FPGA_TX_BYTE((time >> 48) & 0xff);
   FPGA_TX_BYTE((time >> 40) & 0xff);
   FPGA_TX_BYTE((time >> 32) & 0xff);
@@ -362,7 +339,7 @@ void set_fpga_time(uint64_t time) {
 
 void fpga_reset_srtc_state() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe7);
+  FPGA_TX_BYTE(FPGA_CMD_SRTCRESET);
   FPGA_TX_BYTE(0x00);
   FPGA_TX_BYTE(0x00);
   FPGA_DESELECT();
@@ -370,7 +347,7 @@ void fpga_reset_srtc_state() {
 
 void fpga_reset_dspx_addr() {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe8);
+  FPGA_TX_BYTE(FPGA_CMD_DSPRESETPTR);
   FPGA_TX_BYTE(0x00);
   FPGA_TX_BYTE(0x00);
   FPGA_DESELECT();
@@ -378,7 +355,7 @@ void fpga_reset_dspx_addr() {
 
 void fpga_write_dspx_pgm(uint32_t data) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xe9);
+  FPGA_TX_BYTE(FPGA_CMD_DSPWRITEPGM);
   FPGA_TX_BYTE((data>>16)&0xff);
   FPGA_TX_BYTE((data>>8)&0xff);
   FPGA_TX_BYTE((data)&0xff);
@@ -389,7 +366,7 @@ void fpga_write_dspx_pgm(uint32_t data) {
 
 void fpga_write_dspx_dat(uint16_t data) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xea);
+  FPGA_TX_BYTE(FPGA_CMD_DSPWRITEDAT);
   FPGA_TX_BYTE((data>>8)&0xff);
   FPGA_TX_BYTE((data)&0xff);
   FPGA_TX_BYTE(0x00);
@@ -399,7 +376,7 @@ void fpga_write_dspx_dat(uint16_t data) {
 
 void fpga_dspx_reset(uint8_t reset) {
   FPGA_SELECT();
-  FPGA_TX_BYTE(reset ? 0xeb : 0xec);
+  FPGA_TX_BYTE(reset ? FPGA_CMD_DSPRESET : FPGA_CMD_DSPUNRESET);
   FPGA_TX_BYTE(0x00);
   FPGA_DESELECT();
 }
@@ -407,7 +384,7 @@ void fpga_dspx_reset(uint8_t reset) {
 void fpga_set_features(uint8_t feat) {
   printf("set features: %02x\n", feat);
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xed);
+  FPGA_TX_BYTE(FPGA_CMD_SETFEATURE);
   FPGA_TX_BYTE(feat);
   FPGA_DESELECT();
 }
@@ -415,7 +392,7 @@ void fpga_set_features(uint8_t feat) {
 void fpga_set_213f(uint8_t data) {
   printf("set 213f: %d\n", data);
   FPGA_SELECT();
-  FPGA_TX_BYTE(0xee);
+  FPGA_TX_BYTE(FPGA_CMD_SET213F);
   FPGA_TX_BYTE(data);
   FPGA_DESELECT();
 }

src/fpga_spi.h

@@ -57,6 +57,44 @@
 
 #define FPGA_WAIT_RDY()    do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)
 
+/* command parameters */
+#define FPGA_MEM_AUTOINC        (0x8)
+#define FPGA_SDDMA_PARTIAL      (0x4)
+#define FPGA_TGT_MEM      (0x0)
+#define FPGA_TGT_DACBUF   (0x1)
+#define FPGA_TGT_MSUBUF   (0x2)
+
+/* commands */
+#define FPGA_CMD_SETADDR        (0x00)
+#define FPGA_CMD_SETROMMASK     (0x10)
+#define FPGA_CMD_SETRAMMASK     (0x20)
+#define FPGA_CMD_SETMAPPER(x)   (0x30 | (x & 15))
+#define FPGA_CMD_SDDMA          (0x40)
+#define FPGA_CMD_SDDMA_RANGE    (0x60)
+#define FPGA_CMD_READMEM        (0x80)
+#define FPGA_CMD_WRITEMEM       (0x90)
+#define FPGA_CMD_MSUSETBITS     (0xe0)
+#define FPGA_CMD_DACPAUSE       (0xe1)
+#define FPGA_CMD_DACPLAY        (0xe2)
+#define FPGA_CMD_DACRESETPTR    (0xe3)
+#define FPGA_CMD_MSUSETPTR      (0xe4)
+#define FPGA_CMD_RTCSET         (0xe5)
+#define FPGA_CMD_BSXSETBITS     (0xe6)
+#define FPGA_CMD_SRTCRESET      (0xe7)
+#define FPGA_CMD_DSPRESETPTR    (0xe8)
+#define FPGA_CMD_DSPWRITEPGM    (0xe9)
+#define FPGA_CMD_DSPWRITEDAT    (0xea)
+#define FPGA_CMD_DSPRESET       (0xeb)
+#define FPGA_CMD_DSPUNRESET     (0xec)
+#define FPGA_CMD_SETFEATURE     (0xed)
+#define FPGA_CMD_SET213F        (0xee)
+#define FPGA_CMD_TEST           (0xf0)
+#define FPGA_CMD_GETSTATUS      (0xf1)
+#define FPGA_CMD_MSUGETADDR     (0xf2)
+#define FPGA_CMD_MSUGETTRACK    (0xf3)
+#define FPGA_CMD_GETSYSCLK      (0xfe)
+#define FPGA_CMD_ECHO           (0xff)
+
 void fpga_spi_init(void);
 uint8_t fpga_test(void);
 uint16_t fpga_status(void);
@@ -65,7 +103,6 @@ void spi_sd(void);
 void spi_none(void);
 void set_mcu_addr(uint32_t);
 void set_dac_addr(uint16_t);
-void set_dac_vol(uint8_t);
 void dac_play(void);
 void dac_pause(void);
 void dac_reset(void);
@@ -77,7 +114,6 @@ void set_rom_mask(uint32_t);
 void set_mapper(uint8_t val);
 void fpga_sddma(uint8_t tgt, uint8_t partial);
 void fpga_set_sddma_range(uint16_t start, uint16_t end);
-uint8_t get_msu_volume(void);
 uint16_t get_msu_track(void);
 uint32_t get_msu_offset(void);
 uint32_t get_snes_sysclk(void);

src/led.c

@@ -85,12 +85,12 @@ void toggle_write_led() {
   writeled(~led_writeledstate);
 }
 
-void led_panic() {
+void led_panic(uint8_t led_states) {
   led_std();
   while(1) {
-    rdyled(1);
+    rdyled((led_states >> 2) & 1);
-    readled(1);
+    readled((led_states >> 1) & 1);
-    writeled(1);
+    writeled(led_states & 1);
     delay_ms(100);
     rdyled(0);
     readled(0);

src/led.h

@@ -3,6 +3,12 @@
 #ifndef _LED_H
 #define _LED_H
 
+#define LED_PANIC_FPGA_PROGB_STUCK (1)
+#define LED_PANIC_FPGA_NO_INITB    (2)
+#define LED_PANIC_FPGA_DONE_STUCK  (3)
+#define LED_PANIC_FPGA_NOCONF      (4)
+#define LED_PANIC_FPGA_DEAD        (5)
+
 void readbright(uint8_t bright);
 void writebright(uint8_t bright);
 void rdybright(uint8_t bright);
@@ -13,7 +19,7 @@ void led_clkout32(uint32_t val);
 void toggle_rdy_led(void);
 void toggle_read_led(void);
 void toggle_write_led(void);
-void led_panic(void);
+void led_panic(uint8_t led_states);
 void led_pwm(void);
 void led_std(void);
 void led_init(void);

src/lpc1754.cfg

@@ -26,9 +26,9 @@ if { [info exists CPUTAPID ] } {
 }
 
 #delays on reset lines
-#if your OpenOCD version rejects "jtag_nsrst_delay" replace it with:
+#if your OpenOCD version rejects "adapter_nsrst_delay" replace it with:
-#adapter_nsrst_delay 200
+#jtag_nsrst_delay 200
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
 # LPC2000 & LPC1700 -> SRST causes TRST
@@ -39,7 +39,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 #jtag newtap x3s tap -irlen 6 -ircapture 0x11 -irmask 0x11 -expected-id 0x0141c093
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME -event reset-init 0
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME -event reset-init 0
 
 # LPC1754 has 16kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
 # and 16K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
@@ -56,7 +56,7 @@ flash bank $_FLASHNAME lpc2000 0x0 0x20000 0 0 $_TARGETNAME \
 # Run with *real slow* clock by default since the
 # boot rom could have been playing with the PLL, so
 # we have no idea what clock the target is running at.
-jtag_khz 1000
+adapter_khz 1000
 
 $_TARGETNAME configure -event reset-init {
 	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select

src/main.c

@@ -48,12 +48,14 @@ extern volatile int reset_changed;
 
 extern volatile cfg_t CFG;
 
-enum system_states {
+enum system_states
+{
   SYS_RTC_STATUS = 0,
   SYS_LAST_STATUS = 1
 };
 
-int main(void) {
+int main(void)
+{
   LPC_GPIO2->FIODIR = BV(4) | BV(5);
   LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
   BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
@@ -88,7 +90,9 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
   file_init();
   cic_init(0);
 /* setup timer (fpga clk) */
+  LPC_TIM3->TCR=2;
   LPC_TIM3->CTCR=0;
+  LPC_TIM3->PR=0;
   LPC_TIM3->EMR=EMC0TOGGLE;
   LPC_TIM3->MCR=MR0R;
   LPC_TIM3->MR0=1;
@@ -119,17 +123,21 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
     /* some sanity checks */
     uint8_t card_go = 0;
     while(!card_go) {
-      if(disk_status(0) & (STA_NOINIT|STA_NODISK)) {
+      if(disk_status(0) & (STA_NOINIT|STA_NODISK))
-	snes_bootprint("        No SD Card found!       \0");
+      {
-	while(disk_status(0) & (STA_NOINIT|STA_NODISK));
+        snes_bootprint("        No SD Card found!       \0");
-	delay_ms(200);
+        while(disk_status(0) & (STA_NOINIT|STA_NODISK));
+          delay_ms(200);
       }
       file_open((uint8_t*)"/sd2snes/menu.bin", FA_READ);
-      if(file_status != FILE_OK) {
+      if(file_status != FILE_OK)
-	snes_bootprint("  /sd2snes/menu.bin not found!  \0");
+      {
-	while(disk_status(0) == RES_OK);
+        snes_bootprint("  /sd2snes/menu.bin not found!  \0");
-      } else {
+        while(disk_status(0) == RES_OK);
-	card_go = 1;
+      } 
+      else
+      {
+        card_go = 1;
       }
       file_close();
     }
@@ -254,6 +262,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
           cfg_set_last_game_valid(1);
           cfg_save();
 	  filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
+	  printf("Filesize = %lu\n", filesize);
 	  break;
 	case SNES_CMD_SETRTC:
           /* get time from RAM */
@@ -292,9 +301,11 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
 	  break;
       }
     }
+    printf("loaded %lu bytes\n", filesize);
     printf("cmd was %x, going to snes main loop\n", cmd);
 
-    if(romprops.has_msu1 && msu1_loop()) {
+    if(romprops.has_msu1) {
+      while(!msu1_loop());
       prepare_reset();
       continue;
     }
@@ -302,30 +313,38 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
     cmd=0;
     uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
     uint16_t reset_count=0;
-    while(fpga_test() == FPGA_TEST_TOKEN) {
+    while(fpga_test() == FPGA_TEST_TOKEN)
+    {
       cli_entrycheck();
       sleep_ms(250);
       sram_reliable();
       printf("%s ", get_cic_statename(get_cic_state()));
-      if(reset_changed) {
+      if(reset_changed)
+      {
         printf("reset\n");
         reset_changed = 0;
         fpga_reset_srtc_state();
       }
-      snes_reset_now=get_snes_reset();
+      snes_reset_now = get_snes_reset();
-      if(snes_reset_now) {
+      if (snes_reset_now)
-	if(!snes_reset_prev) {
+      {
-	  printf("RESET BUTTON DOWN\n");
+        if (!snes_reset_prev)
-	  snes_reset_state=1;
+        {
-	  reset_count=0;
+          printf("RESET BUTTON DOWN\n");
-	}
+          snes_reset_state = 1;
-      } else {
+          reset_count = 0;
-	if(snes_reset_prev) {
+        }
-	  printf("RESET BUTTON UP\n");
-	  snes_reset_state=0;
-	}
       } 
-      if(snes_reset_state) {
+      else
+      {
+        if (snes_reset_prev)
+        {
+          printf("RESET BUTTON UP\n");
+          snes_reset_state = 0;
+        }
+      }
+      if (snes_reset_state)
+      {
 	reset_count++;
       } else {
 	sram_reliable();
@@ -340,7 +359,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
     }
     /* fpga test fail: panic */
     if(fpga_test() != FPGA_TEST_TOKEN){
-      led_panic();
+      led_panic(LED_PANIC_FPGA_DEAD);
     }
     /* else reset */
   }

src/memory.c

@@ -54,11 +54,12 @@ void sram_hexdump(uint32_t addr, uint32_t len) {
   uint32_t ptr;
   for(ptr=0; ptr < len; ptr += 16) {
     sram_readblock((void*)buf, ptr+addr, 16);
-    uart_trace(buf, 0, 16);
+    uart_trace(buf, 0, 16, addr);
   }
 }
 
 void sram_writebyte(uint8_t val, uint32_t addr) {
+  printf("WriteB %8Xh @%08lXh\n", val, addr);
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x98); /* WRITE */
@@ -74,10 +75,12 @@ uint8_t sram_readbyte(uint32_t addr) {
   FPGA_WAIT_RDY();
   uint8_t val = FPGA_RX_BYTE();
   FPGA_DESELECT();
+  //printf(" ReadB %8Xh @%08lXh\n", val, addr);
   return val;
 }
 
 void sram_writeshort(uint16_t val, uint32_t addr) {
+  printf("WriteS %8Xh @%08lXh\n", val, addr);
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x98); /* WRITE */
@@ -89,6 +92,7 @@ void sram_writeshort(uint16_t val, uint32_t addr) {
 }
 
 void sram_writelong(uint32_t val, uint32_t addr) {
+  printf("WriteL %8lXh @%08lXh\n", val, addr);
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x98); /* WRITE */
@@ -112,6 +116,7 @@ uint16_t sram_readshort(uint32_t addr) {
   FPGA_WAIT_RDY();
   val |= ((uint32_t)FPGA_RX_BYTE()<<8);
   FPGA_DESELECT();
+  //printf(" ReadS %8lXh @%08lXh\n", val, addr);
   return val;
 }
 
@@ -128,6 +133,7 @@ uint32_t sram_readlong(uint32_t addr) {
   FPGA_WAIT_RDY();
   val |= ((uint32_t)FPGA_RX_BYTE()<<24);
   FPGA_DESELECT();
+  //printf(" ReadL %8lXh @%08lXh\n", val, addr);
   return val;
 }
 
@@ -163,7 +169,21 @@ void sram_readblock(void* buf, uint32_t addr, uint16_t size) {
   FPGA_DESELECT();
 }
 
+void sram_readstrn(void* buf, uint32_t addr, uint16_t size) {
+  uint16_t count=size;
+  uint8_t* tgt = buf;
+  set_mcu_addr(addr);
+  FPGA_SELECT();
+  FPGA_TX_BYTE(0x88);	/* READ */
+  while(count--) {
+    FPGA_WAIT_RDY();
+    if(!(*(tgt++) = FPGA_RX_BYTE())) break;
+  }
+  FPGA_DESELECT();
+}
+
 void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
+  printf("WriteZ %08lX -> %08lX [%d]\n", addr, addr+size, size);
   uint16_t count=size;
   uint8_t* src = buf;
   set_mcu_addr(addr);
@@ -178,7 +198,7 @@ void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
 
 uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
   UINT bytes_read;
-  DWORD filesize;
+  DWORD filesize, read_size = 0;
   UINT count=0;
   tick_t ticksstart, ticks_total=0;
   ticksstart=getticks();
@@ -197,7 +217,7 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
     printf("reconfigure FPGA with %s...\n", romprops.fpga_conf);
     fpga_pgm((uint8_t*)romprops.fpga_conf);
   }
-  set_mcu_addr(base_addr);
+  set_mcu_addr(base_addr + romprops.load_address);
   file_open(filename, FA_READ);
   ff_sd_offload=1;
   sd_offload_tgt=0;
@@ -206,12 +226,14 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
     ff_sd_offload=1;
     sd_offload_tgt=0;
     bytes_read = file_read();
+    read_size += bytes_read;
     if (file_res || !bytes_read) break;
     if(!(count++ % 512)) {
       uart_putc('.');
     }
   }
   file_close();
+  printf("Read %ld [%08lX] bytes...\n", read_size, read_size);
   set_mapper(romprops.mapper_id);
   printf("rom header map: %02x; mapper id: %d\n", romprops.header.map, romprops.mapper_id);
   ticks_total=getticks()-ticksstart;
@@ -261,6 +283,9 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
     rammask = romprops.ramsize_bytes - 1;
   }
   rommask = romprops.romsize_bytes - 1;
+  if (rommask >= SRAM_SAVE_ADDR)
+    rommask = SRAM_SAVE_ADDR - 1;
+  
   printf("ramsize=%x rammask=%lx\nromsize=%x rommask=%lx\n", romprops.header.ramsize, rammask, romprops.header.romsize, rommask);
   set_saveram_mask(rammask);
   set_rom_mask(rommask);
@@ -460,7 +485,6 @@ uint32_t load_bootrle(uint32_t base_addr) {
 
 void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
   uint32_t count = 0;
-  uint32_t num = 0;
 
   FPGA_DESELECT();
   file_open(filename, FA_CREATE_ALWAYS | FA_WRITE);
@@ -477,7 +501,7 @@ void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
       count++;
     }
     FPGA_DESELECT();
-    num = file_write();
+    file_write();
     if(file_res) {
       uart_putc(0x30+file_res);
     }
@@ -524,9 +548,9 @@ uint8_t sram_reliable() {
     val=sram_readlong(SRAM_SCRATCHPAD);
     if(val==0x12345678) {
       score++;
-    } else {
+    } //else {
-      printf("i=%d val=%08lX\n", i, val);
+      //printf("i=%d val=%08lX\n", i, val);
-    }
+    //}
   }
   if(score<SRAM_RELIABILITY_SCORE) {
     result = 0;
@@ -581,7 +605,6 @@ uint64_t sram_gettime(uint32_t base_addr) {
 
 void load_dspx(const uint8_t *filename, uint8_t coretype) {
   UINT bytes_read;
-  DWORD filesize;
   uint16_t word_cnt;
   uint8_t wordsize_cnt = 0;
   uint16_t sector_remaining = 0;
@@ -605,7 +628,6 @@ void load_dspx(const uint8_t *filename, uint8_t coretype) {
   }
 
   file_open((uint8_t*)filename, FA_READ);
-  filesize = file_handle.fsize;
   if(file_res) {
     printf("Could not read %s: error %d\n", filename, file_res);
     return;

src/memory.h

@@ -30,24 +30,26 @@
 #include <arm/NXP/LPC17xx/LPC17xx.h>
 #include "smc.h"
 
-#define SRAM_ROM_ADDR           (0x000000L)
+#define MASK_BITS                (0x000000)
-#define SRAM_SAVE_ADDR          (0xE00000L)
 
-#define SRAM_MENU_ADDR          (0xC00000L)
+#define SRAM_ROM_ADDR           ((0x000000L) & ~MASK_BITS)
-#define SRAM_DIR_ADDR           (0xC10000L)
+#define SRAM_SAVE_ADDR          ((0x600000L) & ~MASK_BITS)
-#define SRAM_DB_ADDR            (0xC80000L)
 
-#define SRAM_SPC_DATA_ADDR      (0xFD0000L)
+#define SRAM_MENU_ADDR          ((0x500000L) & ~MASK_BITS)
-#define SRAM_SPC_HEADER_ADDR    (0xFE0000L)
+#define SRAM_DIR_ADDR           ((0x510000L) & ~MASK_BITS)
+#define SRAM_DB_ADDR            ((0x580000L) & ~MASK_BITS)
 
-#define SRAM_MENU_SAVE_ADDR     (0xFF0000L)
+#define SRAM_SPC_DATA_ADDR      ((0x7D0000L) & ~MASK_BITS)
-#define SRAM_CMD_ADDR           (0xFF1000L)
+#define SRAM_SPC_HEADER_ADDR    ((0x7E0000L) & ~MASK_BITS)
-#define SRAM_PARAM_ADDR         (0xFF1004L)
+
-#define SRAM_STATUS_ADDR        (0xFF1100L)
+#define SRAM_MENU_SAVE_ADDR     ((0x7F0000L) & ~MASK_BITS)
-#define SRAM_SYSINFO_ADDR       (0xFF1200L)
+#define SRAM_CMD_ADDR           ((0x7F1000L) & ~MASK_BITS)
-#define SRAM_LASTGAME_ADDR      (0xFF1420L)
+#define SRAM_PARAM_ADDR         ((0x7F1004L) & ~MASK_BITS)
-#define SRAM_SCRATCHPAD         (0xFFFF00L)
+#define SRAM_STATUS_ADDR        ((0x7F1100L) & ~MASK_BITS)
-#define SRAM_DIRID              (0xFFFFF0L)
+#define SRAM_SYSINFO_ADDR       ((0x7F1200L) & ~MASK_BITS)
+#define SRAM_LASTGAME_ADDR      ((0x7F1420L) & ~MASK_BITS)
+#define SRAM_SCRATCHPAD         ((0x7FFF00L) & ~MASK_BITS)
+#define SRAM_DIRID              ((0x7FFFF0L) & ~MASK_BITS)
 #define SRAM_RELIABILITY_SCORE  (0x100)
 
 #define LOADROM_WITH_SRAM	(1)
@@ -68,6 +70,7 @@ void sram_writebyte(uint8_t val, uint32_t addr);
 void sram_writeshort(uint16_t val, uint32_t addr);
 void sram_writelong(uint32_t val, uint32_t addr);
 void sram_readblock(void* buf, uint32_t addr, uint16_t size);
+void sram_readstrn(void* buf, uint32_t addr, uint16_t size);
 void sram_readlongblock(uint32_t* buf, uint32_t addr, uint16_t count);
 void sram_writeblock(void* buf, uint32_t addr, uint16_t size);
 void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr);

src/msu1.c

@@ -161,7 +161,6 @@ int msu1_check(uint8_t* filename) {
 
 int msu1_loop() {
 /* it is assumed that the MSU file is already opened by calling msu1_check(). */
-  set_dac_vol(0x00);
   while(fpga_status() & 0x4000);
   uint16_t dac_addr = 0;
   uint16_t msu_addr = 0;
@@ -204,21 +203,18 @@ int msu1_loop() {
     /* Data buffer refill */
     if((fpga_status_now & 0x2000) != (fpga_status_prev & 0x2000)) {
       DBG_MSU1 printf("data\n");
-      uint8_t pageno = 0;
       if(fpga_status_now & 0x2000) {
         msu_addr = 0x0;
         msu_page1_start = msu_page2_start + msu_page_size;
-        pageno = 1;
       } else {
         msu_addr = 0x2000;
         msu_page2_start = msu_page1_start + msu_page_size;
-        pageno = 2;
       }
       set_msu_addr(msu_addr);
       sd_offload_tgt=2;
       ff_sd_offload=1;
       msu_res = f_read(&msufile, file_buf, 8192, &msu_data_bytes_read);
-      DBG_MSU1 printf("data buffer refilled. res=%d page1=%08lx page2=%08lx\n", msu_res, msu_page1_start, msu_page2_start);
+      DBG_MSU1 printf("data buffer refilled. page=%d res=%d page1=%08lx page2=%08lx\n", pageno, msu_res, msu_page1_start, msu_page2_start);
     }
 
     /* Audio buffer refill */

src/openocd-usb.cfg

@@ -5,8 +5,14 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x0403 0x6010
+ft2232_vid_pid 0x15ba 0x0003
-ft2232_device_desc "Dual RS232"
+ft2232_device_desc "Olimex OpenOCD JTAG"
-ft2232_layout "oocdlink"
+ft2232_layout "olimex-jtag"
-ft2232_latency 2
+
+
+#interface ft2232
+#ft2232_vid_pid 0x0403 0x6010
+#ft2232_device_desc "Dual RS232"
+#ft2232_layout "oocdlink"
+#ft2232_latency 2
 #adapter_khz 10

src/power.c

@@ -21,6 +21,6 @@ void power_init() {
                 | BV(PCRTC)
                 | BV(PCGPIO)
                 | BV(PCPWM1)
-//                 | BV(PCUSB)
+                | BV(PCUSB)
   ;
 }

src/sdcard.h

@@ -1,46 +0,0 @@
-/* sd2iec - SD/MMC to Commodore serial bus interface/controller
-   Copyright (C) 2007-2010  Ingo Korb <ingo@akana.de>
-
-   Inspiration and low-level SD/MMC access based on code from MMC2IEC
-     by Lars Pontoppidan et al., see sdcard.c|h and config.h.
-
-   FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; version 2 of the License only.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-
-   sdcard.h: Definitions for the SD/MMC access routines
-
-*/
-
-#ifndef SDCARD_H
-#define SDCARD_H
-
-#include "diskio.h"
-
-#define SD_TX_BYTE(x)		spi_tx_byte(x, SPI_SD);
-#define SD_RX_BYTE(x)		spi_rx_byte(x, SPI_SD);
-#define SD_TX_BLOCK(x,y)	spi_tx_block(x,y, SPI_SD);
-#define SD_RX_BLOCK(x,y)	spi_rx_block(x,y, SPI_SD);
-
-/* These functions are weak-aliased to disk_... */
-void    sd_init(void);
-DSTATUS sd_status(BYTE drv);
-DSTATUS sd_initialize(BYTE drv);
-DRESULT sd_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count);
-DRESULT sd_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count);
-DRESULT sd_getinfo(BYTE drv, BYTE page, void *buffer);
-
-void    sd_changed(void);
-#endif

src/sdnative.c

@@ -933,7 +933,7 @@ DSTATUS sdn_initialize(BYTE drv) {
 
   if((rsplen=cmd_slow(SEND_IF_COND, 0x000001aa, 0x87, NULL, rsp))) {
     DBG_SD printf("CMD8 response:\n");
-    DBG_SD uart_trace(rsp, 0, rsplen);
+    DBG_SD uart_trace(rsp, 0, rsplen, 0);
     hcs=1;
   }
   while(1) {

src/smc.c

@@ -59,6 +59,7 @@ void smc_id(snes_romprops_t* props) {
   uint8_t score, maxscore=1, score_idx=2; /* assume LoROM */
   snes_header_t* header = &(props->header);
 
+  props->load_address = 0;
   props->has_dspx = 0;
   props->has_st0010 = 0;
   props->has_cx4 = 0;
@@ -95,6 +96,14 @@ void smc_id(snes_romprops_t* props) {
           props->expramsize_bytes = 0;
           props->mapper_id = 3; /* BS-X Memory Map */
           props->region = 0; /* BS-X only existed in Japan */
+          uint8_t alloc = header->name[0x10];
+          if(alloc) {
+            while(!(alloc & 0x01)) {
+              props->load_address += 0x20000;
+              alloc >>= 1;
+            }
+          }
+          printf("load address: %lx\n", props->load_address);
           return;
         }
       }
@@ -199,7 +208,7 @@ void smc_id(snes_romprops_t* props) {
   props->ramsize_bytes = (uint32_t)1024 << header->ramsize;
   props->romsize_bytes = (uint32_t)1024 << header->romsize;
   props->expramsize_bytes = (uint32_t)1024 << header->expramsize;
-/*dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); */
+  //dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); 
   if(props->ramsize_bytes > 32768 || props->ramsize_bytes < 2048) {
     props->ramsize_bytes = 0;
   }

src/smc.h

@@ -84,6 +84,7 @@ typedef struct _snes_romprops {
   uint8_t has_cx4;            /* CX4 presence flag */
   uint8_t fpga_features;      /* feature/peripheral enable bits*/
   uint8_t region;             /* game region (derived from destination code) */
+  uint32_t load_address;      /* where to load the ROM image */
   snes_header_t header;       /* original header from ROM image */
 } snes_romprops_t;
 

src/snes.c

@@ -83,6 +83,10 @@ void snes_reset_pulse() {
  *  state: put SNES in reset state when 1, release when 0
  */
 void snes_reset(int state) {
+  if (state == 0)
+    printf("Releasing SNES RESET\n");
+  else
+    printf("Pull SNES RESET\n");
   BITBAND(SNES_RESET_REG->FIODIR, SNES_RESET_BIT) = state;
 }
 
@@ -123,7 +127,7 @@ void snes_main_loop() {
       samecount++;
     }
     if(diffcount>=1 && samecount==5) {
-      printf("SaveRAM CRC: 0x%04lx; saving\n", saveram_crc);
+      printf("SaveRAM CRC: 0x%04lx; saving %s\n", saveram_crc, file_lfn);
       writeled(1);
       save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR);
       writeled(0);
@@ -170,11 +174,15 @@ void get_selected_name(uint8_t* fn) {
   sram_readblock(fn, addr + 7 + SRAM_MENU_ADDR, 256);
 }
 
-void snes_bootprint(void* msg) {
+void snes_bootprint(void* msg)
+{
+  printf("%s\n", (char*)msg);
   sram_writeblock(msg, SRAM_CMD_ADDR, 33);
 }
 
-void snes_menu_errmsg(int err, void* msg) {
+void snes_menu_errmsg(int err, void* msg)
+{
+  printf("%d: %s\n", err, (char*)msg);
   sram_writeblock(msg, SRAM_CMD_ADDR+1, 64);
   sram_writebyte(err, SRAM_CMD_ADDR);
 }

src/sort.c

@@ -15,7 +15,7 @@
 */
 
 uint32_t stat_getstring = 0;
-static char sort_str1[21], sort_str2[21];
+static char sort_str1[SORT_STRLEN+1], sort_str2[SORT_STRLEN+1];
 uint32_t ptrcache[QSORT_MAXELEM] IN_AHBRAM;
 
 /* get element from pointer table in external RAM*/
@@ -71,13 +71,12 @@ void sort_getstring_for_dirent(char *ptr, uint32_t addr) {
   if(addr & 0x80000000) {
     /* is directory link, name offset 4 */
     leaf_offset = sram_readbyte(addr + 4 + SRAM_MENU_ADDR);
-    sram_readblock(ptr, addr + 5 + leaf_offset + SRAM_MENU_ADDR, 20);
+    sram_readstrn(ptr, addr + 5 + leaf_offset + SRAM_MENU_ADDR, SORT_STRLEN);
   } else {
     /* is file link, name offset 6 */
     leaf_offset = sram_readbyte(addr + 6 + SRAM_MENU_ADDR);
-    sram_readblock(ptr, addr + 7 + leaf_offset + SRAM_MENU_ADDR, 20);
+    sram_readstrn(ptr, addr + 7 + leaf_offset + SRAM_MENU_ADDR, SORT_STRLEN);
   }
-  ptr[20]=0;
 }
 
 void sort_heapify(uint32_t addr, unsigned int i, unsigned int heapsize)

src/tests/Makefile

@@ -138,7 +138,8 @@ CFLAGS += $(CDEFS) $(CINCS)
 CFLAGS += -O$(OPT)
 CFLAGS += $(CPUFLAGS) -nostartfiles
 #CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
-CFLAGS += -Wall -Wstrict-prototypes -Werror
+CFLAGS += -Wall -Wstrict-prototypes
+# -Werror
 CFLAGS += -Wa,-adhlns=$(OBJDIR)/$(<:.c=.lst)
 CFLAGS += -I$(OBJDIR)
 CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))

src/tests/cli.c

@@ -138,7 +138,7 @@ static int8_t parse_wordlist(char *wordlist) {
         return -1;
       }
 
-      if (tolower(c) != tolower(*cur)) {
+      if (tolower((int)c) != tolower((int)*cur)) {
         // Check for end-of-word
         if (cur != curchar && (*cur == ' ' || *cur == 0)) {
           // Partial match found, return that

src/tests/config.h

@@ -38,7 +38,8 @@
 //#define CONFIG_CPU_FREQUENCY      46000000
 #define CONFIG_UART_PCLKDIV       1
 #define CONFIG_UART_TX_BUF_SHIFT  8
-#define CONFIG_UART_BAUDRATE      921600
+//#define CONFIG_UART_BAUDRATE      921600
+#define CONFIG_UART_BAUDRATE 115200
 #define CONFIG_UART_DEADLOCKABLE
 
 #define SSP_CLK_DIVISOR_FAST 2

src/tests/openocd-usb.cfg

@@ -5,8 +5,14 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x0403 0x6010
+ft2232_vid_pid 0x15ba 0x0003
-ft2232_device_desc "Dual RS232"
+ft2232_device_desc "Olimex OpenOCD JTAG"
-ft2232_layout "oocdlink"
+ft2232_layout "olimex-jtag"
-ft2232_latency 2
+
+
+#interface ft2232
+#ft2232_vid_pid 0x0403 0x6010
+#ft2232_device_desc "Dual RS232"
+#ft2232_layout "oocdlink"
+#ft2232_latency 2
 #adapter_khz 10

src/tests/tests.c

@@ -152,74 +152,178 @@ int test_fpga() {
   return PASSED;
 }
 
-int test_mem() {
+/*************************************************************************************/
-  printf("RAM test\n========\n");
+/*************************************************************************************/
-  printf("Testing RAM0 (128Mbit) - writing RAM -");
+
-  uint32_t addr;
+typedef struct memory_test
+{
+  char name[20];
+  int a_len;
+  int d_len;
+
+  unsigned int (*read)(unsigned int addr);
+  void (*write)(unsigned int addr, unsigned int data);
+  void (*open)(void);
+  void (*close)(void);
+} memory_test;
+
+/*************************************************************************************/
+
+void rom_open(void)
+{
   snes_reset(1);
   fpga_select_mem(0);
-  set_mcu_addr(0);
   FPGA_DESELECT();
   delay_ms(1);
   FPGA_SELECT();
   delay_ms(1);
-  FPGA_TX_BYTE(0x98);
+}
-  for(addr=0; addr < 16777216; addr++) {
+void rom_close(void)
-    if((addr&0xffff) == 0)printf("\x8%c", PROGRESS[(addr>>16)&3]);
+{
-    FPGA_TX_BYTE((addr)+(addr>>8)+(addr>>16));
+}
-    FPGA_WAIT_RDY();
+
-  }
+unsigned int rom_read(unsigned int addr)
-  FPGA_DESELECT();
+{
-  printf(" verifying RAM -");
+  return sram_readbyte(addr);
-  uint8_t data, expect, error=0, failed=0;
+}
-  set_mcu_addr(0);
+
-  FPGA_SELECT();
+void rom_write(unsigned int addr, unsigned int data)
-  FPGA_TX_BYTE(0x88);
+{
-  for(addr=0; addr < 16777216; addr++) {
+  sram_writebyte(data, addr);
-    if((addr&0xffff) == 0)printf("\x8%c", PROGRESS[(addr>>16)&3]);
+}
-    FPGA_WAIT_RDY();
+
-    data = FPGA_RX_BYTE();
+memory_test rom = {
-    expect = (addr)+(addr>>8)+(addr>>16);
+  .name = "RAM0 (128Mbit)",
-    if(data != expect) {
+  .a_len = 22,
-      printf("error @0x%06lx: expected 0x%02x, got 0x%02x\n", addr, expect, data);
+  .d_len = 8,
-      error++;
+  .read = rom_read,
-      failed=1;
+  .write = rom_write,
-      if(error>20) {
+  .open = rom_open,
-        printf("too many errors, aborting\n");
+  .close = rom_close,
-        break;
+};
-      }
+
-    }
+/*************************************************************************************/
-  }
+
-  FPGA_DESELECT();
+void sram_open(void)
-  if(error) printf("RAM0 FAILED\n");
+{
-  else printf("RAM0 PASSED\n");
-  printf("Testing RAM1 (4Mbit) - writing RAM - ");
   snes_reset(1);
   fpga_select_mem(1);
-  for(addr=0; addr < 524288; addr++) {
+}
-    sram_writebyte((addr)+(addr>>8)+(addr>>16), addr);
+
-  }
+void sram_close(void)
-  printf("verifying RAM...");
+{
-  error = 0;
+}
-  for(addr=0; addr < 524288; addr++) {
+
-    data = sram_readbyte(addr);
+unsigned int sram_read(unsigned int addr)
-    expect = (addr)+(addr>>8)+(addr>>16);
+{
-    if(data != expect) {
+  return sram_readbyte(addr);
-      printf("error @0x%05lx: expected 0x%02x, got 0x%02x\n", addr, expect, data);
+}
-      error++;
+
-      failed=1;
+void sram_write(unsigned int addr, unsigned int data)
-      if(error>20) {
+{
-        printf("too many errors, aborting\n");
+  sram_writebyte(data, addr);
-        break;
+}
-      }
+
+memory_test sram = 
+{
+  .name = "RAM1(4Mbit)",
+  .a_len = 19,
+  .d_len = 8,
+  .read = sram_read,
+  .write = sram_write,
+  .open = sram_open,
+  .close = sram_close,
+};
+
+int do_test(memory_test *test)
+{
+  int i, j, read, want;
+  int ret = 0;
+  int a_mask = (1 << test->a_len) - 1;
+  int d_mask = (1 << test->d_len) - 1;
+
+  test->open();
+
+  printf("-- Will test %s\n", test->name);
+  printf("---- Fill with AA55  ");
+  test->write(0, 0xAA);
+  for (i = 1; i < a_mask; i++)
+  {
+    if((i&0xffff) == 0)printf("\x8%c", PROGRESS[(i>>16)&3]);
+    want = (i&1)?0x55:0xAA;
+    test->write(i, want);
+
+    want = ((i-1)&1)?0x55:0xAA;
+    read = test->read(i-1);
+
+    if (read != want)
+    {
+      printf("Failed [@%8X Want: %02X Get: %02X]", i-1, want, read);
+      ret |= 1;
+      break;
     }
   }
-  if(error) printf("RAM1 FAILED\n\n\n");
+
-  else printf("RAM1 PASSED\n\n\n");
+  printf("Ok \n---- Fill with 00    ");
-  if(failed) return FAILED;
+  for (i = 0; i < a_mask; i++)
+  {
+    if((i&0xffff) == 0)printf("\x8%c", PROGRESS[(i>>16)&3]);
+    test->write(i, 0);
+  }
+
+  printf("Ok \n---- Check data lines...\n"
+         "-----           ");
+  for (i = 0; i < test->d_len; i++) printf("%X", i);
+  printf("\n");
+  /* Check on 4 addresses, taken evenly */
+#define TEST_NUM (10)
+
+  for (j = 0; j < TEST_NUM; j ++)
+  {
+    printf("----- %8X [", j * a_mask/TEST_NUM);
+    for (i = 0; i < test->d_len; i++)
+    {
+      read = test->read(j * a_mask/TEST_NUM);
+      if ((test->read(j * a_mask/TEST_NUM) & (1<<i)) != 0)
+      {
+        printf("1", read);
+        ret |= 2;
+        goto next_data;
+      }
+      test->write(j * a_mask/TEST_NUM, (1<<i));
+      read = test->read(j * a_mask/TEST_NUM);
+      if (read == 0)
+      {
+        printf("0");
+        ret |= 4;
+        goto next_data;
+      }
+      printf("x");
+
+next_data:
+      test->write(j * a_mask/4, 0);
+    }
+    printf("]\n");
+  }
+
+
+  test->close();
+  return ret;
+}
+
+int test_mem()
+{
+  int ret = PASSED;
+  printf("RAM test\n========\n");
+
+  if (do_test(&rom) != 0)
+    ret = FAILED;
+  if (do_test(&sram) != 0);
+    ret = FAILED;
   return PASSED;
 }
 
+
 int test_clk() {
   uint32_t sysclk[4];
   int32_t diff, max_diff = 0;

src/timer.c

@@ -57,9 +57,17 @@ void timer_init(void) {
   /* clear RIT mask */
   LPC_RIT->RIMASK = 0; /*xffffffff;*/
 
-  /* PCLK = CCLK */
+  /* PCLK_RIT = CCLK */
+  BITBAND(LPC_SC->PCLKSEL1, 27) = 0;
   BITBAND(LPC_SC->PCLKSEL1, 26) = 1;
+
+  /* PCLK_TIMER3 = CCLK/4 */
+  BITBAND(LPC_SC->PCLKSEL1, 15) = 0;
+  BITBAND(LPC_SC->PCLKSEL1, 14) = 0;
+
+  /* enable timer 3 */
   BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1;
+
   /* enable SysTick */
   SysTick_Config((SysTick->CALIB & SysTick_CALIB_TENMS_Msk));
 }

src/uart.c

@@ -238,7 +238,7 @@ void uart_puthex(uint8_t num) {
     uart_putc('a'+tmp-10);
 }
 
-void uart_trace(void *ptr, uint16_t start, uint16_t len) {
+void uart_trace(void *ptr, uint16_t start, uint16_t len, uint32_t addr) {
   uint16_t i;
   uint8_t j;
   uint8_t ch;
@@ -247,8 +247,9 @@ void uart_trace(void *ptr, uint16_t start, uint16_t len) {
   data+=start;
   for(i=0;i<len;i+=16) {
 
-    uart_puthex(start>>8);
+    uart_puthex((addr + start)>>16);
-    uart_puthex(start&0xff);
+    uart_puthex(((addr + start)>>8) & 0xff);
+    uart_puthex((addr + start)&0xff);
     uart_putc('|');
     uart_putc(' ');
     for(j=0;j<16;j++) {

src/uart.h

@@ -26,7 +26,7 @@ unsigned char uart_gotc(void);
 void uart_putc(char c);
 void uart_puts(const char *str);
 void uart_puthex(uint8_t num);
-void uart_trace(void *ptr, uint16_t start, uint16_t len);
+void uart_trace(void *ptr, uint16_t start, uint16_t len, uint32_t addr);
 void uart_flush(void);
 int  printf(const char *fmt, ...);
 int  snprintf(char *str, size_t size, const char *format, ...);

src/utils/Makefile

@@ -2,11 +2,14 @@
 CC = gcc
 CFLAGS = -Wall -Wstrict-prototypes -Werror
 
-all: lpcchksum genhdr
+all: lpcchksum genhdr bin2h
 
 genhdr: genhdr.o
 	$(CC) $(CFLAGS) $^ --output $@
 
+bin2h: bin2h.o
+	$(CC) $(CFLAGS) $^ --output $@
+
 lpcchksum: lpcchksum.o
 	$(CC) $(CFLAGS) $^ --output $@
 

src/utils/bin2h.c

@@ -0,0 +1,49 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(int argc, char *argv[])
+{
+   char var_name[30] = "cfgware"
+   FILE *fpIn = NULL, *fpOut = NULL;
+   unsigned char buffer[5], i;
+   if ( argc == 4 )
+   {
+      fpIn = fopen(argv[1], "rb");
+      fpOut = fopen(argv[2], "wt");
+   }
+   else if (argc == 3)
+   {
+      fpIn = fopen(argv[1], "rb");
+      fpOut = stdout;
+   }
+   else if ( argc == 2 )
+   {
+      fpIn = stdin;
+      fpOut = stdout;
+   }
+   else
+   {
+      fprintf(stderr, "usage: %s [infile] [outfile]\n", argv[0]);
+      return -1;
+   }
+   
+   if (argc > 1)
+      sprintf()
+
+   if (fpIn == NULL) { fprintf(stderr, "Can't open '%s`: Aborting.", argv[1]); return -1; }
+   if (fpOut == NULL) { fprintf(stderr, "Can't open '%s`: Aborting.", argv[2]); return -1; }
+   
+   fprintf(fpOut, "const uint8_t %s[] = {\n", var_name);
+   i = 0;
+   while(!feof(fpIn))
+   {
+      fread(buffer, 1, 1, fpIn);
+      fprintf(fpOut, "0x%02X, ", buffer[0]);
+      i++; if (i > 8) { fprintf(fpOut, "\n"); i = 0; }
+   }
+   if (i > 0)
+      fprintf(fpOut, "\n");
+   fprintf(fpOut, "};");
+   fclose(fpOut); fclose(fpIn);
+   return 0;
+}

src/xmodem.c

@@ -6,8 +6,8 @@
 #include "xmodem.h"
 
 void xmodem_rxfile(FIL* fil) {
-  uint8_t rxbuf[XMODEM_BLKSIZE], sum=0, sender_sum;
+  uint8_t rxbuf[XMODEM_BLKSIZE], sum=0/*, sender_sum*/;
-  uint8_t blknum, blknum2;
+/*  uint8_t blknum, blknum2;*/
   uint8_t count;
   uint32_t totalbytes = 0;
   uint32_t totalwritten = 0;
@@ -19,13 +19,13 @@ void xmodem_rxfile(FIL* fil) {
     uart_putc(ASC_NAK);
   } while (uart_getc() != ASC_SOH);
   do {
-    blknum=uart_getc();
+    /*blknum=*/uart_getc();
-    blknum2=uart_getc();
+    /*blknum2=*/uart_getc();
     for(count=0; count<XMODEM_BLKSIZE; count++) {
       sum += rxbuf[count] = uart_getc();
       totalbytes++;
     }
-    sender_sum = uart_getc();
+    /*sender_sum =*/ uart_getc();
     res=f_write(fil, rxbuf, XMODEM_BLKSIZE, &written);
     totalwritten += written;
     uart_putc(ASC_ACK);
@@ -33,5 +33,7 @@ void xmodem_rxfile(FIL* fil) {
   uart_putc(ASC_ACK);
   uart_flush();
   sleep_ms(1000);
+  sender_sum = blknum + blknum2;
+  printf("%x:%x:%x\n", blknum, blknum2, sender_sum);
   printf("received %ld bytes, wrote %ld bytes. last res = %d\n", totalbytes, totalwritten, res);
 }

verilog/sd2snes/address.v

@@ -33,6 +33,7 @@ module address(
   output msu_enable,
   output srtc_enable,
   output use_bsx,
+  output bsx_tristate,
   input [14:0] bsx_regs,
   output dspx_enable,
   output dspx_dp_enable,
@@ -85,12 +86,12 @@ assign IS_SAVERAM = SAVERAM_MASK[0]
                          & &SNES_ADDR[14:13]
                          & !SNES_ADDR[15]
                         )
-/*  LoROM:   SRAM @ Bank 0x70-0x7d, 0xf0-0xfd Offset 0000-7fff
+/*  LoROM:   SRAM @ Bank 0x70-0x7d, 0xf0-0xfd
-             TODO: 0000-ffff for small ROMs? */
+ *  Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff */
                       :(MAPPER == 3'b001)
                       ? (&SNES_ADDR[22:20]
                          & (SNES_ADDR[19:16] < 4'b1110)
-                         & !SNES_ADDR[15]
+                         & (~SNES_ADDR[15] | ~ROM_MASK[21])
                         )
 /*  BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
                       :(MAPPER == 3'b011)
@@ -101,17 +102,38 @@ assign IS_SAVERAM = SAVERAM_MASK[0]
 
 
 /* BS-X has 4 MBits of extra RAM that can be mapped to various places */
+wire [2:0] BSX_PSRAM_BANK = {bsx_regs[2], bsx_regs[6], bsx_regs[5]};
+wire [23:0] BSX_CHKADDR = bsx_regs[2] ? SNES_ADDR : {SNES_ADDR[23], 1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]};
+wire BSX_PSRAM_LOHI = (bsx_regs[3] & ~SNES_ADDR[23]) | (bsx_regs[4] & SNES_ADDR[23]);
+wire BSX_IS_PSRAM = BSX_PSRAM_LOHI
+                     & (( (BSX_CHKADDR[22:20] == BSX_PSRAM_BANK)
+                         &(SNES_ADDR[15] | bsx_regs[2])
+                         &(~(SNES_ADDR[19] & bsx_regs[2])))
+                       | (bsx_regs[2]
+                          ? (SNES_ADDR[22:21] == 2'b01 & SNES_ADDR[15:13] == 3'b011)
+                          : (&SNES_ADDR[22:20] & ~SNES_ADDR[15]))
+                       );
+
+wire BSX_IS_CARTROM = ((bsx_regs[7] & (SNES_ADDR[23:22] == 2'b00))
+                      |(bsx_regs[8] & (SNES_ADDR[23:22] == 2'b10)))
+							 & SNES_ADDR[15];
+
+wire BSX_HOLE_LOHI = (bsx_regs[9] & ~SNES_ADDR[23]) | (bsx_regs[10] & SNES_ADDR[23]);
+
+wire BSX_IS_HOLE = BSX_HOLE_LOHI
+                   & (bsx_regs[2] ? (SNES_ADDR[21:20] == {bsx_regs[11], 1'b0})
+                                  : (SNES_ADDR[22:21] == {bsx_regs[11], 1'b0}));
+
+assign bsx_tristate = (MAPPER == 3'b011) & ~BSX_IS_CARTROM & ~BSX_IS_PSRAM & BSX_IS_HOLE;
+
 assign IS_WRITABLE = IS_SAVERAM
                      |((MAPPER == 3'b011)
-                       ?((bsx_regs[3] && SNES_ADDR[23:20]==4'b0110)
+                       ? BSX_IS_PSRAM
-                         |(!bsx_regs[5] && SNES_ADDR[23:20]==4'b0100)
-                         |(!bsx_regs[6] && SNES_ADDR[23:20]==4'b0101)
-                         |(SNES_ADDR[23:19] == 5'b01110)
-                         |(SNES_ADDR[23:21] == 3'b001
-                           && SNES_ADDR[15:13] == 3'b011)
-                        )
                        : 1'b0);
 
+wire [23:0] BSX_ADDR = bsx_regs[2] ? {1'b0, SNES_ADDR[22:0]}
+                                   : {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]};
+
 /* BSX regs:
  Index  Function
     1   0=map flash to ROM area; 1=map PRAM to ROM area
@@ -125,47 +147,33 @@ assign IS_WRITABLE = IS_SAVERAM
 
 assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
                           ?(IS_SAVERAM
-                            ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
+                            ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
                                             & SAVERAM_MASK)
                             : ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
 
                           :(MAPPER == 3'b001)
                           ?(IS_SAVERAM
-                            ? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
+                            ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[14:0]}
+                                            & SAVERAM_MASK)
                             : ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
                                & ROM_MASK))
 
                           :(MAPPER == 3'b010)
                           ?(IS_SAVERAM
-                            ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
+                            ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
                                             & SAVERAM_MASK)
                             : ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
                                & ROM_MASK))
                           :(MAPPER == 3'b011)
-                          ?(IS_SAVERAM
+                          ?(  IS_SAVERAM
-                            ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
+                              ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
-                            : IS_WRITABLE
+                              : BSX_IS_CARTROM
-                              ? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
+                              ? (24'h800000 + ({SNES_ADDR[22:16], SNES_ADDR[14:0]} & 24'h0fffff))
-                            : bs_page_enable
+                              : BSX_IS_PSRAM
-									   ? (24'h900000 + {bs_page,bs_page_offset})
+                              ? (24'h400000 + (BSX_ADDR & 24'h07FFFF))
-								    :((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
+                              : bs_page_enable
-                                 |(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
+                              ? (24'h900000 + {bs_page,bs_page_offset})
-                                 ?(24'h800000
+                              : (BSX_ADDR & 24'h0fffff)
-                                   + ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
-                                     & 24'h0FFFFF)
-                                   )
-                                 :((bsx_regs[1]
-                                   ? 24'h400000
-                                   : 24'h000000
-                                   )
-                                   + bsx_regs[2]
-                                     ?({2'b00, SNES_ADDR[21:0]}
-                                       & (ROM_MASK /* >> bsx_regs[1] */)
-                                      )
-                                     :({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
-                                       & (ROM_MASK /* >> bsx_regs[1] */)
-                                      )
-                                  )
                            )
                            :(MAPPER == 3'b110)
                            ?(IS_SAVERAM

verilog/sd2snes/bsx.v

@@ -135,8 +135,8 @@ wire [7:0] rtc_year100 = rtc_data[51:48] + (rtc_data[55:52] << 3) + (rtc_data[55
 wire [15:0] rtc_year = (rtc_year100 << 6) + (rtc_year100 << 5) + (rtc_year100 << 2) + rtc_year1;
 
 initial begin
-  regs_tmpr <= 15'b000000100000000;
+  regs_tmpr <= 15'b000101111101100;
-  regs_outr <= 15'b000000100000000;
+  regs_outr <= 15'b000101111101100;
   bsx_counter <= 0;
   base_regs[5'h08] <= 0;
   base_regs[5'h09] <= 0;
@@ -213,7 +213,7 @@ always @(posedge clkin) begin
 				14: reg_data_outr <= rtc_day;
 				15: reg_data_outr <= rtc_month;
 				16: reg_data_outr <= rtc_year[7:0];
-				17: reg_data_outr <= rtc_year[15:8];
+				17: reg_data_outr <= rtc_hour;
             default: reg_data_outr <= 8'h0;
           endcase
         end
@@ -240,8 +240,8 @@ always @(posedge clkin) begin
     regs_tmpr[8:1] <= (regs_tmpr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
     regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
   end else if(reg_we_rising && cart_enable) begin
-    if(reg_addr == 4'he && reg_data_in[7])
+    if(reg_addr == 4'he)
-      regs_outr <= regs_tmpr | 15'b100000000000000;
+      regs_outr <= regs_tmpr;
     else
       regs_tmpr[reg_addr] <= reg_data_in[7];
   end else if(reg_we_rising && base_enable) begin

verilog/sd2snes/main.v

@@ -440,6 +440,7 @@ address snes_addr(
   .bs_page_offset(bs_page_offset),
   .bs_page(bs_page),
   .bs_page_enable(bs_page_enable),
+  .bsx_tristate(bsx_tristate),
   //SRTC
   .srtc_enable(srtc_enable),
   //uPD77C25
@@ -472,10 +473,10 @@ parameter ST_MCU_WR_WAIT  = 18'b000100000000000000;
 parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
 parameter ST_MCU_WR_END   = 18'b010000000000000000;
 
-parameter ROM_RD_WAIT = 4'h0;
+parameter ROM_RD_WAIT = 4'h1;
 parameter ROM_RD_WAIT_MCU = 4'h6;
 parameter ROM_WR_WAIT = 4'h4;
-parameter ROM_WR_WAIT1 = 4'h2;
+parameter ROM_WR_WAIT1 = 4'h3;
 parameter ROM_WR_WAIT2 = 4'h1;
 parameter ROM_WR_WAIT_MCU = 4'h5;
 
@@ -533,8 +534,12 @@ initial ROM_SAr = 1'b1;
 //wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
 wire ROM_SA = ROM_SAr;
 
-assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
+//assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
-assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
+//assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
+
+//WARNING DUE TO BAD SOLDER WE LOST HALF OF THE PSRAM!!!
+assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[22:0] : (ROM_SA) ? MAPPED_SNES_ADDR[22:0] : ROM_ADDRr[22:0];
+assign ROM_ADDR0 = 1'b0; //(SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
 
 reg ROM_WEr;
 initial ROM_WEr = 1'b1;
@@ -581,14 +586,12 @@ always @(posedge CLK2) begin
 		ROM_DOUT_ENr <= 1'b0;
 	   if(SNES_cycle_start & ~SNES_WRITE) begin
 		  STATE <= ST_SNES_WR_ADDR;
-		  if(IS_SAVERAM | IS_WRITABLE | IS_FLASHWR) begin
+		  if(IS_WRITABLE | (IS_FLASHWR & ~bsx_tristate)) begin
 		    ROM_WEr <= 1'b0;
-          ROM_DOUT_ENr <= 1'b1;
         end
 		end else if(SNES_cycle_start) begin
-//		  STATE <= ST_SNES_RD_ADDR;		  
+		  STATE <= ST_SNES_RD_ADDR;		  
-        STATE <= ST_SNES_RD_END;
+//        STATE <= ST_SNES_RD_END;
-        SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
 		end else if(SNES_DEADr & MCU_RD_PENDr) begin
 		  STATE <= ST_MCU_RD_ADDR;
 		end else if(SNES_DEADr & MCU_WR_PENDr) begin
@@ -601,12 +604,15 @@ always @(posedge CLK2) begin
 	 end
 	 ST_SNES_RD_WAIT: begin
 	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
-//		if(ST_MEM_DELAYr == 0) begin
+		if(ST_MEM_DELAYr == 0) begin
-//		end
+		  STATE <= ST_SNES_RD_END;
-//		else STATE <= ST_SNES_RD_WAIT;
+		  SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
+		end
+		else STATE <= ST_SNES_RD_WAIT;
 	 end
 	 
 	 ST_SNES_WR_ADDR: begin
+      ROM_DOUT_ENr <= 1'b1;
 	   ST_MEM_DELAYr <= ROM_WR_WAIT1;
 	   STATE <= ST_SNES_WR_WAIT1;
 	 end
@@ -624,11 +630,12 @@ always @(posedge CLK2) begin
 		if(ST_MEM_DELAYr == 0) begin
         STATE <= ST_SNES_WR_END;
 		  ROM_WEr <= 1'b1;
+        ROM_DOUT_ENr <= 1'b0;		
 		end
 		else STATE <= ST_SNES_WR_WAIT2;
     end
 	 ST_SNES_RD_END, ST_SNES_WR_END: begin
-	   ROM_DOUT_ENr <= 1'b0;		
+//	   ROM_DOUT_ENr <= 1'b0;		
       if(MCU_RD_PENDr) begin
         STATE <= ST_MCU_RD_ADDR;
       end else if(MCU_WR_PENDr) begin
@@ -648,7 +655,7 @@ always @(posedge CLK2) begin
 		else STATE <= ST_MCU_RD_WAIT;
 	 end
 	 ST_MCU_RD_END: begin
-      MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
+      MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8]; /*ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];*/
 	   STATE <= ST_IDLE;
 	 end
 	 
@@ -657,18 +664,18 @@ always @(posedge CLK2) begin
       ROM_SAr <= 1'b0;
 	   ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
 		STATE <= ST_MCU_WR_WAIT;
-		ROM_DOUT_ENr <= 1'b1;
 		ROM_WEr <= 1'b0;
 	 end
 	 ST_MCU_WR_WAIT: begin
 	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		ROM_DOUT_ENr <= 1'b1;
 		if(ST_MEM_DELAYr == 0) begin
 		  ROM_WEr <= 1'b1;
 		  STATE <= ST_MCU_WR_END;
 		end
 		else STATE <= ST_MCU_WR_WAIT;	 
 	 end
-	 ST_MCU_WR_END: begin
+ 	 ST_MCU_WR_END: begin
 		ROM_DOUT_ENr <= 1'b0;
 	   STATE <= ST_IDLE;
 	 end
@@ -704,18 +711,25 @@ always @(posedge CLK2) begin
   MCU_WRITE_1<= MCU_WRITE;
 end
 
+/*
 assign ROM_DATA[7:0] = ROM_ADDR0
                        ?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
-							                   /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+							                   //: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA 
                                         : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                         )
                        :8'bZ;
 
 assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
                         :(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
-								                 /*:  ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+								                 //:  ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA 
                                          : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                          );
+*/
+assign ROM_DATA[7:0] = SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+							  : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
+
+assign ROM_DATA[15:8] = SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+								                 : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
 
 assign ROM_WE = SD_DMA_TO_ROM
                 ?MCU_WRITE
@@ -726,8 +740,8 @@ assign ROM_OE = 1'b0;
 
 assign ROM_CE = 1'b0;
 
-assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BHE = 1'b0; ///*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
-assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BLE = 1'b0; ///*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
 
 assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
                          msu_enable ? 1'b0 :
@@ -739,6 +753,7 @@ assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
                          ((IS_ROM & SNES_CS)
                           |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
                           |(SNES_READr[0] & SNES_WRITEr[0])
+                          | bsx_tristate
                          );
 
 assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescmd_rd_enable)))
@@ -747,7 +762,7 @@ assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescm
 
 assign SNES_IRQ = 1'b0;
 
-assign p113_out = 1'b0;
+assign p113_out = 1'b1;
 
 /*
 wire [35:0] CONTROL0;

verilog/sd2snes/sd2snes.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">

verilog/sd2snes_cx4/main.v

@@ -370,13 +370,13 @@ parameter ST_CX4_RD_ADDR  = 21'b000100000000000000000;
 parameter ST_CX4_RD_WAIT  = 21'b001000000000000000000;
 parameter ST_CX4_RD_END   = 21'b010000000000000000000;
 
-parameter ROM_RD_WAIT = 4'h0;
+parameter ROM_RD_WAIT = 4'h1;
 parameter ROM_RD_WAIT_MCU = 4'h6;
 parameter ROM_WR_WAIT = 4'h4;
-parameter ROM_WR_WAIT1 = 4'h2;
+parameter ROM_WR_WAIT1 = 4'h3;
 parameter ROM_WR_WAIT2 = 4'h1;
 parameter ROM_WR_WAIT_MCU = 4'h5;
-parameter ROM_RD_WAIT_CX4 = 4'h6;
+parameter ROM_RD_WAIT_CX4 = 4'h7;
 
 parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
 
@@ -510,9 +510,8 @@ always @(posedge CLK2) begin
           ROM_DOUT_ENr <= 1'b1;
         end
 		end else if(SNES_cycle_start) begin
-//		  STATE <= ST_SNES_RD_ADDR;		  
+		  STATE <= ST_SNES_RD_ADDR;		  
-        STATE <= ST_SNES_RD_END;
+//        STATE <= ST_SNES_RD_END;
-        SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
 		end else if(SNES_DEADr & MCU_RD_PENDr) begin
 		  STATE <= ST_MCU_RD_ADDR;
 		end else if(SNES_DEADr & MCU_WR_PENDr) begin
@@ -525,12 +524,15 @@ always @(posedge CLK2) begin
 	 end
 	 ST_SNES_RD_WAIT: begin
 	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
-//		if(ST_MEM_DELAYr == 0) begin
+           if(ST_MEM_DELAYr == 0) begin
-//		end
+             STATE <= ST_SNES_RD_END;
-//		else STATE <= ST_SNES_RD_WAIT;
+             SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
+           end
+           else STATE <= ST_SNES_RD_WAIT;
 	 end
 	 
 	 ST_SNES_WR_ADDR: begin
+           ROM_DOUT_ENr <= 1'b1;
 	   ST_MEM_DELAYr <= ROM_WR_WAIT1;
 	   STATE <= ST_SNES_WR_WAIT1;
 	 end
@@ -546,19 +548,19 @@ always @(posedge CLK2) begin
 	 ST_SNES_WR_WAIT2: begin
 	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
 		if(ST_MEM_DELAYr == 0) begin
-        STATE <= ST_SNES_WR_END;
+                  STATE <= ST_SNES_WR_END;
-		  ROM_WEr <= 1'b1;
+                  ROM_WEr <= 1'b1;
 		end
 		else STATE <= ST_SNES_WR_WAIT2;
-    end
+         end
-	 ST_SNES_RD_END, ST_SNES_WR_END: begin
+         ST_SNES_RD_END, ST_SNES_WR_END: begin
-	   ROM_DOUT_ENr <= 1'b0;		
+//         ROM_DOUT_ENr <= 1'b0;
-      if(MCU_RD_PENDr) begin
+           if(MCU_RD_PENDr) begin
-        STATE <= ST_MCU_RD_ADDR;
+             STATE <= ST_MCU_RD_ADDR;
-      end else if(MCU_WR_PENDr) begin
+           end else if(MCU_WR_PENDr) begin
-        STATE <= ST_MCU_WR_ADDR;
+             STATE <= ST_MCU_WR_ADDR;
-      end else STATE <= ST_IDLE;
+           end else STATE <= ST_IDLE;
-    end
+         end
     ST_MCU_RD_ADDR: begin
       ROM_SAr <= 1'b0;
 		ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
@@ -581,12 +583,12 @@ always @(posedge CLK2) begin
       ROM_SAr <= 1'b0;
 	   ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
 		STATE <= ST_MCU_WR_WAIT;
-		ROM_DOUT_ENr <= 1'b1;
 		ROM_WEr <= 1'b0;
 	 end
 	 ST_MCU_WR_WAIT: begin
-	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+           ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
-		if(ST_MEM_DELAYr == 0) begin
+           ROM_DOUT_ENr <= 1'b1;
+           if(ST_MEM_DELAYr == 0) begin
 		  ROM_WEr <= 1'b1;
 		  STATE <= ST_MCU_WR_END;
 		end
@@ -604,13 +606,13 @@ always @(posedge CLK2) begin
 	 ST_CX4_RD_WAIT: begin
 	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
 		if(ST_MEM_DELAYr == 0) begin
+                  CX4_DINr <= CX4_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
 		  STATE <= ST_CX4_RD_END;
 		end
 		else STATE <= ST_CX4_RD_WAIT;
 	 end
 	 ST_CX4_RD_END: begin
 	   ROM_CAr <= 1'b0;
-	   CX4_DINr <= CX4_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
 	   STATE <= ST_IDLE;
 	 end
 	 

verilog/sd2snes_test/ipcore_dir/PA.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.2
+# Xilinx Core Generator version 13.4
-# Date: Fri Dec  9 20:36:25 2011
+# Date: Fri Aug 17 17:03:15 2012
 #
 ##############################################################
 #
@@ -99,7 +99,7 @@ CSET write_width_a=8
 CSET write_width_b=8
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-03-11T08:24:14.000Z
+MISC pkg_timestamp=2011-03-11T08:24:14Z
 # END Extra information
 GENERATE
-# CRC: 213d12c4
+# CRC: 370f2518

verilog/sd2snes_test/ipcore_dir/PA.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="PA.ngc" xil_pn:type="FILE_NGC">

verilog/sd2snes_test/ipcore_dir/bram.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.2
+# Xilinx Core Generator version 13.4
-# Date: Fri Dec  9 20:35:22 2011
+# Date: Fri Aug 17 17:07:29 2012
 #
 ##############################################################
 #
@@ -99,7 +99,7 @@ CSET write_width_a=8
 CSET write_width_b=8
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-03-11T08:24:14.000Z
+MISC pkg_timestamp=2011-03-11T08:24:14Z
 # END Extra information
 GENERATE
-# CRC: cb4729a5
+# CRC:  1d2c05e

verilog/sd2snes_test/ipcore_dir/bram.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="bram.ngc" xil_pn:type="FILE_NGC">

verilog/sd2snes_test/ipcore_dir/dac_buf.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.2
+# Xilinx Core Generator version 13.4
-# Date: Fri Dec  9 20:37:13 2011
+# Date: Fri Aug 17 17:13:12 2012
 #
 ##############################################################
 #
@@ -99,7 +99,7 @@ CSET write_width_a=8
 CSET write_width_b=32
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-06-21T06:43:52.000Z
+MISC pkg_timestamp=2012-01-07T13:55:09Z
 # END Extra information
 GENERATE
-# CRC: 360f80d1
+# CRC: 786d7d96

verilog/sd2snes_test/ipcore_dir/dac_buf.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="dac_buf.ngc" xil_pn:type="FILE_NGC">

verilog/sd2snes_test/main.v

@@ -29,12 +29,12 @@ module main(
   input SNES_CS,
   inout [7:0] SNES_DATA,
   input SNES_CPU_CLK,
-  input SNES_REFRESH,
   output SNES_IRQ,
   output SNES_DATABUS_OE,
   output SNES_DATABUS_DIR,
-  input SNES_SYSCLK,
 
+  input SNES_SYSCLK,  
+  input SNES_REFRESH,
   input [7:0] SNES_PA,
   input SNES_PARD,
   input SNES_PAWR,
@@ -386,8 +386,8 @@ end
 
 wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
 
-assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? ram0_addr[23:1] : ROM_ADDRr[23:1];
+assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[22:0] : (ASSERT_SNES_ADDR) ? ram0_addr[22:0] : ROM_ADDRr[22:0];
-assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? ram0_addr[0] : ROM_ADDRr[0];
+assign ROM_ADDR0 = 1'b0; //(SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? ram0_addr[0] : ROM_ADDRr[0];
 
 assign RAM_ADDR = ASSERT_SNES_ADDR ? ram1_addr : RAM_ADDRr;
 
@@ -441,8 +441,8 @@ always @(posedge CLK2) begin
         if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
         else STATE <= ST_SNES_RD_WAIT;
         if(ram0_enable) begin
-          if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
+          if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
-          else SNES_DINr <= ROM_DATA[15:8];
+          else SNES_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
         end else if(ram1_enable) begin
           SNES_DINr <= RAM_DATA[7:0];
         end
@@ -450,8 +450,8 @@ always @(posedge CLK2) begin
       ST_SNES_RD_END: begin
         STATE <= ST_IDLE;
         if(ram0_enable) begin
-          if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
+          if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
-          else SNES_DINr <= ROM_DATA[15:8];
+          else SNES_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
         end else if(ram1_enable) begin
           SNES_DINr <= RAM_DATA[7:0];
         end
@@ -498,8 +498,8 @@ always @(posedge CLK2) begin
         end
         else STATE <= ST_MCU_RD_WAIT;
         if(MCU_RAMSEL == 1'b0) begin
-          if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
+          if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
-          else MCU_DINr <= ROM_DATA[15:8];
+          else MCU_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
         end else MCU_DINr <= RAM_DATA;
       end
       ST_MCU_RD_WAIT2: begin
@@ -548,14 +548,11 @@ always @(posedge CLK2) begin
   end
 end
 
-assign ROM_DATA[7:0] = ROM_ADDR0
+assign ROM_DATA[7:0] = (SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
                                         : (!ROM_WE ? ROM_DOUTr : 8'bZ)
-                        )
+                        );
-                       :8'bZ;
 
-assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
+assign ROM_DATA[15:8] = (SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                        :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
                                          : (!ROM_WE ? ROM_DOUTr : 8'bZ)
                          );
 
@@ -575,7 +572,7 @@ assign ROM_OE = 1'b0;
 assign ROM_CE = 1'b0;
 
 assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
-assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
+assign ROM_BLE = !ROM_WE ? ROM_ADDR0 : 1'b0;
 
 assign SNES_DATABUS_OE = PA_enable ? 1'b0
                          : bram_enable ? 1'b0

verilog/sd2snes_test/sd2snes_test.xise

@@ -9,72 +9,63 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
-    <file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../sd2snes/srtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="ipcore_dir/bram.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="ipcore_dir/PA.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="ipcore_dir/bram.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/PA.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
   </files>
 
   <properties>
@@ -126,8 +117,8 @@
     <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
     <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xa3s400" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan3" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
@@ -242,7 +233,7 @@
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="pqg208" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
@@ -316,7 +307,7 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="11" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="11" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -364,7 +355,7 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes_test" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan3" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>

verilog/sd2sneslite/address.v

@@ -47,10 +47,10 @@ assign IS_SAVERAM = (!SNES_ADDR[22]
                         );
 
 assign SRAM_SNES_ADDR = (IS_SAVERAM
-                             ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
+                             ? 24'h7F0000 + ((SNES_ADDR[14:0] - 15'h6000)
                                              & SAVERAM_MASK)
                              : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
-                                + 24'hC00000)
+                                + 24'h500000)
                          );
 								 
 assign ROM_ADDR = SRAM_SNES_ADDR;

verilog/sd2sneslite/main.v

@@ -101,7 +101,6 @@ wire [23:0] SAVERAM_MASK;
 wire [23:0] ROM_MASK;
 
 wire [23:0] MAPPED_SNES_ADDR;
-wire ROM_ADDR0;
 
 spi snes_spi(
   .clk(CLK2),
@@ -253,8 +252,7 @@ initial ROM_SAr = 1'b1;
 //wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
 wire ROM_SA = ROM_SAr;
 
-assign ROM_ADDR  = (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
+assign ROM_ADDR  = (ROM_SA) ? MAPPED_SNES_ADDR[22:0] : ROM_ADDRr[22:0];
-assign ROM_ADDR0 = (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
 
 reg ROM_WEr;
 initial ROM_WEr = 1'b1;
@@ -308,7 +306,8 @@ always @(posedge CLK2) begin
 		end else if(SNES_cycle_start) begin
 //		  STATE <= ST_SNES_RD_ADDR;		  
         STATE <= ST_SNES_RD_END;
-        SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
+        SNES_DOUTr <= ROM_DATA[7:0] | ROM_DATA[15:8];
+		  //(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
 		end else if(SNES_DEADr & MCU_RD_PENDr) begin
 		  STATE <= ST_MCU_RD_ADDR;
 		end else if(SNES_DEADr & MCU_WR_PENDr) begin
@@ -368,7 +367,8 @@ always @(posedge CLK2) begin
 		else STATE <= ST_MCU_RD_WAIT;
 	 end
 	 ST_MCU_RD_END: begin
-      MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
+      MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
+		//ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
 	   STATE <= ST_IDLE;
 	 end
 	 
@@ -401,12 +401,8 @@ always @(posedge CLK2) begin
   ROM_WE_1 <= ROM_WE;
 end
 
-assign ROM_DATA[7:0] = ROM_ADDR0
+assign ROM_DATA[7:0] = (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
-                       ?(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ)
+assign ROM_DATA[15:8] = (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
-                       :8'bZ;
-
-assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
-                        :(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
 								
 assign ROM_WE = ROM_WEr;
 
@@ -415,8 +411,8 @@ assign ROM_OE = 1'b0;
 
 assign ROM_CE = 1'b0;
 
-assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BHE = 1'b0;// /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
-assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BLE = 1'b0;// /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
 
 assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
                           |(!IS_ROM & !IS_SAVERAM)

verilog/sd2sneslite/sd2sneslite.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
@@ -312,6 +312,7 @@
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>