Maximilian Rehkopf
3f2e4e37db
menu: rename menu.a65 to filesel.a65; add required library to README
2013-10-18 14:20:19 +02:00
Maximilian Rehkopf
39b07df47e
Correct LoROM SRAM mapping for smaller ROMs
...
SRAM is sometimes mapped not just to 70:0000-7fff but also to
70:8000-ffff if ROM size permits it (i.e. the ROM is small enough
to avoid overlap).
Map SRAM to 8000-ffff if the ROM mask denotes a ROM <= 16 MBits.
2013-06-30 23:42:28 +02:00
Maximilian Rehkopf
78beed80d7
FPGA: fix BSX PSRAM mapping
2013-06-26 10:44:57 +02:00
Maximilian Rehkopf
f7aa9832c6
update changelog
2012-11-18 21:01:39 +01:00
Maximilian Rehkopf
7233278db2
Firmware: fix FPGA DMA call
2012-11-18 20:12:19 +01:00
Maximilian Rehkopf
443f7b138c
Firmware: update version number to 0.1.5
2012-11-18 20:11:46 +01:00
Maximilian Rehkopf
e92ad06f38
FPGA/Cx4: slow down bus timing
2012-11-18 20:10:29 +01:00
Maximilian Rehkopf
fa1e09d867
FPGA: fix large SRAM mapping
2012-11-18 17:18:26 +01:00
Maximilian Rehkopf
e504079e5d
FPGA: slow down bus timing
2012-11-07 22:32:33 +01:00
Maximilian Rehkopf
1f5af01bc0
FPGA: add BS-X "hole" (regs 09-0b)
2012-11-07 22:31:28 +01:00
Maximilian Rehkopf
648569d900
Firmware: fix big SRAM handling
2012-11-07 22:29:38 +01:00
Maximilian Rehkopf
b91b598758
Firmware: fix MSU1 main loop behaviour
2012-11-07 11:06:56 +01:00
Maximilian Rehkopf
04c3cbc7a2
Firmware: [debug] log file size after loading
2012-11-07 11:06:29 +01:00
Maximilian Rehkopf
c204aa9a0b
Firmware/FPGA: replace magic numbers with constants
2012-11-07 11:03:58 +01:00
Maximilian Rehkopf
605fc2dfb1
Firmware: remove unused file sdcard.h
2012-11-07 09:54:30 +01:00
Maximilian Rehkopf
b67e2a5c77
Firmware: clean up clock/timer init
2012-11-07 09:44:50 +01:00
Maximilian Rehkopf
fee97e5016
Firmware/CLI: list short file name and file size in ls command; print file name when saving SRAM
2012-11-07 09:31:33 +01:00
Maximilian Rehkopf
ce23ff6954
Firmware/CLI: add memset command, rename 'resume' to 'exit'
2012-11-07 09:27:00 +01:00
Maximilian Rehkopf
83b18cc447
Firmware: fix compile errors with newer gccs
2012-11-07 09:23:50 +01:00
Maximilian Rehkopf
e33fbdf77f
menu: Ignore input from non-standard controllers ( resolve #29 )
2012-09-30 00:24:48 +02:00
Maximilian Rehkopf
9287d637d1
FPGA: properly map large SRAM (LoROM > 32kB, HiROM > 8kB)
2012-09-24 22:52:05 +02:00
Maximilian Rehkopf
13c24bea9d
FPGA: more accurate BS-X memory map
2012-09-24 22:49:54 +02:00
Maximilian Rehkopf
791b688f40
menu: fix #26 : first note cut off on S-APU SNESes
2012-09-24 22:37:39 +02:00
Maximilian Rehkopf
5939b6e581
Firmware: sort by entire filename, not just first 20 characters
2012-08-25 19:36:24 +02:00
Maximilian Rehkopf
82998d7a48
PCB/Rev.E2: Add BOM
2012-08-06 23:33:01 +02:00
Maximilian Rehkopf
32a0a50c54
update changelog for 0.1.4a
2012-07-15 20:21:14 +02:00
Maximilian Rehkopf
b8d3b952ad
firmware: bump version no. to 0.1.4a
2012-07-14 21:27:07 +02:00
Maximilian Rehkopf
e97396adc9
menu: fix DMA initialization (sprite glitches in some games)
2012-07-14 21:25:51 +02:00
mrehkopf
a72476ea6c
Merge pull request #24 from Godzil/develop
...
Develop
2012-07-10 03:53:32 -07:00
Maximilian Rehkopf
d47858083a
FPGA/Cx4: update user constraints for changed system clock
2012-07-09 18:52:51 +02:00
Maximilian Rehkopf
a7ac2f8900
update changelog
2012-07-09 18:52:03 +02:00
Maximilian Rehkopf
c80bdfbf59
Firmware: do not turn off write LED in case of periodic SRAM saving
2012-07-09 02:28:26 +02:00
Maximilian Rehkopf
a9ea821c0d
Firmware: implement MSU1 interface changes
2012-07-09 02:27:53 +02:00
Maximilian Rehkopf
9baa4b7f9f
Firmware: move SaveRAM to $E00000
2012-07-09 02:26:50 +02:00
Maximilian Rehkopf
2ef480f751
FPGA/DSPx: buffer register input
2012-07-09 02:23:57 +02:00
Maximilian Rehkopf
6b3a7eb4ae
FPGA/SRTC: buffer register/address input
2012-07-09 02:22:57 +02:00
Maximilian Rehkopf
effa2a6972
FPGA/SDDMA: fix clock glitch, adjust RAM write timings
2012-07-09 02:22:07 +02:00
Maximilian Rehkopf
9253cc45b0
FPGA: implement MSU1 "audio error" status bit
2012-07-09 02:20:13 +02:00
Maximilian Rehkopf
9fbe61bad1
FPGA: Use internal clock instead of SNES master clock for $213F RMW timing
2012-07-09 02:18:28 +02:00
Maximilian Rehkopf
968c347986
FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input
2012-07-09 02:17:01 +02:00
Maximilian Rehkopf
c231c8b821
FPGA: misc cleanup
2012-07-09 02:15:21 +02:00
Maximilian Rehkopf
60d7a08117
FPGA: Adjust Cx4 timing to new master clock rate
2012-07-09 02:13:44 +02:00
Maximilian Rehkopf
7df6909266
FPGA: rework shared memory access FSM
2012-07-09 02:12:59 +02:00
Maximilian Rehkopf
006ea8c44a
FPGA: debug wires
2012-07-09 02:03:59 +02:00
Maximilian Rehkopf
684e2c3b81
FPGA/BSX: fix checksum registers
2012-07-09 02:00:29 +02:00
Maximilian Rehkopf
3af05cef91
FPGA/sd2sneslite: add missing file mcu_cmd.v; remove avr_cmd.v
2012-07-09 01:55:02 +02:00
Maximilian Rehkopf
a083d80ff9
FPGA: update clock speed to 88MHz
2012-07-09 01:54:05 +02:00
Maximilian Rehkopf
8148f5567c
FPGA: properly synchronize external signals
2012-07-09 01:48:43 +02:00
Maximilian Rehkopf
1a52da6272
FPGA: Adjust DAC I²S signal timing
2012-07-09 01:41:47 +02:00
Maximilian Rehkopf
e33b2b2bc7
FPGA: simple SNES address input filtering
2012-07-09 01:37:57 +02:00
