Maximilian Rehkopf
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e504079e5d
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FPGA: slow down bus timing
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2012-11-07 22:32:33 +01:00 |
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Maximilian Rehkopf
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1f5af01bc0
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FPGA: add BS-X "hole" (regs 09-0b)
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2012-11-07 22:31:28 +01:00 |
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Maximilian Rehkopf
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648569d900
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Firmware: fix big SRAM handling
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2012-11-07 22:29:38 +01:00 |
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Maximilian Rehkopf
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b91b598758
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Firmware: fix MSU1 main loop behaviour
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2012-11-07 11:06:56 +01:00 |
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Maximilian Rehkopf
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04c3cbc7a2
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Firmware: [debug] log file size after loading
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2012-11-07 11:06:29 +01:00 |
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Maximilian Rehkopf
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c204aa9a0b
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Firmware/FPGA: replace magic numbers with constants
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2012-11-07 11:03:58 +01:00 |
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Maximilian Rehkopf
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605fc2dfb1
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Firmware: remove unused file sdcard.h
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2012-11-07 09:54:30 +01:00 |
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Maximilian Rehkopf
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b67e2a5c77
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Firmware: clean up clock/timer init
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2012-11-07 09:44:50 +01:00 |
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Maximilian Rehkopf
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fee97e5016
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Firmware/CLI: list short file name and file size in ls command; print file name when saving SRAM
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2012-11-07 09:31:33 +01:00 |
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Maximilian Rehkopf
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ce23ff6954
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Firmware/CLI: add memset command, rename 'resume' to 'exit'
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2012-11-07 09:27:00 +01:00 |
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Maximilian Rehkopf
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83b18cc447
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Firmware: fix compile errors with newer gccs
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2012-11-07 09:23:50 +01:00 |
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Maximilian Rehkopf
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e33fbdf77f
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menu: Ignore input from non-standard controllers (resolve #29)
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2012-09-30 00:24:48 +02:00 |
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Maximilian Rehkopf
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9287d637d1
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FPGA: properly map large SRAM (LoROM > 32kB, HiROM > 8kB)
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2012-09-24 22:52:05 +02:00 |
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Maximilian Rehkopf
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13c24bea9d
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FPGA: more accurate BS-X memory map
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2012-09-24 22:49:54 +02:00 |
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Maximilian Rehkopf
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791b688f40
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menu: fix #26: first note cut off on S-APU SNESes
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2012-09-24 22:37:39 +02:00 |
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Maximilian Rehkopf
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5939b6e581
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Firmware: sort by entire filename, not just first 20 characters
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2012-08-25 19:36:24 +02:00 |
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Maximilian Rehkopf
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82998d7a48
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PCB/Rev.E2: Add BOM
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2012-08-06 23:33:01 +02:00 |
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Maximilian Rehkopf
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32a0a50c54
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update changelog for 0.1.4a
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2012-07-15 20:21:14 +02:00 |
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Maximilian Rehkopf
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b8d3b952ad
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firmware: bump version no. to 0.1.4a
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2012-07-14 21:27:07 +02:00 |
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Maximilian Rehkopf
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e97396adc9
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menu: fix DMA initialization (sprite glitches in some games)
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2012-07-14 21:25:51 +02:00 |
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mrehkopf
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a72476ea6c
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Merge pull request #24 from Godzil/develop
Develop
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2012-07-10 03:53:32 -07:00 |
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Maximilian Rehkopf
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d47858083a
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FPGA/Cx4: update user constraints for changed system clock
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2012-07-09 18:52:51 +02:00 |
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Maximilian Rehkopf
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a7ac2f8900
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update changelog
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2012-07-09 18:52:03 +02:00 |
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Maximilian Rehkopf
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c80bdfbf59
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Firmware: do not turn off write LED in case of periodic SRAM saving
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2012-07-09 02:28:26 +02:00 |
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Maximilian Rehkopf
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a9ea821c0d
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Firmware: implement MSU1 interface changes
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2012-07-09 02:27:53 +02:00 |
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Maximilian Rehkopf
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9baa4b7f9f
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Firmware: move SaveRAM to $E00000
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2012-07-09 02:26:50 +02:00 |
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Maximilian Rehkopf
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2ef480f751
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FPGA/DSPx: buffer register input
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2012-07-09 02:23:57 +02:00 |
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Maximilian Rehkopf
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6b3a7eb4ae
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FPGA/SRTC: buffer register/address input
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2012-07-09 02:22:57 +02:00 |
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Maximilian Rehkopf
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effa2a6972
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FPGA/SDDMA: fix clock glitch, adjust RAM write timings
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2012-07-09 02:22:07 +02:00 |
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Maximilian Rehkopf
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9253cc45b0
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FPGA: implement MSU1 "audio error" status bit
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2012-07-09 02:20:13 +02:00 |
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Maximilian Rehkopf
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9fbe61bad1
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FPGA: Use internal clock instead of SNES master clock for $213F RMW timing
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2012-07-09 02:18:28 +02:00 |
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Maximilian Rehkopf
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968c347986
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FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input
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2012-07-09 02:17:01 +02:00 |
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Maximilian Rehkopf
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c231c8b821
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FPGA: misc cleanup
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2012-07-09 02:15:21 +02:00 |
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Maximilian Rehkopf
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60d7a08117
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FPGA: Adjust Cx4 timing to new master clock rate
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2012-07-09 02:13:44 +02:00 |
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Maximilian Rehkopf
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7df6909266
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FPGA: rework shared memory access FSM
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2012-07-09 02:12:59 +02:00 |
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Maximilian Rehkopf
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006ea8c44a
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FPGA: debug wires
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2012-07-09 02:03:59 +02:00 |
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Maximilian Rehkopf
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684e2c3b81
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FPGA/BSX: fix checksum registers
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2012-07-09 02:00:29 +02:00 |
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Maximilian Rehkopf
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3af05cef91
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FPGA/sd2sneslite: add missing file mcu_cmd.v; remove avr_cmd.v
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2012-07-09 01:55:02 +02:00 |
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Maximilian Rehkopf
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a083d80ff9
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FPGA: update clock speed to 88MHz
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2012-07-09 01:54:05 +02:00 |
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Maximilian Rehkopf
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8148f5567c
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FPGA: properly synchronize external signals
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2012-07-09 01:48:43 +02:00 |
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Maximilian Rehkopf
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1a52da6272
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FPGA: Adjust DAC I²S signal timing
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2012-07-09 01:41:47 +02:00 |
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Maximilian Rehkopf
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e33b2b2bc7
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FPGA: simple SNES address input filtering
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2012-07-09 01:37:57 +02:00 |
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Maximilian Rehkopf
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3530613349
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FPGA: prepare new SNES command interface for future use (SNES side)
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2012-07-09 01:29:47 +02:00 |
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Maximilian Rehkopf
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0d02bfded7
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Firmware: adjust to SPI changes
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2012-07-09 01:19:44 +02:00 |
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Maximilian Rehkopf
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576cedd285
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Update embedded FPGA config
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2012-07-09 01:17:32 +02:00 |
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Maximilian Rehkopf
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e6f77c242b
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Update changelog for version 0.1.4
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2012-07-09 01:16:39 +02:00 |
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Godzil
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86d6f04870
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Add gitignore file.
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2012-07-05 14:42:02 +02:00 |
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Godzil
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e2af175f05
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Correct baudrate on normal application.
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2012-07-05 14:41:29 +02:00 |
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Godzil
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583309491c
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Change baudrate to more standard 115200
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2012-07-05 14:41:06 +02:00 |
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Maximilian Rehkopf
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40099772f7
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menu: comments
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2012-07-03 20:44:17 +02:00 |
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