Maximilian Rehkopf
39b07df47e
Correct LoROM SRAM mapping for smaller ROMs
...
SRAM is sometimes mapped not just to 70:0000-7fff but also to
70:8000-ffff if ROM size permits it (i.e. the ROM is small enough
to avoid overlap).
Map SRAM to 8000-ffff if the ROM mask denotes a ROM <= 16 MBits.
2013-06-30 23:42:28 +02:00
Maximilian Rehkopf
78beed80d7
FPGA: fix BSX PSRAM mapping
2013-06-26 10:44:57 +02:00
Maximilian Rehkopf
e92ad06f38
FPGA/Cx4: slow down bus timing
2012-11-18 20:10:29 +01:00
Maximilian Rehkopf
fa1e09d867
FPGA: fix large SRAM mapping
2012-11-18 17:18:26 +01:00
Maximilian Rehkopf
e504079e5d
FPGA: slow down bus timing
2012-11-07 22:32:33 +01:00
Maximilian Rehkopf
1f5af01bc0
FPGA: add BS-X "hole" (regs 09-0b)
2012-11-07 22:31:28 +01:00
Maximilian Rehkopf
9287d637d1
FPGA: properly map large SRAM (LoROM > 32kB, HiROM > 8kB)
2012-09-24 22:52:05 +02:00
Maximilian Rehkopf
13c24bea9d
FPGA: more accurate BS-X memory map
2012-09-24 22:49:54 +02:00
Maximilian Rehkopf
d47858083a
FPGA/Cx4: update user constraints for changed system clock
2012-07-09 18:52:51 +02:00
Maximilian Rehkopf
2ef480f751
FPGA/DSPx: buffer register input
2012-07-09 02:23:57 +02:00
Maximilian Rehkopf
6b3a7eb4ae
FPGA/SRTC: buffer register/address input
2012-07-09 02:22:57 +02:00
Maximilian Rehkopf
effa2a6972
FPGA/SDDMA: fix clock glitch, adjust RAM write timings
2012-07-09 02:22:07 +02:00
Maximilian Rehkopf
9253cc45b0
FPGA: implement MSU1 "audio error" status bit
2012-07-09 02:20:13 +02:00
Maximilian Rehkopf
9fbe61bad1
FPGA: Use internal clock instead of SNES master clock for $213F RMW timing
2012-07-09 02:18:28 +02:00
Maximilian Rehkopf
968c347986
FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input
2012-07-09 02:17:01 +02:00
Maximilian Rehkopf
c231c8b821
FPGA: misc cleanup
2012-07-09 02:15:21 +02:00
Maximilian Rehkopf
60d7a08117
FPGA: Adjust Cx4 timing to new master clock rate
2012-07-09 02:13:44 +02:00
Maximilian Rehkopf
7df6909266
FPGA: rework shared memory access FSM
2012-07-09 02:12:59 +02:00
Maximilian Rehkopf
006ea8c44a
FPGA: debug wires
2012-07-09 02:03:59 +02:00
Maximilian Rehkopf
684e2c3b81
FPGA/BSX: fix checksum registers
2012-07-09 02:00:29 +02:00
Maximilian Rehkopf
3af05cef91
FPGA/sd2sneslite: add missing file mcu_cmd.v; remove avr_cmd.v
2012-07-09 01:55:02 +02:00
Maximilian Rehkopf
a083d80ff9
FPGA: update clock speed to 88MHz
2012-07-09 01:54:05 +02:00
Maximilian Rehkopf
8148f5567c
FPGA: properly synchronize external signals
2012-07-09 01:48:43 +02:00
Maximilian Rehkopf
1a52da6272
FPGA: Adjust DAC I²S signal timing
2012-07-09 01:41:47 +02:00
Maximilian Rehkopf
e33b2b2bc7
FPGA: simple SNES address input filtering
2012-07-09 01:37:57 +02:00
Maximilian Rehkopf
3530613349
FPGA: prepare new SNES command interface for future use (SNES side)
2012-07-09 01:29:47 +02:00
Maximilian Rehkopf
a5a02992e5
FPGA/embedded config: slightly tighten timing constraints
2012-06-11 01:52:45 +02:00
Maximilian Rehkopf
034b39588c
FPGA: adjust menu memory mapping to make more room for file database
2012-06-10 20:07:45 +02:00
Maximilian Rehkopf
2a1ef40796
FPGA/cx4: adjust Cx4 CPU timing
2012-05-19 18:07:13 +02:00
Maximilian Rehkopf
7109f9e030
FPGA: add SD clock pullup to test configuration
2012-05-02 10:46:27 +02:00
Maximilian Rehkopf
e63658e2ad
FPGA: Map mode 21 SRAM to 20:xxxx as well
2012-05-02 10:46:01 +02:00
Maximilian Rehkopf
37a309fd0e
FPGA: improve BS support (more date fields, initial download data support)
2012-05-02 10:42:46 +02:00
Maximilian Rehkopf
f5caf21fac
FPGA: slightly tighten timing constraints
2012-05-02 10:41:07 +02:00
Maximilian Rehkopf
1b272a7a7d
FPGA/Cx4: introduce wait states (fix MMX2 attract mode)
2012-05-02 10:30:22 +02:00
ikari
8e7f77e49b
FPGA/cx4: map ROM above bank 3F/BF
2012-02-27 22:14:19 +01:00
ikari
e2f33c28c9
FPGA: pull-up SD clock
2012-02-27 22:12:35 +01:00
ikari
f0a2e85c65
FPGA: updated project files
2012-01-14 23:16:57 +01:00
ikari
d7ad740843
FPGA/Cx4: add missing file main.ucf
2012-01-14 02:25:34 +01:00
ikari
059966f06a
FPGA/Cx4: optimize non-sector-aligned SD DMA reads
2012-01-14 02:21:01 +01:00
ikari
3243143c39
FPGA/Cx4: region override (patch register $213f)
2012-01-14 02:19:39 +01:00
ikari
a50522b4e9
FPGA: optimize non-sector-aligned SD DMA reads
2012-01-14 01:22:38 +01:00
ikari
eefcc712ca
FPGA: add RAM1 pinout to user constraints
2012-01-14 01:21:40 +01:00
ikari
5a3e935a3e
FPGA: region override (patch register $213f)
2012-01-14 01:21:21 +01:00
ikari
dc01edfe9a
FPGA: add test suite
2011-12-19 22:26:09 +01:00
ikari
93a12f3ca1
FPGA: fix occasional erroneous write inhibit
2011-11-10 23:41:33 +01:00
ikari
68f255d75b
firmware, FPGA: fix for some SD cards
2011-11-10 17:54:52 +01:00
ikari
1987968db2
FPGA/cx4: clean up tab/whitespace mix
2011-11-01 21:09:31 +01:00
ikari
3dd64cb98f
FPGA/cx4: timing closure
2011-11-01 20:56:30 +01:00
ikari
ecd75210a9
FPGA/cx4: fix memory sharing
2011-11-01 20:55:59 +01:00
ikari
314da586a4
FPGA/cx4: implement reset vector access
2011-11-01 20:54:07 +01:00
