PCB/Rev.E2: Add BOM

Develop

CHANGELOG

@@ -38,3 +38,44 @@ v0.1.3
  * Some FPGA configuration error detection (mainly useful for hardware diag)
  * Fixes:
    - FPGA-side SD clock pullup (increases reliability with some cards)
+
+
+v0.1.4
+======
+
+ * SPC Player (contributed by necronomfive/blargg)
+ * System Information screen now shows CPU/PPU revision (contributed by necronomfive)
+ * Satellaview: basic data transmission packet support (makes some more games boot, thanks to LuigiBlood for assistance and sample data packets)
+ * Number of supported files increased to 50000 per card / 16380 per directory
+ * Slight speedup of menu text rendering
+ * Reduce load time of menu
+ * Adjust Cx4 timing to be more faithful
+   (Mega Man now defeats the boss in attract mode in Mega Man X2)
+ * adapt ROM mirroring size to file size if header information is invalid
+   (fixes Super Noah's Ark 3D, possibly others)
+ * MSU1 interface changes suggested by byuu:
+   - Data offset 0 and audio track 0 are automatically requested on reset.
+     This causes the busy flags to become 0 shortly after reset/startup.
+   - $2000 bit 3 is now "audio error", becomes valid after "audio busy" -> 0
+     set when an error occurred while preparing playback of the requested audio track
+ * write LED stays on when SRAM content changes constantly
+ * Fixes:
+   - fix empty save files on FAT16 / incorrect free cluster count on FAT32
+   - correct directory sorting (force parent directory at top of list)
+   - fix text corruption when entering a directory with a scrollable name
+   - fix files/dirs count in system information
+   - make 'sd2snes' directory hiding case-insensitive
+   - improve DAC I²S timing
+   - fix occasional palette corruption in menu
+   - fix SD clock glitch on ROM loading (occasional glitches/crashes)
+   - fix memory write timing on ROM loading (occasional glitches/crashes)
+   - fix SPI timing (ROMs not loading; System Information not working)
+   - properly synchronize SNES control signals (occasional glitches/crashes)
+   - fix floating IRQ output (occasional glitches/slowdowns)
+
+
+v0.1.4a (bugfix release)
+========================
+
+ * Fix DMA initialization in the menu (could cause sprite corruption in some games)
+

cic/supercic/supercic-key.asm

@@ -744,4 +744,4 @@ supercic_pairmode_loop
 ; eeprom memory
 DEEPROM	CODE
 	de      0x09	; D411 (NTSC)
-	end
+end

cic/supercic/supercic-lock.asm

@@ -192,11 +192,11 @@ rst_loop
 	clrf	0x59		; clear D4
 	clrf	0x5e		;
 	clrf	0x5f		;
-	banksel EEADR		; fetch current mode from EEPROM
-	clrf    EEADR		; address 0
-	bsf     EECON1, RD	; 
-	movf    EEDAT, w        ; 
-	banksel PORTA
+        banksel EEADR		; fetch current mode from EEPROM
+        clrf    EEADR		; address 0
+        bsf     EECON1, RD	; 
+        movf    EEDAT, w        ; 
+        banksel PORTA
 	movwf	0x55		; store saved mode in mode var
 	movwf	0x56		; and temp LED
 	movwf	0x58		; and forced region

pcb/kicad/RevE2/sd2snes.pro

@@ -1,4 +1,4 @@
-update=ven. 20 avril 2012 18:26:30 CEST
+update=Sat 25 Feb 2012 11:51:50 PM CET
 version=1
 last_client=pcbnew
 [general]
@@ -87,7 +87,6 @@ PadDrlX=0
 PadDimH=197
 PadDimV=276
 BoardThickness=630
-SgPcb45=1
 TxtPcbV=800
 TxtPcbH=600
 TxtModV=600

snes/Makefile

@@ -1,4 +1,4 @@
-OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 # gfx.o65 # vars.o65
+OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 spc700.o65 spcplay.o65 # gfx.o65 # vars.o65
 
 all: clean menu.bin map
 

snes/const.a65

@@ -168,4 +168,24 @@ text_mm_vmode_game	.byt "Game video mode", 0
 text_mm_sysinfo		.byt "System Information", 0
 text_statusbar_keys	.byt "A:Select B:Back X:Menu", 0
 text_last		.byt "Run previous ROM: Press Start again to confirm", 0
+text_system		.byt "CPU Rev.: x  PPU1 Rev.: y  PPU2 Rev.: z",0
 
+
+text_spcplay		.byt "SPC Music Player", 0
+spcplay_win_x		.byt 15
+spcplay_win_y		.byt 15
+spcplay_win_w		.byt 33
+spcplay_win_h		.byt 5
+
+text_spcload		.byt "Loading SPC data to SPC700...", 0
+text_spcstarta		.byt "**** Now playing SPC tune ****", 0
+text_spcstartb		.byt "Name:  ",0
+text_spcstartc		.byt "Song:  ",0
+text_spcstartd		.byt "Artist:",0
+
+spcstart_win_x		.byt 10
+spcstart_win_y		.byt 13
+spcstart_win_w		.byt 44
+spcstart_win_h		.byt 9
+
+text_spcid		.byt "SNES-SPC700"

snes/data.a65

@@ -16,7 +16,7 @@ dirend_onscreen	.byt 0
 dirlog_idx	.byt 0,0,0 ; long ptr
 direntry_fits_idx
 		.byt 0,0
-
+longptr		.byt 0,0,0 ; general purpose long ptr
 ;----------parameters for text output----------
 print_x	.byt 0		;x coordinate
 	.byt 0
@@ -26,8 +26,8 @@ print_src	.word 0	;source data address
 print_bank	.byt 0	;source data bank
 print_pal	.word 0	;palette number for text output
 print_temp	.word 0 ;work variable
-print_count	.byt 0	;how many characters may be printed?
-print_count_tmp .byt 0	;work variable
+print_ptr	.byt 0,0,0 ;read pointer
+print_count	.word 0	;how many characters may be printed?
 print_done	.word 0 ;how many characters were printed?
 print_over	.byt 0  ;was the string printed incompletely?
 ;----------parameters for dma----------
@@ -183,5 +183,18 @@ direntry_xscroll
 	.word	0
 direntry_xscroll_wait
 	.word	0
-infloop		.byt 0,0  ; to be filled w/ 80 FE
+infloop	.byt 0,0  ; to be filled w/ 80 FE
+tgt_bright
+	.byt 0
+cur_bright
+	.byt 0
+
+;------------------------
+saved_sp
+	.word 0
+warm_signature
+	.word 0
+snes_system_config
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+
 wram_fadeloop	.byt 0

snes/dma.a65

@@ -1,21 +1,4 @@
 
-dma0:
-	rep #$10 : .xl
-	sep #$20 : .as
-	lda dma_mode
-	sta $4300
-	lda dma_b_reg
-	sta $4301
-	lda dma_a_bank
-	ldx dma_a_addr
-	stx $4302
-	sta $4304
-	ldx dma_len
-	stx $4305
-	lda #$01
-	sta $420b
-	rts
-
 setup_hdma:
 	sep #$20 : .as
 	rep #$10 : .xl
@@ -67,8 +50,11 @@ setup_hdma:
 	sty $4352
 	sta $4354
 
-;	lda #$06
-;	sta $420c		;enable HDMA ch. 1+2
+	lda #$3a
+	sta $420c		;enable HDMA ch. 1+3+4+5
+	jsr waitblank
+	lda #$3e
+	sta $420c		;enable HDMA ch. 2 too
 	lda #$81		;VBlank NMI + Auto Joypad Read
 	sta $4200		;enable V-BLANK NMI
 	rts

snes/dma.i65

@@ -1,13 +1,22 @@
+#define hash #
+#define f(x) x
+#define imm(a) f(hash)a
+
 #define DMA0(mode, len, a_bank, a_addr, b_reg)\
-	lda mode \
-: 	sta dma_mode \
+	php \
+:	sep imm($20) : .as \
+:	rep imm($10) : .xl \
+:	lda mode \
+: 	sta $4300 \
 :	ldx a_addr \
 :	lda a_bank \
-:	stx dma_a_addr \
-:	sta dma_a_bank \
+:	stx $4302 \
+:	sta $4304 \
 :	ldx len \
-:	stx dma_len \
+:	stx $4305 \
 :	lda b_reg \
-:	sta dma_b_reg \
-:	jsr dma0
+:	sta $4301 \
+:	lda imm($01) \
+:	sta $420b \
+:	plp
 

snes/main.a65

@@ -4,13 +4,45 @@
 GAME_MAIN:
 	sep #$20 : .as
 	lda #$00
-	sta @AVR_CMD
+	sta @MCU_CMD		; clear MCU command register
 	rep #$20 : .al
 	lda #$0000
-	sta @AVR_PARAM
-	sta @AVR_PARAM+2
+	sta @MCU_PARAM		; clear MCU command parameters
+	sta @MCU_PARAM+2
 	sep #$20 : .as
 	stz $4200 ; inhibit VBlank NMI
+	rep #$20 : .al
+	lda @warm_signature	; Was CMD_RESET issued before reset?
+	cmp #$fa50		; If yes, then perform warm boot procedure
+	bne coldboot
+	lda #$0000
+	sta @warm_signature
+	lda @saved_sp		; Restore previous stack pointer
+	tcs
+	sep #$20 : .as
+
+	jsr killdma		; The following initialization processes must not touch memory
+	jsr waitblank		; structures used by the main menu !
+	jsr snes_init
+	cli
+	lda #$01
+	sta $420d 		; fast cpu
+	jsr setup_gfx
+	jsr colortest
+	jsr tests
+	jsr setup_hdma
+	lda #$0f
+	sta cur_bright
+	sta tgt_bright
+	sta $2100
+
+	jmp @set_bank		; Set bios bank, just to be sure
+set_bank:
+	plp			; Restore processor state
+	rts			; Jump to the routine which called the sub-routine issuing CMD_RESET
+
+coldboot:							; Regular, cold-start init
+	sep #$20 : .as
 	jsr killdma
 	jsr waitblank
 	jsr snes_init
@@ -18,9 +50,11 @@ GAME_MAIN:
 	sta $420d ; fast cpu
 	jsr setup_gfx
 	jsr colortest
-	jsr setup_hdma
 	jsr menu_init
 	jsr tests
+	jsr setup_hdma
+	jsr screen_on
+
 	sep #$20 : .as
 	lda @RTC_STATUS
 	beq +
@@ -32,50 +66,93 @@ GAME_MAIN:
 	jmp @infloop	;infinite loop in WRAM
 
 killdma:
-	stz $420b
-	stz $420c
+	stz $4300
+	stz $4301
+	stz $4302
+	stz $4303
+	stz $4304
+	stz $4305
+	stz $4306
+	stz $4307
+	stz $4308
+	stz $4309
+	stz $430a
+	stz $430b
 	stz $4310
 	stz $4311
 	stz $4312
 	stz $4313
 	stz $4314
+	stz $4315
+	stz $4316
+	stz $4317
+	stz $4318
+	stz $4319
+	stz $431a
+	stz $431b
 	stz $4320
 	stz $4321
 	stz $4322
 	stz $4323
 	stz $4324
+	stz $4325
+	stz $4326
+	stz $4327
+	stz $4328
+	stz $4329
+	stz $432a
+	stz $432b
 	stz $4330
 	stz $4331
 	stz $4332
 	stz $4333
 	stz $4334
+	stz $4335
+	stz $4336
+	stz $4337
+	stz $4338
+	stz $4339
+	stz $433a
+	stz $433b
 	stz $4340
 	stz $4341
 	stz $4342
 	stz $4343
 	stz $4344
+	stz $4345
+	stz $4346
+	stz $4347
+	stz $4348
+	stz $4349
+	stz $434a
+	stz $434b
 	stz $4350
 	stz $4351
 	stz $4352
 	stz $4353
 	stz $4354
-	stz $4360
-	stz $4361
-	stz $4362
-	stz $4363
-	stz $4364
+	stz $4355
+	stz $4356
+	stz $4357
+	stz $4358
+	stz $4359
+	stz $435a
+	stz $435b
+
+	stz $420b
+	stz $420c
 	rts
 
-
-
-
 waitblank:
+	php
+	sep #$30 : .as : .xs
 -	lda $4212
 	and #$80
 	bne -
 -	lda $4212
 	and #$80
 	beq -
+	plp
 	rts
 
 colortest:
@@ -91,11 +168,11 @@ setup_gfx:
 	stz $420b
 	stz $420c
 ;clear tilemap buffers
-	ldx #$0000
+	ldx #$8000
 	stx $2181
-	lda #$01
+	lda #$00
 	sta $2183
-	DMA0(#$08, #0, #^zero, #!zero, #$80)
+	DMA0(#$08, #$8000, #^zero, #!zero, #$80)
 
 ;generate fonts
 	jsr genfonts
@@ -146,6 +223,7 @@ setup_gfx:
 ;set palette
 	stz $2121
 	DMA0(#$00, #$200, #^palette, #!palette, #$22)
+	stz $2121
 
 ;copy hdma tables so we can work "without" the cartridge
 ;palette
@@ -198,7 +276,7 @@ setup_gfx:
 tests:
 	sep #$20 : .as		;8-bit accumulator
 	rep #$10 : .xl		;16-bit index
-	lda #$03		;mode 3, mode 5 via HDMA :D
+	lda #$03		;mode 3, mode 5 via HDMA
 	sta $2105
 	lda #$58		;Tilemap addr 0xB000
 	ora #$02		;SC size 32x64
@@ -224,11 +302,17 @@ tests:
 	lda #$1f
 	sta $212e
 	sta $212f
-	stz $2121
-	lda #$0f
-	sta $2100		;screen on, full brightness
-	lda #9
+;	stz $2121
+	lda #8
 	sta bar_yl
+	stz cur_bright
+	stz tgt_bright
+	rts
+
+screen_on:
+	stz $2100		;screen on, 0% brightness
+	lda #$0f
+	sta tgt_bright
 	rts
 
 snes_init:
@@ -248,6 +332,7 @@ snes_init:
 	stz $420a		;
 	stz $420b		;
 	stz $420c		;
+	stz $420d		;
 	lda #$8f
 	sta $2100		;INIDISP: force blank
 	lda #$03		; 8x8+16x16; name=0; base=3
@@ -339,7 +424,7 @@ snes_init:
 
 fadeloop:
 	sep #$30 : .as : .xs
-	ldx #$0f
+	ldx cur_bright
 	and #$00
 	pha
 	plb

snes/memmap.i65

@@ -6,19 +6,24 @@
 /* These must be defined as constants, because they're used
  * in calculation that is sent to PPU as parameters */
 
+#define APUIO0		$2140
+#define APUIO1		$2141
+#define APUIO2		$2142
+#define APUIO3		$2143
+
 #define BG1_TILE_BASE	$5800
 #define BG2_TILE_BASE	$5000
 
 #define OAM_TILE_BASE	$6000
 
-#define BG1_TILE_BUF	$7FB000
-#define BG2_TILE_BUF	$7FA000
+#define BG1_TILE_BUF	$7EB000
+#define BG2_TILE_BUF	$7EA000
 
-#define BG1_TILE_BAK	$7F9000
-#define BG2_TILE_BAK	$7F8000
+#define BG1_TILE_BAK	$7E9000
+#define BG2_TILE_BAK	$7E8000
 
-#define AVR_CMD		$307000
-#define AVR_PARAM	$307004
+#define MCU_CMD		$307000
+#define MCU_PARAM	$307004
 #define RTC_STATUS	$307100
 #define LAST_STATUS	$307101
 #define SYSINFO_BLK	$307200
@@ -27,3 +32,9 @@
 #define ROOT_DIR	$C10000
 
 #define CMD_SYSINFO	$03
+#define CMD_LOADSPC	$05
+#define CMD_RESET	$06
+
+#define SPC_DATA	$FD0000
+#define SPC_HEADER	$FE0000
+#define SPC_DSP_REGS	$FE0100

snes/menu.a65

@@ -42,7 +42,6 @@ menuloop_s1
 	lda isr_done
 	lsr
 	bcc menuloop_s1
-
 	stz isr_done
 	jsr printtime
 	jsr menu_updates	;update stuff, check keys etc
@@ -272,6 +271,10 @@ dirent_is_file
 	lda #$0000
 	bra dirent_type_cont
 +
+	cmp #$0003  ;SPC -> palette 2
+	bne +
+	lda #$0002
+	bra dirent_type_cont
 	cmp #$0004	;IPS -> palette 2 (green)
 	bne +
         lda #$0002
@@ -502,6 +505,8 @@ select_item:
 	lda [dirptr_addr], y
 	cmp #$01
 	beq sel_is_file
+	cmp #$03
+	beq sel_is_spc
 	cmp #$04
 	beq sel_is_file
 	cmp #$80
@@ -519,25 +524,28 @@ sel_is_parent
 sel_is_dir
 	jsr select_dir
 	bra select_item_cont
+sel_is_spc
+	jsr select_spc
+	bra select_item_cont
 
 select_file:
-	; have avr load the rom
+	; have MCU load the rom
 	dey
 	rep #$20 : .al
 	lda [dirptr_addr], y
 	and #$00ff
-	sta @AVR_PARAM+2
+	sta @MCU_PARAM+2
 	dey
 	dey
 	lda [dirptr_addr], y
-	sta @AVR_PARAM
+	sta @MCU_PARAM
 	sep #$20 : .as
-	lda #$01
-	sta @AVR_CMD
-select_file_fade:
 	lda #$00
 	sta @$4200
 	sei
+	lda #$01
+	sta @MCU_CMD
+select_file_fade:
 	jsl @wram_fadeloop
 	rts
 
@@ -597,6 +605,8 @@ select_dir:
 	sta @dirstart_addr
 	lda #$0000
 	sta @menu_sel
+	sta @direntry_xscroll
+	sta @direntry_xscroll_state
 	sep #$20 : .as
 	lda #$01
 	sta @menu_dirty
@@ -635,6 +645,27 @@ select_parent:
 	sta @menu_dirty
 	rts
 
+select_spc:
+	dey
+	rep #$20 : .al
+	lda [dirptr_addr], y
+	and #$00ff
+	sta @MCU_PARAM+2
+	dey
+	dey
+	lda [dirptr_addr], y
+	sta @MCU_PARAM
+	sep #$20 : .as
+	lda #CMD_LOADSPC
+	sta @MCU_CMD
+wait_spc:
+	lda @MCU_CMD
+	cmp #$00
+	bne wait_spc
+	jsr spcplayer
+	jsr restore_screen
+	rts
+
 menu_key_x:
 	jsr mainmenu
 	rts
@@ -774,7 +805,7 @@ select_last_file:
 	and pad1trig+1
 	beq -
 	lda #$04
-	sta @AVR_CMD
+	sta @MCU_CMD
 	jmp select_file_fade
 +	jsr restore_screen
 	plp
@@ -850,6 +881,7 @@ scroll_direntry_scrollfast
 	lda #$28
 	sta direntry_xscroll_wait
 +	lda direntry_xscroll_state
+	clc
 	adc direntry_xscroll
 	sta direntry_xscroll
 	bne +

snes/reset.a65

@@ -84,9 +84,29 @@ math_cont
 	clc
 	adc bar_x	; + X start coord
 	sta $2127	; window 1 right
-	lda #$3e	; ch. 1-5
-	sta @$420c	; trigger HDMA
-	lda #$01
+;	lda #$3e	; ch. 1-5
+;	sta @$420c	; trigger HDMA
+
+	lda cur_bright
+	cmp tgt_bright
+	beq +
+	bpl bright_down
+bright_up
+	inc
+	sta cur_bright
+	lda $2100
+	and #$f0
+	ora cur_bright
+	sta $2100
+	bra +
+bright_down
+	dec
+	sta cur_bright
+	lda $2100
+	and #$f0
+	ora cur_bright
+	sta $2100
++	lda #$01
 	sta isr_done
         rtl
 

snes/spc700.a65

@@ -0,0 +1,61 @@
+; All SPC700 routines in SPC700 machine code
+; SPC loader & transfer routines by Shay Green <gblargg@gmail.com>
+
+loader				; .org $0002
+	.byt $F8,$21		;	mov x,@loader_data
+	.byt $BD		;	mov sp,x
+	.byt $CD,$22		;	mov x,#@loader_data+1
+
+	; Push PC and PSW from SPC header
+	.byt $BF		;	mov a,(x)+
+	.byt $2D		;	push a
+	.byt $BF		;	mov a,(x)+
+	.byt $2D		;	push a
+	.byt $BF		;	mov a,(x)+
+	.byt $2D		;	push a
+
+	; Set FLG to $60 rather than value from SPC
+	.byt $E8,$60		;	mov a,#$60
+	.byt $D4,$6C		;	mov FLG+x,a
+
+	; Restore DSP registers
+	.byt $8D,$00		;	mov y,#0
+	.byt $BF		; next:	mov a,(x)+
+	.byt $CB,$F2		;	mov $F2,y
+	.byt $C4,$F3		;	mov $F3,a
+	.byt $FC		;	inc y
+	.byt $10,-8		;	bpl next
+
+	.byt $8F,$6C,$F2	;	mov $F2,#FLG	; set for later
+
+	; Rerun loader
+	.byt $5F,$C0,$FF	;	jmp $FFC0
+
+;---------------------------------------
+
+transfer			; .org $0002
+
+	.byt $CD,$FE		; mov x,#$FE		; transfer 254 pages
+
+	; Transfer four-byte chunks
+	.byt $8D,$3F		; page: mov y,#$3F
+	.byt $E4,$F4		; quad: mov a,$F4
+	.byt $D6,$00,$02	; mov0: mov !$0200+y,a
+	.byt $E4,$F5		;	mov a,$F5
+	.byt $D6,$40,$02	; mov1: mov !$0240+y,a
+	.byt $E4,$F6		;	mov a,$F6
+	.byt $D6,$80,$02	; mov2: mov !$0280+y,a
+	.byt $E4,$F7		;	mov a,$F7	; tell S-CPU we're ready for more
+	.byt $CB,$F7		;	mov $F7,Y
+	.byt $D6,$C0,$02	; mov3: mov !$02C0+y,a
+	.byt $DC 		;	dec y
+	.byt $10,-25		;	bpl quad
+	; Increment MSBs of addresses
+	.byt $AB,$0A		;	inc mov0+2
+	.byt $AB,$0F		;	inc mov1+2
+	.byt $AB,$14		;	inc mov2+2
+	.byt $AB,$1B		;	inc mov3+2
+	.byt $1D    		;	dec x
+	.byt $D0,-38		;	bne page
+	; Rerun loader
+	.byt $5F,$C0,$FF	;	jmp $FFC0

snes/spcplay.a65

@@ -0,0 +1,656 @@
+#include "memmap.i65"
+
+; SPC Player
+; SPC700 transfer and IO routines by Shay Green <gblargg@gmail.com>
+
+spcplayer:
+	php
+	sep #$30 : .as : .xs
+
+	ldx #$0a	; Check if SPC header is present
+-
+	lda @SPC_HEADER,x
+	cmp @text_spcid,x
+	beq +
+	jmp spc_exit
++
+	dey
+	bne -
+
+	rep #$10 : .xl	; Now draw lots of stuff
+
+	stz bar_wl
+	dec bar_wl
+	stz bar_xl
+	dec bar_xl
+	stz bar_yl
+	dec bar_yl
+	jsr backup_screen
+
+	lda #^text_spcplay	; Loading window
+	sta window_tbank
+	ldx #!text_spcplay
+	stx window_taddr
+	lda @spcplay_win_x
+	sta window_x
+	lda @spcplay_win_y
+	sta window_y
+	lda @spcplay_win_w
+	sta window_w
+	lda @spcplay_win_h
+	sta window_h
+	jsr draw_window
+
+	lda #^text_spcload	; Loading text
+	ldx #!text_spcload
+	sta print_bank
+	stx print_src
+	stz print_pal
+	lda #29
+	sta print_count
+	lda #17
+	sta print_y
+	lda #17
+	sta print_x
+	jsr hiprint
+
+	stz isr_done
+-
+	lda isr_done		; Wait until text is being printed...
+	beq -
+
+	jsr spc700_load		; Load SPC into SPC700
+
+	lda #^text_spcplay
+	sta window_tbank
+	ldx #!text_spcplay
+	stx window_taddr
+	lda @spcstart_win_x
+	sta window_x
+	lda @spcstart_win_y
+	sta window_y
+	lda @spcstart_win_w
+	sta window_w
+	lda @spcstart_win_h
+	sta window_h
+	jsr draw_window
+
+	lda #^text_spcstarta
+	ldx #!text_spcstarta
+	sta print_bank
+	stx print_src
+	lda #$01
+	sta print_pal
+	lda #30
+	sta print_count
+	lda #15
+	sta print_y
+	lda #17
+	sta print_x
+	jsr hiprint
+
+	lda #^text_spcstartb
+	ldx #!text_spcstartb
+	sta print_bank
+	stx print_src
+	lda #$01
+	sta print_pal
+	lda #07
+	sta print_count
+	lda #17
+	sta print_y
+	lda #12
+	sta print_x
+	jsr hiprint
+
+	lda #$fe
+	ldx #$004e
+	sta print_bank
+	stx print_src
+	stz print_pal
+	lda #32
+	sta print_count
+	lda #17
+	sta print_y
+	lda #20
+	sta print_x
+	jsr hiprint
+
+	lda #^text_spcstartc
+	ldx #!text_spcstartc
+	sta print_bank
+	stx print_src
+	lda #$01
+	sta print_pal
+	lda #07
+	sta print_count
+	lda #18
+	sta print_y
+	lda #12
+	sta print_x
+	jsr hiprint
+
+	lda #$fe
+	ldx #$002e
+	sta print_bank
+	stx print_src
+	stz print_pal
+	lda #32
+	sta print_count
+	lda #18
+	sta print_y
+	lda #20
+	sta print_x
+	jsr hiprint
+
+	lda #^text_spcstartd
+	ldx #!text_spcstartd
+	sta print_bank
+	stx print_src
+	lda #$01
+	sta print_pal
+	lda #07
+	sta print_count
+	lda #19
+	sta print_y
+	lda #12
+	sta print_x
+	jsr hiprint
+
+	lda #$fe
+	ldx #$00b0
+        sta longptr+2
+	sta print_bank
+        stx longptr
+        ldy #$00
+        lda [longptr], y
+        cmp #$41
+        bpl +
+        inx
++	stx print_src
+	stz print_pal
+	lda #32
+	sta print_count
+	lda #19
+	sta print_y
+	lda #20
+	sta print_x
+	jsr hiprint
+
+spc_playloop:
+	lda isr_done	; SPC player loop
+	lsr
+	bcc spc_playloop
+	jsr printtime
+	stz isr_done
+
+	jsr read_pad
+	lda #$80
+	and pad1trig+1
+	bne spc_key_b
+	bra spc_playloop
+
+spc_key_b:
+	rep #$20 : .al
+	tsc
+	sta saved_sp	; Save SP for later re-entry
+	lda #$fa50	; Write reset signature
+	sta @warm_signature
+	sep #$20 : .as
+
+	sei		; Blank screen & issue CMD_RESET command to Microcontroller...
+	stz $2100	; ...this is required, because there is no other way to stop S-SMP & S-DSP
+	lda #CMD_RESET
+	sta @MCU_CMD
+-
+	bra -		; At this point, the SNES waits for an external reset from the Microcontroller
+
+spc_exit:		; Return from player in case of wrong SPC file data
+	plp
+	rts
+
+;---------------------------------------
+spc700_load:
+	php
+	sep #$20 : .as
+	rep #$10 : .xl
+
+	sei			; Disable NMI & IRQ
+	stz $4200		; The SPC player code is really timing sensitive ;)
+	jsr upload_dsp_regs	; Upload S-DSP registers
+	jsr upload_high_ram	; Upload 63.5K of SPC700 ram
+	jsr upload_low_ram	; Upload rest of ram
+	jsr restore_final	; Restore SPC700 state & start execution
+
+	lda #$81		; VBlank NMI + Auto Joypad Read
+	sta $4200		; enable V-BLANK NMI
+	cli
+	plp
+	rts
+;---------------------------------------
+; Uploads DSP registers and some other setup code
+upload_dsp_regs:
+
+; ---- Begin upload
+
+	ldy #$0002
+	jsr spc_begin_upload
+
+; ---- Upload loader
+
+	ldx #$0000
+-
+	lda @loader,x
+	jsr spc_upload_byte
+	inx
+	cpy #31		; size of loader
+	bne -
+
+; ---- Upload SP, PC & PSW
+
+	lda @SPC_HEADER+43
+	jsr spc_upload_byte
+	lda @SPC_HEADER+38
+	jsr spc_upload_byte
+	lda @SPC_HEADER+37
+	jsr spc_upload_byte
+	lda @SPC_HEADER+42
+	jsr spc_upload_byte
+
+; ---- Upload DSP registers
+
+	ldx #$0000
+-
+	lda @SPC_DSP_REGS,x
+	jsr spc_upload_byte
+	inx
+	cpx #128
+	bne -
+
+; --- Upload fixed values for $F1-$F3
+
+	ldy #$00F1
+	jsr spc_next_upload
+
+	lda #$80        ; stop timers
+	jsr spc_upload_byte
+	lda #$6c        ; get dspaddr set for later
+	jsr spc_upload_byte
+	lda #$60
+	jsr spc_upload_byte
+
+; ---- Upload $f8-$1ff
+
+	ldy #$00F8
+	jsr spc_next_upload
+
+	ldx #$00F8
+-
+	lda @SPC_DATA,x
+	jsr spc_upload_byte
+	inx
+	cpx #$200
+	bne -
+
+; ---- Execute loader
+
+	ldy #$0002
+	jsr spc_execute
+	rts
+;---------------------------------------
+upload_high_ram:
+
+	ldy #$0002
+	jsr spc_begin_upload
+
+; ---- Upload transfer routine
+
+	ldx #$0000
+-
+	lda @transfer,x
+	jsr spc_upload_byte
+	inx
+	cpy #43		; size of transfer routine
+	bne -
+
+	ldx #$023f	; prepare transfer address
+
+; ---- Execute transfer routine
+
+	ldy #$0002
+	sty APUIO2
+	stz APUIO1
+	lda APUIO0
+	inc
+	inc
+	sta APUIO0
+; Wait for acknowledgement
+-
+	cmp APUIO0
+	bne -
+
+; ---- Burst transfer of 63.5K using custom routine
+
+outer_transfer_loop:
+	ldy #$003f		; 3
+inner_transfer_loop:
+	lda @SPC_DATA,x		; 5 |
+	sta APUIO0		; 4 |
+	lda @SPC_DATA+$40,x	; 5 |
+	sta APUIO1		; 4 |
+	lda @SPC_DATA+$80,x	; 5 |
+	sta APUIO2		; 4 |
+	lda @SPC_DATA+$C0,x	; 5 |
+	sta APUIO3		; 4 |
+	tya			; 2 >> 38 cycles
+-
+	cmp APUIO3		; 4 |
+	bne -			; 3 |
+	dex			; 2 |
+	dey			; 2 |
+	bpl inner_transfer_loop	; 3 >> 14 cycles
+
+	rep #$21 : .al		; 3 |
+	txa			; 2 |
+	adc #$140		; 3 |
+	tax			; 2 |
+	sep #$20 : .as		; 3 |
+	cpx #$003f		; 3 |
+	bne outer_transfer_loop	; 3 >> 19 cycles
+
+	rts
+
+;---------------------------------------
+upload_low_ram:
+
+; ---- Upload $0002-$00EF using IPL
+
+	ldy #$0002
+	jsr spc_begin_upload
+
+	ldx #$0002
+-
+	lda @SPC_DATA,x
+	jsr spc_upload_byte
+	inx
+	cpx #$00F0
+	bne -
+	rts
+;---------------------------------------
+; Executes final restoration code
+restore_final:
+	jsr start_exec_io ; prepare execution from I/O registers
+
+	stz $420d	; SPC700 I/O code requires SLOW timing
+
+; ---- Restore first two bytes of RAM
+
+	lda @SPC_DATA
+	xba
+	lda #$e8	; MOV A,#@SPC_DATA
+	tax
+	jsr exec_instr
+	ldx #$00C4	; MOV $00,A
+	jsr exec_instr
+
+	lda @SPC_DATA+1
+	xba
+	lda #$e8	; MOV A,#@SPC_DATA+1
+	tax
+	jsr exec_instr
+	ldx #$01C4	; MOV $01,A
+	jsr exec_instr
+
+; ---- Restore SP
+
+	lda @SPC_HEADER+43
+	sec
+	sbc #3
+	xba
+	lda #$cd	; MOV X,#@SPC_HEADER+43
+	tax
+	jsr exec_instr
+	ldx #$bd	; MOV SP,X
+	jsr exec_instr
+
+; ---- Restore X
+
+	lda @SPC_HEADER+40
+	xba
+	lda #$cd	; MOV X,#@SPC_HEADER+40
+	tax
+	jsr exec_instr
+
+; ---- Restore Y
+
+	lda @SPC_HEADER+41
+	xba
+	lda #$8d	; MOV Y,#@SPC_HEADER+41
+	tax
+	jsr exec_instr
+
+; ---- Restore DSP FLG register
+
+	lda @SPC_DSP_REGS+$6c
+	xba
+	lda #$e8	; MOV A,#@SPC_DSP_REGS+$6c
+	tax
+	jsr exec_instr
+	ldx #$f3C4	; MOV $f3,A -> $f2 has been set-up before by SPC700 loader
+	jsr exec_instr
+
+; ---- Restore DSP KON register
+
+	lda #$4C
+	xba
+	lda #$e8	; MOV A,#$4c
+	tax
+	jsr exec_instr
+	ldx #$f2C4	; MOV $f2,A
+	jsr exec_instr
+	lda @SPC_DSP_REGS+$4C
+	xba
+	lda #$e8	; MOV A,#@SPC_DSP_REGS+$4c
+	tax
+	jsr exec_instr
+	ldx #$f3C4	; MOV $f3,A
+	jsr exec_instr
+
+; ---- Restore DSP register address
+
+ 	lda @SPC_DATA+$F2
+	xba
+	lda #$e8	; MOV A,#@SPC_DATA+$F2
+	tax
+	jsr exec_instr
+	ldx #$f2C4	; MOV dest,A
+	jsr exec_instr
+
+; ---- Restore CONTROL register
+
+	lda @SPC_DATA+$F1
+	and #$CF	; don't clear input ports
+	xba
+	lda #$e8	; MOV A,#@SPC_DATA+$F1
+	tax
+	jsr exec_instr
+	ldx #$f1C4  	; MOV $F1,A
+	jsr exec_instr
+
+;---- Restore A
+
+	lda @SPC_HEADER+39
+	xba
+	lda #$e8	; MOV A,#@SPC_HEADER+39
+	tax
+	jsr exec_instr
+
+;---- Restore PSW and PC
+
+	ldx #$7F00	; NOP; RTI
+	stx APUIO0
+	lda #$FC	; Patch loop to execute instruction just written
+	sta APUIO3
+
+;---- restore IO ports $f4 - $f7
+
+	rep #$20 : .al
+	lda @SPC_DATA+$F4
+	tax
+	lda @SPC_DATA+$F6
+	sta APUIO2
+	stx APUIO0	; last to avoid overwriting RETI before run
+	sep #$20 : .as
+
+	lda #$01
+	sta $420d	; restore FAST CPU operation
+	rts
+;---------------------------------------
+spc_begin_upload:
+
+	sty APUIO2	; Set address
+
+	ldy #$BBAA	; Wait for SPC
+-
+	cpy APUIO0
+	bne -
+
+	lda #$CC	; Send acknowledgement
+	sta APUIO1
+	sta APUIO0
+
+-       		; Wait for acknowledgement
+	cmp APUIO0
+	bne -
+
+	ldy #0		; Initialize index
+	rts
+;---------------------------------------
+spc_upload_byte:
+	sta APUIO1
+
+	tya		; Signal it's ready
+	sta APUIO0
+-     			; Wait for acknowledgement
+	cmp APUIO0
+	bne -
+
+	iny
+
+	rts
+;---------------------------------------
+spc_next_upload:
+	sty APUIO2
+
+; Send command
+; Special case operation has been fully tested.
+	lda APUIO0
+	inc
+	inc
+	bne +
+	inc
++
+	sta APUIO1
+	sta APUIO0
+
+; Wait for acknowledgement
+-
+	cmp APUIO0
+	bne -
+
+	ldy #0
+	rts
+;---------------------------------------
+spc_execute:
+	sty APUIO2
+
+	stz APUIO1
+
+	lda APUIO0
+	inc
+	inc
+	sta APUIO0
+
+; Wait for acknowledgement
+-
+	cmp APUIO0
+	bne -
+
+	rts
+;---------------------------------------
+start_exec_io:
+; Set execution address
+	ldx #$00F5
+	stx APUIO2
+
+	stz APUIO1      ; NOP
+	ldx #$FE2F      ; BRA *-2
+
+; Signal to SPC that we're ready
+	lda APUIO0
+	inc
+	inc
+	sta APUIO0
+
+; Wait for acknowledgement
+-
+	cmp APUIO0
+	bne -
+
+; Quickly write branch
+	stx APUIO2
+
+	rts
+;---------------------------------------
+exec_instr:
+; Replace instruction
+	stx APUIO0
+	lda #$FC
+	sta APUIO3      ; 30
+
+        ; SPC BRA loop takes 4 cycles, so it reads
+        ; the branch offset every 4 SPC cycles (84 master).
+        ; We must handle the case where it read just before
+        ; the write above, and when it reads just after it.
+        ; If it reads just after, we have at least 7 SPC
+        ; cycles (147 master) to change restore the branch
+        ; offset.
+
+        ; 48 minimum, 90 maximum
+        ora #0
+        ora #0
+        ora #0
+        nop
+        nop
+        nop
+
+        ; 66 delay, about the middle of the above limits
+	phd ;4
+	pld ;5
+
+        ; Give plenty of extra time if single execution
+        ; isn't needed, as this avoids such tight timing
+        ; requirements.
+
+;	phd ;4
+;	pld ;5
+;	phd ;4
+;	pld ;5
+
+        ; Patch loop to skip first two bytes
+	lda #$FE        ; 16
+	sta APUIO3      ; 30
+
+        ; 38 minimum (assuming 66 delay above)
+	phd ; 4
+	pld ; 5
+
+        ; Give plenty of extra time if single execution
+        ; isn't needed, as this avoids such tight timing
+        ; requirements.
+
+	phd
+	pld
+	phd
+	pld
+	rts

snes/sysinfo.a65

@@ -35,11 +35,19 @@ show_sysinfo:
 	sta window_h
 	jsr draw_window
 	stz print_pal
+	
+	ldx #38
+copy_snes_system_text:
+	lda @text_system,x
+	sta @snes_system_config,x
+	dex
+	bpl copy_snes_system_text
+	
 sysinfo_printloop:
 	sep #$20 : .as
 	rep #$10 : .xl
 	lda #CMD_SYSINFO
-	sta @AVR_CMD
+	sta @MCU_CMD
 	lda #^SYSINFO_BLK
 	ldx #!SYSINFO_BLK
 	sta print_bank
@@ -51,7 +59,7 @@ sysinfo_printloop:
 	sta print_x
 	lda #40
 	sta print_count
-	lda #13
+	lda #12
 -	pha
 	jsr hiprint
 	inc print_y
@@ -64,6 +72,41 @@ sysinfo_printloop:
 	pla
 	dec
 	bne -
+	
+	ldx #24
+	lda $213e
+	and #$0f
+	clc
+	adc #$30
+	sta @snes_system_config,x
+	
+	ldx #38
+	lda $213f
+	and #$0f
+	clc
+	adc #$30
+	sta @snes_system_config,x
+	
+	ldx #10
+	lda $4210
+	and #$0f
+	clc
+	adc #$30
+	sta @snes_system_config,x		
+	
+	lda #^snes_system_config		; System text
+	ldx #!snes_system_config
+	sta print_bank
+	stx print_src
+	stz print_pal
+	lda #39
+	sta print_count
+	lda #23
+	sta print_y
+	lda #12
+	sta print_x
+	jsr hiprint		
+	
 -	lda isr_done
 	lsr
 	bcc -
@@ -87,5 +130,5 @@ sysinfo_printloop:
 +	plp
 	jsr restore_screen
 	lda #$00
-	sta @AVR_CMD
+	sta @MCU_CMD
 	rtl

snes/text.a65

@@ -1,146 +1,95 @@
 .text
 #include "memmap.i65"
 .byt "===HIPRINT==="
+; input:
+; print_count
+; print_x
+; print_y
+; print_src
+; print_bank
+; print_pal
+;
+; output:
+; print_done (# of chars printed)
+; print_over (char after print_count)
+
 hiprint:
+	php
 	sep #$20 : .as
-	lda print_count
-	sta print_count_tmp
-	stz print_over
-	rep #$30 : .xl : .al
-	stz print_done
-	lda print_x
-	and #$00ff
-	lsr
-	bcs print_bg1
-	ldx #!BG1_TILE_BUF ; for 2nd loop
-	phx
-	ldx #!BG2_TILE_BUF ; for 1st loop
-	phx
-	bra print_bg_cont
-print_bg1
-	ldx #!BG2_TILE_BUF+2 ; for 2nd loop
-	phx
-	ldx #!BG1_TILE_BUF ; for 1st loop da whoop
-	phx
-	bra print_bg_cont
-print_bg_cont
-	sta !print_temp
-	lda !print_y
-	and #$00ff
-	asl
-	asl
-	asl
-	asl
-	asl
-	clc
-	adc !print_temp
-	asl ; double the offset for WRAM addressing
-	tay	; zonday
-	plx
-	phy	; offset from tilemap start
-	stx !print_temp
-	clc
-	adc !print_temp
-; we need to transfer to WRAM and from there to VRAM via DMA during VBLANK
-; because VRAM can only be accessed during VBLANK and forced blanking.
-	sta $2181
-	sep #$20 : .as
-	lda #$7f ;we really only need bit 0. full bank given for clarity
-	sta $2183
-print_loop
-	ldx !print_src
-	lda !print_bank
-	pha
-	plb
-	phx	; source addr
-print_loop_inner
-	lda !0,x
-	bne +
-	jmp print_end2
-+	asl
-	sta @$2180
-	lda @print_pal
-	asl
-	asl
-	adc #$00
-	ora #$20
-	sta @$2180
-	lda @print_done
-	inc
-	sta @print_done
-	inx
-	lda !0,x
-	beq print_loop2
-	inx
-	lda !0,x
-	beq print_loop2
-	lda @print_count_tmp
-	dec
-	dec
-	sta @print_count_tmp
-	beq print_loop2
-	bmi print_loop2
-	bra print_loop_inner
-print_loop2
-	lda @print_count
-	dec
-	sta @print_count_tmp
-	beq print_end2
-	lda #$00
+	rep #$10 : .xl
+	ldx print_src
+	stx print_ptr
+	lda print_bank
+	sta print_ptr+2
+	phb
+	lda #$7e
 	pha
 	plb
 	rep #$30 : .al : .xl
-	ply	; source addr
-	iny
-	pla	; offset from tilemap start
-	plx	; other tilemap addr
-	stx !print_temp
+	lda print_pal
+	and #$00ff
+	xba
+	asl
+	asl
+	ora #$2000
+	sta print_temp
+	lda print_count
+	and #$00ff
+	beq hiprint_end
+	tay
+	lda print_x
+	and #$00ff
+	sta print_x
+	lda print_y
+	and #$00ff
+	asl
+	asl
+	asl
+	asl
+	asl
+	asl
 	clc
-	adc !print_temp ; tilemap+offset
-	sta $2181
-	tyx
+	adc print_x
+	and #$fffe
+	tax
+	lda print_x
+	lsr
+	bcs hiprint_bg1
+hiprint_bg2
+	lda [print_ptr]
+	and #$00ff
+	beq hiprint_end
+	inc print_ptr
+	asl
+	ora print_temp
+	sta !BG2_TILE_BUF, x
+	dey
+	beq hiprint_end
+hiprint_bg1
+	lda [print_ptr]
+	and #$00ff
+	beq hiprint_end
+	inc print_ptr
+	asl
+	ora print_temp
+	sta !BG1_TILE_BUF, x
+	inx
+	inx
+	dey
+	beq hiprint_end
+	bra hiprint_bg2
+hiprint_end
+	plb
 	sep #$20 : .as
-	lda print_bank
-	pha
-	plb
-print_loop2_inner
-	lda !0,x
-	bne +
-	jmp print_end
-+	asl
-	sta @$2180
-	lda @print_pal
-	asl
-	asl
-	adc #$00
-	ora #$20
-	sta @$2180
-	lda @print_done
+	lda [print_ptr]
+	sta print_over
+	tya
+	sec
+	sbc print_count
+	eor #$ff
 	inc
-	sta @print_done
-	inx
-	lda !0,x
-	beq print_end
-	lda @print_count_tmp
-	dec
-	dec
-	sta @print_count_tmp
-	beq print_end
-	bmi print_end
-	inx
-	lda !0,x
-	beq print_end
-	bra print_loop2_inner
-print_end2 ; clean up the stack (6 bytes)
-	ply
-	ply
-	ply
-print_end
-	lda !0,x
-	sta @print_over
-	lda #$00
-	pha
-	plb
+	sta print_done
+	plp
 	rts
 
 
@@ -290,6 +239,7 @@ draw_window:
 	sta print_count
 	jsr hiprint
 	lda print_done
+	clc
 	adc print_x
 	sta print_x
 	lda #^window_tr

snes/time.a65

@@ -499,6 +499,8 @@ time_dec_y1_normal
 	rts
 
 gettime
+	php
+	sep #$20 : .as
 	lda #$0d
 	sta $2801
 	lda $2800
@@ -526,6 +528,7 @@ gettime
 	sta time_y10
 	lda $2800
 	sta time_y100
+	plp
 	rts
 
 rendertime
@@ -677,31 +680,31 @@ is_leapyear_400th
 
 settime
 	lda time_y100
-	sta @AVR_PARAM
+	sta @MCU_PARAM
 	lda time_y10
-	sta @AVR_PARAM+1
+	sta @MCU_PARAM+1
 	lda time_y1
-	sta @AVR_PARAM+2
+	sta @MCU_PARAM+2
 	lda time_mon
-	sta @AVR_PARAM+3
+	sta @MCU_PARAM+3
 	lda time_d10
-	sta @AVR_PARAM+4
+	sta @MCU_PARAM+4
 	lda time_d1
-	sta @AVR_PARAM+5
+	sta @MCU_PARAM+5
 	lda time_h10
-	sta @AVR_PARAM+6
+	sta @MCU_PARAM+6
 	lda time_h1
-	sta @AVR_PARAM+7
+	sta @MCU_PARAM+7
 	lda time_m10
-	sta @AVR_PARAM+8
+	sta @MCU_PARAM+8
 	lda time_m1
-	sta @AVR_PARAM+9
+	sta @MCU_PARAM+9
 	lda time_s10
-	sta @AVR_PARAM+10
+	sta @MCU_PARAM+10
 	lda time_s1
-	sta @AVR_PARAM+11
+	sta @MCU_PARAM+11
 	lda #$02 ; set clock
-	sta @AVR_CMD
+	sta @MCU_CMD
 	rts
 
 printtime:

src/Makefile

@@ -117,7 +117,6 @@ endif
 # CC must be defined here to generate the correct CFLAGS
 SHELL = sh
 CC = $(ARCH)-gcc
-#CC = clang
 OBJCOPY = $(ARCH)-objcopy
 OBJDUMP = $(ARCH)-objdump
 SIZE = $(ARCH)-size
@@ -126,6 +125,7 @@ REMOVE = rm -f
 COPY = cp
 AWK = awk
 
+
 #---------------- Compiler Options ----------------
 #  -g*:          generate debugging information
 #  -O*:          optimization level
@@ -138,10 +138,8 @@ CFLAGS += $(CDEFS) $(CINCS)
 CFLAGS += -O$(OPT)
 CFLAGS += $(CPUFLAGS) -nostartfiles
 #CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
-CFLAGS += -Wall -Wstrict-prototypes
-#-Werror
+CFLAGS += -Wall -Wstrict-prototypes -Werror
 CFLAGS += -Wa,-adhlns=$(OBJDIR)/$(<:.c=.lst)
-#CFLAGS += -I/opt/arm-none-eabi-4.6.2/arm-none-eabi/include/
 CFLAGS += -I$(OBJDIR)
 CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
 CFLAGS += $(CSTANDARD)

src/README

@@ -25,6 +25,7 @@ b) Cortex M3 toolchain
     - libexpat-dev
     - make
     - gcc
+   Package names may differ for your distribution.
    Newer gccs complain when compiling binutils, so you may have to add
    '--disable-werror' to the compiler options for binutils in the Makefile.
    The Makefile will install immediately so make sure you can write to the

src/bootldr/baudcalc.c

@@ -1,80 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include "config.h"
-
-static uint8_t uart_lookupratio(float f_fr) {
-  uint16_t errors[72]={0,67,71,77,83,91,100,111,125,
-                       133,143,154,167,182,200,214,222,231,
-                       250,267,273,286,300,308,333,357,364,
-                       375,385,400,417,429,444,455,462,467,
-                       500,533,538,545,556,571,583,600,615,
-                       625,636,643,667,692,700,714,727,733,
-                       750,769,778,786,800,818,833,846,857,
-                       867,875,889,900,909,917,923,929,933};
-
-  uint8_t ratios[72]={0x10,0xf1,0xe1,0xd1,0xc1,0xb1,0xa1,0x91,0x81,
-                      0xf2,0x71,0xd2,0x61,0xb2,0x51,0xe3,0x92,0xd3,
-                      0x41,0xf4,0xb3,0x72,0xa3,0xd4,0x31,0xe5,0xb4,
-                      0x83,0xd5,0x52,0xc5,0x73,0x94,0xb5,0xd6,0xf7,
-                      0x21,0xf8,0xd7,0xb6,0x95,0x74,0xc7,0x53,0xd8,
-                      0x85,0xb7,0xe9,0x32,0xd9,0xa7,0x75,0xb8,0xfb,
-                      0x43,0xda,0x97,0xeb,0x54,0xb9,0x65,0xdb,0x76,
-                      0xfd,0x87,0x98,0xa9,0xba,0xcb,0xdc,0xed,0xfe};
-
-  int fr = (f_fr-1)*1000;
-  int i=0, i_result=0;
-  int err=0, lasterr=1000;
-  for(i=0; i<72; i++) {
-    if(fr<errors[i]) {
-      err=errors[i]-fr;
-    } else {
-      err=fr-errors[i];
-    }
-    if(err<lasterr) {
-      i_result=i;
-      lasterr=err;
-    }
-  }
-  return ratios[i_result];
-}
-static uint32_t baud2divisor(unsigned int baudrate) {
-  uint32_t int_ratio;
-  uint32_t error;
-  uint32_t dl=0;
-  float f_ratio;
-  float f_fr;
-  float f_dl;
-  float f_pclk = (float)CONFIG_CPU_FREQUENCY / CONFIG_UART_PCLKDIV;
-  uint8_t fract_ratio;
-  f_ratio=(f_pclk / 16 / baudrate);
-  int_ratio = (int)f_ratio;
-  error=(f_ratio*1000)-(int_ratio*1000);
-  if(error>990) {
-    int_ratio++;
-  } else if(error>10) {
-    f_fr=1.5;
-    f_dl=f_pclk / (16 * baudrate * (f_fr));
-    dl = (int)f_dl;
-    f_fr=f_pclk / (16 * baudrate * dl);
-    fract_ratio = uart_lookupratio(f_fr);
-  }
-  if(!dl) {
-    return int_ratio;
-  } else {
-    return ((fract_ratio<<16)&0xff0000) | dl;
-  }
-}
-
-int main(int argc, char *argv[])
-{
-   if (argc != 2)
-   {
-      printf("usage: %s baud\n", argv[0]);
-      return -1;
-   }
-      
-   printf("Baud %d : 0x%X\n", atoi(argv[1]), baud2divisor(atoi(argv[1])));
-
-   return 0;
-}

src/bootldr/conf2h.awk

@@ -4,7 +4,7 @@
 # file to a C header. No copyright claimed.
 
 BEGIN {
-  print "// autoconf.h generated from " ARGV[1] " at TODAY \n" \
+  print "// autoconf.h generated from " ARGV[1] " at " strftime() "\n" \
     "#ifndef AUTOCONF_H\n" \
     "#define AUTOCONF_H"
 }

src/bootldr/fileops.h

@@ -31,9 +31,7 @@
 
 enum filestates { FILE_OK=0, FILE_ERR, FILE_EOF };
 
-#define GCC_ALIGN_WORKAROUND __attribute__ ((aligned(4)))
-BYTE file_buf[512] GCC_ALIGN_WORKAROUND;
-
+BYTE file_buf[512];
 FATFS fatfs;
 FIL file_handle;
 FRESULT file_res;

src/bootldr/openocd-usb.cfg

@@ -5,14 +5,8 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x15ba 0x0003
-ft2232_device_desc "Olimex OpenOCD JTAG"
-ft2232_layout "olimex-jtag"
-
-
-#interface ft2232
-#ft2232_vid_pid 0x0403 0x6010
-#ft2232_device_desc "Dual RS232"
-#ft2232_layout "oocdlink"
-#ft2232_latency 2
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232"
+ft2232_layout "oocdlink"
+ft2232_latency 2
 #adapter_khz 10

src/cli.c

@@ -58,8 +58,8 @@ static char *curchar;
 
 /* Word lists */
 static char command_words[] =
-  "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0rm\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0stramtest\0";
-enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16, CMD_SRAMTEST };
+  "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0rm\0mkdir\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0";
+enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_MKDIR, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16 };
 
 /* ------------------------------------------------------------------------- */
 /*   Parse functions                                                         */
@@ -294,7 +294,8 @@ static void cmd_loadraw(void) {
 static void cmd_saveraw(void) {
   uint32_t address = parse_unsigned(0,16777216,16);
   uint32_t length = parse_unsigned(0,16777216,16);
-  save_sram((uint8_t*)curchar, length, address);
+  if(address != -1 && length != -1)
+    save_sram((uint8_t*)curchar, length, address);
 }
 
 static void cmd_d4(void) {
@@ -348,6 +349,11 @@ void cmd_rm(void) {
   if(res) printf("Error %d removing %s\n", res, curchar);
 }
 
+void cmd_mkdir(void) {
+  FRESULT res = f_mkdir(curchar);
+  if(res) printf("Error %d creating directory %s\n", res, curchar);
+}
+
 void cmd_mapper(void) {
   int32_t mapper;
   mapper = parse_unsigned(0,7,10);
@@ -361,9 +367,7 @@ void cmd_sreset(void) {
     resetstate = parse_unsigned(0,1,10);
     snes_reset(resetstate);
   } else {
-    snes_reset(1);
-    delay_ms(20);
-    snes_reset(0);
+    snes_reset_pulse();
   }
 }
 void cmd_settime(void) {
@@ -416,10 +420,6 @@ void cmd_w16(void) {
   sram_writeshort(val, offset);
 }
 
-void cmd_sramtest(void) {
-   sram_memtest();
-}
-
 /* ------------------------------------------------------------------------- */
 /*   CLI interface functions                                                 */
 /* ------------------------------------------------------------------------- */
@@ -428,7 +428,7 @@ void cli_init(void) {
 }
 
 void cli_entrycheck() {
-  if(uart_gotc() && ((uart_getc() == 27) || (uart_getc() == 13))) {
+  if(uart_gotc() && uart_getc() == 27) {
     printf("*** BREAK\n");
     cli_loop();
   }
@@ -522,6 +522,10 @@ void cli_loop(void) {
       cmd_rm();
       break;
 
+    case CMD_MKDIR:
+      cmd_mkdir();
+      break;
+
     case CMD_D4:
       cmd_d4();
       break;
@@ -565,10 +569,7 @@ void cli_loop(void) {
     case CMD_W16:
       cmd_w16();
       break;
-    
-    case CMD_SRAMTEST:
-      cmd_sramtest();
-      break;
     }
+
   }
 }

src/clock.c

@@ -48,11 +48,9 @@ void clock_init() {
  */
   enableMainOsc();
   setClkSrc(CLKSRC_MAINOSC);
-// XXX  setPLL0MultPrediv(429, 19);
-// XXX  setPLL0MultPrediv(23, 2);
-  setPLL0MultPrediv(12, 1);
+  setPLL0MultPrediv(22, 1);
   enablePLL0();
-  setCCLKDiv(3);
+  setCCLKDiv(6);
   connectPLL0();
 }
 

src/conf2h.awk

@@ -4,7 +4,7 @@
 # file to a C header. No copyright claimed.
 
 BEGIN {
-  print "// autoconf.h generated from " ARGV[1] " at TODAY\n" \
+  print "// autoconf.h generated from " ARGV[1] " at " strftime() "\n" \
     "#ifndef AUTOCONF_H\n" \
     "#define AUTOCONF_H"
 }

src/config

@@ -1,4 +1,4 @@
-CONFIG_VERSION="0.1.30"
+CONFIG_VERSION="0.1.4a"
 #FWVER=00010300
-CONFIG_FWVER=66305
+CONFIG_FWVER=0x01010400
 CONFIG_MCU_FOSC=12000000

src/config.h

@@ -35,7 +35,7 @@
 
 #define CONFIG_UART_NUM	          3
 // #define CONFIG_CPU_FREQUENCY      90315789
-#define CONFIG_CPU_FREQUENCY      96000000
+#define CONFIG_CPU_FREQUENCY      88000000
 //#define CONFIG_CPU_FREQUENCY      46000000
 #define CONFIG_UART_PCLKDIV       1
 #define CONFIG_UART_TX_BUF_SHIFT  8
@@ -43,11 +43,7 @@
 #define CONFIG_UART_BAUDRATE      115200
 #define CONFIG_UART_DEADLOCKABLE
 
-#define SSP_CLK_DIVISOR_FAST 2
-#define SSP_CLK_DIVISOR_SLOW 250
-
-#define SSP_CLK_DIVISOR_FPGA_FAST 6
-#define SSP_CLK_DIVISOR_FPGA_SLOW 20
+#define SSP_CLK_DIVISOR           2
 
 #define SNES_RESET_REG            LPC_GPIO1
 #define SNES_RESET_BIT            26
@@ -69,6 +65,9 @@
 
 #define QSORT_MAXELEM             2048
 #define CLTBL_SIZE		  100
+
+#define DIR_FILE_MAX              16380
+
 #define SSP_REGS LPC_SSP0
 #define SSP_PCLKREG PCLKSEL1
 // 1: PCLKSEL0

src/diskio.h

@@ -55,7 +55,7 @@ DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
 #if	_READONLY == 0
 DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
 #endif
-#define disk_ioctl(a,b,c) RES_OK
+DRESULT disk_ioctl (BYTE, BYTE, void*);
 
 void disk_init(void);
 

src/ff.c

@@ -3644,6 +3644,7 @@ TCHAR* f_gets (
 		*p++ = c;
 		n++;
 		if (c == '\n') break;		/* Break on EOL */
+		if (c == 0) break;		/* Break on NUL */
 	}
 	*p = 0;
 	return n ? buff : 0;			/* When no data read (eof or error), return with error. */

src/filetypes.c

@@ -31,7 +31,7 @@
 #include "ff.h"
 #include "smc.h"
 #include "fileops.h"
-#include "crc32.h"
+#include "crc.h"
 #include "memory.h"
 #include "led.h"
 #include "sort.h"
@@ -60,7 +60,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
   uint8_t len;
   TCHAR* fn;
   static unsigned char depth = 0;
-  static uint32_t crc;
+  static uint32_t crc, fncrc;
   static uint32_t db_tgt;
   static uint32_t next_subdir_tgt;
   static uint32_t parent_tgt;
@@ -69,6 +69,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
   static uint16_t num_files_total = 0;
   static uint16_t num_dirs_total = 0;
   uint32_t dir_tgt;
+  uint32_t switched_dir_tgt = 0;
   uint16_t numentries;
   uint32_t dirsize;
   uint8_t pass = 0;
@@ -76,6 +77,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
   char *size_units[3] = {" ", "k", "M"};
   uint32_t entry_fsize;
   uint8_t entry_unit_idx;
+  uint16_t entrycnt;
 
   dir_tgt = this_dir_tgt;
   if(depth==0) {
@@ -91,10 +93,18 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
   fno.lfsize = 255;
   fno.lfname = (TCHAR*)file_lfn;
   numentries=0;
-  for(pass = 0; pass < 2; pass++) {
+  for(pass = 0; pass < (mkdb ? 2 : 1); pass++) {
     if(pass) {
-      num_dirs_total++;
       dirsize = 4*(numentries);
+      if(((next_subdir_tgt + dirsize + 8) & 0xff0000) > (next_subdir_tgt & 0xff0000)) {
+        printf("switchdir! old=%lX ", next_subdir_tgt + dirsize + 4);
+        next_subdir_tgt &= 0xffff0000;
+        next_subdir_tgt += 0x00010004;
+        printf("new=%lx\n", next_subdir_tgt);
+        dir_tgt &= 0xffff0000;
+        dir_tgt += 0x00010004;
+      }
+      switched_dir_tgt = dir_tgt;
       next_subdir_tgt += dirsize + 4;
       if(parent_tgt) next_subdir_tgt += 4;
       if(next_subdir_tgt > dir_end) {
@@ -102,6 +112,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
       }
       DBG_FS printf("path=%s depth=%d ptr=%lx entries=%d parent=%lx next subdir @%lx\n", path, depth, db_tgt, numentries, parent_tgt, next_subdir_tgt);
       if(mkdb) {
+        num_dirs_total++;
 //        printf("d=%d Saving %lx to Address %lx  [end]\n", depth, 0L, next_subdir_tgt - 4);
         sram_writelong(0L, next_subdir_tgt - 4);
       }
@@ -130,7 +141,8 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
         dir_tgt += 4;
       }
       len = strlen((char*)path);
-      for (;;) {
+      /* scan at most DIR_FILE_MAX entries per directory */
+      for(entrycnt=0; entrycnt < DIR_FILE_MAX; entrycnt++) {
 //        toggle_read_led();
         res = f_readdir(&dir, &fno);
         if (res != FR_OK || fno.fname[0] == 0) {
@@ -140,17 +152,19 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
           break;
         }
         fn = *fno.lfname ? fno.lfname : fno.fname;
-        if ((*fn == '.') || !(memcmp(fn, SYS_DIR_NAME, sizeof(SYS_DIR_NAME)))) continue;
+        if ((*fn == '.') || !(strncasecmp(fn, SYS_DIR_NAME, sizeof(SYS_DIR_NAME)))) continue;
         if (fno.fattrib & AM_DIR) {
           depth++;
           if(depth < FS_MAX_DEPTH) {
             numentries++;
-            if(pass) {
+            if(pass && mkdb) {
               path[len]='/';
               strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
+              uint16_t pathlen = 0;
+              uint32_t old_db_tgt = 0;
               if(mkdb) {
-                uint16_t pathlen = strlen(path);
-//                printf("d=%d Saving %lx to Address %lx  [dir]\n", depth, db_tgt, dir_tgt);
+                pathlen = strlen(path);
+                DBG_FS printf("d=%d Saving %lx to Address %lx  [dir]\n", depth, db_tgt, dir_tgt);
                 /* save element:
                    - path name
                    - pointer to sub dir structure */
@@ -160,22 +174,31 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
                   db_tgt += 0x00010000;
                   printf("new=%lx\n", db_tgt);
                 }
-//                printf("    Saving dir descriptor to %lx tgt=%lx, path=%s\n", db_tgt, next_subdir_tgt, path);
                 /* write element pointer to current dir structure */
                 sram_writelong((db_tgt-SRAM_MENU_ADDR)|((uint32_t)0x80<<24), dir_tgt);
                 /* save element:
                    - path name
-                   - pointer to sub dir structure */
-                sram_writelong((next_subdir_tgt-SRAM_MENU_ADDR), db_tgt);
-                sram_writebyte(len+1, db_tgt+sizeof(next_subdir_tgt));
-                sram_writeblock(path, db_tgt+sizeof(next_subdir_tgt)+sizeof(len), pathlen);
-                sram_writeblock("/\0", db_tgt + sizeof(next_subdir_tgt) + sizeof(len) + pathlen, 2);
+                   - pointer to sub dir structure
+                   moved below */
+                old_db_tgt = db_tgt;
                 db_tgt += sizeof(next_subdir_tgt) + sizeof(len) + pathlen + 2;
               }
               parent_tgt = this_dir_tgt;
-              scan_dir(path, &fno, mkdb, next_subdir_tgt);
+              /* scan subdir before writing current dir element to account for bank switches */
+              uint32_t corrected_subdir_tgt = scan_dir(path, &fno, mkdb, next_subdir_tgt);
+              if(mkdb) {
+                DBG_FS printf("    Saving dir descriptor to %lx tgt=%lx, path=%s\n", old_db_tgt, corrected_subdir_tgt, path);
+                sram_writelong((corrected_subdir_tgt-SRAM_MENU_ADDR), old_db_tgt);
+                sram_writebyte(len+1, old_db_tgt+sizeof(next_subdir_tgt));
+                sram_writeblock(path, old_db_tgt+sizeof(next_subdir_tgt)+sizeof(len), pathlen);
+                sram_writeblock("/\0", old_db_tgt + sizeof(next_subdir_tgt) + sizeof(len) + pathlen, 2);
+              }
               dir_tgt += 4;
               was_empty = 0;
+            } else if(!mkdb) {
+              path[len]='/';
+              strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
+              scan_dir(path, &fno, mkdb, next_subdir_tgt);
             }
           }
           depth--;
@@ -183,10 +206,10 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
         } else {
           SNES_FTYPE type = determine_filetype((char*)fn);
           if(type != TYPE_UNKNOWN) {
-            num_files_total++;
             numentries++;
             if(pass) {
               if(mkdb) {
+                num_files_total++;
 /*                snes_romprops_t romprops; */
                 path[len]='/';
                 strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
@@ -194,13 +217,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
                 switch(type) {
                   case TYPE_IPS:
                   case TYPE_SMC:
-/*                    file_open_by_filinfo(&fno);
-                    if(file_res){
-                      printf("ZOMG NOOOO %d\n", file_res);
-                    }
-                    smc_id(&romprops);
-                    file_close(); */
-
+                  case TYPE_SPC:
                     /* write element pointer to current dir structure */
                     DBG_FS printf("d=%d Saving %lX to Address %lX  [file %s]\n", depth, db_tgt, dir_tgt, path);
                     if((db_tgt&0xffff) > ((0x10000-(sizeof(len) + pathlen + sizeof(buf)-1 + 1))&0xffff)) {
@@ -234,19 +251,19 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
                   default:
                    break;
                 }
-                path[len]=0;
+                path[len] = 0;
 /*              printf("%s ", path);
                 _delay_ms(30); */
               }
             } else {
               TCHAR* fn2 = fn;
+              fncrc = 0;
               while(*fn2 != 0) {
-                crc += crc32_update(crc, *((unsigned char*)fn2++));
+                fncrc += crc_xmodem_update(fncrc, *((unsigned char*)fn2++));
               }
+              crc += fncrc;
             }
           }
-/*        printf("%s/%s\n", path, fn);
-          _delay_ms(50); */
         }
       }
     } else uart_putc(0x30+res);
@@ -256,7 +273,8 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
   sram_writelong(dir_end, SRAM_DB_ADDR+8);
   sram_writeshort(num_files_total, SRAM_DB_ADDR+12);
   sram_writeshort(num_dirs_total, SRAM_DB_ADDR+14);
-  return crc;
+  if(depth==0) return crc;
+  else return switched_dir_tgt;
 }
 
 
@@ -271,18 +289,14 @@ SNES_FTYPE determine_filetype(char* filename) {
     ) {
     return TYPE_SMC;
   }
-  if(  (!strcasecmp(ext+1, "IPS"))
+/*  if(  (!strcasecmp(ext+1, "IPS"))
      ||(!strcasecmp(ext+1, "UPS"))
     ) {
     return TYPE_IPS;
-  }
-  /* later
-  if(!strcasecmp_P(ext+1, PSTR("SRM"))) {
-    return TYPE_SRM;
-  }
-  if(!strcasecmp_P(ext+1, PSTR("SPC"))) {
-    return TYPE_SPC;
   }*/
+  if(!strcasecmp(ext+1, "SPC")) {
+    return TYPE_SPC;
+  }
   return TYPE_UNKNOWN;
 }
 

src/filetypes.h

@@ -36,7 +36,7 @@
 #include "ff.h"
 
 #define FS_MAX_DEPTH	(10)
-#define SYS_DIR_NAME	((const uint8_t*)"sd2snes")
+#define SYS_DIR_NAME	((const char*)"sd2snes")
 typedef enum {
   TYPE_UNKNOWN = 0, /* 0 */
   TYPE_SMC,         /* 1 */

src/fpga.c

@@ -119,17 +119,17 @@ if(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) {
       led_panic();
     }
     LPC_GPIO2->FIOMASK1 = ~(BV(0));
-    //uart_putc('p');
+    uart_putc('p');
 
 
     /* open configware file */
     file_open(filename, FA_READ);
     if(file_res) {
-      //uart_putc('?');
-      //uart_putc(0x30+file_res);
+      uart_putc('?');
+      uart_putc(0x30+file_res);
       return;
     }
-    //uart_putc('C');
+    uart_putc('C');
 
     for (;;) {
       data = rle_file_getc();
@@ -137,16 +137,16 @@ if(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) {
       if (file_status || file_res) break;   /* error or eof */
       FPGA_SEND_BYTE_SERIAL(data);
     }
-    //uart_putc('c');
+    uart_putc('c');
     file_close();
-    printf("%s: %d bytes programmed\n", __func__, i);
+    printf("fpga_pgm: %d bytes programmed\n", i);
     delay_ms(1);
   } while (!fpga_get_done() && retries--);
   if(!fpga_get_done()) {
     printf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
     led_panic();
   }
-  printf("%s: FPGA configured\n", __func__);
+  printf("FPGA configured\n");
   fpga_postinit();
 }
 
@@ -160,7 +160,7 @@ void fpga_rompgm() {
     i=0;
     timeout = getticks() + 100;
     fpga_set_prog_b(0);
-    //uart_putc('P');
+    uart_putc('P');
     fpga_set_prog_b(1);
     while(!fpga_get_initb()){
       if(getticks() > timeout) {
@@ -173,26 +173,26 @@ void fpga_rompgm() {
       led_panic();
     }
     LPC_GPIO2->FIOMASK1 = ~(BV(0));
-    //uart_putc('p');
+    uart_putc('p');
 
     /* open configware file */
     rle_mem_init(cfgware, sizeof(cfgware));
-    //printf("sizeof(cfgware) = %d\n", sizeof(cfgware));
+    printf("sizeof(cfgware) = %d\n", sizeof(cfgware));
     for (;;) {
       data = rle_mem_getc();
       if(rle_state) break;
       i++;
       FPGA_SEND_BYTE_SERIAL(data);
     }
-    //uart_putc('c');
-    printf("%s: %d bytes programmed\n", __func__, i);
+    uart_putc('c');
+    printf("fpga_pgm: %d bytes programmed\n", i);
     delay_ms(1);
   } while (!fpga_get_done() && retries--);
   if(!fpga_get_done()) {
     printf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
     led_panic();
   }
-  printf("%s: FPGA configured\n", __func__);
+  printf("FPGA configured\n");
   fpga_postinit();
 }
 

src/fpga_spi.c

@@ -143,7 +143,7 @@
 #include "sdnative.h"
 
 void fpga_spi_init(void) {
-  spi_init(SPI_SPEED_FAST);
+  spi_init();
   BITBAND(FPGA_MCU_RDY_REG->FIODIR, FPGA_MCU_RDY_BIT) = 0;
 }
 
@@ -199,7 +199,6 @@ void set_mapper(uint8_t val) {
 uint8_t fpga_test() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF0); /* TEST */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint8_t result = FPGA_RX_BYTE();
   FPGA_DESELECT();
   return result;
@@ -208,7 +207,6 @@ uint8_t fpga_test() {
 uint16_t fpga_status() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF1); /* STATUS */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint16_t result = (FPGA_RX_BYTE()) << 8;
   result |= FPGA_RX_BYTE();
   FPGA_DESELECT();
@@ -237,12 +235,12 @@ void fpga_sddma(uint8_t tgt, uint8_t partial) {
   FPGA_DESELECT();
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF1); /* STATUS */
-  FPGA_TX_BYTE(0x00); /* dummy */
   DBG_SD printf("FPGA DMA request sent, wait for completion...");
   while((status=FPGA_RX_BYTE()) & 0x80) {
     FPGA_RX_BYTE(); /* eat the 2nd status byte */
     test++;
   }
+
   DBG_SD printf("...complete\n");
   FPGA_DESELECT();
 //  if(test<5)printf("loopy: %ld %02x\n", test, status);
@@ -302,7 +300,6 @@ void set_msu_status(uint8_t set, uint8_t reset) {
 uint8_t get_msu_volume() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF4); /* MSU_VOLUME */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint8_t result = FPGA_RX_BYTE();
   FPGA_DESELECT();
   return result;
@@ -311,7 +308,6 @@ uint8_t get_msu_volume() {
 uint16_t get_msu_track() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF3); /* MSU_TRACK */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint16_t result = (FPGA_RX_BYTE()) << 8;
   result |= FPGA_RX_BYTE();
   FPGA_DESELECT();
@@ -321,7 +317,6 @@ uint16_t get_msu_track() {
 uint32_t get_msu_offset() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF2); /* MSU_OFFSET */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint32_t result = (FPGA_RX_BYTE()) << 24;
   result |= (FPGA_RX_BYTE()) << 16;
   result |= (FPGA_RX_BYTE()) << 8;
@@ -333,8 +328,7 @@ uint32_t get_msu_offset() {
 uint32_t get_snes_sysclk() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xFE); /* GET_SYSCLK */
-  FPGA_TX_BYTE(0x00); /* dummy */
-  FPGA_TX_BYTE(0x00); /* dummy */
+  FPGA_TX_BYTE(0x00); /* dummy (copy current sysclk count to register) */
   uint32_t result = (FPGA_RX_BYTE()) << 24;
   result |= (FPGA_RX_BYTE()) << 16;
   result |= (FPGA_RX_BYTE()) << 8;

src/fpga_spi.h

@@ -47,9 +47,6 @@
 #define FPGA_TX_BLOCK(x,y) spi_tx_block(x,y)
 #define FPGA_RX_BLOCK(x,y) spi_rx_block(x,y)
 
-#define FPGA_SPI_FAST()    spi_set_speed(SPI_SPEED_FPGA_FAST)
-#define FPGA_SPI_SLOW()    spi_set_speed(SPI_SPEED_FPGA_SLOW)
-
 #define FEAT_213F          (1 << 4)
 #define FEAT_MSU1          (1 << 3)
 #define FEAT_SRTC          (1 << 2)

src/main.c

@@ -53,356 +53,296 @@ enum system_states {
   SYS_LAST_STATUS = 1
 };
 
-int main(void)
-{
-   /* Start by initial configuration, needed in all cases */
-   LPC_GPIO2->FIODIR = BV(4) | BV(5);
-   LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
-   BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
-   LPC_GPIO0->FIODIR = BV(16);
+int main(void) {
+  LPC_GPIO2->FIODIR = BV(4) | BV(5);
+  LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
+  BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
+  LPC_GPIO0->FIODIR = BV(16);
 
-   /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */
-   LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */
-                       | BV(3) | BV(5);                    /* SSP0 (FPGA) except SS */
-   LPC_PINCON->PINSEL0 = BV(31);                            /* SSP0 */
-   /*                      | BV(13) | BV(15) | BV(17) | BV(19)  SSP1 (SD) */
+ /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */
+  LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */
+                      | BV(3) | BV(5);                    /* SSP0 (FPGA) except SS */
+  LPC_PINCON->PINSEL0 = BV(31);                            /* SSP0 */
+/*                      | BV(13) | BV(15) | BV(17) | BV(19)  SSP1 (SD) */
 
-   /* pull-down CIC data lines */
-   LPC_PINCON->PINMODE0 = BV(0) | BV(1) | BV(2) | BV(3);
+ /* pull-down CIC data lines */
+  LPC_PINCON->PINMODE0 = BV(0) | BV(1) | BV(2) | BV(3);
 
-   clock_disconnect();
-   /* First init all SNES functions */
-   snes_init();
-   snes_reset(1); /* Maintain RESET UP, to prevent SNES to start */
+  clock_disconnect();
+  snes_init();
+  snes_reset(1);
+  power_init();
+  timer_init();
+  uart_init();
+  fpga_spi_init();
+  spi_preinit();
+  led_init();
+ /* do this last because the peripheral init()s change PCLK dividers */
+  clock_init();
+  LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
+led_pwm();
+  sdn_init();
+  printf("\n\nsd2snes mk.2\n============\nfw ver.: " CONFIG_VERSION "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
+printf("PCONP=%lx\n", LPC_SC->PCONP);
 
-   /* Init all other parts */
-   power_init();
-   timer_init();
-   uart_init();
-   fpga_spi_init();
-   spi_preinit();
-   led_init();
-
-   /* do this last because the peripheral init()s change PCLK dividers */
-   clock_init();
-
-   LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
-   led_pwm();
-   sdn_init();
-
-   /* Banner */
-   printf("\n\nsd2snes mk.2\n============\nfw ver.: " CONFIG_VERSION "\nfwver: %d\ncpu clock: %d Hz\n", CONFIG_FWVER, CONFIG_CPU_FREQUENCY);
-   printf("PCONP=%lx\n", LPC_SC->PCONP);
-
-   file_init();
-   cic_init(0);
-
-   /* FPGA Initialisation */
-   /* setup timer (fpga clk) */
-   LPC_TIM3->CTCR = 0;
-   LPC_TIM3->EMR  = EMC0TOGGLE;
-   LPC_TIM3->MCR  = MR0R;
-   LPC_TIM3->MR0  = 1;
-   LPC_TIM3->TCR  = 1;
-   fpga_init();
-   fpga_rompgm();
-
-   sram_writebyte(0, SRAM_CMD_ADDR);
-
-   /* Should test SRAM here */
- 
-
-   while(1)
-   {
-      if(disk_state == DISK_CHANGED)
-      {
-         sdn_init();
-         newcard = 1;
-      }
-
-      load_bootrle(SRAM_MENU_ADDR);
-      set_saveram_mask(0x1fff);
-      set_rom_mask(0x3fffff);
-      set_mapper(0x7);
-      
-      /* Unlock SNES */
-      snes_reset(0);
-      
-      /* Check CIC status */
-      while(get_cic_state() == CIC_FAIL)
-      {
-         rdyled(0);
-         readled(0);
-         writeled(0);
-         delay_ms(500);
-         rdyled(1);
-         readled(1);
-         writeled(1);
-         delay_ms(500);
-      }
-
-      fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
-      sram_memtest();
-      
-      /* some sanity checks */
-      uint8_t card_go = 0;
-      while(!card_go)
-      {
-         if(disk_status(0) & (STA_NOINIT|STA_NODISK))
-         {
-	         snes_bootprint("        No SD Card found!       \0");
-      	   while(disk_status(0) & (STA_NOINIT|STA_NODISK));
-      	   delay_ms(200);
-         }
-         file_open((uint8_t*)"/sd2snes/menu.bin", FA_READ);
-      
-         if(file_status != FILE_OK)
-         {
-         	snes_bootprint("  /sd2snes/menu.bin not found!  \0");
-         	while(disk_status(0) == RES_OK);
-         } 
-         else
-         {
-	         card_go = 1;
-         }
-         file_close();
-      }
-      snes_bootprint("           Loading ...          \0");
-      if(get_cic_state() == CIC_PAIR)
-      {
-         printf("PAIR MODE ENGAGED!\n");
-         cic_pair(CIC_NTSC, CIC_NTSC);
-      }
-      
-      rdyled(1);
+  file_init();
+  cic_init(0);
+/* setup timer (fpga clk) */
+  LPC_TIM3->CTCR=0;
+  LPC_TIM3->EMR=EMC0TOGGLE;
+  LPC_TIM3->MCR=MR0R;
+  LPC_TIM3->MR0=1;
+  LPC_TIM3->TCR=1;
+  fpga_init();
+  fpga_rompgm();
+  sram_writebyte(0, SRAM_CMD_ADDR);
+  while(1) {
+    if(disk_state == DISK_CHANGED) {
+      sdn_init();
+      newcard = 1;
+    }
+    load_bootrle(SRAM_MENU_ADDR);
+    set_saveram_mask(0x1fff);
+    set_rom_mask(0x3fffff);
+    set_mapper(0x7);
+    snes_reset(0);
+    while(get_cic_state() == CIC_FAIL) {
+      rdyled(0);
       readled(0);
       writeled(0);
-
-      cfg_load();
-      cfg_save();
-      
-      sram_writebyte(cfg_is_last_game_valid(), SRAM_STATUS_ADDR+SYS_LAST_STATUS);
-      cfg_get_last_game(file_lfn);
-      sram_writeblock(strrchr((const char*)file_lfn, '/')+1, SRAM_LASTGAME_ADDR, 256);
-      
-      *fs_path=0;
-      uint32_t saved_dir_id;
-      get_db_id(&saved_dir_id);
-
-      uint32_t mem_dir_id = sram_readlong(SRAM_DIRID);
-      uint32_t mem_magic = sram_readlong(SRAM_SCRATCHPAD);
-      
-      printf("mem_magic=%lx mem_dir_id=%lx saved_dir_id=%lx\n", mem_magic, mem_dir_id, saved_dir_id);
-      
-      if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id) || (newcard))
-      {
-         newcard = 0;
-         /* generate fs footprint (interesting files only) */
-         uint32_t curr_dir_id = scan_dir(fs_path, NULL, 0, 0);
-         printf("curr dir id = %lx\n", curr_dir_id);
-         /* files changed or no database found? */
-         if((get_db_id(&saved_dir_id) != FR_OK) || saved_dir_id != curr_dir_id)
-         {
-	         /* rebuild database */
-	         printf("saved dir id = %lx\n", saved_dir_id);
-	         snes_bootprint("     rebuilding database ...    \0");
-	         curr_dir_id = scan_dir(fs_path, NULL, 1, 0);
-         	sram_writeblock(&curr_dir_id, SRAM_DB_ADDR, 4);
-         	uint32_t endaddr, direndaddr;
-         	sram_readblock(&endaddr, SRAM_DB_ADDR+4, 4);
-         	sram_readblock(&direndaddr, SRAM_DB_ADDR+8, 4);
-         	printf("endaddr: 0x%lX dirend: 0x%lX\n", endaddr, direndaddr);
-         	snes_bootprint("       sorting database ...     \0");
-         	sort_all_dir(direndaddr);
-         	printf("done\n");
-         	snes_bootprint("        saving database ...     \0");
-         	save_sram((uint8_t*)"/sd2snes/sd2snes.db", endaddr-SRAM_DB_ADDR, SRAM_DB_ADDR);
-         	save_sram((uint8_t*)"/sd2snes/sd2snes.dir", direndaddr-(SRAM_DIR_ADDR), SRAM_DIR_ADDR);
-         	printf("done\n");
-         }
-         else
-         {
-         	printf("saved dir id = %lx\n", saved_dir_id);
-         	printf("different card, consistent db, loading db...\n");
-         	load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
-         	load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
-         }
-      
-         sram_writelong(curr_dir_id, SRAM_DIRID);
-         sram_writelong(0x12345678, SRAM_SCRATCHPAD);
+      delay_ms(500);
+      rdyled(1);
+      readled(1);
+      writeled(1);
+      delay_ms(500);
+    }
+    /* some sanity checks */
+    uint8_t card_go = 0;
+    while(!card_go) {
+      if(disk_status(0) & (STA_NOINIT|STA_NODISK)) {
+	snes_bootprint("        No SD Card found!       \0");
+	while(disk_status(0) & (STA_NOINIT|STA_NODISK));
+	delay_ms(200);
       }
-      else
-      {
-         snes_bootprint("    same card, loading db...     \0");
-         printf("same card, loading db...\n");
-         load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
-         load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
+      file_open((uint8_t*)"/sd2snes/menu.bin", FA_READ);
+      if(file_status != FILE_OK) {
+	snes_bootprint("  /sd2snes/menu.bin not found!  \0");
+	while(disk_status(0) == RES_OK);
+      } else {
+	card_go = 1;
       }
+      file_close();
+    }
+    snes_bootprint("           Loading ...          \0");
+    if(get_cic_state() == CIC_PAIR) {
+      printf("PAIR MODE ENGAGED!\n");
+      cic_pair(CIC_NTSC, CIC_NTSC);
+    }
+    rdyled(1);
+    readled(0);
+    writeled(0);
 
-#if 1
-      cli_loop();
-#endif
+    cfg_load();
+    cfg_save();
+    sram_writebyte(cfg_is_last_game_valid(), SRAM_STATUS_ADDR+SYS_LAST_STATUS);
+    cfg_get_last_game(file_lfn);
+    sram_writeblock(strrchr((const char*)file_lfn, '/')+1, SRAM_LASTGAME_ADDR, 256);
+    *fs_path=0;
+    uint32_t saved_dir_id;
+    get_db_id(&saved_dir_id);
 
-      /* load menu */
+    uint32_t mem_dir_id = sram_readlong(SRAM_DIRID);
+    uint32_t mem_magic = sram_readlong(SRAM_SCRATCHPAD);
+    printf("mem_magic=%lx mem_dir_id=%lx saved_dir_id=%lx\n", mem_magic, mem_dir_id, saved_dir_id);
+    if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id) || (newcard)) {
+      newcard = 0;
+      /* generate fs footprint (interesting files only) */
+      uint32_t curr_dir_id = scan_dir(fs_path, NULL, 0, 0);
+      printf("curr dir id = %lx\n", curr_dir_id);
+      /* files changed or no database found? */
+      if((get_db_id(&saved_dir_id) != FR_OK)
+	|| saved_dir_id != curr_dir_id) {
+	/* rebuild database */
+	printf("saved dir id = %lx\n", saved_dir_id);
+	printf("rebuilding database...");
+	snes_bootprint("     rebuilding database ...    \0");
+	curr_dir_id = scan_dir(fs_path, NULL, 1, 0);
+	sram_writeblock(&curr_dir_id, SRAM_DB_ADDR, 4);
+	uint32_t endaddr, direndaddr;
+	sram_readblock(&endaddr, SRAM_DB_ADDR+4, 4);
+	sram_readblock(&direndaddr, SRAM_DB_ADDR+8, 4);
+	printf("%lx %lx\n", endaddr, direndaddr);
+	printf("sorting database...");
+	snes_bootprint("       sorting database ...     \0");
+	sort_all_dir(direndaddr);
+	printf("done\n");
+	snes_bootprint("        saving database ...     \0");
+	save_sram((uint8_t*)"/sd2snes/sd2snes.db", endaddr-SRAM_DB_ADDR, SRAM_DB_ADDR);
+	save_sram((uint8_t*)"/sd2snes/sd2snes.dir", direndaddr-(SRAM_DIR_ADDR), SRAM_DIR_ADDR);
+        fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
+	printf("done\n");
+      } else {
+	printf("saved dir id = %lx\n", saved_dir_id);
+	printf("different card, consistent db, loading db...\n");
+        fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
+	load_sram_offload((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
+	load_sram_offload((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
+      }
+      sram_writelong(curr_dir_id, SRAM_DIRID);
+      sram_writelong(0x12345678, SRAM_SCRATCHPAD);
+    } else {
+      snes_bootprint("    same card, loading db...     \0");
+      printf("same card, loading db...\n");
       fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
-      fpga_dspx_reset(1);
+      load_sram_offload((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
+      load_sram_offload((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
+    }
+    /* cli_loop(); */
+    /* load menu */
 
-      uart_putc('(');
-      load_rom((uint8_t*)"/sd2snes/menu.bin", SRAM_MENU_ADDR, 0);
-      /* force memory size + mapper */
-      set_rom_mask(0x3fffff);
-      set_mapper(0x7);
-      uart_putc(')');
-      uart_putcrlf();
+    fpga_dspx_reset(1);
+    uart_putc('(');
+    load_rom((uint8_t*)"/sd2snes/menu.bin", SRAM_MENU_ADDR, 0);
+    /* force memory size + mapper */
+    set_rom_mask(0x3fffff);
+    set_mapper(0x7);
+    uart_putc(')');
+    uart_putcrlf();
 
-      sram_writebyte(0, SRAM_CMD_ADDR);
+    sram_writebyte(0, SRAM_CMD_ADDR);
 
-      if((rtc_state = rtc_isvalid()) != RTC_OK)
-      {
-         printf("RTC invalid!\n");
-         sram_writebyte(0xff, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
-         set_bcdtime(0x20110401000000LL);
-         set_fpga_time(0x20110401000000LL);
-         invalidate_rtc();
-      }
-      else
-      {
-         printf("RTC valid!\n");
-         sram_writebyte(0x00, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
-         set_fpga_time(get_bcdtime());
-      }
-      sram_memset(SRAM_SYSINFO_ADDR, 13*40, 0x20);
-      printf("SNES GO!\n");
-      snes_reset(1);
-      delay_ms(1);
-      snes_reset(0);
-
-      uint8_t cmd = 0;
-      uint64_t btime = 0;
-      uint32_t filesize=0;
-      sram_writebyte(32, SRAM_CMD_ADDR);
-      
-      printf("test sram\n");
-      while(!sram_reliable()) cli_entrycheck();
-      
-      printf("ok\n");
+    if((rtc_state = rtc_isvalid()) != RTC_OK) {
+      printf("RTC invalid!\n");
+      sram_writebyte(0xff, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
+      set_bcdtime(0x20120701000000LL);
+      set_fpga_time(0x20120701000000LL);
+      invalidate_rtc();
+    } else {
+      printf("RTC valid!\n");
+      sram_writebyte(0x00, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
+      set_fpga_time(get_bcdtime());
+    }
+    sram_memset(SRAM_SYSINFO_ADDR, 13*40, 0x20);
+    printf("SNES GO!\n");
+    snes_reset(1);
+    fpga_reset_srtc_state();
+    delay_ms(SNES_RESET_PULSELEN_MS);
+    sram_writebyte(32, SRAM_CMD_ADDR);
+    snes_reset(0);
 
+    uint8_t cmd = 0;
+    uint64_t btime = 0;
+    uint32_t filesize=0;
+    printf("test sram\n");
+    while(!sram_reliable()) cli_entrycheck();
+    printf("ok\n");
 //while(1) {
 //  delay_ms(1000);
 //  printf("Estimated SNES master clock: %ld Hz\n", get_snes_sysclk());
 //}
   //sram_hexdump(SRAM_DB_ADDR, 0x200);
   //sram_hexdump(SRAM_MENU_ADDR, 0x400);
-
-      while(!cmd)
-      {
-         cmd=menu_main_loop();
-         printf("cmd: %d\n", cmd);
-         uart_putc('-');
-         switch(cmd)
-         {
-	      case SNES_CMD_LOADROM:
-	         get_selected_name(file_lfn);
-	         printf("Selected name: %s\n", file_lfn);
-            cfg_save_last_game(file_lfn);
-            cfg_set_last_game_valid(1);
-            cfg_save();
-	         filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
-	         break;
-
-	      case SNES_CMD_SETRTC:
-            /* get time from RAM */
-            btime = sram_gettime(SRAM_PARAM_ADDR);
-            /* set RTC */
-            set_bcdtime(btime);
-            set_fpga_time(btime);
-	         cmd=0; /* stay in menu loop */
-	         break;
-
-         case SNES_CMD_SYSINFO:
-            /* go to sysinfo loop */
-            sysinfo_loop();
-            cmd=0; /* stay in menu loop */
-            break;
-
-         case SNES_CMD_LOADLAST:
-            cfg_get_last_game(file_lfn);
-            printf("Selected name: %s\n", file_lfn);
-            filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
-            break;
-
-	      default:
-	         printf("unknown cmd: %d\n", cmd);
-	         cmd=0; /* unknown cmd: stay in loop */
-	         break;
-         }
+    while(!cmd) {
+      cmd=menu_main_loop();
+      printf("cmd: %d\n", cmd);
+      uart_putc('-');
+      switch(cmd) {
+	case SNES_CMD_LOADROM:
+	  get_selected_name(file_lfn);
+	  printf("Selected name: %s\n", file_lfn);
+          cfg_save_last_game(file_lfn);
+          cfg_set_last_game_valid(1);
+          cfg_save();
+	  filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
+	  break;
+	case SNES_CMD_SETRTC:
+          /* get time from RAM */
+          btime = sram_gettime(SRAM_PARAM_ADDR);
+          /* set RTC */
+          set_bcdtime(btime);
+          set_fpga_time(btime);
+	  cmd=0; /* stay in menu loop */
+	  break;
+        case SNES_CMD_SYSINFO:
+          /* go to sysinfo loop */
+          sysinfo_loop();
+          cmd=0; /* stay in menu loop */
+          break;
+        case SNES_CMD_LOADSPC:
+          /* load SPC file */
+          get_selected_name(file_lfn);
+          printf("Selected name: %s\n", file_lfn);
+          filesize = load_spc(file_lfn, SRAM_SPC_DATA_ADDR, SRAM_SPC_HEADER_ADDR);
+          cmd=0; /* stay in menu loop */
+          break;
+        case SNES_CMD_RESET:
+          /* process RESET request from SNES */
+          printf("RESET requested by SNES\n");
+          snes_reset_pulse();
+          cmd=0; /* stay in menu loop */
+          break;
+        case SNES_CMD_LOADLAST:
+          cfg_get_last_game(file_lfn);
+          printf("Selected name: %s\n", file_lfn);
+          filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
+          break;
+	default:
+	  printf("unknown cmd: %d\n", cmd);
+	  cmd=0; /* unknown cmd: stay in loop */
+	  break;
       }
-      
-      printf("cmd was %x, going to snes main loop\n", cmd);
+    }
+    printf("cmd was %x, going to snes main loop\n", cmd);
 
-      if(romprops.has_msu1 && msu1_loop())
-      {
-         prepare_reset();
-         continue;
-      }
+    if(romprops.has_msu1 && msu1_loop()) {
+      prepare_reset();
+      continue;
+    }
 
-      cmd=0;
-      uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
-      uint16_t reset_count=0;
-      while(fpga_test() == FPGA_TEST_TOKEN)
-      {
-         cli_entrycheck();
-         sleep_ms(250);
-         sram_reliable();
-         printf("%s ", get_cic_statename(get_cic_state()));
-         if(reset_changed)
-         {
-            printf("reset\n");
-            reset_changed = 0;
-            fpga_reset_srtc_state();
-         }
-         snes_reset_now=get_snes_reset();
-         if(snes_reset_now)
-         {
-	         if(!snes_reset_prev)
-	         {
-	            printf("RESET BUTTON DOWN\n");
-	            snes_reset_state=1;
-	            reset_count=0;
-	         }
-         }
-         else
-         {
-	         if(snes_reset_prev)
-	         {
-	            printf("RESET BUTTON UP\n");
-	            snes_reset_state=0;
-	         }
-         }
-         if(snes_reset_state)
-         {
-         	reset_count++;
-         }
-         else
-         {
-	         sram_reliable();
-	         snes_main_loop();
-         }
-         if(reset_count>4)
-         {
-	         reset_count=0;
-            prepare_reset();
-	         break;
-         }
-         snes_reset_prev = snes_reset_now;
+    cmd=0;
+    uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
+    uint16_t reset_count=0;
+    while(fpga_test() == FPGA_TEST_TOKEN) {
+      cli_entrycheck();
+      sleep_ms(250);
+      sram_reliable();
+      printf("%s ", get_cic_statename(get_cic_state()));
+      if(reset_changed) {
+        printf("reset\n");
+        reset_changed = 0;
+        fpga_reset_srtc_state();
       }
-
-      /* fpga test fail: panic */
-      if(fpga_test() != FPGA_TEST_TOKEN)
-      {
-         led_panic();
+      snes_reset_now=get_snes_reset();
+      if(snes_reset_now) {
+	if(!snes_reset_prev) {
+	  printf("RESET BUTTON DOWN\n");
+	  snes_reset_state=1;
+	  reset_count=0;
+	}
+      } else {
+	if(snes_reset_prev) {
+	  printf("RESET BUTTON UP\n");
+	  snes_reset_state=0;
+	}
       }
-      /* else reset */
-   }
+      if(snes_reset_state) {
+	reset_count++;
+      } else {
+	sram_reliable();
+	snes_main_loop();
+      }
+      if(reset_count>4) {
+	reset_count=0;
+        prepare_reset();
+	break;
+      }
+      snes_reset_prev = snes_reset_now;
+    }
+    /* fpga test fail: panic */
+    if(fpga_test() != FPGA_TEST_TOKEN){
+      led_panic();
+    }
+    /* else reset */
+  }
 }
 

src/memory.c

@@ -182,7 +182,7 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
   UINT count=0;
   tick_t ticksstart, ticks_total=0;
   ticksstart=getticks();
-  printf("Loading: %s\n", filename);
+  printf("%s\n", filename);
   file_open(filename, FA_READ);
   if(file_res) {
     uart_putc('?');
@@ -199,6 +199,8 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
   }
   set_mcu_addr(base_addr);
   file_open(filename, FA_READ);
+  ff_sd_offload=1;
+  sd_offload_tgt=0;
   f_lseek(&file_handle, romprops.offset);
   for(;;) {
     ff_sd_offload=1;
@@ -218,6 +220,8 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
     printf("BSX Flash cart image\n");
     printf("attempting to load BSX BIOS /sd2snes/bsxbios.bin...\n");
     load_sram_offload((uint8_t*)"/sd2snes/bsxbios.bin", 0x800000);
+    printf("attempting to load BS data file /sd2snes/bsxpage.bin...\n");
+    load_sram_offload((uint8_t*)"/sd2snes/bsxpage.bin", 0x900000);
     printf("Type: %02x\n", romprops.header.destcode);
     set_bsx_regs(0xc0, 0x3f);
     uint16_t rombase;
@@ -288,15 +292,90 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
 
   if(flags & LOADROM_WITH_RESET) {
     fpga_dspx_reset(1);
-    snes_reset(1);
-    delay_ms(10);
-    snes_reset(0);
+    snes_reset_pulse();
     fpga_dspx_reset(0);
   }
 
   return (uint32_t)filesize;
 }
 
+uint32_t load_spc(uint8_t* filename, uint32_t spc_data_addr, uint32_t spc_header_addr) {
+  DWORD filesize;
+  UINT bytes_read;
+  uint8_t data;
+  UINT j;
+
+  printf("%s\n", filename);
+
+  file_open(filename, FA_READ); /* Open SPC file */
+  if(file_res) return 0;
+  filesize = file_handle.fsize;
+  if (filesize < 65920) { /*  At this point, we care about filesize only */
+    file_close();         /* since SNES decides if it is an SPC file */
+    sram_writebyte(0, spc_header_addr);	/* If file is too small, destroy previous SPC header */
+    return 0;
+  }
+
+  set_mcu_addr(spc_data_addr);
+  f_lseek(&file_handle, 0x100L); /* Load 64K data segment */
+
+  for(;;) {
+    bytes_read = file_read();
+    if (file_res || !bytes_read) break;
+    FPGA_SELECT();
+    FPGA_TX_BYTE(0x98);
+    for(j=0; j<bytes_read; j++) {
+      FPGA_TX_BYTE(file_buf[j]);
+      FPGA_WAIT_RDY();
+    }
+    FPGA_DESELECT();
+  }
+
+  file_close();
+  file_open(filename, FA_READ); /* Reopen SPC file to reset file_getc state*/
+
+  set_mcu_addr(spc_header_addr);
+  f_lseek(&file_handle, 0x0L); /* Load 256 bytes header */
+
+  FPGA_SELECT();
+  FPGA_TX_BYTE(0x98);
+  for (j = 0; j < 256; j++) {
+    data = file_getc();
+    FPGA_TX_BYTE(data);
+    FPGA_WAIT_RDY();
+  }
+  FPGA_DESELECT();
+
+  file_close();
+  file_open(filename, FA_READ); /* Reopen SPC file to reset file_getc state*/
+
+  set_mcu_addr(spc_header_addr+0x100);
+  f_lseek(&file_handle, 0x10100L); /* Load 128 DSP registers */
+
+  FPGA_SELECT();
+  FPGA_TX_BYTE(0x98);
+  for (j = 0; j < 128; j++) {
+    data = file_getc();
+    FPGA_TX_BYTE(data);
+    FPGA_WAIT_RDY();
+  }
+  FPGA_DESELECT();
+  file_close(); /* Done ! */
+
+  /* clear echo buffer to avoid artifacts */
+  uint8_t esa = sram_readbyte(spc_header_addr+0x100+0x6d);
+  uint8_t edl = sram_readbyte(spc_header_addr+0x100+0x7d);
+  uint8_t flg = sram_readbyte(spc_header_addr+0x100+0x6c);
+  if(!(flg & 0x20) && (edl & 0x0f)) {
+    int echo_start = esa << 8;
+    int echo_length = (edl & 0x0f) << 11;
+    printf("clearing echo buffer %04x-%04x...\n", echo_start, echo_start+echo_length-1);
+    sram_memset(spc_data_addr+echo_start, echo_length, 0);
+  }
+
+  return (uint32_t)filesize;
+}
+
 uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr) {
   set_mcu_addr(base_addr);
   UINT bytes_read;
@@ -470,99 +549,6 @@ void sram_memset(uint32_t base_addr, uint32_t len, uint8_t val) {
   FPGA_DESELECT();
 }
 
-/* memtest functions */
-uint8_t memtest_checkvalue(uint8_t value)
-{
-   uint8_t ret = 0;
-   uint32_t idx, lasterr = 0, errwas = 0, errcount = 0;
-   uint8_t data;
-   set_saveram_mask(0x0);
-   set_rom_mask(0x0);
-   printf("%s: Set memory to 0x%02X...\n", __func__, value);
-   sram_memset(0x00000, 0x1000000, value);
-   printf("Checking... [");
-   
-   set_mcu_addr(0x0);
-   
-   FPGA_SELECT();
-   FPGA_WAIT_RDY();
-   FPGA_TX_BYTE(0x88);
-   for(idx = 0; idx < 0x1000000; idx++)
-   {
-      FPGA_WAIT_RDY();
-      data = FPGA_RX_BYTE();
-      if ((idx % 0x100000) == 0)
-         uart_putc('.');
-
-      if ((idx % 0x10000) == 0)
-         toggle_read_led();
-
-      if (data != value)
-      {
-         //printf("%06x [%02x],", idx, data);
-         lasterr = idx;
-         errwas = data;
-         errcount++;
-         writeled(1);
-         ret = 0xFF;
-      }
-   }
-   printf("]\n");
-   if (errcount > 0)
-      printf("Found %d error(s) - last @ %x [%02x]\n", errcount, lasterr, errwas);
-
-   FPGA_DESELECT(); 
-   return ret;
-}
-
-uint8_t fpga_check(uint8_t value)
-{
-   uint8_t ret = 0, read;
-   FPGA_SELECT();
-   FPGA_WAIT_RDY();
-   FPGA_TX_BYTE(0xFF);
-   FPGA_TX_BYTE(value);
-   FPGA_TX_BYTE(value);
-   read = FPGA_RX_BYTE();
-   if (read != value)
-   {
-      printf("%02x != %02x!!\n", value, read);
-      ret = 0xFF;
-   }
-   FPGA_DESELECT();
-   return ret;
-}
-
-uint8_t sram_memtest(void)
-{
-   uint32_t ret;
-   printf("%s: Start memory test...\n", __func__);
-   writeled(0);
-   printf("Check FPGA Communication..\n");
-   printf("fpga_test   =   %02X\n", fpga_test());
-      
-   printf("fpga_status = %04X\n", fpga_status());
-   
-   ret  = fpga_check(0x00);
-   ret |= fpga_check(0xFF);
-   ret |= fpga_check(0xAA);
-   ret |= fpga_check(0x55);
-   if (ret != 0x00)
-   {
-      printf("Error communicating with FPGA...\n");
-      //return ret;
-   }
-    
-   
-    
-   ret  = memtest_checkvalue(0x00);
-   ret |= memtest_checkvalue(0xFF);
-   ret |= memtest_checkvalue(0xAA);
-   ret |= memtest_checkvalue(0x55);
-
-   return ret;
-}
-
 uint64_t sram_gettime(uint32_t base_addr) {
   set_mcu_addr(base_addr);
   FPGA_SELECT();

src/memory.h

@@ -33,15 +33,19 @@
 #define SRAM_ROM_ADDR           (0x000000L)
 #define SRAM_SAVE_ADDR          (0xE00000L)
 
-#define SRAM_MENU_ADDR          (0xE00000L)
-#define SRAM_DB_ADDR            (0xE40000L)
-#define SRAM_DIR_ADDR           (0xE10000L)
+#define SRAM_MENU_ADDR          (0xC00000L)
+#define SRAM_DIR_ADDR           (0xC10000L)
+#define SRAM_DB_ADDR            (0xC80000L)
+
+#define SRAM_SPC_DATA_ADDR      (0xFD0000L)
+#define SRAM_SPC_HEADER_ADDR    (0xFE0000L)
+
+#define SRAM_MENU_SAVE_ADDR     (0xFF0000L)
 #define SRAM_CMD_ADDR           (0xFF1000L)
 #define SRAM_PARAM_ADDR         (0xFF1004L)
 #define SRAM_STATUS_ADDR        (0xFF1100L)
 #define SRAM_SYSINFO_ADDR       (0xFF1200L)
 #define SRAM_LASTGAME_ADDR      (0xFF1420L)
-#define SRAM_MENU_SAVE_ADDR     (0xFF0000L)
 #define SRAM_SCRATCHPAD         (0xFFFF00L)
 #define SRAM_DIRID              (0xFFFFF0L)
 #define SRAM_RELIABILITY_SCORE  (0x100)
@@ -50,6 +54,7 @@
 #define LOADROM_WITH_RESET	(2)
 
 uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags);
+uint32_t load_spc(uint8_t* filename, uint32_t spc_data_addr, uint32_t spc_header_addr);
 uint32_t load_sram(uint8_t* filename, uint32_t base_addr);
 uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr);
 uint32_t load_sram_rle(uint8_t* filename, uint32_t base_addr);
@@ -71,6 +76,4 @@ uint8_t sram_reliable(void);
 void sram_memset(uint32_t base_addr, uint32_t len, uint8_t val);
 uint64_t sram_gettime(uint32_t base_addr);
 
-uint8_t sram_memtest(void);
-
 #endif

src/msu1.c

@@ -13,25 +13,132 @@
 #include "smc.h"
 
 FIL msufile;
+FRESULT msu_res;
 DWORD msu_cltbl[CLTBL_SIZE] IN_AHBRAM;
 DWORD pcm_cltbl[CLTBL_SIZE] IN_AHBRAM;
+UINT msu_audio_bytes_read = 1024;
+UINT msu_data_bytes_read = 1;
 
 extern snes_romprops_t romprops;
+uint32_t msu_loop_point = 0;
+uint32_t msu_page1_start = 0x0000;
+uint32_t msu_page2_start = 0x2000;
+uint32_t msu_page_size = 0x2000;
+uint16_t fpga_status_prev;
+uint16_t fpga_status_now;
+
+enum msu_reset_state { MSU_RESET_NONE = 0, MSU_RESET_SHORT, MSU_RESET_LONG };
+
+void prepare_audio_track(uint16_t msu_track) {
+  /* open file, fill buffer */
+  char suffix[11];
+  f_close(&file_handle);
+  snprintf(suffix, sizeof(suffix), "-%d.pcm", msu_track);
+  strcpy((char*)file_buf, (char*)file_lfn);
+  strcpy(strrchr((char*)file_buf, (int)'.'), suffix);
+  DBG_MSU1 printf("filename: %s\n", file_buf);
+  if(f_open(&file_handle, (const TCHAR*)file_buf, FA_READ) == FR_OK) {
+    file_handle.cltbl = pcm_cltbl;
+    pcm_cltbl[0] = CLTBL_SIZE;
+    f_lseek(&file_handle, CREATE_LINKMAP);
+    f_lseek(&file_handle, 4L);
+    f_read(&file_handle, &msu_loop_point, 4, &msu_audio_bytes_read);
+    DBG_MSU1 printf("loop point: %ld samples\n", msu_loop_point);
+    ff_sd_offload=1;
+    sd_offload_tgt=1;
+    f_lseek(&file_handle, 8L);
+    set_dac_addr(0);
+    dac_pause();
+    dac_reset();
+    ff_sd_offload=1;
+    sd_offload_tgt=1;
+    f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE, &msu_audio_bytes_read);
+    /* clear busy bit */
+    set_msu_status(0x00, 0x28); /* set no bits, reset audio_busy + audio_error */
+  } else {
+    f_close(&file_handle);
+    set_msu_status(0x08, 0x20); /* reset audio_busy, set audio_error */
+  }
+}
+
+void prepare_data(uint32_t msu_offset) {
+  DBG_MSU1 printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start);
+  if(   ((msu_offset < msu_page1_start)
+     || (msu_offset >= msu_page1_start + msu_page_size))
+     && ((msu_offset < msu_page2_start)
+     || (msu_offset >= msu_page2_start + msu_page_size))) {
+    DBG_MSU1 printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start,
+           msu_page1_start+msu_page_size-1, msu_page2_start, msu_page2_start+msu_page_size-1);
+    /* "cache miss" */
+    /* fill buffer */
+    set_msu_addr(0x0);
+    sd_offload_tgt=2;
+    ff_sd_offload=1;
+    msu_res = f_lseek(&msufile, msu_offset);
+    DBG_MSU1 printf("seek to %08lx, res = %d\n", msu_offset, msu_res);
+    sd_offload_tgt=2;
+    ff_sd_offload=1;
+    msu_res = f_read(&msufile, file_buf, 16384, &msu_data_bytes_read);
+    DBG_MSU1 printf("read res = %d\n", msu_res);
+    DBG_MSU1 printf("read %d bytes\n", msu_data_bytes_read);
+    msu_reset(0x0);
+    msu_page1_start = msu_offset;
+    msu_page2_start = msu_offset + msu_page_size;
+  } else {
+    if (msu_offset >= msu_page1_start && msu_offset <= msu_page1_start + msu_page_size) {
+      msu_reset(0x0000 + msu_offset - msu_page1_start);
+      DBG_MSU1 printf("inside page1, new offset: %08lx\n", 0x0000 + msu_offset-msu_page1_start);
+      if(!(msu_page2_start == msu_page1_start + msu_page_size)) {
+        set_msu_addr(0x2000);
+        sd_offload_tgt=2;
+        ff_sd_offload=1;
+        f_read(&msufile, file_buf, 8192, &msu_data_bytes_read);
+        DBG_MSU1 printf("next page dirty (was: %08lx), loaded page2 (start now: ", msu_page2_start);
+        msu_page2_start = msu_page1_start + msu_page_size;
+        DBG_MSU1 printf("%08lx)\n", msu_page2_start);
+      }
+    } else if (msu_offset >= msu_page2_start && msu_offset <= msu_page2_start + msu_page_size) {
+      DBG_MSU1 printf("inside page2, new offset: %08lx\n", 0x2000 + msu_offset-msu_page2_start);
+      msu_reset(0x2000 + msu_offset - msu_page2_start);
+      if(!(msu_page1_start == msu_page2_start + msu_page_size)) {
+        set_msu_addr(0x0);
+        sd_offload_tgt=2;
+        ff_sd_offload=1;
+        f_read(&msufile, file_buf, 8192, &msu_data_bytes_read);
+        DBG_MSU1 printf("next page dirty (was: %08lx), loaded page1 (start now: ", msu_page1_start);
+        msu_page1_start = msu_page2_start + msu_page_size;
+        DBG_MSU1 printf("%08lx)\n", msu_page1_start);
+      }
+    } else printf("!!!WATWATWAT!!!\n");
+  }
+  /* clear bank bit to mask bank reset artifact */
+  fpga_status_now &= ~0x2000;
+  fpga_status_prev &= ~0x2000;
+  /* clear busy bit */
+  set_msu_status(0x00, 0x10);
+}
 
 int msu1_check_reset(void) {
   static tick_t rising_ticks;
 
   static uint8_t resbutton=0, resbutton_prev=0;
+  int result = MSU_RESET_NONE;
   resbutton = get_snes_reset();
   if(resbutton && !resbutton_prev) { /* push */
     rising_ticks = getticks();
   } else if(resbutton && resbutton_prev) { /* hold */
     if(getticks() > rising_ticks + 99) {
-      return 1;
+      result = MSU_RESET_LONG;
     }
+  } else if(!resbutton && resbutton_prev) { /* release */
+    if(getticks() < rising_ticks + 99) {
+      result = MSU_RESET_SHORT;
+    }
+  } else {
+    result = MSU_RESET_NONE;
   }
   resbutton_prev = resbutton;
-  return 0;
+  return result;
 }
 
 int msu1_check(uint8_t* filename) {
@@ -54,23 +161,29 @@ int msu1_check(uint8_t* filename) {
 
 int msu1_loop() {
 /* it is assumed that the MSU file is already opened by calling msu1_check(). */
-  UINT bytes_read = 1024;
-  UINT bytes_read2 = 1;
-  FRESULT res;
   set_dac_vol(0x00);
   while(fpga_status() & 0x4000);
-  uint16_t fpga_status_prev = fpga_status();
-  uint16_t fpga_status_now = fpga_status();
   uint16_t dac_addr = 0;
   uint16_t msu_addr = 0;
   uint8_t msu_repeat = 0;
   uint16_t msu_track = 0;
   uint32_t msu_offset = 0;
-  uint32_t msu_loop_point = 0;
+  fpga_status_prev = fpga_status();
+  fpga_status_now = fpga_status();
+  int msu_res;
 
-  uint32_t msu_page1_start = 0x0000;
-  uint32_t msu_page2_start = 0x2000;
-  uint32_t msu_page_size = 0x2000;
+/*  set_msu_addr(0x0);
+  msu_reset(0x0);
+  ff_sd_offload=1;
+  sd_offload_tgt=2;
+  f_lseek(&msufile, 0L);
+  ff_sd_offload=1;
+  sd_offload_tgt=2;
+  f_read(&msufile, file_buf, 16384, &msu_data_bytes_read);
+*/
+  set_dac_addr(dac_addr);
+  dac_pause();
+  dac_reset();
 
   set_msu_addr(0x0);
   msu_reset(0x0);
@@ -79,13 +192,12 @@ int msu1_loop() {
   f_lseek(&msufile, 0L);
   ff_sd_offload=1;
   sd_offload_tgt=2;
-  f_read(&msufile, file_buf, 16384, &bytes_read2);
+  f_read(&msufile, file_buf, 16384, &msu_data_bytes_read);
 
-  set_dac_addr(dac_addr);
-  dac_pause();
-  dac_reset();
+  prepare_audio_track(0);
+  prepare_data(0);
 /* audio_start, data_start, 0, audio_ctrl[1:0], ctrl_start */
-  while(1){
+  while((msu_res = msu1_check_reset()) == MSU_RESET_NONE){
     cli_entrycheck();
     fpga_status_now = fpga_status();
 
@@ -94,175 +206,99 @@ int msu1_loop() {
       DBG_MSU1 printf("data\n");
       uint8_t pageno = 0;
       if(fpga_status_now & 0x2000) {
-	msu_addr = 0x0;
-	msu_page1_start = msu_page2_start + msu_page_size;
-	pageno = 1;
+        msu_addr = 0x0;
+        msu_page1_start = msu_page2_start + msu_page_size;
+        pageno = 1;
       } else {
-	msu_addr = 0x2000;
-	msu_page2_start = msu_page1_start + msu_page_size;
-	pageno = 2;
+        msu_addr = 0x2000;
+        msu_page2_start = msu_page1_start + msu_page_size;
+        pageno = 2;
       }
       set_msu_addr(msu_addr);
       sd_offload_tgt=2;
       ff_sd_offload=1;
-      res = f_read(&msufile, file_buf, 8192, &bytes_read2);
-      DBG_MSU1 printf("data buffer refilled. res=%d page1=%08lx page2=%08lx\n", res, msu_page1_start, msu_page2_start);
+      msu_res = f_read(&msufile, file_buf, 8192, &msu_data_bytes_read);
+      DBG_MSU1 printf("data buffer refilled. res=%d page1=%08lx page2=%08lx\n", msu_res, msu_page1_start, msu_page2_start);
     }
 
     /* Audio buffer refill */
     if((fpga_status_now & 0x4000) != (fpga_status_prev & 0x4000)) {
       if(fpga_status_now & 0x4000) {
-	dac_addr = 0;
+        dac_addr = 0;
       } else {
-	dac_addr = MSU_DAC_BUFSIZE/2;
+        dac_addr = MSU_DAC_BUFSIZE/2;
       }
       set_dac_addr(dac_addr);
       sd_offload_tgt=1;
       ff_sd_offload=1;
-      f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE/2, &bytes_read);
+      f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE/2, &msu_audio_bytes_read);
     }
 
     if(fpga_status_now & 0x0020) {
-      char suffix[11];
-
       /* get trackno */
       msu_track = get_msu_track();
       DBG_MSU1 printf("Audio requested! Track=%d\n", msu_track);
 
-      /* open file, fill buffer */
-      f_close(&file_handle);
-      snprintf(suffix, sizeof(suffix), "-%d.pcm", msu_track);
-      strcpy((char*)file_buf, (char*)file_lfn);
-      strcpy(strrchr((char*)file_buf, (int)'.'), suffix);
-      DBG_MSU1 printf("filename: %s\n", file_buf);
-      f_open(&file_handle, (const TCHAR*)file_buf, FA_READ);
-      file_handle.cltbl = pcm_cltbl;
-      pcm_cltbl[0] = CLTBL_SIZE;
-      f_lseek(&file_handle, CREATE_LINKMAP);
-      f_lseek(&file_handle, 4L);
-      f_read(&file_handle, &msu_loop_point, 4, &bytes_read);
-      DBG_MSU1 printf("loop point: %ld samples\n", msu_loop_point);
-      ff_sd_offload=1;
-      sd_offload_tgt=1;
-      f_lseek(&file_handle, 8L);
-      set_dac_addr(0);
-      dac_pause();
-      dac_reset();
-      ff_sd_offload=1;
-      sd_offload_tgt=1;
-      f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE, &bytes_read);
-
-      /* clear busy bit */
-      set_msu_status(0x00, 0x20); /* set no bits, reset bit 5 */
+      prepare_audio_track(msu_track);
     }
 
     if(fpga_status_now & 0x0010) {
       /* get address */
       msu_offset=get_msu_offset();
-      DBG_MSU1 printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start);
-      if(   ((msu_offset < msu_page1_start)
-	 || (msu_offset >= msu_page1_start + msu_page_size))
-	 && ((msu_offset < msu_page2_start)
-	 || (msu_offset >= msu_page2_start + msu_page_size))) {
-	DBG_MSU1 printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start,
-	       msu_page1_start+msu_page_size-1, msu_page2_start, msu_page2_start+msu_page_size-1);
-	/* "cache miss" */
-	/* fill buffer */
-	set_msu_addr(0x0);
-	sd_offload_tgt=2;
-	ff_sd_offload=1;
-        res = f_lseek(&msufile, msu_offset);
-	DBG_MSU1 printf("seek to %08lx, res = %d\n", msu_offset, res);
-	sd_offload_tgt=2;
-	ff_sd_offload=1;
-
-        res = f_read(&msufile, file_buf, 16384, &bytes_read2);
-	DBG_MSU1 printf("read res = %d\n", res);
-	DBG_MSU1 printf("read %d bytes\n", bytes_read2);
-	msu_reset(0x0);
-	msu_page1_start = msu_offset;
-	msu_page2_start = msu_offset + msu_page_size;
-      } else {
-	if (msu_offset >= msu_page1_start && msu_offset <= msu_page1_start + msu_page_size) {
-	  msu_reset(0x0000 + msu_offset - msu_page1_start);
-	  DBG_MSU1 printf("inside page1, new offset: %08lx\n", 0x0000 + msu_offset-msu_page1_start);
-	  if(!(msu_page2_start == msu_page1_start + msu_page_size)) {
-	    set_msu_addr(0x2000);
-	    sd_offload_tgt=2;
-	    ff_sd_offload=1;
-	    f_read(&msufile, file_buf, 8192, &bytes_read2);
-	    DBG_MSU1 printf("next page dirty (was: %08lx), loaded page2 (start now: ", msu_page2_start);
-	    msu_page2_start = msu_page1_start + msu_page_size;
-	    DBG_MSU1 printf("%08lx)\n", msu_page2_start);
-	  }
-	} else if (msu_offset >= msu_page2_start && msu_offset <= msu_page2_start + msu_page_size) {
-	  DBG_MSU1 printf("inside page2, new offset: %08lx\n", 0x2000 + msu_offset-msu_page2_start);
-	  msu_reset(0x2000 + msu_offset - msu_page2_start);
-	  if(!(msu_page1_start == msu_page2_start + msu_page_size)) {
-	    set_msu_addr(0x0);
-	    sd_offload_tgt=2;
-	    ff_sd_offload=1;
-	    f_read(&msufile, file_buf, 8192, &bytes_read2);
-	    DBG_MSU1 printf("next page dirty (was: %08lx), loaded page1 (start now: ", msu_page1_start);
-	    msu_page1_start = msu_page2_start + msu_page_size;
-	    DBG_MSU1 printf("%08lx)\n", msu_page1_start);
-	  }
-	} else printf("!!!WATWATWAT!!!\n");
-      }
-      /* clear bank bit to mask bank reset artifact */
-      fpga_status_now &= ~0x2000;
-      fpga_status_prev &= ~0x2000;
-      /* clear busy bit */
-      set_msu_status(0x00, 0x10);
+      prepare_data(msu_offset);
     }
 
     if(fpga_status_now & 0x0001) {
       if(fpga_status_now & 0x0004) {
-	msu_repeat = 1;
-	set_msu_status(0x04, 0x01); /* set bit 2, reset bit 0 */
-	DBG_MSU1 printf("Repeat set!\n");
+        msu_repeat = 1;
+        set_msu_status(0x04, 0x01); /* set bit 2, reset bit 0 */
+        DBG_MSU1 printf("Repeat set!\n");
       } else {
-	msu_repeat = 0;
-	set_msu_status(0x00, 0x05); /* set no bits, reset bit 0+2 */
-	DBG_MSU1 printf("Repeat clear!\n");
+        msu_repeat = 0;
+        set_msu_status(0x00, 0x05); /* set no bits, reset bit 0+2 */
+        DBG_MSU1 printf("Repeat clear!\n");
       }
 
       if(fpga_status_now & 0x0002) {
-	DBG_MSU1 printf("PLAY!\n");
-	set_msu_status(0x02, 0x01); /* set bit 0, reset bit 1 */
-	dac_play();
+        DBG_MSU1 printf("PLAY!\n");
+        set_msu_status(0x02, 0x01); /* set bit 0, reset bit 1 */
+        dac_play();
       } else {
-	DBG_MSU1 printf("PAUSE!\n");
-	set_msu_status(0x00, 0x03); /* set no bits, reset bit 1+0 */
-	dac_pause();
+        DBG_MSU1 printf("PAUSE!\n");
+        set_msu_status(0x00, 0x03); /* set no bits, reset bit 1+0 */
+        dac_pause();
       }
     }
 
     fpga_status_prev = fpga_status_now;
 
     /* handle loop / end */
-    if(bytes_read < MSU_DAC_BUFSIZE / 2) {
+    if(msu_audio_bytes_read < MSU_DAC_BUFSIZE / 2) {
       ff_sd_offload=0;
       sd_offload=0;
       if(msu_repeat) {
-	DBG_MSU1 printf("loop\n");
-	ff_sd_offload=1;
-	sd_offload_tgt=1;
-	f_lseek(&file_handle, 8L+msu_loop_point*4);
-	ff_sd_offload=1;
-	sd_offload_tgt=1;
-	f_read(&file_handle, file_buf, (MSU_DAC_BUFSIZE / 2) - bytes_read, &bytes_read);
+        DBG_MSU1 printf("loop\n");
+        ff_sd_offload=1;
+        sd_offload_tgt=1;
+        f_lseek(&file_handle, 8L+msu_loop_point*4);
+        ff_sd_offload=1;
+        sd_offload_tgt=1;
+        f_read(&file_handle, file_buf, (MSU_DAC_BUFSIZE / 2) - msu_audio_bytes_read, &msu_audio_bytes_read);
       } else {
-	set_msu_status(0x00, 0x02); /* clear play bit */
-	dac_pause();
+        set_msu_status(0x00, 0x02); /* clear play bit */
+        dac_pause();
       }
-      bytes_read = MSU_DAC_BUFSIZE;
-    }
-    if(msu1_check_reset()) {
-      f_close(&msufile);
-      f_close(&file_handle);
-      return 1;
+      msu_audio_bytes_read = MSU_DAC_BUFSIZE;
     }
   }
+  f_close(&file_handle);
+  DBG_MSU1 printf("Reset ");
+  if(msu_res == MSU_RESET_LONG) {
+    f_close(&msufile);
+    DBG_MSU1 printf("to menu\n");
+    return 1;
+  }
+  DBG_MSU1 printf("game\n");
+  return 0;
 }
 /* END OF MSU1 STUFF */

src/openocd-usb.cfg

@@ -5,14 +5,8 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x15ba 0x0003
-ft2232_device_desc "Olimex OpenOCD JTAG"
-ft2232_layout "olimex-jtag"
-
-
-#interface ft2232
-#ft2232_vid_pid 0x0403 0x6010
-#ft2232_device_desc "Dual RS232"
-#ft2232_layout "oocdlink"
-#ft2232_latency 2
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232"
+ft2232_layout "oocdlink"
+ft2232_latency 2
 #adapter_khz 10

src/sdnative.c

@@ -857,10 +857,38 @@ void write_block(uint32_t address, uint8_t* buf) {
   }
 }
 
+/* send STOP_TRANSMISSION after multiple block write
+ * and reset during_blocktrans status */
+
+void flush_write(void) {
+  cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp);
+  wait_busy();
+  during_blocktrans = TRANS_NONE;
+}
+
 //
 // Public functions
 //
 
+DRESULT sdn_ioctl(BYTE drv, BYTE cmd, void *buffer) {
+  DRESULT res;
+  if(drv >= MAX_CARDS) {
+    res = STA_NOINIT|STA_NODISK;
+  } else {
+    switch(cmd) {
+      case CTRL_SYNC:
+        flush_write();
+        res = RES_OK;
+        break;
+
+      default:
+        res = RES_PARERR;
+    }
+  }
+  return res;
+}
+DRESULT disk_ioctl(BYTE drv, BYTE cmd, void *buffer) __attribute__ ((weak, alias("sdn_ioctl")));
+
 DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) {
   uint8_t sec;
   if(drv >= MAX_CARDS) {
@@ -876,7 +904,7 @@ DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) {
 }
 DRESULT disk_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) __attribute__ ((weak, alias("sdn_read")));
 
-DRESULT sdn_initialize(BYTE drv) {
+DSTATUS sdn_initialize(BYTE drv) {
 
   uint8_t rsp[17]; /* space for response */
   int rsplen;

src/sdnative.h

@@ -22,6 +22,7 @@ DSTATUS sdn_initialize(BYTE drv);
 DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count);
 DRESULT sdn_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count);
 DRESULT sdn_getinfo(BYTE drv, BYTE page, void *buffer);
+DRESULT sdn_ioctl(BYTE drv, BYTE cmd, void *buffer);
 
 void    sdn_changed(void);
 uint8_t* sdn_getcid(void);

src/smc.c

@@ -94,6 +94,7 @@ void smc_id(snes_romprops_t* props) {
           props->romsize_bytes = 0x100000;
           props->expramsize_bytes = 0;
           props->mapper_id = 3; /* BS-X Memory Map */
+          props->region = 0; /* BS-X only existed in Japan */
           return;
         }
       }
@@ -186,7 +187,14 @@ void smc_id(snes_romprops_t* props) {
       }
   }
   if(header->romsize == 0 || header->romsize > 13) {
-    header->romsize = 13;
+    props->romsize_bytes = 1024;
+    header->romsize = 0;
+    if(file_handle.fsize >= 1024) {
+      while(props->romsize_bytes < file_handle.fsize-1) {
+        header->romsize++;
+        props->romsize_bytes <<= 1;
+      }
+    }
   }
   props->ramsize_bytes = (uint32_t)1024 << header->ramsize;
   props->romsize_bytes = (uint32_t)1024 << header->romsize;

src/snes.c

@@ -48,7 +48,7 @@ volatile int reset_pressed;
 
 void prepare_reset() {
   snes_reset(1);
-  delay_ms(1);
+  delay_ms(SNES_RESET_PULSELEN_MS);
   if(romprops.ramsize_bytes && fpga_test() == FPGA_TEST_TOKEN) {
     writeled(1);
     save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR);
@@ -71,6 +71,12 @@ void snes_init() {
   snes_reset(1);
 }
 
+void snes_reset_pulse() {
+  snes_reset(1);
+  delay_ms(SNES_RESET_PULSELEN_MS);
+  snes_reset(0);
+}
+
 /*
  * sets the SNES reset state.
  *
@@ -129,7 +135,7 @@ void snes_main_loop() {
       writeled(1);
       save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR);
       didnotsave=0;
-      writeled(0);
+      writeled(1);
     }
     saveram_crc_old = saveram_crc;
   }
@@ -165,7 +171,6 @@ void get_selected_name(uint8_t* fn) {
 }
 
 void snes_bootprint(void* msg) {
-  printf("snes_boot: %s\n",msg);
   sram_writeblock(msg, SRAM_CMD_ADDR, 33);
 }
 

src/snes.h

@@ -31,15 +31,20 @@
 #define SNES_CMD_SETRTC    (2)
 #define SNES_CMD_SYSINFO   (3)
 #define SNES_CMD_LOADLAST  (4)
+#define SNES_CMD_LOADSPC   (5)
+#define SNES_CMD_RESET     (6)
 
-#define MENU_ERR_OK		(0)
-#define MENU_ERR_NODSP	(1)
-#define MENU_ERR_NOBSX	(2)
+#define MENU_ERR_OK     (0)
+#define MENU_ERR_NODSP  (1)
+#define MENU_ERR_NOBSX  (2)
+
+#define SNES_RESET_PULSELEN_MS	(1)
 
 uint8_t crc_valid;
 
 void prepare_reset(void);
 void snes_init(void);
+void snes_reset_pulse(void);
 void snes_reset(int state);
 uint8_t get_snes_reset(void);
 void snes_main_loop(void);

src/sort.c

@@ -50,13 +50,18 @@ int sort_cmp_elem(const void* elem1, const void* elem2) {
   if (!(el1 & 0x80000000) && (el2 & 0x80000000)) {
     return 1;
   }
-/*  
-  uint16_t cmp_i;
-  for(cmp_i=0; cmp_i<8 && sort_long1[cmp_i] == sort_long2[cmp_i]; cmp_i++);
-  if(cmp_i==8) {
-    return 0;
+
+  if (*sort_str1 == '.') return -1;
+  if (*sort_str2 == '.') return 1;
+
+  /* Do not compare trailing slashes of directory names */
+  if ((el1 & 0x80000000) && (el2 & 0x80000000)) {
+    char *str1_slash = strrchr(sort_str1, '/');
+    char *str2_slash = strrchr(sort_str2, '/');
+    if(str1_slash != NULL) *str1_slash = 0;
+    if(str2_slash != NULL) *str2_slash = 0;
   }
-  return sort_long1[cmp_i]-sort_long2[cmp_i]; */
+
   return strcasecmp(sort_str1, sort_str2);
 }
 

src/spi.c

@@ -36,21 +36,13 @@ void spi_preinit() {
   BITBAND(LPC_SC->SSP_PCLKREG, SSP_PCLKBIT) = 1;
 }
 
-void spi_init(spi_speed_t speed) {
+void spi_init() {
 
   /* configure data format - 8 bits, SPI, CPOL=0, CPHA=0, 1 clock per bit */
   SSP_REGS->CR0 = (8-1);
 
   /* set clock prescaler */
-  if (speed == SPI_SPEED_FAST) {
-    SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
-  } else if (speed == SPI_SPEED_SLOW) {
-    SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
-  } else if (speed == SPI_SPEED_FPGA_FAST) {
-    SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST;
-  } else {
-    SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW;
-  }
+  SSP_REGS->CPSR = SSP_CLK_DIVISOR;
 
   /* Enable SSP */
   SSP_REGS->CR1 = BV(1);
@@ -189,25 +181,3 @@ void spi_rx_block(void *ptr, unsigned int length) {
     SSP_REGS->DMACR = 0;
   }
 }
-
-void spi_set_speed(spi_speed_t speed) {
-  /* Wait until TX fifo is empty */
-  while (!BITBAND(SSP_REGS->SR, 0)) ;
-
-  /* Disable SSP (FIXME: Is this required?) */
-  SSP_REGS->CR1 = 0;
-
-  /* Change clock divisor */
-  if (speed == SPI_SPEED_FAST) {
-    SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
-  } else if (speed == SPI_SPEED_SLOW) {
-    SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
-  } else if (speed == SPI_SPEED_FPGA_FAST) {
-    SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST;
-  } else {
-    SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW;
-  }
-
-  /* Enable SSP */
-  SSP_REGS->CR1 = BV(1);
-}

src/spi.h

@@ -42,7 +42,7 @@ typedef enum { SPI_SPEED_FAST, SPI_SPEED_SLOW, SPI_SPEED_FPGA_FAST, SPI_SPEED_FP
 void spi_preinit(void);
 
 /* Initialize SPI interface */
-void spi_init(spi_speed_t speed);
+void spi_init(void);
 
 /* Transmit a single byte */
 void spi_tx_byte(uint8_t data);
@@ -59,9 +59,6 @@ uint8_t spi_rx_byte(void);
 /* Receive a data block */
 void spi_rx_block(void *data, unsigned int length);
 
-/* Switch speed of SPI interface */
-void spi_set_speed(spi_speed_t speed);
-
 /* wait for SPI TX FIFO to become empty */
 void spi_tx_sync(void);
 

src/tests/Makefile

@@ -138,8 +138,7 @@ CFLAGS += $(CDEFS) $(CINCS)
 CFLAGS += -O$(OPT)
 CFLAGS += $(CPUFLAGS) -nostartfiles
 #CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
-CFLAGS += -Wall -Wstrict-prototypes
-#-Werror
+CFLAGS += -Wall -Wstrict-prototypes -Werror
 CFLAGS += -Wa,-adhlns=$(OBJDIR)/$(<:.c=.lst)
 CFLAGS += -I$(OBJDIR)
 CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))

src/tests/tests.c

@@ -0,0 +1,262 @@
+/* ___DISCLAIMER___ */
+
+#include <arm/NXP/LPC17xx/LPC17xx.h>
+#include "bits.h"
+#include "config.h"
+#include "uart.h"
+#include "timer.h"
+#include "led.h"
+#include "cli.h"
+#include "fpga.h"
+#include "fpga_spi.h"
+#include "ff.h"
+#include "fileops.h"
+#include "crc32.h"
+#include "diskio.h"
+#include "cic.h"
+#include "rtc.h"
+#include "memory.h"
+#include "snes.h"
+#include "cli.h"
+
+#include "tests.h"
+
+#define PROGRESS	("-\\|/")
+
+int test_sd() {
+  printf("SD test... please insert card\n=============================\n");
+  while(disk_status(0) & (STA_NOINIT|STA_NODISK)) cli_entrycheck();
+
+  file_open((uint8_t*)"/sd2snes/testfile.bin", FA_WRITE | FA_CREATE_ALWAYS);
+  if(file_res) {
+    printf("could not open /sd2snes/testfile.bin: Error %d\n", file_res);
+    printf("FAILED\n\n\n");
+    return FAILED;
+  }
+  uint32_t testval = 0x55AA55AA;
+  uint32_t crc = 0;
+  uint32_t count, blkcount;
+  for(count=0; count < 8192; count++) {
+    for(blkcount=0; blkcount < 512; blkcount++) {
+      file_buf[blkcount] = testval&0xff;
+      crc=crc32_update(crc, testval&0xff);
+      testval ^= (crc * (count + blkcount + 7)) - 1;
+    }
+    file_write();
+  }
+  printf("crc1 = %08lx ", crc);
+  file_close();
+  file_open((uint8_t*)"/sd2snes/testfile.bin", FA_READ);
+  uint32_t crc2 = 0;
+  for(count=0; count < 8192; count++) {
+    file_read();
+    for(blkcount=0; blkcount < 512; blkcount++) {
+      testval = file_buf[blkcount];
+      crc2 = crc32_update(crc2, testval&0xff);
+    }
+  }
+  file_close();
+  printf("crc2 = %08lx ", crc2);
+  if(crc==crc2) {
+    printf("  PASSED\n\n\n");
+    return PASSED;
+  } else {
+    printf("  FAILED\n\n\n");
+    return FAILED;
+  }
+}
+
+int test_cic() {
+  int cic_state = get_cic_state();
+  printf("CIC Test:\n=========\n");
+  printf("Current CIC state: %s\n", get_cic_statename(cic_state));
+  if(cic_state == CIC_FAIL) {
+    printf("CIC reports error, push reset...\n");
+    while((cic_state = get_cic_state()) == CIC_FAIL);
+  }
+  if(cic_state == CIC_OK) {
+    printf("CIC reports OK; no pair mode available. Provoking CIC error...\n");
+    cic_pair(1,1);
+    delay_ms(200);
+    cic_init(0);
+    printf("new CIC state: %s\n", get_cic_statename(get_cic_state()));
+    if(get_cic_state() == CIC_FAIL) {
+      printf("***Please reset SNES***\n");
+      int failcount=2;
+      while(failcount--) {
+        while(get_cic_state() == CIC_FAIL);
+        delay_ms(200);
+      }
+      if(get_cic_state() != CIC_FAIL) {
+        printf("PASSED\n\n\n");
+        return PASSED;
+      }
+      printf("CIC did not recover properly.\nFAILED\n");
+      return FAILED;
+    }
+    printf("FAILED\n\n\n");
+    return FAILED;
+  }
+  if(cic_state == CIC_SCIC) {
+    printf("CIC reports OK; pair mode available. Switching to pair mode...\n");
+    cic_init(1);
+    delay_ms(100);
+    cic_pair(0,0);
+    delay_ms(1000);
+    printf("new CIC state: %s\n", get_cic_statename(cic_state = get_cic_state()));
+    if(get_cic_state() != CIC_PAIR) {
+      printf("FAILED to switch to pair mode!!!\n");
+      return FAILED;
+    }
+  }
+  if(cic_state == CIC_PAIR) {
+    cic_init(1);
+    cic_pair(0,0);
+    printf("cycling modes, observe power LED color\n");
+    for(cic_state = 0; cic_state < 17; cic_state++) {
+      cic_videomode(cic_state & 1);
+      delay_ms(200);
+    }
+  }
+  printf("PASSED\n\n\n");
+  return PASSED;
+}
+
+int test_rtc() {
+  struct tm time;
+  printf("RTC Test\n========\n");
+  printf("setting clock to 2011-01-01 00:00:00\n");
+  set_bcdtime(0x20110101000000LL);
+  printf("waiting 5 seconds\n");
+  delay_ms(5000);
+//  uint64_t newtime = get_bcdtime();
+  printf("new time: ");
+  read_rtc(&time);
+  printtime(&time);
+  if((get_bcdtime() & 0xffffffffffffff) >= 0x20110101000004LL) {
+    printf("PASSED\n\n\n");
+    return PASSED;
+  } else printf("FAILED\n\n\n");
+  return FAILED;
+}
+
+int test_fpga() {
+  printf("FPGA test\n=========\n");
+  printf("configuring fpga...\n");
+  fpga_pgm((uint8_t*)"/sd2snes/test.bit");
+  printf("basic communication test...");
+  if(fpga_test() != FPGA_TEST_TOKEN) {
+    printf("FAILED\n\n\n");
+    return FAILED;
+  } else printf("PASSED\n\n\n");
+  return PASSED;
+}
+
+int test_mem() {
+  printf("RAM test\n========\n");
+  printf("Testing RAM0 (128Mbit) - writing RAM -");
+  uint32_t addr;
+  snes_reset(1);
+  fpga_select_mem(0);
+  set_mcu_addr(0);
+  FPGA_DESELECT();
+  delay_ms(1);
+  FPGA_SELECT();
+  delay_ms(1);
+  FPGA_TX_BYTE(0x98);
+  for(addr=0; addr < 16777216; addr++) {
+    if((addr&0xffff) == 0)printf("\x8%c", PROGRESS[(addr>>16)&3]);
+    FPGA_TX_BYTE((addr)+(addr>>8)+(addr>>16));
+    FPGA_WAIT_RDY();
+  }
+  FPGA_DESELECT();
+  printf(" verifying RAM -");
+  uint8_t data, expect, error=0, failed=0;
+  set_mcu_addr(0);
+  FPGA_SELECT();
+  FPGA_TX_BYTE(0x88);
+  for(addr=0; addr < 16777216; addr++) {
+    if((addr&0xffff) == 0)printf("\x8%c", PROGRESS[(addr>>16)&3]);
+    FPGA_WAIT_RDY();
+    data = FPGA_RX_BYTE();
+    expect = (addr)+(addr>>8)+(addr>>16);
+    if(data != expect) {
+      printf("error @0x%06lx: expected 0x%02x, got 0x%02x\n", addr, expect, data);
+      error++;
+      failed=1;
+      if(error>20) {
+        printf("too many errors, aborting\n");
+        break;
+      }
+    }
+  }
+  FPGA_DESELECT();
+  if(error) printf("RAM0 FAILED\n");
+  else printf("RAM0 PASSED\n");
+  printf("Testing RAM1 (4Mbit) - writing RAM - ");
+  snes_reset(1);
+  fpga_select_mem(1);
+  for(addr=0; addr < 524288; addr++) {
+    sram_writebyte((addr)+(addr>>8)+(addr>>16), addr);
+  }
+  printf("verifying RAM...");
+  error = 0;
+  for(addr=0; addr < 524288; addr++) {
+    data = sram_readbyte(addr);
+    expect = (addr)+(addr>>8)+(addr>>16);
+    if(data != expect) {
+      printf("error @0x%05lx: expected 0x%02x, got 0x%02x\n", addr, expect, data);
+      error++;
+      failed=1;
+      if(error>20) {
+        printf("too many errors, aborting\n");
+        break;
+      }
+    }
+  }
+  if(error) printf("RAM1 FAILED\n\n\n");
+  else printf("RAM1 PASSED\n\n\n");
+  if(failed) return FAILED;
+  return PASSED;
+}
+
+int test_clk() {
+  uint32_t sysclk[4];
+  int32_t diff, max_diff = 0;
+  int i, error=0;
+  printf("sysclk test\n===========\n");
+  printf("measuring SNES clock...\n");
+  for(i=0; i<4; i++) {
+    sysclk[i]=get_snes_sysclk();
+    if(sysclk[i] < 21000000 || sysclk[i] > 22000000) error = 1;
+    printf("%lu Hz ", sysclk[i]);
+    if(i) {
+      diff = sysclk[i] - sysclk[i-1];
+      if(diff < 0) diff = -diff;
+      if(diff > max_diff) max_diff = diff;
+      printf("diff = %ld  max = %ld", diff, max_diff);
+    }
+    printf("\n");
+    delay_ms(1010);
+  }
+  if(error) {
+    printf("clock frequency out of range!\n");
+  }
+  if(diff > 1000000) {
+    printf("clock variation too great!\n");
+    error = 1;
+  }
+  printf("   CPUCLK: %lu\n", get_snes_cpuclk());
+  printf("  READCLK: %lu\n", get_snes_readclk());
+  printf(" WRITECLK: %lu\n", get_snes_writeclk());
+  printf("  PARDCLK: %lu\n", get_snes_pardclk());
+  printf("  PAWRCLK: %lu\n", get_snes_pawrclk());
+  printf("  REFRCLK: %lu\n", get_snes_refreshclk());
+  printf("ROMSELCLK: %lu\n", get_snes_romselclk());
+  if(error) {
+    printf("FAILED\n\n\n");
+    return FAILED;
+  }
+  printf("PASSED\n\n\n");
+  return PASSED;
+}

src/utils/genhdr.c

@@ -73,7 +73,7 @@ int main(int argc, char **argv) {
     return 1;
   }
   char *remaining = NULL;
-  uint32_t version = (uint32_t)strtol(argv[3], &remaining, 10);
+  uint32_t version = (uint32_t)strtol(argv[3], &remaining, 0);
   if(*remaining) {
     printf("could not parse version number (remaining portion: %s)\n", remaining);
     fclose(f);

verilog/sd2snes/address.v

@@ -37,7 +37,12 @@ module address(
   output dspx_enable,
   output dspx_dp_enable,
   output dspx_a0,
-  output r213f_enable
+  output r213f_enable,
+  output snescmd_rd_enable,
+  output snescmd_wr_enable,
+  input [8:0] bs_page_offset,
+  input [9:0] bs_page,
+  input bs_page_enable
 );
 
 parameter [2:0]
@@ -76,7 +81,7 @@ assign IS_SAVERAM = SAVERAM_MASK[0]
                         || MAPPER == 3'b110
                         || MAPPER == 3'b111)
                       ? (!SNES_ADDR[22]
-                         & &SNES_ADDR[21:20]
+                         & SNES_ADDR[21]
                          & &SNES_ADDR[14:13]
                          & !SNES_ADDR[15]
                         )
@@ -141,7 +146,9 @@ assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
                             ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
                             : IS_WRITABLE
                               ? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
-                              : ((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
+                            : bs_page_enable
+									   ? (24'h900000 + {bs_page,bs_page_offset})
+								    :((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
                                  |(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
                                  ?(24'h800000
                                    + ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
@@ -178,7 +185,7 @@ assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
                              ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
                                              & SAVERAM_MASK)
                              : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
-                                + 24'hE00000)
+                                + 24'hC00000)
                             )
                            : 24'b0);
 
@@ -187,14 +194,19 @@ assign ROM_ADDR = SRAM_SNES_ADDR;
 assign ROM_SEL = 1'b0;
 
 assign msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
-reg [5:0] msu_enable_r;
-initial msu_enable_r = 6'b000000;
-always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w};
-assign msu_enable = &msu_enable_r[5:2];
+//reg [5:0] msu_enable_r;
+//initial msu_enable_r = 6'b000000;
+//always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w};
+assign msu_enable = msu_enable_w /*&msu_enable_r[5:2]*/;
 
 assign use_bsx = (MAPPER == 3'b011);
 
-assign srtc_enable = featurebits[FEAT_SRTC] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
+assign srtc_enable_w = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
+//reg [5:0] srtc_enable_r;
+//initial srtc_enable_r = 6'b000000;
+//always @(posedge CLK) srtc_enable_r <= {srtc_enable_r[4:0], srtc_enable_w};
+assign srtc_enable = srtc_enable_w /*&srtc_enable_r[3:0]*/ & featurebits[FEAT_SRTC];
+
 
 // DSP1 LoROM: DR=30-3f:8000-bfff; SR=30-3f:c000-ffff
 //          or DR=60-6f:0000-3fff; SR=60-6f:4000-7fff
@@ -228,15 +240,27 @@ assign dspx_a0 = featurebits[FEAT_DSPX]
 
 assign dspx_dp_enable = dspx_dp_enable_w;
 
-reg [5:0] dspx_enable_r;
-initial dspx_enable_r = 6'b000000;
-always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[4:0], dspx_enable_w};
-assign dspx_enable = &dspx_enable_r[5:2];
+//reg [5:0] dspx_enable_r;
+//initial dspx_enable_r = 6'b000000;
+//always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[4:0], dspx_enable_w};
+assign dspx_enable = dspx_enable_w /*&dspx_enable_r[5:1]*/;
 
 wire r213f_enable_w = (SNES_PA == 8'h3f);
-reg [5:0] r213f_enable_r;
-initial r213f_enable_r = 6'b000000;
-always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
-assign r213f_enable = &r213f_enable_r[5:2] & featurebits[FEAT_213F];
+//reg [5:0] r213f_enable_r;
+//initial r213f_enable_r = 6'b000000;
+//always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
+assign r213f_enable = r213f_enable_w /*&r213f_enable_r[5:2]*/ & featurebits[FEAT_213F];
+
+wire snescmd_rd_enable_w = (SNES_PA[7:4] == 4'b1111);
+//reg [5:0] snescmd_rd_enable_r;
+//initial snescmd_rd_enable_r = 6'b000000;
+//always @(posedge CLK) snescmd_rd_enable_r <= {snescmd_rd_enable_r[4:0], snescmd_rd_enable_w};
+assign snescmd_rd_enable = snescmd_rd_enable_w /*&snescmd_rd_enable_r[5:1]*/;
+
+assign snescmd_wr_enable_w = (SNES_ADDR[23:4] == 20'hccccc);
+//reg [5:0] snescmd_wr_enable_r;
+//initial snescmd_wr_enable_r = 6'b000000;
+//always @(posedge CLK) snescmd_wr_enable_r <= {snescmd_wr_enable_r[4:0], snescmd_wr_enable_w};
+assign snescmd_wr_enable = snescmd_wr_enable_w /*&snescmd_wr_enable_r[5:1]*/;
 
 endmodule

verilog/sd2snes/bsx.v

@@ -32,7 +32,10 @@ module bsx(
   input use_bsx,
   output data_ovr,
   output flash_writable,
-  input [55:0] rtc_data
+  input [59:0] rtc_data,
+  output [9:0] bs_page_out, // support only page 0000-03ff
+  output bs_page_enable,
+  output [8:0] bs_page_offset
 );
 
 wire [3:0] reg_addr = snes_addr[19:16]; // 00-0f:5000-5fff
@@ -67,15 +70,44 @@ assign flash_writable = (use_bsx)
                         && flash_we_r
                         && !is_flash_special_address;
 
-assign data_ovr = cart_enable | base_enable | flash_ovr;
+assign data_ovr = (cart_enable | base_enable | flash_ovr) & ~bs_page_enable;
+
+
+reg [9:0] bs_page0;
+reg [9:0] bs_page1;
+
+reg [8:0] bs_page0_offset;
+reg [8:0] bs_page1_offset;
+reg [4:0] bs_stb0_offset;
+reg [4:0] bs_stb1_offset;
+
+wire bs_sta0_en = base_addr == 5'h0a;
+wire bs_stb0_en = base_addr == 5'h0b;
+wire bs_page0_en = base_addr == 5'h0c;
+
+wire bs_sta1_en = base_addr == 5'h10;
+wire bs_stb1_en = base_addr == 5'h11;
+wire bs_page1_en = base_addr == 5'h12;
+
+assign bs_page_enable = base_enable & ((|bs_page0 & (bs_page0_en | bs_sta0_en | bs_stb0_en))
+                                      |(|bs_page1 & (bs_page1_en | bs_sta1_en | bs_stb1_en)));
+
+assign bs_page_out = (bs_page0_en | bs_sta0_en | bs_stb0_en) ? bs_page0 : bs_page1;
+
+assign bs_page_offset = bs_sta0_en ? 9'h032
+                        : bs_stb0_en ? (9'h034 + bs_stb0_offset)
+								: bs_sta1_en ? 9'h032
+								: bs_stb1_en ? (9'h034 + bs_stb1_offset)
+								: (9'h048 + (bs_page0_en ? bs_page0_offset : bs_page1_offset));
 
 reg [3:0] reg_oe_sreg;
 always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[2:0], reg_oe};
-wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000);
+wire reg_oe_falling = (reg_oe_sreg[3:1] == 3'b100);
+wire reg_oe_rising = (reg_oe_sreg[3:1] == 3'b001);
 
-reg [1:0] reg_we_sreg;
-always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we};
-wire reg_we_rising = (reg_we_sreg[1:0] == 2'b01);
+reg [2:0] reg_we_sreg;
+always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[1:0], reg_we};
+wire reg_we_rising = (reg_we_sreg[2:1] == 2'b01);
 
 reg [1:0] pgm_we_sreg;
 always @(posedge clkin) pgm_we_sreg <= {pgm_we_sreg[0], pgm_we};
@@ -96,40 +128,40 @@ wire [7:0] rtc_sec = rtc_data[3:0] + (rtc_data[7:4] << 3) + (rtc_data[7:4] << 1)
 wire [7:0] rtc_min = rtc_data[11:8] + (rtc_data[15:12] << 3) + (rtc_data[15:12] << 1);
 wire [7:0] rtc_hour = rtc_data[19:16] + (rtc_data[23:20] << 3) + (rtc_data[23:20] << 1);
 wire [7:0] rtc_day = rtc_data[27:24] + (rtc_data[31:28] << 3) + (rtc_data[31:28] << 1);
-/* The following signals are currently unused.
-   They are kept in case more Satellaview date registers are discovered. */
 wire [7:0] rtc_month = rtc_data[35:32] + (rtc_data[39:36] << 3) + (rtc_data[39:36] << 1);
+wire [7:0] rtc_dow = {4'b0,rtc_data[59:56]};
 wire [7:0] rtc_year1 = rtc_data[43:40] + (rtc_data[47:44] << 3) + (rtc_data[47:44] << 1);
 wire [7:0] rtc_year100 = rtc_data[51:48] + (rtc_data[55:52] << 3) + (rtc_data[55:52] << 1);
+wire [15:0] rtc_year = (rtc_year100 << 6) + (rtc_year100 << 5) + (rtc_year100 << 2) + rtc_year1;
 
 initial begin
   regs_tmpr <= 15'b000000100000000;
   regs_outr <= 15'b000000100000000;
   bsx_counter <= 0;
-  base_regs[8] <= 0;
-  base_regs[9] <= 0;
-  base_regs[10] <= 0;
-  base_regs[11] <= 8'h9f;
-  base_regs[12] <= 8'h10;
-  base_regs[13] <= 8'h9f;
-  base_regs[14] <= 0;
-  base_regs[15] <= 0;
-  base_regs[16] <= 0;
-  base_regs[17] <= 8'h9f;
-  base_regs[18] <= 8'h01;
-  base_regs[19] <= 8'h9f;
-  base_regs[20] <= 0;
-  base_regs[21] <= 0;
-  base_regs[22] <= 8'h02;
-  base_regs[23] <= 8'hff;
-  base_regs[24] <= 8'h80;
-  base_regs[25] <= 8'h01;
-  base_regs[26] <= 0;
-  base_regs[27] <= 0;
-  base_regs[28] <= 0;
-  base_regs[29] <= 0;
-  base_regs[30] <= 0;
-  base_regs[31] <= 0;
+  base_regs[5'h08] <= 0;
+  base_regs[5'h09] <= 0;
+  base_regs[5'h0a] <= 8'h01;
+  base_regs[5'h0b] <= 0;
+  base_regs[5'h0c] <= 0;
+  base_regs[5'h0d] <= 0;
+  base_regs[5'h0e] <= 0;
+  base_regs[5'h0f] <= 0;
+  base_regs[5'h10] <= 8'h01;
+  base_regs[5'h11] <= 0;
+  base_regs[5'h12] <= 0;
+  base_regs[5'h13] <= 0;
+  base_regs[5'h14] <= 0;
+  base_regs[5'h15] <= 0;
+  base_regs[5'h16] <= 0;
+  base_regs[5'h17] <= 0;
+  base_regs[5'h18] <= 0;
+  base_regs[5'h19] <= 0;
+  base_regs[5'h1a] <= 0;
+  base_regs[5'h1b] <= 0;
+  base_regs[5'h1c] <= 0;
+  base_regs[5'h1d] <= 0;
+  base_regs[5'h1e] <= 0;
+  base_regs[5'h1f] <= 0;
   flash_vendor_data[3'h0] <= 8'h4d;
   flash_vendor_data[3'h1] <= 8'h00;
   flash_vendor_data[3'h2] <= 8'h50;
@@ -140,39 +172,55 @@ initial begin
   flash_vendor_data[3'h7] <= 8'h00;
   flash_ovr_r <= 1'b0;
   flash_we_r <= 1'b0;
+  bs_page0 <= 10'h0;
+  bs_page1 <= 10'h0;
+  bs_page0_offset <= 9'h0;
+  bs_page1_offset <= 9'h0;
+  bs_stb0_offset <= 5'h00;
+  bs_stb1_offset <= 5'h00;
 end
 
 
 always @(posedge clkin) begin
+  if(reg_oe_rising && base_enable) begin
+    case(base_addr)
+	   5'h0b: begin
+		  bs_stb0_offset <= bs_stb0_offset + 1;
+		  base_regs[5'h0d] <= base_regs[5'h0d] | reg_data_in;
+		end
+		5'h0c: bs_page0_offset <= bs_page0_offset + 1; 
+		5'h11: begin
+		  bs_stb1_offset <= bs_stb1_offset + 1;
+  		  base_regs[5'h13] <= base_regs[5'h13] | reg_data_in;
+		end
+		5'h12: bs_page1_offset <= bs_page1_offset + 1;
+	 endcase
+  end else 
   if(reg_oe_falling) begin
     if(cart_enable)
       reg_data_outr <= {regs_outr[reg_addr], 7'b0};
     else if(base_enable) begin
       case(base_addr)
-        5'b10010: begin
-          if(bsx_counter < 18) begin
-            bsx_counter <= bsx_counter + 1;
-            case (bsx_counter)
-              5:
-                reg_data_outr <= 8'h1;
-              6:
-                reg_data_outr <= 8'h1;
-              10:
-                reg_data_outr <= rtc_sec;
-              11:
-                reg_data_outr <= rtc_min;
-              12:
-                reg_data_outr <= rtc_hour;
-              default:
-                reg_data_outr <= 8'h0;
-            endcase
-          end else begin
-            reg_data_outr <= 8'h0;
-            bsx_counter <= 0;
-          end
+        5'h0c, 5'h12: begin
+          case (bs_page1_offset)
+            4: reg_data_outr <= 8'h3;
+            5: reg_data_outr <= 8'h1;
+            6: reg_data_outr <= 8'h1;
+            10: reg_data_outr <= rtc_sec;
+            11: reg_data_outr <= rtc_min;
+            12: reg_data_outr <= rtc_hour;
+				13: reg_data_outr <= rtc_dow;
+				14: reg_data_outr <= rtc_day;
+				15: reg_data_outr <= rtc_month;
+				16: reg_data_outr <= rtc_year[7:0];
+				17: reg_data_outr <= rtc_year[15:8];
+            default: reg_data_outr <= 8'h0;
+          endcase
+        end
+        5'h0d, 5'h13: begin
+          reg_data_outr <= base_regs[base_addr];
+			 base_regs[base_addr] <= 8'h00;
         end
-        5'b10011:
-          reg_data_outr <= base_regs[base_addr] & 8'h3f;
         default:
           reg_data_outr <= base_regs[base_addr];
       endcase
@@ -190,7 +238,7 @@ always @(posedge clkin) begin
     end
   end else if(pgm_we_rising) begin
     regs_tmpr[8:1] <= (regs_tmpr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
-      regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
+    regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
   end else if(reg_we_rising && cart_enable) begin
     if(reg_addr == 4'he && reg_data_in[7])
       regs_outr <= regs_tmpr | 15'b100000000000000;
@@ -198,16 +246,27 @@ always @(posedge clkin) begin
       regs_tmpr[reg_addr] <= reg_data_in[7];
   end else if(reg_we_rising && base_enable) begin
     case(base_addr)
-      5'h0f: begin
-        base_regs[base_addr-1] <= base_regs[base_addr]-(base_regs[base_addr-1] >> 1);
-        base_regs[base_addr] <= base_regs[base_addr] >> 1;
+		5'h09: begin
+		  base_regs[8'h09] <= reg_data_in;
+		  bs_page0 <= {reg_data_in[1:0], base_regs[8'h08]};
+		  bs_page0_offset <= 9'h00;
+		end
+		5'h0b: begin
+		  bs_stb0_offset <= 5'h00;
+		end
+      5'h0c: begin
+        bs_page0_offset <= 9'h00;
+      end
+		5'h0f: begin
+		  base_regs[8'h0f] <= reg_data_in;
+		  bs_page1 <= {reg_data_in[1:0], base_regs[8'h0e]};
+		  bs_page1_offset <= 9'h00;
       end
       5'h11: begin
-        bsx_counter <= 0;
-        base_regs[base_addr] <= reg_data_in;
+		  bs_stb1_offset <= 5'h00;
       end
       5'h12: begin
-        base_regs[8'h10] <= 8'h80;
+        bs_page1_offset <= 9'h00;
       end
       default:
         base_regs[base_addr] <= reg_data_in;

verilog/sd2snes/clk_test.v

@@ -39,7 +39,7 @@ always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
 wire sysclk_rising = (sysclk_sreg == 2'b01);
 
 always @(posedge clk) begin
-  if(sysclk_counter < 96000000) begin
+  if(sysclk_counter < 88000000) begin
     sysclk_counter <= sysclk_counter + 1;
     if(sysclk_rising) sysclk_value <= sysclk_value + 1;
   end else begin

verilog/sd2snes/dac.v

@@ -30,7 +30,8 @@ module dac(
   input reset,
   output sdout,
   output lrck,
-  output mclk,
+  output mclk,
+  output sclk,
   output DAC_STATUS
 );
 
@@ -68,14 +69,15 @@ reg [15:0] smpshift;
 
 assign mclk = cnt[2]; // mclk = clk/8
 assign lrck = cnt[8]; // lrck = mclk/128
-wire sclk = cnt[3];   // sclk = lrck*32
+assign sclk = cnt[3]; // sclk = lrck*32
 
 reg [2:0] lrck_sreg;
 reg [2:0] sclk_sreg;
-wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01);
-wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10);
+wire lrck_rising = (lrck_sreg[1:0] == 2'b01);
+wire lrck_falling = (lrck_sreg[1:0] == 2'b10);
 
-wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01);
+wire sclk_rising = (sclk_sreg[1:0] == 2'b01);
+wire sclk_falling = (sclk_sreg[1:0] == 2'b10);
 
 wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
 reg sdout_reg;
@@ -143,17 +145,17 @@ always @(posedge clkin) begin
 end
 
 always @(posedge clkin) begin
-  if (lrck_rising) begin // right channel
-    smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
-    samples <= samples + 1;
-  end else if (lrck_falling) begin // left channel
-    smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
-  end else begin
-    if (sclk_rising) begin
-      smpcnt <= smpcnt + 1;
-      sdout_reg <= smpshift[15];
+  if (sclk_falling) begin
+    smpcnt <= smpcnt + 1;
+    sdout_reg <= smpshift[15];
+    if (lrck_rising) begin // right channel
+      smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
+      samples <= samples + 1;
+    end else if (lrck_falling) begin // left channel
+      smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
+    end else begin
       smpshift <= {smpshift[14:0], 1'b0};
-    end
+    end
   end
 end
 

verilog/sd2snes/ipcore_dir/dac_buf.v

@@ -1,28 +1,29 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used solely      *
-*     for design, simulation, implementation and creation of design files      *
-*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
-*     devices or technologies is expressly prohibited and immediately          *
-*     terminates your license.                                                 *
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
-*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
-*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
-*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
-*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
-*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
-*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
-*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
-*     PARTICULAR PURPOSE.                                                      *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
 *                                                                              *
-*     Xilinx products are not intended for use in life support appliances,     *
-*     devices, or systems.  Use in such applications are expressly             *
-*     prohibited.                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file dac_buf.v when simulating
@@ -56,7 +57,7 @@ output [31 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_3 #(
+  BLK_MEM_GEN_V6_1 #(
     .C_ADDRA_WIDTH(11),
     .C_ADDRB_WIDTH(9),
     .C_ALGORITHM(1),
@@ -68,7 +69,6 @@ output [31 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
-    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/dac_buf.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.4
-# Date: Tue May 15 16:23:22 2012
+# Xilinx Core Generator version 13.1
+# Date: Mon Jun 13 22:11:22 2011
 #
 ##############################################################
 #
@@ -12,16 +12,12 @@
 #
 ##############################################################
 #
-#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
-#
-##############################################################
-#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Verilog
+SET designentry = Advanced
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Foundation_ISE
@@ -33,10 +29,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = false
+SET vhdlsim = true
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -53,7 +49,6 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
-CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -100,7 +95,7 @@ CSET write_width_a=8
 CSET write_width_b=32
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-10-21T13:54:23Z
+MISC pkg_timestamp=2011-02-03T22:20:43.000Z
 # END Extra information
 GENERATE
-# CRC: e5078255
+# CRC: 70eef295

verilog/sd2snes/ipcore_dir/dac_buf.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="dac_buf.ngc" xil_pn:type="FILE_NGC">
@@ -26,7 +26,13 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="dac_buf.vhd" xil_pn:type="FILE_VHDL"/>
+    <file xil_pn:name="dac_buf.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
+    </file>
   </files>
 
   <properties>

verilog/sd2snes/ipcore_dir/msu_databuf.v

@@ -1,28 +1,29 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used solely      *
-*     for design, simulation, implementation and creation of design files      *
-*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
-*     devices or technologies is expressly prohibited and immediately          *
-*     terminates your license.                                                 *
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
-*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
-*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
-*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
-*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
-*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
-*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
-*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
-*     PARTICULAR PURPOSE.                                                      *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
 *                                                                              *
-*     Xilinx products are not intended for use in life support appliances,     *
-*     devices, or systems.  Use in such applications are expressly             *
-*     prohibited.                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file msu_databuf.v when simulating
@@ -56,7 +57,7 @@ output [7 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_3 #(
+  BLK_MEM_GEN_V6_1 #(
     .C_ADDRA_WIDTH(14),
     .C_ADDRB_WIDTH(14),
     .C_ALGORITHM(1),
@@ -68,7 +69,6 @@ output [7 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
-    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/msu_databuf.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.4
-# Date: Tue May 15 16:26:06 2012
+# Xilinx Core Generator version 13.1
+# Date: Mon Jun 13 22:13:20 2011
 #
 ##############################################################
 #
@@ -12,16 +12,12 @@
 #
 ##############################################################
 #
-#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
-#
-##############################################################
-#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Verilog
+SET designentry = Advanced
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Foundation_ISE
@@ -33,10 +29,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = false
+SET vhdlsim = true
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -53,7 +49,6 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
-CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -100,7 +95,7 @@ CSET write_width_a=8
 CSET write_width_b=8
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-10-21T13:54:23Z
+MISC pkg_timestamp=2011-02-03T22:20:43.000Z
 # END Extra information
 GENERATE
-# CRC: cbebd26a
+# CRC: eabbe14d

verilog/sd2snes/ipcore_dir/msu_databuf.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="msu_databuf.ngc" xil_pn:type="FILE_NGC">
@@ -26,7 +26,13 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="msu_databuf.vhd" xil_pn:type="FILE_VHDL"/>
+    <file xil_pn:name="msu_databuf.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
+    </file>
   </files>
 
   <properties>

verilog/sd2snes/ipcore_dir/upd77c25_datram.v

@@ -1,28 +1,29 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used solely      *
-*     for design, simulation, implementation and creation of design files      *
-*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
-*     devices or technologies is expressly prohibited and immediately          *
-*     terminates your license.                                                 *
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
-*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
-*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
-*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
-*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
-*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
-*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
-*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
-*     PARTICULAR PURPOSE.                                                      *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
 *                                                                              *
-*     Xilinx products are not intended for use in life support appliances,     *
-*     devices, or systems.  Use in such applications are expressly             *
-*     prohibited.                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file upd77c25_datram.v when simulating
@@ -62,7 +63,7 @@ output [7 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_3 #(
+  BLK_MEM_GEN_V6_1 #(
     .C_ADDRA_WIDTH(10),
     .C_ADDRB_WIDTH(11),
     .C_ALGORITHM(1),
@@ -74,7 +75,6 @@ output [7 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
-    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/upd77c25_datram.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.4
-# Date: Wed May 16 07:50:33 2012
+# Xilinx Core Generator version 13.1
+# Date: Sun Jun 19 20:18:04 2011
 #
 ##############################################################
 #
@@ -12,16 +12,12 @@
 #
 ##############################################################
 #
-#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
-#
-##############################################################
-#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Verilog
+SET designentry = Advanced
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Other
@@ -33,10 +29,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = false
+SET vhdlsim = true
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -53,7 +49,6 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
-CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -100,7 +95,7 @@ CSET write_width_a=16
 CSET write_width_b=8
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-10-21T13:54:23Z
+MISC pkg_timestamp=2011-02-03T22:20:43.000Z
 # END Extra information
 GENERATE
-# CRC: 94c2e5cc
+# CRC: 78e2bfe1

verilog/sd2snes/ipcore_dir/upd77c25_datram.xise

@@ -12,12 +12,12 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="upd77c25_datram.ngc" xil_pn:type="FILE_NGC">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="upd77c25_datram.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -26,7 +26,13 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="upd77c25_datram.vhd" xil_pn:type="FILE_VHDL"/>
+    <file xil_pn:name="upd77c25_datram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
+    </file>
   </files>
 
   <properties>

verilog/sd2snes/ipcore_dir/upd77c25_datrom.v

@@ -1,28 +1,29 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used solely      *
-*     for design, simulation, implementation and creation of design files      *
-*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
-*     devices or technologies is expressly prohibited and immediately          *
-*     terminates your license.                                                 *
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
-*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
-*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
-*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
-*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
-*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
-*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
-*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
-*     PARTICULAR PURPOSE.                                                      *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
 *                                                                              *
-*     Xilinx products are not intended for use in life support appliances,     *
-*     devices, or systems.  Use in such applications are expressly             *
-*     prohibited.                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file upd77c25_datrom.v when simulating
@@ -56,7 +57,7 @@ output [15 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_3 #(
+  BLK_MEM_GEN_V6_1 #(
     .C_ADDRA_WIDTH(11),
     .C_ADDRB_WIDTH(11),
     .C_ALGORITHM(1),
@@ -68,7 +69,6 @@ output [15 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
-    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.4
-# Date: Wed May 16 07:43:52 2012
+# Xilinx Core Generator version 13.1
+# Date: Wed Jun 22 21:30:01 2011
 #
 ##############################################################
 #
@@ -12,16 +12,12 @@
 #
 ##############################################################
 #
-#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
-#
-##############################################################
-#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Verilog
+SET designentry = Advanced
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Other
@@ -33,10 +29,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = false
+SET vhdlsim = true
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -53,7 +49,6 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
-CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -100,7 +95,7 @@ CSET write_width_a=16
 CSET write_width_b=16
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-10-21T13:54:23Z
+MISC pkg_timestamp=2011-02-03T22:20:43.000Z
 # END Extra information
 GENERATE
-# CRC: 4c89ee28
+# CRC: 7b2b203b

verilog/sd2snes/ipcore_dir/upd77c25_datrom.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="upd77c25_datrom.ngc" xil_pn:type="FILE_NGC">
@@ -26,7 +26,13 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="upd77c25_datrom.vhd" xil_pn:type="FILE_VHDL"/>
+    <file xil_pn:name="upd77c25_datrom.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
+    </file>
   </files>
 
   <properties>

verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v

@@ -1,28 +1,29 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used solely      *
-*     for design, simulation, implementation and creation of design files      *
-*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
-*     devices or technologies is expressly prohibited and immediately          *
-*     terminates your license.                                                 *
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
-*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
-*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
-*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
-*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
-*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
-*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
-*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
-*     PARTICULAR PURPOSE.                                                      *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
 *                                                                              *
-*     Xilinx products are not intended for use in life support appliances,     *
-*     devices, or systems.  Use in such applications are expressly             *
-*     prohibited.                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file upd77c25_pgmrom.v when simulating
@@ -56,7 +57,7 @@ output [23 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_3 #(
+  BLK_MEM_GEN_V6_1 #(
     .C_ADDRA_WIDTH(11),
     .C_ADDRB_WIDTH(11),
     .C_ALGORITHM(1),
@@ -68,7 +69,6 @@ output [23 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
-    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.4
-# Date: Wed May 16 08:14:01 2012
+# Xilinx Core Generator version 13.1
+# Date: Wed Jun 22 21:31:49 2011
 #
 ##############################################################
 #
@@ -12,16 +12,12 @@
 #
 ##############################################################
 #
-#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
-#
-##############################################################
-#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Verilog
+SET designentry = Advanced
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Other
@@ -33,10 +29,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = false
+SET vhdlsim = true
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -53,7 +49,6 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
-CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -100,7 +95,7 @@ CSET write_width_a=24
 CSET write_width_b=24
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-10-21T13:54:23Z
+MISC pkg_timestamp=2011-02-03T22:20:43.000Z
 # END Extra information
 GENERATE
-# CRC: 4fd43971
+# CRC: b11006ad

verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="upd77c25_pgmrom.ngc" xil_pn:type="FILE_NGC">
@@ -26,7 +26,13 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="upd77c25_pgmrom.vhd" xil_pn:type="FILE_VHDL"/>
+    <file xil_pn:name="upd77c25_pgmrom.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
+    </file>
   </files>
 
   <properties>

verilog/sd2snes/main.ucf

@@ -1,6 +1,5 @@
 NET "CLKIN" TNM_NET = "CLKIN";
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %;
-//TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.05 MHz HIGH 50 %;
 
 NET "p113_out" IOSTANDARD = LVCMOS33;
 NET "p113_out" LOC = P113;
@@ -8,7 +7,7 @@ NET "p113_out" LOC = P113;
 NET "SPI_SCK" LOC = P71;
 NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
 NET "SPI_SCK" TNM_NET = "SPI_SCK";
-TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48MHz HIGH 50 %;
+TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 88.2MHz HIGH 50 %;
 
 NET "SPI_SCK" IOSTANDARD = LVCMOS33;
 NET "SPI_SCK" DRIVE = 8;
@@ -33,30 +32,30 @@ NET "ROM_CE" LOC = P172;
 NET "ROM_CE" IOSTANDARD = LVCMOS33;
 NET "ROM_CE" DRIVE = 8;
 
-NET "SNES_ADDR[0]" LOC = P119;
-NET "SNES_ADDR[10]" LOC = P146;
-NET "SNES_ADDR[11]" LOC = P148;
-NET "SNES_ADDR[12]" LOC = P147;
-NET "SNES_ADDR[13]" LOC = P144;
-NET "SNES_ADDR[14]" LOC = P141;
-NET "SNES_ADDR[15]" LOC = P139;
-NET "SNES_ADDR[16]" LOC = P137;
-NET "SNES_ADDR[17]" LOC = P133;
-NET "SNES_ADDR[18]" LOC = P131;
-NET "SNES_ADDR[19]" LOC = P128;
-NET "SNES_ADDR[1]" LOC = P122;
-NET "SNES_ADDR[20]" LOC = P125;
-NET "SNES_ADDR[21]" LOC = P123;
-NET "SNES_ADDR[22]" LOC = P120;
-NET "SNES_ADDR[23]" LOC = P117;
-NET "SNES_ADDR[2]" LOC = P124;
-NET "SNES_ADDR[3]" LOC = P126;
-NET "SNES_ADDR[4]" LOC = P130;
-NET "SNES_ADDR[5]" LOC = P132;
-NET "SNES_ADDR[6]" LOC = P135;
-NET "SNES_ADDR[7]" LOC = P138;
-NET "SNES_ADDR[8]" LOC = P140;
-NET "SNES_ADDR[9]" LOC = P143;
+NET "SNES_ADDR_IN[0]" LOC = P119;
+NET "SNES_ADDR_IN[10]" LOC = P146;
+NET "SNES_ADDR_IN[11]" LOC = P148;
+NET "SNES_ADDR_IN[12]" LOC = P147;
+NET "SNES_ADDR_IN[13]" LOC = P144;
+NET "SNES_ADDR_IN[14]" LOC = P141;
+NET "SNES_ADDR_IN[15]" LOC = P139;
+NET "SNES_ADDR_IN[16]" LOC = P137;
+NET "SNES_ADDR_IN[17]" LOC = P133;
+NET "SNES_ADDR_IN[18]" LOC = P131;
+NET "SNES_ADDR_IN[19]" LOC = P128;
+NET "SNES_ADDR_IN[1]" LOC = P122;
+NET "SNES_ADDR_IN[20]" LOC = P125;
+NET "SNES_ADDR_IN[21]" LOC = P123;
+NET "SNES_ADDR_IN[22]" LOC = P120;
+NET "SNES_ADDR_IN[23]" LOC = P117;
+NET "SNES_ADDR_IN[2]" LOC = P124;
+NET "SNES_ADDR_IN[3]" LOC = P126;
+NET "SNES_ADDR_IN[4]" LOC = P130;
+NET "SNES_ADDR_IN[5]" LOC = P132;
+NET "SNES_ADDR_IN[6]" LOC = P135;
+NET "SNES_ADDR_IN[7]" LOC = P138;
+NET "SNES_ADDR_IN[8]" LOC = P140;
+NET "SNES_ADDR_IN[9]" LOC = P143;
 NET "SNES_DATA[0]" LOC = P107;
 NET "SNES_DATA[1]" LOC = P102;
 NET "SNES_DATA[2]" LOC = P100;
@@ -379,54 +378,54 @@ NET "ROM_WE" LOC = P190;
 
 NET "ROM_WE" IOSTANDARD = LVCMOS33;
 NET "ROM_WE" DRIVE = 8;
-NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[0]" DRIVE = 8;
-NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[10]" DRIVE = 8;
-NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[11]" DRIVE = 8;
-NET "SNES_ADDR[12]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[12]" DRIVE = 8;
-NET "SNES_ADDR[13]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[13]" DRIVE = 8;
-NET "SNES_ADDR[14]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[14]" DRIVE = 8;
-NET "SNES_ADDR[15]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[15]" DRIVE = 8;
-NET "SNES_ADDR[16]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[16]" DRIVE = 8;
-NET "SNES_ADDR[17]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[17]" DRIVE = 8;
-NET "SNES_ADDR[18]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[18]" DRIVE = 8;
-NET "SNES_ADDR[19]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[19]" DRIVE = 8;
-NET "SNES_ADDR[1]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[1]" DRIVE = 8;
-NET "SNES_ADDR[20]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[20]" DRIVE = 8;
-NET "SNES_ADDR[21]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[21]" DRIVE = 8;
-NET "SNES_ADDR[22]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[22]" DRIVE = 8;
-NET "SNES_ADDR[23]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[23]" DRIVE = 8;
-NET "SNES_ADDR[2]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[2]" DRIVE = 8;
-NET "SNES_ADDR[3]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[3]" DRIVE = 8;
-NET "SNES_ADDR[4]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[4]" DRIVE = 8;
-NET "SNES_ADDR[5]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[5]" DRIVE = 8;
-NET "SNES_ADDR[6]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[6]" DRIVE = 8;
-NET "SNES_ADDR[7]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[7]" DRIVE = 8;
-NET "SNES_ADDR[8]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[8]" DRIVE = 8;
-NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[9]" DRIVE = 8;
+NET "SNES_ADDR_IN[0]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[0]" DRIVE = 8;
+NET "SNES_ADDR_IN[10]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[10]" DRIVE = 8;
+NET "SNES_ADDR_IN[11]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[11]" DRIVE = 8;
+NET "SNES_ADDR_IN[12]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[12]" DRIVE = 8;
+NET "SNES_ADDR_IN[13]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[13]" DRIVE = 8;
+NET "SNES_ADDR_IN[14]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[14]" DRIVE = 8;
+NET "SNES_ADDR_IN[15]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[15]" DRIVE = 8;
+NET "SNES_ADDR_IN[16]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[16]" DRIVE = 8;
+NET "SNES_ADDR_IN[17]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[17]" DRIVE = 8;
+NET "SNES_ADDR_IN[18]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[18]" DRIVE = 8;
+NET "SNES_ADDR_IN[19]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[19]" DRIVE = 8;
+NET "SNES_ADDR_IN[1]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[1]" DRIVE = 8;
+NET "SNES_ADDR_IN[20]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[20]" DRIVE = 8;
+NET "SNES_ADDR_IN[21]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[21]" DRIVE = 8;
+NET "SNES_ADDR_IN[22]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[22]" DRIVE = 8;
+NET "SNES_ADDR_IN[23]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[23]" DRIVE = 8;
+NET "SNES_ADDR_IN[2]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[2]" DRIVE = 8;
+NET "SNES_ADDR_IN[3]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[3]" DRIVE = 8;
+NET "SNES_ADDR_IN[4]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[4]" DRIVE = 8;
+NET "SNES_ADDR_IN[5]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[5]" DRIVE = 8;
+NET "SNES_ADDR_IN[6]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[6]" DRIVE = 8;
+NET "SNES_ADDR_IN[7]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[7]" DRIVE = 8;
+NET "SNES_ADDR_IN[8]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[8]" DRIVE = 8;
+NET "SNES_ADDR_IN[9]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[9]" DRIVE = 8;
 
 
 NET "SNES_CPU_CLK" LOC = P95;

verilog/sd2snes/main.v

@@ -23,7 +23,7 @@ module main(
   input CLKIN,
 
   /* SNES signals */
-  input [23:0] SNES_ADDR,
+  input [23:0] SNES_ADDR_IN,
   input SNES_READ,
   input SNES_WRITE,
   input SNES_CS,
@@ -76,6 +76,17 @@ module main(
   /* debug */
   output p113_out
 );
+
+wire CLK2;
+
+reg [23:0] SNES_ADDR_r [2:0];
+always @(posedge CLK2) begin
+  SNES_ADDR_r[2] <= SNES_ADDR_r[1];
+  SNES_ADDR_r[1] <= SNES_ADDR_r[0];
+  SNES_ADDR_r[0] <= SNES_ADDR_IN;
+end
+wire [23:0] SNES_ADDR = SNES_ADDR_r[2] & SNES_ADDR_r[1];
+
 wire dspx_dp_enable;
 
 wire [7:0] spi_cmd_data;
@@ -133,6 +144,22 @@ wire [7:0] featurebits;
 wire [23:0] MAPPED_SNES_ADDR;
 wire ROM_ADDR0;
 
+wire [9:0] bs_page;
+wire [8:0] bs_page_offset;
+wire bs_page_enable;
+
+
+wire [4:0] DBG_srtc_state;
+wire DBG_srtc_we_rising;
+wire [3:0] DBG_srtc_ptr;
+wire [5:0] DBG_srtc_we_sreg;
+wire [13:0] DBG_msu_address;
+wire DBG_msu_reg_oe_rising;
+wire DBG_msu_reg_oe_falling;
+wire DBG_msu_reg_we_rising;
+wire [2:0] SD_DMA_DBG_clkcnt;
+wire [10:0] SD_DMA_DBG_cyclecnt;
+
 sd_dma snes_sd_dma(
   .CLK(CLK2),
   .SD_DAT(SD_DAT),
@@ -146,7 +173,9 @@ sd_dma snes_sd_dma(
   .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
   .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
   .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
-  .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
+  .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
+  .DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
+  .DBG_clkcnt(SD_DMA_DBG_clkcnt)
 );
 
 wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
@@ -178,7 +207,11 @@ srtc snes_srtc (
   .enable(srtc_enable),
   .rtc_data_out(srtc_rtc_data_out),
   .rtc_we(srtc_rtc_we),
-  .reset(srtc_reset)
+  .reset(srtc_reset),
+  .srtc_state(DBG_srtc_state),
+  .srtc_reg_we_rising(DBG_srtc_we_rising),
+  .srtc_rtc_ptr(DBG_srtc_ptr),
+  .srtc_we_sreg(DBG_srtc_we_sreg)
 );
 
 rtc snes_rtc (
@@ -210,7 +243,12 @@ msu snes_msu (
   .status_set_bits(msu_status_set_bits),
   .status_reset_we(msu_status_reset_we),
   .msu_address_ext(msu_ptr_addr),
-  .msu_address_ext_write(msu_addr_reset)
+  .msu_address_ext_write(msu_addr_reset),
+  .DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
+  .DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
+  .DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
+  .DBG_msu_address(DBG_msu_address),
+  .DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
 );
 
 bsx snes_bsx(
@@ -227,7 +265,11 @@ bsx snes_bsx(
   .reg_set_bits(bsx_regs_set_bits),
   .data_ovr(bsx_data_ovr),
   .flash_writable(IS_FLASHWR),
-  .rtc_data(rtc_data[55:0])
+  .rtc_data(rtc_data[59:0]),
+  .bs_page_out(bs_page), // support only page 0000-03ff
+  .bs_page_enable(bs_page_enable),
+  .bs_page_offset(bs_page_offset)
+
 );
 
 spi snes_spi(
@@ -330,7 +372,8 @@ mcu_cmd snes_mcu_cmd(
   .mcu_rrq(MCU_RRQ),
   .mcu_wrq(MCU_WRQ),
   .mcu_rq_rdy(MCU_RDY),
-  .region_out(mcu_region)
+  .region_out(mcu_region),
+  .DBG_mcu_nextaddr(DBG_mcu_nextaddr)
 );
 
 wire [7:0] DCM_STATUS;
@@ -343,33 +386,37 @@ my_dcm snes_dcm(
   .STATUS(DCM_STATUS)
 );
 
-my_dcm snes_dcm2(
-  .CLKIN(SNES_SYSCLK),
-  .CLKFX(SYSCLK2),
-  .RST(DCM_RST)
-);
-
 assign DCM_RST=0;
 
-reg [5:0] SNES_PARDr;
-reg [5:0] SNES_READr;
-reg [5:0] SNES_WRITEr;
-reg [5:0] SNES_CPU_CLKr;
+reg [7:0] SNES_PARDr;
+reg [7:0] SNES_PAWRr;
+reg [7:0] SNES_READr;
+reg [7:0] SNES_WRITEr;
+reg [7:0] SNES_CPU_CLKr;
 
-wire SNES_PARD_start = (SNES_PARDr == 6'b111110);
-wire SNES_RD_start = (SNES_READr == 6'b111110);
-wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
-wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
-wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
+wire SNES_FAKE_CLK = &SNES_CPU_CLKr[2:1];
+//wire SNES_FAKE_CLK = ~(SNES_READ & SNES_WRITE);
 
-always @(posedge SYSCLK2) begin
-  SNES_PARDr <= {SNES_PARDr[4:0], SNES_PARD};
+reg SNES_DEADr;
+initial SNES_DEADr = 0;
+
+wire SNES_PARD_start = (SNES_PARDr[7:1] == 7'b1111110);
+wire SNES_PAWR_start = (SNES_PAWRr[7:1] == 7'b0000001);
+wire SNES_RD_start = (SNES_READr[7:1] == 7'b1111110);
+wire SNES_WR_start = (SNES_WRITEr[7:1] == 7'b1111110);
+wire SNES_WR_end = (SNES_WRITEr[7:1] == 7'b0000001);
+wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000001);
+wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b111110);
+
+always @(posedge CLK2) begin
+  SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD};
 end
 
 always @(posedge CLK2) begin
-  SNES_READr <= {SNES_READr[4:0], SNES_READ};
-  SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
-  SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
+  SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR};
+  SNES_READr <= {SNES_READr[6:0], SNES_READ};
+  SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE};
+  SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK};
 end
 
 address snes_addr(
@@ -390,13 +437,18 @@ address snes_addr(
   //BS-X
   .use_bsx(use_bsx),
   .bsx_regs(bsx_regs),
+  .bs_page_offset(bs_page_offset),
+  .bs_page(bs_page),
+  .bs_page_enable(bs_page_enable),
   //SRTC
   .srtc_enable(srtc_enable),
   //uPD77C25
   .dspx_enable(dspx_enable),
   .dspx_dp_enable(dspx_dp_enable),
   .dspx_a0(DSPX_A0),
-  .r213f_enable(r213f_enable)
+  .r213f_enable(r213f_enable),
+  .snescmd_rd_enable(snescmd_rd_enable),
+  .snescmd_wr_enable(snescmd_wr_enable)
 );
 
 parameter MODE_SNES = 1'b0;
@@ -420,23 +472,27 @@ parameter ST_MCU_WR_WAIT  = 18'b000100000000000000;
 parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
 parameter ST_MCU_WR_END   = 18'b010000000000000000;
 
-parameter ROM_RD_WAIT = 4'h4;
+parameter ROM_RD_WAIT = 4'h0;
 parameter ROM_RD_WAIT_MCU = 4'h6;
+parameter ROM_WR_WAIT = 4'h4;
 parameter ROM_WR_WAIT1 = 4'h2;
-parameter ROM_WR_WAIT2 = 4'h3;
-parameter ROM_WR_WAIT_MCU = 4'h6;
+parameter ROM_WR_WAIT2 = 4'h1;
+parameter ROM_WR_WAIT_MCU = 4'h5;
+
+parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
 
 reg [17:0] STATE;
 initial STATE = ST_IDLE;
 
+reg [7:0] SNES_DINr;
+reg [7:0] SNES_DOUTr;
+reg [7:0] ROM_DOUTr;
+
 assign DSPX_SNES_DATA_IN = SNES_DATA;
 assign SRTC_SNES_DATA_IN = SNES_DATA[3:0];
 assign MSU_SNES_DATA_IN = SNES_DATA;
 assign BSX_SNES_DATA_IN = SNES_DATA;
 
-reg [7:0] SNES_DINr;
-reg [7:0] ROM_DOUTr;
-
 reg [7:0] r213fr;
 reg r213f_forceread;
 reg [2:0] r213f_delay;
@@ -446,15 +502,17 @@ initial r213f_forceread = 0;
 initial r213f_state = 2'b01;
 initial r213f_delay = 3'b011;
 
+reg[7:0] snescmd_regs[15:0];
 
-assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr
-                   :(!SNES_READ ^ r213f_forceread)
+assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
+                   :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
+                   :(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
                                 ? (srtc_enable ? SRTC_SNES_DATA_OUT
                                   :dspx_enable ? DSPX_SNES_DATA_OUT
                                   :dspx_dp_enable ? DSPX_SNES_DATA_OUT
                                   :msu_enable ? MSU_SNES_DATA_OUT
                                   :bsx_data_ovr ? BSX_SNES_DATA_OUT
-                                  :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
+                                  :SNES_DOUTr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
 
 reg [3:0] ST_MEM_DELAYr;
 reg MCU_RD_PENDr;
@@ -466,25 +524,35 @@ always @(posedge CLK2) begin
   else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
 end
 
-wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
-
-assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
-assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
-
-reg ROM_WEr;
-initial ROM_WEr = 1'b1;
-
 reg RQ_MCU_RDYr;
 initial RQ_MCU_RDYr = 1'b1;
 assign MCU_RDY = RQ_MCU_RDYr;
 
+reg ROM_SAr;
+initial ROM_SAr = 1'b1;
+//wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
+wire ROM_SA = ROM_SAr;
+
+assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
+assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
+
+reg ROM_WEr;
+initial ROM_WEr = 1'b1;
+reg ROM_DOUT_ENr;
+initial ROM_DOUT_ENr = 1'b0;
+
+reg[17:0] SNES_DEAD_CNTr;
+initial SNES_DEAD_CNTr = 0;
+
 always @(posedge CLK2) begin
   if(MCU_RRQ) begin
     MCU_RD_PENDr <= 1'b1;
     RQ_MCU_RDYr <= 1'b0;
+    ROM_ADDRr <= MCU_ADDR;
   end else if(MCU_WRQ) begin
     MCU_WR_PENDr <= 1'b1;
     RQ_MCU_RDYr <= 1'b0;
+    ROM_ADDRr <= MCU_ADDR;
   end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
     MCU_RD_PENDr <= 1'b0;
     MCU_WR_PENDr <= 1'b0;
@@ -492,121 +560,125 @@ always @(posedge CLK2) begin
   end
 end
 
+always @(posedge CLK2) begin
+  if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
+  else SNES_DEAD_CNTr <= 17'h0;
+end
+
+always @(posedge CLK2) begin
+  if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
+  else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
+end
+
 reg snes_wr_cycle;
 
 always @(posedge CLK2) begin
-  if(SNES_cycle_start & ~SNES_WR_start) begin
-    STATE <= ST_SNES_RD_ADDR;
-  end else if(SNES_WR_start) begin
-    STATE <= ST_SNES_WR_ADDR;
-  end else begin
-    case(STATE)
-	   ST_IDLE: begin
-		  ROM_ADDRr <= MAPPED_SNES_ADDR;
-		  if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
-		  else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
-      else STATE <= ST_IDLE;
+  if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
+  else
+  case(STATE)
+    ST_IDLE: begin
+	   ROM_SAr <= 1'b1;
+		ROM_DOUT_ENr <= 1'b0;
+	   if(SNES_cycle_start & ~SNES_WRITE) begin
+		  STATE <= ST_SNES_WR_ADDR;
+		  if(IS_SAVERAM | IS_WRITABLE | IS_FLASHWR) begin
+		    ROM_WEr <= 1'b0;
+          ROM_DOUT_ENr <= 1'b1;
+        end
+		end else if(SNES_cycle_start) begin
+//		  STATE <= ST_SNES_RD_ADDR;		  
+        STATE <= ST_SNES_RD_END;
+        SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
+		end else if(SNES_DEADr & MCU_RD_PENDr) begin
+		  STATE <= ST_MCU_RD_ADDR;
+		end else if(SNES_DEADr & MCU_WR_PENDr) begin
+		  STATE <= ST_MCU_WR_ADDR;
 		end
-		ST_SNES_RD_ADDR: begin
-		  STATE <= ST_SNES_RD_WAIT;
-		  ST_MEM_DELAYr <= ROM_RD_WAIT;
-		end
-		ST_SNES_RD_WAIT: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
-		  else STATE <= ST_SNES_RD_WAIT;
-		  if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
-		  else SNES_DINr <= ROM_DATA[15:8];
-		end
-		ST_SNES_RD_END: begin
-		  STATE <= ST_IDLE;
-		  if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
-		  else SNES_DINr <= ROM_DATA[15:8];
-		end
-      ST_SNES_WR_ADDR: begin
-        ROM_WEr <= (!IS_FLASHWR & !IS_WRITABLE);
-        snes_wr_cycle <= 1'b1;
-		  STATE <= ST_SNES_WR_WAIT1;
-		  ST_MEM_DELAYr <= ROM_WR_WAIT1;
-		end
-		ST_SNES_WR_WAIT1: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
-		  else STATE <= ST_SNES_WR_WAIT1;
-		end
-		ST_SNES_WR_DATA: begin
-        ROM_DOUTr <= SNES_DATA;
+	 end
+	 ST_SNES_RD_ADDR: begin
+	   ST_MEM_DELAYr <= ROM_RD_WAIT;
+		STATE <= ST_SNES_RD_WAIT;
+	 end
+	 ST_SNES_RD_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+//		if(ST_MEM_DELAYr == 0) begin
+//		end
+//		else STATE <= ST_SNES_RD_WAIT;
+	 end
+	 
+	 ST_SNES_WR_ADDR: begin
+	   ST_MEM_DELAYr <= ROM_WR_WAIT1;
+	   STATE <= ST_SNES_WR_WAIT1;
+	 end
+	 ST_SNES_WR_WAIT1: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
 		  ST_MEM_DELAYr <= ROM_WR_WAIT2;
-		  STATE <= ST_SNES_WR_WAIT2;
+        STATE <= ST_SNES_WR_WAIT2;
+		  ROM_DOUTr <= SNES_DATA;
 		end
-      ST_SNES_WR_WAIT2: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
-		  else STATE <= ST_SNES_WR_WAIT2;
-		end
-		ST_SNES_WR_END: begin
-		  STATE <= ST_IDLE;
+		else STATE <= ST_SNES_WR_WAIT1;
+	 end
+	 ST_SNES_WR_WAIT2: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+        STATE <= ST_SNES_WR_END;
 		  ROM_WEr <= 1'b1;
-		  snes_wr_cycle <= 1'b0;
 		end
-		ST_MCU_RD_ADDR: begin
-		  ROM_ADDRr <= MCU_ADDR;
-		  STATE <= ST_MCU_RD_WAIT;
-		  ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
+		else STATE <= ST_SNES_WR_WAIT2;
+    end
+	 ST_SNES_RD_END, ST_SNES_WR_END: begin
+	   ROM_DOUT_ENr <= 1'b0;		
+      if(MCU_RD_PENDr) begin
+        STATE <= ST_MCU_RD_ADDR;
+      end else if(MCU_WR_PENDr) begin
+        STATE <= ST_MCU_WR_ADDR;
+      end else STATE <= ST_IDLE;
+    end
+    ST_MCU_RD_ADDR: begin
+      ROM_SAr <= 1'b0;
+		ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
+		STATE <= ST_MCU_RD_WAIT;
+	 end
+	 ST_MCU_RD_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+        STATE <= ST_MCU_RD_END;
 		end
-		ST_MCU_RD_WAIT: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) begin
-		    STATE <= ST_MCU_RD_WAIT2;
-			 ST_MEM_DELAYr <= 4'h2;
-		  end
-		  else STATE <= ST_MCU_RD_WAIT;
-		  if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
-		  else MCU_DINr <= ROM_DATA[15:8];
-      end
-		ST_MCU_RD_WAIT2: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) begin
-		    STATE <= ST_MCU_RD_END;
-		  end else STATE <= ST_MCU_RD_WAIT2;
+		else STATE <= ST_MCU_RD_WAIT;
+	 end
+	 ST_MCU_RD_END: begin
+      MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
+	   STATE <= ST_IDLE;
+	 end
+	 
+	 ST_MCU_WR_ADDR: begin
+      ROM_DOUTr <= MCU_DOUT;
+      ROM_SAr <= 1'b0;
+	   ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
+		STATE <= ST_MCU_WR_WAIT;
+		ROM_DOUT_ENr <= 1'b1;
+		ROM_WEr <= 1'b0;
+	 end
+	 ST_MCU_WR_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+		  ROM_WEr <= 1'b1;
+		  STATE <= ST_MCU_WR_END;
 		end
-		ST_MCU_RD_END: begin
-		  STATE <= ST_IDLE;
-		end
-		ST_MCU_WR_ADDR: begin
-		  ROM_ADDRr <= MCU_ADDR;
-		  STATE <= ST_MCU_WR_WAIT;
-		  ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
-		  ROM_DOUTr <= MCU_DOUT;
-		  ROM_WEr <= 1'b0;
-		end
-		ST_MCU_WR_WAIT: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) begin
-          ROM_WEr <= 1'b1;
-		    STATE <= ST_MCU_WR_WAIT2;
-			 ST_MEM_DELAYr <= 4'h2;
-		  end
-		  else STATE <= ST_MCU_WR_WAIT;
-      end
-		ST_MCU_WR_WAIT2: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) begin
-		    STATE <= ST_MCU_WR_END;
-        end else STATE <= ST_MCU_WR_WAIT2;
-		end
-		ST_MCU_WR_END: begin
-		  STATE <= ST_IDLE;
-		end
-
-    endcase
-  end
+		else STATE <= ST_MCU_WR_WAIT;	 
+	 end
+	 ST_MCU_WR_END: begin
+		ROM_DOUT_ENr <= 1'b0;
+	   STATE <= ST_IDLE;
+	 end
+  endcase
 end
 
-always @(posedge SYSCLK2) begin
-  if(SNES_PARD_start & r213f_enable) begin
-    r213f_forceread <= 1'b1;
-    r213f_delay <= 3'b001;
+always @(posedge CLK2) begin
+  if(SNES_cycle_end) r213f_forceread <= 1'b1;
+  else if(SNES_PARD_start & r213f_enable) begin
+    r213f_delay <= 3'b000;
     r213f_state <= 2'b10;
   end else if(r213f_state == 2'b10) begin
     r213f_delay <= r213f_delay - 1;
@@ -618,46 +690,98 @@ always @(posedge SYSCLK2) begin
   end
 end
 
+always @(posedge CLK2) begin
+  if(SNES_WR_end & snescmd_wr_enable) begin
+    snescmd_regs[SNES_ADDR[3:0]] <= SNES_DATA;
+  end
+end
+
+reg ROM_WE_1;
+reg MCU_WRITE_1;
+
+always @(posedge CLK2) begin
+  ROM_WE_1 <= ROM_WE;
+  MCU_WRITE_1<= MCU_WRITE;
+end
+
 assign ROM_DATA[7:0] = ROM_ADDR0
-                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                                        : (!ROM_WE ? ROM_DOUTr : 8'bZ)
+                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+							                   /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+                                        : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                         )
                        :8'bZ;
 
 assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
-                        :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                                         : (!ROM_WE ? ROM_DOUTr : 8'bZ)
+                        :(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+								                 /*:  ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+                                         : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                          );
 
 assign ROM_WE = SD_DMA_TO_ROM
                 ?MCU_WRITE
-                :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
+                :/*(SNES_FAKE_CLK & (IS_WRITABLE | IS_FLASHWR)) ? SNES_WRITE :*/ ROM_WEr;
 
 // OE always active. Overridden by WE when needed.
 assign ROM_OE = 1'b0;
 
 assign ROM_CE = 1'b0;
 
-assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
-assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
+assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
 
 assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
                          msu_enable ? 1'b0 :
                          bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
                          srtc_enable ? (SNES_READ & SNES_WRITE) :
+								 bs_page_enable ? (SNES_READ) :
                          r213f_enable & !SNES_PARD ? 1'b0 :
+								 (snescmd_wr_enable | snescmd_rd_enable) & !SNES_PARD ? 1'b0 :
                          ((IS_ROM & SNES_CS)
                           |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
-                          |(SNES_READ & SNES_WRITE)
+                          |(SNES_READr[0] & SNES_WRITEr[0])
                          );
 
-assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & r213f_enable))
-                           ? 1'b1 ^ r213f_forceread
+assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescmd_rd_enable)))
+                           ? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
                            : 1'b0;
 
-assign IRQ_DIR = 1'b0;
-assign SNES_IRQ = 1'bZ;
+assign SNES_IRQ = 1'b0;
 
 assign p113_out = 1'b0;
 
+/*
+wire [35:0] CONTROL0;
+
+icon icon (
+    .CONTROL0(CONTROL0) // INOUT BUS [35:0]
+);
+
+ila_srtc ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SNES_ADDR), // IN BUS [23:0]
+    .TRIG1(SNES_DATA), // IN BUS [7:0]
+    .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}),	 // IN BUS [15:0]
+    .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(spi_byte_cnt[3:0])
+);
+*/
+/*
+ila_srtc ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
+    .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
+    .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}),	 // IN BUS [15:0]
+    .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(ST_MEM_DELAYr)
+);
+*/
+
 endmodule

verilog/sd2snes/mcu_cmd.v

@@ -97,7 +97,10 @@ module mcu_cmd(
   
   output reg region_out,
   // SNES sync/clk
-  input snes_sysclk
+  input snes_sysclk,
+  
+  // debug
+  output DBG_mcu_nextaddr
 );
 
 initial begin
@@ -140,12 +143,13 @@ reg [55:0] rtc_data_out_buf;
 reg rtc_pgm_we_buf;
 
 reg srtc_reset_buf;
+initial srtc_reset_buf = 0;
 
 reg [31:0] SNES_SYSCLK_FREQ_BUF;
 
 reg [7:0] MCU_DATA_OUT_BUF;
 reg [7:0] MCU_DATA_IN_BUF;
-reg [1:0] mcu_nextaddr_buf;
+reg [2:0] mcu_nextaddr_buf;
 
 wire mcu_nextaddr;
 
@@ -198,7 +202,7 @@ always @(posedge clk) begin
         SD_DMA_PARTIALr <= cmd_data[2];
       end
       4'h8: SD_DMA_TGTr <= 2'b00;
-      4'h9: SD_DMA_TGTr <= cmd_data[1:0]; // not implemented
+      4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
 //      4'hE:
 //      select memory unit
     endcase
@@ -410,9 +414,9 @@ end
 
 // value fetch during last SPI bit
 always @(posedge clk) begin
-  if (cmd_data[7:4] == 4'h8 && mcu_nextaddr_buf == 2'b01)
+  if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
     MCU_DATA_IN_BUF <= mcu_data_in;
-  else if (spi_bit_cnt == 3'h7) begin
+  else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
     if (cmd_data[7:0] == 8'hF0)
       MCU_DATA_IN_BUF <= 8'hA5;
     else if (cmd_data[7:0] == 8'hF1)
@@ -462,7 +466,7 @@ end
 
 // nextaddr pulse generation
 always @(posedge clk) begin
-  mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], mcu_rq_rdy};
+  mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
 end
 
 parameter ST_RQ = 2'b01;
@@ -545,4 +549,5 @@ assign mcu_mapper = MAPPER_BUF;
 assign rom_mask_out = ROM_MASK;
 assign saveram_mask_out = SAVERAM_MASK;
 
+assign DBG_mcu_nextaddr = mcu_nextaddr;
 endmodule

verilog/sd2snes/msu.v

@@ -38,7 +38,13 @@ module msu(
   input [5:0] status_set_bits,
   input status_reset_we,
   input [13:0] msu_address_ext,
-  input msu_address_ext_write
+  input msu_address_ext_write,
+  
+  output DBG_msu_reg_oe_rising,
+  output DBG_msu_reg_oe_falling,
+  output DBG_msu_reg_we_rising,
+  output [13:0] DBG_msu_address,
+  output DBG_msu_address_ext_write_rising
 );
 
 reg [2:0] reg_addr_r [3:0];
@@ -56,13 +62,15 @@ wire status_reset_en = (status_reset_we_r == 2'b01);
 
 reg [13:0] msu_address_r;
 wire [13:0] msu_address = msu_address_r;
+initial msu_address_r = 13'b0;
 
 wire [7:0] msu_data;
+reg [7:0] msu_data_r;
 
-reg [1:0] msu_address_ext_write_sreg;
+reg [2:0] msu_address_ext_write_sreg;
 always @(posedge clkin)
-  msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write};
-wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01);
+  msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
+wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
 
 reg [4:0] reg_enable_sreg;
 initial reg_enable_sreg = 5'b11111;
@@ -70,11 +78,12 @@ always @(posedge clkin) reg_enable_sreg <= {reg_enable_sreg[3:0], enable};
 
 reg [5:0] reg_oe_sreg;
 always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe};
-wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
+wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:1] == 5'b00001);
+wire reg_oe_falling = reg_enable_sreg[1] && (reg_oe_sreg[5:1] == 5'b11110);
 
 reg [5:0] reg_we_sreg;
 always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[4:0], reg_we};
-wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
+wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[5:1] == 5'b00001);
 
 reg [31:0] addr_out_r;
 assign addr_out = addr_out_r;
@@ -93,14 +102,27 @@ reg audio_busy_r;
 reg data_start_r;
 reg data_busy_r;
 reg ctrl_start_r;
+reg audio_error_r;
 reg [1:0] audio_ctrl_r;
 reg [1:0] audio_status_r;
 
 initial begin
-  audio_busy_r <= 1'b1;
-  data_busy_r <= 1'b1;
+  audio_busy_r = 1'b1;
+  data_busy_r = 1'b1;
+  audio_error_r = 1'b0;
+  volume_r = 8'h00;
+  addr_out_r = 32'h00000000;
+  track_out_r = 16'h0000;
+  data_start_r = 1'b0;
+  audio_start_r = 1'b0;
 end
 
+assign DBG_msu_address = msu_address;
+assign DBG_msu_reg_oe_rising = reg_oe_rising;
+assign DBG_msu_reg_oe_falling = reg_oe_falling;
+assign DBG_msu_reg_we_rising = reg_we_rising;
+assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
+
 assign status_out = {msu_address_r[13], // 6
                      audio_start_r,     // 5
                      data_start_r,      // 4
@@ -124,8 +146,8 @@ reg [7:0] data_out_r;
 assign reg_data_out = data_out_r;
 
 always @(posedge clkin) begin
-  case(reg_addr_r[3])
-    3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, 4'b0001};
+  case(reg_addr_r[1])
+    3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b001};
     3'h1: data_out_r <= msu_data;
     3'h2: data_out_r <= 8'h53;
     3'h3: data_out_r <= 8'h2d;
@@ -138,7 +160,7 @@ end
 
 always @(posedge clkin) begin
   if(reg_we_rising) begin
-    case(reg_addr_r[3])
+    case(reg_addr_r[1])
       3'h0: addr_out_r[7:0] <= reg_data_in;
       3'h1: addr_out_r[15:8] <= reg_data_in;
       3'h2: addr_out_r[23:16] <= reg_data_in;
@@ -173,7 +195,7 @@ always @(posedge clkin) begin
     data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
     if(status_reset_bits[4]) data_start_r <= 1'b0;
 
-//    volume_start_r <= (volume_start_r | status_set_bits[3]) & ~status_reset_bits[3];
+    audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
 
     audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
 

verilog/sd2snes/rtc.v

@@ -42,7 +42,7 @@ reg [31:0] tick_cnt;
 
 always @(posedge clkin) begin
   tick_cnt <= tick_cnt + 1;
-  if((tick_cnt == 24000000) || pgm_we_rising) tick_cnt <= 0;
+  if((tick_cnt == 22000000) || pgm_we_rising) tick_cnt <= 0;
 end
 
 assign rtc_data = rtc_data_out_r;

verilog/sd2snes/sd2snes.xise

@@ -9,107 +9,91 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
-    <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="main_tf.v" xil_pn:type="FILE_VERILOG"/>
     <file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="19"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="ipcore_dir/upd77c25_datram.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="ipcore_dir/upd77c25_datrom.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
-    <file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/upd77c25_datrom.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/msu_databuf.xise" xil_pn:type="FILE_COREGENISE">
+    <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
@@ -377,8 +361,8 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="11" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="11" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -449,9 +433,7 @@
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
 
-  <bindings>
-    <binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
-  </bindings>
+  <bindings/>
 
   <libraries/>
 

verilog/sd2snes/sd_dma.v

@@ -31,7 +31,10 @@ module sd_dma(
   input [10:0] SD_DMA_PARTIAL_START,
   input [10:0] SD_DMA_PARTIAL_END,
   input SD_DMA_START_MID_BLOCK,
-  input SD_DMA_END_MID_BLOCK
+  input SD_DMA_END_MID_BLOCK,
+  
+  output [10:0] DBG_cyclecnt,
+  output [2:0] DBG_clkcnt
 );
 
 reg [10:0] SD_DMA_STARTr;
@@ -74,7 +77,11 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
 reg [2:0] clkcnt;
 initial clkcnt = 3'b000;
 reg [1:0] SD_CLKr;
-always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
+initial SD_CLKr = 3'b111;
+always @(posedge CLK)
+  if(SD_DMA_EN_rising) SD_CLKr <= 3'b111;
+  else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
+
 assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
 
 always @(posedge CLK) begin
@@ -116,20 +123,20 @@ always @(posedge CLK) begin
   if(SD_DMA_STATUSr) begin
     case(clkcnt[2:0])
       3'h0: begin
-        SD_DMA_SRAM_WEr <= 1'b1;
         SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
         if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
       end
-      3'h1:
+      3'h1: begin
         SD_DMA_NEXTADDRr <= 1'b0;
-//  3'h2:
-      3'h3:
-        if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
+		end
+      3'h2: if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
+//  3'h3:
       3'h4:
         SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
 //  3'h5:
 //  3'h6:
-//  3'h7:
+      3'h7:
+		  SD_DMA_SRAM_WEr <= 1'b1;
     endcase
   end
 end

verilog/sd2snes/spi.v

@@ -39,15 +39,27 @@ module spi(
 reg [7:0] cmd_data_r;
 reg [7:0] param_data_r;
 
-reg [1:0] SSELr;  always @(posedge clk) SSELr <= {SSELr[0], SSEL};
+reg [2:0] SSELr;
+reg [2:0] SSELSCKr;
+
+always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
+always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
+
+wire SSEL_inactive = SSELr[1];
 wire SSEL_active = ~SSELr[1];  // SSEL is active low
-wire SSEL_startmessage = (SSELr[1:0]==2'b10);  // message starts at falling edge
-wire SSEL_endmessage = (SSELr[1:0]==2'b01);  // message stops at rising edge
+wire SSEL_startmessage = (SSELr[2:1]==2'b10);  // message starts at falling edge
+wire SSEL_endmessage = (SSELr[2:1]==2'b01);  // message stops at rising edge
 assign endmessage = SSEL_endmessage;
 assign startmessage = SSEL_startmessage;
 
 // bit count for one SPI byte + byte count for the message
 reg [2:0] bitcnt;
+initial bitcnt = 3'b000;
+wire bitcnt_msb = bitcnt[2];
+reg [2:0] bitcnt_wrap_r;
+always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
+wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
+
 reg [31:0] byte_cnt_r;
 
 reg byte_received;  // high when a byte has been received
@@ -56,23 +68,26 @@ reg [7:0] byte_data_received;
 assign bit_cnt = bitcnt;
 
 always @(posedge SCK) begin
-  if(SSEL) bitcnt <= 3'b000;
-  else begin
-    bitcnt <= bitcnt + 3'b001;
+  if(SSELSCKr[1]) bitcnt <= 3'b000;
+  else bitcnt <= bitcnt + 3'b001;
+end
+
+always @(posedge SCK) begin
+  if(~SSELSCKr[1]) begin
 	 byte_data_received <= {byte_data_received[6:0], MOSI};
   end
-  if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1;
+  if(~SSELSCKr[1] && bitcnt==3'b111) byte_received <= 1'b1;
   else byte_received <= 1'b0;
 end
 
-reg [1:0] byte_received_r;
-always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received};
-wire byte_received_sync = (byte_received_r == 2'b01);
+//reg [2:0] byte_received_r;
+//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
+//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
 
 always @(posedge clk) begin
-  if(~SSEL_active)
+  if(SSEL_inactive) begin
     byte_cnt_r <= 16'h0000;
-  else if(byte_received_sync) begin
+  end else if(byte_received_sync) begin
     byte_cnt_r <= byte_cnt_r + 16'h0001;
   end
 end

verilog/sd2snes/srtc.v

@@ -29,7 +29,13 @@ module srtc(
   input reg_oe,
   input enable,
   output rtc_we,
-  input reset
+  input reset,
+  
+  /* DEBUG */
+  output [4:0] srtc_state,
+  output srtc_reg_we_rising,
+  output [3:0] srtc_rtc_ptr,
+  output [5:0] srtc_we_sreg
 );
 
 reg [59:0] rtc_data_r;
@@ -44,13 +50,14 @@ reg rtc_we_r;
 assign rtc_we = rtc_we_r;
 assign data_out = data_out_r;
 
-reg [3:0] reg_oe_sreg;
-always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[2:0], reg_oe};
-wire reg_oe_falling = (reg_oe_sreg == 4'b1000);
+reg [5:0] reg_oe_sreg;
+always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe};
+wire reg_oe_falling = (reg_oe_sreg[5:1] == 5'b11110);
+wire reg_oe_rising = (reg_oe_sreg[5:1] == 5'b00001);
 
-reg [1:0] reg_we_sreg;
-always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we};
-wire reg_we_rising = (reg_we_sreg[1:0] == 2'b01);
+reg [5:0] reg_we_sreg;
+always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[4:0], reg_we};
+wire reg_we_rising = (reg_we_sreg[5:1] == 5'b00001);
 
 reg [1:0] reset_sreg;
 always @(posedge clkin) reset_sreg <= {reset_sreg[0], reset};
@@ -64,27 +71,37 @@ parameter SRTC_COMMAND = 5'b00100;
 parameter SRTC_WRITE = 5'b01000;
 parameter SRTC_WRITE2 = 5'b10000;
 
+reg [3:0] data_in_r;
+
+reg [3:0] addr_in_r;
+always @(posedge clkin) addr_in_r <= {addr_in_r[2:0], addr_in};
+
+assign srtc_reg_we_rising = reg_we_rising;
+assign srtc_state = mode_r;
+assign srtc_rtc_ptr = rtc_ptr;
+assign srtc_we_sreg = reg_we_sreg;
+
 initial begin
   rtc_we_r = 0;
-  mode_r <= SRTC_READ;
-  rtc_ptr <= 4'hf;
+  mode_r = SRTC_READ;
+  rtc_ptr = 4'hf;
+  data_out_r = 8'h00;
+end
+
+//always @(posedge clkin) data_in_r <= data_in;
+always @(posedge clkin) begin
+  if(~reg_we) data_in_r <= data_in;
 end
 
 always @(posedge clkin) begin
   if(reset_rising) begin
     mode_r <= SRTC_READ;
     rtc_ptr <= 4'hf;
-  end else if(mode_r == SRTC_WRITE2) begin
-    we_countdown_r <= we_countdown_r - 1;
-    if (we_countdown_r == 3'b000) begin
-      mode_r <= SRTC_WRITE;
-      rtc_we_r <= 0;
-    end
   end else if(reg_we_rising && enable) begin
-    case (addr_in)
+    case (addr_in_r[0])
 //     1'b0: // data register is read only
       1'b1: // control register
-        case (data_in)
+        case (data_in_r)
           4'hd: begin
             mode_r <= SRTC_READ;
             rtc_ptr <= 4'hf;
@@ -92,11 +109,9 @@ always @(posedge clkin) begin
           4'he: begin
             mode_r <= SRTC_COMMAND;
           end
-          4'hf: begin
-          end
           default: begin
             if(mode_r == SRTC_COMMAND) begin
-              case (data_in)
+              case (data_in_r)
                 4'h0: begin
                   mode_r <= SRTC_WRITE;
                   rtc_data_out_r <= rtc_data_in;
@@ -112,38 +127,38 @@ always @(posedge clkin) begin
             end else if(mode_r == SRTC_WRITE) begin
               rtc_ptr <= rtc_ptr + 1;
               case(rtc_ptr)
-                0: rtc_data_out_r[3:0] <= data_in;
-                1: rtc_data_out_r[7:4] <= data_in;
-                2: rtc_data_out_r[11:8] <= data_in;
-                3: rtc_data_out_r[15:12] <= data_in;
-                4: rtc_data_out_r[19:16] <= data_in;
-                5: rtc_data_out_r[23:20] <= data_in;
-                6: rtc_data_out_r[27:24] <= data_in;
-                7: rtc_data_out_r[31:28] <= data_in;
+                0: rtc_data_out_r[3:0] <= data_in_r;
+                1: rtc_data_out_r[7:4] <= data_in_r;
+                2: rtc_data_out_r[11:8] <= data_in_r;
+                3: rtc_data_out_r[15:12] <= data_in_r;
+                4: rtc_data_out_r[19:16] <= data_in_r;
+                5: rtc_data_out_r[23:20] <= data_in_r;
+                6: rtc_data_out_r[27:24] <= data_in_r;
+                7: rtc_data_out_r[31:28] <= data_in_r;
                 8: begin
-                  rtc_data_out_r[35:32] <= (data_in < 10)
-                                           ? data_in
-                                           : data_in - 10;
-                  rtc_data_out_r[39:36] <= data_in < 10 ? 0 : 1;
+                  rtc_data_out_r[35:32] <= (data_in_r < 10)
+                                           ? data_in_r
+                                           : data_in_r - 10;
+                  rtc_data_out_r[39:36] <= data_in_r < 10 ? 0 : 1;
                 end
-                9: rtc_data_out_r[43:40] <= data_in;
-                10: rtc_data_out_r[47:44] <= data_in;
+                9: rtc_data_out_r[43:40] <= data_in_r;
+                10: rtc_data_out_r[47:44] <= data_in_r;
                 11: begin
-                  rtc_data_out_r[51:48] <= (data_in < 10)
-                                           ? data_in
-                                           : data_in - 10;
-                  rtc_data_out_r[55:52] <= data_in < 10 ? 1 : 2;
+                  rtc_data_out_r[51:48] <= (data_in_r < 10)
+                                           ? data_in_r
+                                           : data_in_r - 10;
+                  rtc_data_out_r[55:52] <= data_in_r < 10 ? 1 : 2;
                 end
               endcase
               mode_r <= SRTC_WRITE2;
-              we_countdown_r <= 5;
+              we_countdown_r <= 4;
               rtc_we_r <= 1;
             end
           end
         endcase
     endcase
   end else if(reg_oe_falling && enable) begin
-    case (addr_in)
+    case (addr_in_r[0])
       1'b0: // read data register
       if(mode_r == SRTC_READ) begin
         case(rtc_ptr)
@@ -164,18 +179,25 @@ always @(posedge clkin) begin
                             + (rtc_data_r[55:52] << 1)
                             + (rtc_data_r[55:52] << 3) - 10;
           12: data_out_r <= rtc_data_r[59:56];
+//			 14: mode_r <= SRTC_IDLE;
           15: begin
             rtc_data_r <= rtc_data_in;
             data_out_r <= 8'h0f;
           end
-        default: data_out_r <= 8'h0f;
-      endcase
+          default: data_out_r <= 8'h0f;
+        endcase
         rtc_ptr <= rtc_ptr == 13 ? 15 : rtc_ptr + 1;
       end else begin
         data_out_r <= 8'h00;
       end
 //      1'b1: // control register is write only
     endcase
+  end else if(mode_r == SRTC_WRITE2) begin
+    we_countdown_r <= we_countdown_r - 1;
+    if (we_countdown_r == 3'b000) begin
+      mode_r <= SRTC_WRITE;
+      rtc_we_r <= 0;
+    end
   end
 end
 

verilog/sd2snes/upd77c25.v

@@ -98,6 +98,9 @@ upd77c25_pgmrom pgmrom (
   .doutb(pgm_doutb) // output [23 : 0] doutb
 );
 
+reg [7:0] DIr;
+always @(posedge CLK) if(~nWR) DIr <= DI;
+
 wire [23:0] opcode_w = pgm_doutb;
 reg [1:0] op;
 reg [1:0] op_pselect;
@@ -128,8 +131,8 @@ always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[3:0], nCS};
 reg [5:0] reg_oe_sreg;
 initial reg_oe_sreg = 6'b111111;
 always @(posedge CLK) reg_oe_sreg <= {reg_oe_sreg[4:0], nRD};
-wire reg_oe_rising = !reg_nCS_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
-wire reg_oe_falling = (reg_oe_sreg[5:0] == 6'b100000);
+wire reg_oe_rising = !reg_nCS_sreg[4] && (reg_oe_sreg[5:1] == 5'b00001);
+wire reg_oe_falling = (reg_oe_sreg[5:1] == 5'b10000);
 
 reg [4:0] reg_DP_nCS_sreg;
 initial reg_DP_nCS_sreg = 5'b11111;
@@ -138,7 +141,7 @@ always @(posedge CLK) reg_DP_nCS_sreg <= {reg_DP_nCS_sreg[3:0], DP_nCS};
 reg [5:0] reg_we_sreg;
 initial reg_we_sreg = 6'b111111;
 always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[4:0], nWR};
-wire reg_we_rising = !reg_nCS_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
+wire reg_we_rising = !reg_nCS_sreg[4] && (reg_we_sreg[5:1] == 5'b00001);
 
 wire [15:0] ram_douta;
 wire [9:0] ram_addra;
@@ -303,12 +306,12 @@ always @(posedge CLK) begin
     if(reg_we_rising && (A0r[3] == 1'b0)) begin
       if(!regs_sr[SR_DRC]) begin
         if(regs_sr[SR_DRS] == 1'b0) begin
-          regs_dr[7:0] <= DI;
+          regs_dr[7:0] <= DIr;
         end else begin
-          regs_dr[15:8] <= DI;
+          regs_dr[15:8] <= DIr;
         end
       end else begin
-        regs_dr[7:0] <= DI;
+        regs_dr[7:0] <= DIr;
       end
     end else if(ld_dst == 4'b0110 && insn_state == STATE_STORE) begin
       if (op == I_OP || op == I_RT) regs_dr <= idb;

verilog/sd2snes_cx4/address.v

@@ -34,7 +34,9 @@ module address(
   output msu_enable,
   output cx4_enable,
   output cx4_vect_enable,
-  output r213f_enable
+  output r213f_enable,
+  output snescmd_rd_enable,
+  output snescmd_wr_enable
 );
 
 wire [23:0] SRAM_SNES_ADDR;
@@ -54,23 +56,20 @@ assign ROM_ADDR = SRAM_SNES_ADDR;
 assign ROM_SEL = 1'b0;
 
 wire msu_enable_w = use_msu1 & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
-reg [5:0] msu_enable_r;
-initial msu_enable_r = 6'b000000;
-always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w};
-assign msu_enable = &msu_enable_r[5:2];
+assign msu_enable = msu_enable_w;
 
 wire cx4_enable_w = (!SNES_ADDR[22] && (SNES_ADDR[15:13] == 3'b011));
-reg [5:0] cx4_enable_r;
-initial cx4_enable_r = 6'b000000;
-always @(posedge CLK) cx4_enable_r <= {cx4_enable_r[4:0], cx4_enable_w};
-assign cx4_enable = &cx4_enable_r[5:2];
+assign cx4_enable = cx4_enable_w;
 
 assign cx4_vect_enable = &SNES_ADDR[15:5];
 
 wire r213f_enable_w = (SNES_PA == 8'h3f);
-reg [5:0] r213f_enable_r;
-initial r213f_enable_r = 6'b000000;
-always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
-assign r213f_enable = &r213f_enable_r[5:2];
+assign r213f_enable = r213f_enable_w;
+
+wire snescmd_rd_enable_w = (SNES_PA[7:4] == 4'b1111);
+assign snescmd_rd_enable = snescmd_rd_enable_w;
+
+wire snescmd_wr_enable_w = (SNES_ADDR[23:4] == 20'hccccc);
+assign snescmd_wr_enable = snescmd_wr_enable_w;
 
 endmodule

verilog/sd2snes_cx4/cx4.v

@@ -334,6 +334,7 @@ always @(posedge CLK) begin
         CACHE_ST <= ST_CACHE_START;
         cache_pgmpage <= cx4_mmio_pgmpage;
         cache_cachepage <= cx4_mmio_cachepage;
+		  cx4_busy[BUSY_CACHE] <= 1'b1;
       end else if(cpu_cache_en
          & (~cachevalid[~cpu_page]
             | |(cachetag[~cpu_page] ^ cpu_p))) begin
@@ -431,7 +432,7 @@ end
 /***************************
  =========== CPU ===========
  ***************************/
-reg [4:0] CPU_STATE;
+reg [5:0] CPU_STATE;
 reg [2:0] cpu_sp;
 initial cpu_sp = 3'b000;
 wire [15:0] cpu_op_w;
@@ -451,16 +452,19 @@ reg [23:0] cpu_dummy;
 reg [23:0] cpu_tmp;
 
 reg [23:0] cpu_sa;  // tmp register for shifted accumulator
+reg [7:0] cpu_wait;
+initial cpu_wait = 8'h00;
 
 wire [9:0] cx4_datrom_addr = cpu_a[9:0];
 wire [23:0] cx4_datrom_do;
 wire [7:0] cx4_datram_do;
 
-parameter ST_CPU_IDLE = 5'b00001;
-parameter ST_CPU_0    = 5'b00010;
-parameter ST_CPU_1    = 5'b00100;
-parameter ST_CPU_2    = 5'b01000;
-parameter ST_CPU_3    = 5'b10000;
+parameter ST_CPU_IDLE = 6'b000001;
+parameter ST_CPU_0    = 6'b000010;
+parameter ST_CPU_1    = 6'b000100;
+parameter ST_CPU_2    = 6'b001000;
+parameter ST_CPU_3    = 6'b010000;
+parameter ST_CPU_4    = 6'b100000;
 
 initial CPU_STATE = ST_CPU_IDLE;
 
@@ -636,7 +640,7 @@ always @(posedge CLK) begin
           cpu_sp <= cpu_sp - 1;
         end
         OP_WAI: if(BUS_RDY) cpu_pc <= cpu_pc + 1;
-        OP_BUS: begin 
+        OP_BUS: begin
           cpu_bus_rq <= 1'b0;
           cpu_pc <= cpu_pc + 1;
         end
@@ -710,7 +714,6 @@ always @(posedge CLK) begin
       endcase
     end
     ST_CPU_3: begin
-      CPU_STATE <= ST_CPU_0;
       case(op)
         OP_BUS: cpu_busaddr <= cpu_busaddr + 1;
         OP_WRRAM: cx4_cpu_datram_we <= 1'b0;
@@ -747,6 +750,29 @@ always @(posedge CLK) begin
         end
       endcase
       cpu_op <= cpu_op_w;
+		casex(cpu_op_w[15:11])
+        5'b00x01, 5'b00x10, 5'b00100, 5'b00111: begin
+		    cpu_wait <= 8'h07;
+	       CPU_STATE <= ST_CPU_4;
+		  end
+        5'b01110, 5'b01101, 5'b11101: begin
+		    cpu_wait <= 8'h03;
+	       CPU_STATE <= ST_CPU_4;
+		  end
+        /*5'b10011: begin
+		    cpu_wait <= 8'h02;
+	       CPU_STATE <= ST_CPU_4;
+		  end
+        5'b01000: begin
+		    cpu_wait <= 8'h0e;
+	       CPU_STATE <= ST_CPU_4;
+		  end*/
+		  default: begin
+		    cpu_wait <= 8'h00;
+	       CPU_STATE <= ST_CPU_0;
+		  end
+		endcase
+		
       casex(cpu_op_w[15:11])
         5'b00000: op <= OP_NOP;
 
@@ -790,6 +816,11 @@ always @(posedge CLK) begin
       op_param <= cpu_op_w[7:0];
       op_sa <= cpu_op_w[9:8];
     end
+    ST_CPU_4: begin
+	   cpu_wait <= cpu_wait - 1;
+	   if(cpu_wait) CPU_STATE <= ST_CPU_4;
+		else CPU_STATE <= ST_CPU_0;
+	 end
   endcase
 end
 

verilog/sd2snes_cx4/dac.v

@@ -31,6 +31,7 @@ module dac(
   output sdout,
   output lrck,
   output mclk,
+  output sclk,
   output DAC_STATUS
 );
 
@@ -68,14 +69,15 @@ reg [15:0] smpshift;
 
 assign mclk = cnt[2]; // mclk = clk/8
 assign lrck = cnt[8]; // lrck = mclk/128
-wire sclk = cnt[3];   // sclk = lrck*32
+assign sclk = cnt[3]; // sclk = lrck*32
 
 reg [2:0] lrck_sreg;
 reg [2:0] sclk_sreg;
-wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01);
-wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10);
+wire lrck_rising = (lrck_sreg[1:0] == 2'b01);
+wire lrck_falling = (lrck_sreg[1:0] == 2'b10);
 
-wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01);
+wire sclk_rising = (sclk_sreg[1:0] == 2'b01);
+wire sclk_falling = (sclk_sreg[1:0] == 2'b10);
 
 wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
 reg sdout_reg;
@@ -143,15 +145,15 @@ always @(posedge clkin) begin
 end
 
 always @(posedge clkin) begin
-  if (lrck_rising) begin // right channel
-    smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
-    samples <= samples + 1;
-  end else if (lrck_falling) begin // left channel
-    smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
-  end else begin
-    if (sclk_rising) begin
-      smpcnt <= smpcnt + 1;
-      sdout_reg <= smpshift[15];
+  if (sclk_falling) begin
+    smpcnt <= smpcnt + 1;
+    sdout_reg <= smpshift[15];
+    if (lrck_rising) begin // right channel
+      smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
+      samples <= samples + 1;
+    end else if (lrck_falling) begin // left channel
+      smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
+    end else begin
       smpshift <= {smpshift[14:0], 1'b0};
     end
   end

verilog/sd2snes_cx4/main.ucf

@@ -1,5 +1,5 @@
 NET "CLKIN" TNM_NET = "CLKIN";
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.1 MHz HIGH 50 %;
 //TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
 NET "p113_out" IOSTANDARD = LVCMOS33;
 NET "p113_out" LOC = P113;
@@ -10,7 +10,7 @@ TIMESPEC TS_SNES_SYSCLK = PERIOD "SNES_SYSCLK" 21.5 MHz HIGH 50 %;
 NET "SPI_SCK" LOC = P71;
 NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
 NET "SPI_SCK" TNM_NET = "SPI_SCK";
-TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48MHz HIGH 50 %;
+TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 44.2 MHz HIGH 50 %;
 
 NET "SPI_SCK" IOSTANDARD = LVCMOS33;
 NET "SPI_SCK" DRIVE = 8;
@@ -35,30 +35,30 @@ NET "ROM_CE" LOC = P172;
 NET "ROM_CE" IOSTANDARD = LVCMOS33;
 NET "ROM_CE" DRIVE = 8;
 
-NET "SNES_ADDR[0]" LOC = P119;
-NET "SNES_ADDR[10]" LOC = P146;
-NET "SNES_ADDR[11]" LOC = P148;
-NET "SNES_ADDR[12]" LOC = P147;
-NET "SNES_ADDR[13]" LOC = P144;
-NET "SNES_ADDR[14]" LOC = P141;
-NET "SNES_ADDR[15]" LOC = P139;
-NET "SNES_ADDR[16]" LOC = P137;
-NET "SNES_ADDR[17]" LOC = P133;
-NET "SNES_ADDR[18]" LOC = P131;
-NET "SNES_ADDR[19]" LOC = P128;
-NET "SNES_ADDR[1]" LOC = P122;
-NET "SNES_ADDR[20]" LOC = P125;
-NET "SNES_ADDR[21]" LOC = P123;
-NET "SNES_ADDR[22]" LOC = P120;
-NET "SNES_ADDR[23]" LOC = P117;
-NET "SNES_ADDR[2]" LOC = P124;
-NET "SNES_ADDR[3]" LOC = P126;
-NET "SNES_ADDR[4]" LOC = P130;
-NET "SNES_ADDR[5]" LOC = P132;
-NET "SNES_ADDR[6]" LOC = P135;
-NET "SNES_ADDR[7]" LOC = P138;
-NET "SNES_ADDR[8]" LOC = P140;
-NET "SNES_ADDR[9]" LOC = P143;
+NET "SNES_ADDR_IN[0]" LOC = P119;
+NET "SNES_ADDR_IN[10]" LOC = P146;
+NET "SNES_ADDR_IN[11]" LOC = P148;
+NET "SNES_ADDR_IN[12]" LOC = P147;
+NET "SNES_ADDR_IN[13]" LOC = P144;
+NET "SNES_ADDR_IN[14]" LOC = P141;
+NET "SNES_ADDR_IN[15]" LOC = P139;
+NET "SNES_ADDR_IN[16]" LOC = P137;
+NET "SNES_ADDR_IN[17]" LOC = P133;
+NET "SNES_ADDR_IN[18]" LOC = P131;
+NET "SNES_ADDR_IN[19]" LOC = P128;
+NET "SNES_ADDR_IN[1]" LOC = P122;
+NET "SNES_ADDR_IN[20]" LOC = P125;
+NET "SNES_ADDR_IN[21]" LOC = P123;
+NET "SNES_ADDR_IN[22]" LOC = P120;
+NET "SNES_ADDR_IN[23]" LOC = P117;
+NET "SNES_ADDR_IN[2]" LOC = P124;
+NET "SNES_ADDR_IN[3]" LOC = P126;
+NET "SNES_ADDR_IN[4]" LOC = P130;
+NET "SNES_ADDR_IN[5]" LOC = P132;
+NET "SNES_ADDR_IN[6]" LOC = P135;
+NET "SNES_ADDR_IN[7]" LOC = P138;
+NET "SNES_ADDR_IN[8]" LOC = P140;
+NET "SNES_ADDR_IN[9]" LOC = P143;
 NET "SNES_DATA[0]" LOC = P107;
 NET "SNES_DATA[1]" LOC = P102;
 NET "SNES_DATA[2]" LOC = P100;
@@ -381,54 +381,54 @@ NET "ROM_WE" LOC = P190;
 
 NET "ROM_WE" IOSTANDARD = LVCMOS33;
 NET "ROM_WE" DRIVE = 8;
-NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[0]" DRIVE = 8;
-NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[10]" DRIVE = 8;
-NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[11]" DRIVE = 8;
-NET "SNES_ADDR[12]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[12]" DRIVE = 8;
-NET "SNES_ADDR[13]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[13]" DRIVE = 8;
-NET "SNES_ADDR[14]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[14]" DRIVE = 8;
-NET "SNES_ADDR[15]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[15]" DRIVE = 8;
-NET "SNES_ADDR[16]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[16]" DRIVE = 8;
-NET "SNES_ADDR[17]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[17]" DRIVE = 8;
-NET "SNES_ADDR[18]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[18]" DRIVE = 8;
-NET "SNES_ADDR[19]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[19]" DRIVE = 8;
-NET "SNES_ADDR[1]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[1]" DRIVE = 8;
-NET "SNES_ADDR[20]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[20]" DRIVE = 8;
-NET "SNES_ADDR[21]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[21]" DRIVE = 8;
-NET "SNES_ADDR[22]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[22]" DRIVE = 8;
-NET "SNES_ADDR[23]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[23]" DRIVE = 8;
-NET "SNES_ADDR[2]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[2]" DRIVE = 8;
-NET "SNES_ADDR[3]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[3]" DRIVE = 8;
-NET "SNES_ADDR[4]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[4]" DRIVE = 8;
-NET "SNES_ADDR[5]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[5]" DRIVE = 8;
-NET "SNES_ADDR[6]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[6]" DRIVE = 8;
-NET "SNES_ADDR[7]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[7]" DRIVE = 8;
-NET "SNES_ADDR[8]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[8]" DRIVE = 8;
-NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33;
-NET "SNES_ADDR[9]" DRIVE = 8;
+NET "SNES_ADDR_IN[0]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[0]" DRIVE = 8;
+NET "SNES_ADDR_IN[10]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[10]" DRIVE = 8;
+NET "SNES_ADDR_IN[11]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[11]" DRIVE = 8;
+NET "SNES_ADDR_IN[12]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[12]" DRIVE = 8;
+NET "SNES_ADDR_IN[13]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[13]" DRIVE = 8;
+NET "SNES_ADDR_IN[14]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[14]" DRIVE = 8;
+NET "SNES_ADDR_IN[15]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[15]" DRIVE = 8;
+NET "SNES_ADDR_IN[16]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[16]" DRIVE = 8;
+NET "SNES_ADDR_IN[17]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[17]" DRIVE = 8;
+NET "SNES_ADDR_IN[18]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[18]" DRIVE = 8;
+NET "SNES_ADDR_IN[19]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[19]" DRIVE = 8;
+NET "SNES_ADDR_IN[1]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[1]" DRIVE = 8;
+NET "SNES_ADDR_IN[20]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[20]" DRIVE = 8;
+NET "SNES_ADDR_IN[21]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[21]" DRIVE = 8;
+NET "SNES_ADDR_IN[22]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[22]" DRIVE = 8;
+NET "SNES_ADDR_IN[23]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[23]" DRIVE = 8;
+NET "SNES_ADDR_IN[2]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[2]" DRIVE = 8;
+NET "SNES_ADDR_IN[3]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[3]" DRIVE = 8;
+NET "SNES_ADDR_IN[4]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[4]" DRIVE = 8;
+NET "SNES_ADDR_IN[5]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[5]" DRIVE = 8;
+NET "SNES_ADDR_IN[6]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[6]" DRIVE = 8;
+NET "SNES_ADDR_IN[7]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[7]" DRIVE = 8;
+NET "SNES_ADDR_IN[8]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[8]" DRIVE = 8;
+NET "SNES_ADDR_IN[9]" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR_IN[9]" DRIVE = 8;
 
 
 NET "SNES_CPU_CLK" LOC = P95;
@@ -594,7 +594,7 @@ TIMESPEC TS_CX4_MUL = FROM "CX4_MUL_downstream" TO "cx4_cpu_idb" TS_CLK21 / 2;
 TIMEGRP "CX4_FL_Z" = FFS("*cx4*fl_z*");
 TIMEGRP "CX4_FL_C" = FFS("*cx4*fl_c*");
 TIMEGRP "CX4_FL_N" = FFS("*cx4*fl_n*");
-TIMEGRP "CX4_MULT" = MULTS("snes_cx4/cx4_mul/sig000000e5") MULTS("snes_cx4/cx4_mul/sig000000e4") MULTS("snes_cx4/cx4_mul/sig000000e3") MULTS("snes_cx4/cx4_mul/sig000000e2") MULTS("snes_cx4/cx4_mul/sig000000ee") MULTS("snes_cx4/cx4_mul/sig000000ed") MULTS("snes_cx4/cx4_mul/sig000000ec") MULTS("snes_cx4/cx4_mul/sig000000eb") MULTS("snes_cx4/cx4_mul/sig000000ea") MULTS("snes_cx4/cx4_mul/sig000000e9") MULTS("snes_cx4/cx4_mul/sig000000e8") MULTS("snes_cx4/cx4_mul/sig000000e7") MULTS("snes_cx4/cx4_mul/sig000000e6") MULTS("snes_cx4/cx4_mul/sig000000e1") MULTS("snes_cx4/cx4_mul/sig000000d8") MULTS("snes_cx4/cx4_mul/sig000000d7") MULTS("snes_cx4/cx4_mul/sig000000d6") MULTS("snes_cx4/cx4_mul/sig000000d5") MULTS("snes_cx4/cx4_mul/sig000000d3") MULTS("snes_cx4/cx4_mul/sig000000d2") MULTS("snes_cx4/cx4_mul/sig000000d1") MULTS("snes_cx4/cx4_mul/sig000000d0") MULTS("snes_cx4/cx4_mul/sig000000cf") MULTS("snes_cx4/cx4_mul/sig000000ce") MULTS("snes_cx4/cx4_mul/sig000000cd") MULTS("snes_cx4/cx4_mul/sig000000cc") MULTS("snes_cx4/cx4_mul/sig000000cb") MULTS("snes_cx4/cx4_mul/sig000000ca") MULTS("snes_cx4/cx4_mul/sig000000e0") MULTS("snes_cx4/cx4_mul/sig000000df") MULTS("snes_cx4/cx4_mul/sig000000de") MULTS("snes_cx4/cx4_mul/sig000000dd") MULTS("snes_cx4/cx4_mul/sig000000dc") MULTS("snes_cx4/cx4_mul/sig000000db") MULTS("snes_cx4/cx4_mul/sig000000da") MULTS("snes_cx4/cx4_mul/sig000000d9") MULTS("snes_cx4/cx4_mul/sig000000d4") MULTS("snes_cx4/cx4_mul/sig000000c9") MULTS("snes_cx4/cx4_mul/sig000000c0") MULTS("snes_cx4/cx4_mul/sig000000bf") MULTS("snes_cx4/cx4_mul/sig000000be") MULTS("snes_cx4/cx4_mul/sig000000bd") MULTS("snes_cx4/cx4_mul/sig000000bb") MULTS("snes_cx4/cx4_mul/sig000000ba") MULTS("snes_cx4/cx4_mul/sig000000b9") MULTS("snes_cx4/cx4_mul/sig000000b8") MULTS("snes_cx4/cx4_mul/sig000000b7") MULTS("snes_cx4/cx4_mul/sig000000b6") MULTS("snes_cx4/cx4_mul/sig000000b5") MULTS("snes_cx4/cx4_mul/sig000000b4") MULTS("snes_cx4/cx4_mul/sig000000b3") MULTS("snes_cx4/cx4_mul/sig000000b2") MULTS("snes_cx4/cx4_mul/sig000000c8") MULTS("snes_cx4/cx4_mul/sig000000c7") MULTS("snes_cx4/cx4_mul/sig000000c6") MULTS("snes_cx4/cx4_mul/sig000000c5") MULTS("snes_cx4/cx4_mul/sig000000c4") MULTS("snes_cx4/cx4_mul/sig000000c3") MULTS("snes_cx4/cx4_mul/sig000000c2") MULTS("snes_cx4/cx4_mul/sig000000c1") MULTS("snes_cx4/cx4_mul/sig000000bc") MULTS("snes_cx4/cx4_mul/sig000000b1") MULTS("snes_cx4/cx4_mul/sig000000a9") MULTS("snes_cx4/cx4_mul/sig000000a8") MULTS("snes_cx4/cx4_mul/sig000000a7") MULTS("snes_cx4/cx4_mul/sig000000a6") MULTS("snes_cx4/cx4_mul/sig000000a5") MULTS("snes_cx4/cx4_mul/sig000000a3") MULTS("snes_cx4/cx4_mul/sig000000a2") MULTS("snes_cx4/cx4_mul/sig000000a1") MULTS("snes_cx4/cx4_mul/sig000000a0") MULTS("snes_cx4/cx4_mul/sig0000009f") MULTS("snes_cx4/cx4_mul/sig0000009e") MULTS("snes_cx4/cx4_mul/sig0000009d") MULTS("snes_cx4/cx4_mul/sig0000009c") MULTS("snes_cx4/cx4_mul/sig0000009b") MULTS("snes_cx4/cx4_mul/sig0000009a") MULTS("snes_cx4/cx4_mul/sig00000098") MULTS("snes_cx4/cx4_mul/sig00000097") MULTS("snes_cx4/cx4_mul/sig00000096") MULTS("snes_cx4/cx4_mul/sig00000095") MULTS("snes_cx4/cx4_mul/sig00000094") MULTS("snes_cx4/cx4_mul/sig00000093") MULTS("snes_cx4/cx4_mul/sig00000092") MULTS("snes_cx4/cx4_mul/sig00000091") MULTS("snes_cx4/cx4_mul/sig00000090") MULTS("snes_cx4/cx4_mul/sig0000008f") MULTS("snes_cx4/cx4_mul/sig000000b0") MULTS("snes_cx4/cx4_mul/sig000000af") MULTS("snes_cx4/cx4_mul/sig000000ae") MULTS("snes_cx4/cx4_mul/sig000000ad") MULTS("snes_cx4/cx4_mul/sig000000ac") MULTS("snes_cx4/cx4_mul/sig000000ab") MULTS("snes_cx4/cx4_mul/sig000000aa") MULTS("snes_cx4/cx4_mul/sig000000a4") MULTS("snes_cx4/cx4_mul/sig00000099") MULTS("snes_cx4/cx4_mul/sig0000008e");
+#TIMEGRP "CX4_MULT" = MULTS("snes_cx4/cx4_mul/sig000000e5") MULTS("snes_cx4/cx4_mul/sig000000e4") MULTS("snes_cx4/cx4_mul/sig000000e3") MULTS("snes_cx4/cx4_mul/sig000000e2") MULTS("snes_cx4/cx4_mul/sig000000ee") MULTS("snes_cx4/cx4_mul/sig000000ed") MULTS("snes_cx4/cx4_mul/sig000000ec") MULTS("snes_cx4/cx4_mul/sig000000eb") MULTS("snes_cx4/cx4_mul/sig000000ea") MULTS("snes_cx4/cx4_mul/sig000000e9") MULTS("snes_cx4/cx4_mul/sig000000e8") MULTS("snes_cx4/cx4_mul/sig000000e7") MULTS("snes_cx4/cx4_mul/sig000000e6") MULTS("snes_cx4/cx4_mul/sig000000e1") MULTS("snes_cx4/cx4_mul/sig000000d8") MULTS("snes_cx4/cx4_mul/sig000000d7") MULTS("snes_cx4/cx4_mul/sig000000d6") MULTS("snes_cx4/cx4_mul/sig000000d5") MULTS("snes_cx4/cx4_mul/sig000000d3") MULTS("snes_cx4/cx4_mul/sig000000d2") MULTS("snes_cx4/cx4_mul/sig000000d1") MULTS("snes_cx4/cx4_mul/sig000000d0") MULTS("snes_cx4/cx4_mul/sig000000cf") MULTS("snes_cx4/cx4_mul/sig000000ce") MULTS("snes_cx4/cx4_mul/sig000000cd") MULTS("snes_cx4/cx4_mul/sig000000cc") MULTS("snes_cx4/cx4_mul/sig000000cb") MULTS("snes_cx4/cx4_mul/sig000000ca") MULTS("snes_cx4/cx4_mul/sig000000e0") MULTS("snes_cx4/cx4_mul/sig000000df") MULTS("snes_cx4/cx4_mul/sig000000de") MULTS("snes_cx4/cx4_mul/sig000000dd") MULTS("snes_cx4/cx4_mul/sig000000dc") MULTS("snes_cx4/cx4_mul/sig000000db") MULTS("snes_cx4/cx4_mul/sig000000da") MULTS("snes_cx4/cx4_mul/sig000000d9") MULTS("snes_cx4/cx4_mul/sig000000d4") MULTS("snes_cx4/cx4_mul/sig000000c9") MULTS("snes_cx4/cx4_mul/sig000000c0") MULTS("snes_cx4/cx4_mul/sig000000bf") MULTS("snes_cx4/cx4_mul/sig000000be") MULTS("snes_cx4/cx4_mul/sig000000bd") MULTS("snes_cx4/cx4_mul/sig000000bb") MULTS("snes_cx4/cx4_mul/sig000000ba") MULTS("snes_cx4/cx4_mul/sig000000b9") MULTS("snes_cx4/cx4_mul/sig000000b8") MULTS("snes_cx4/cx4_mul/sig000000b7") MULTS("snes_cx4/cx4_mul/sig000000b6") MULTS("snes_cx4/cx4_mul/sig000000b5") MULTS("snes_cx4/cx4_mul/sig000000b4") MULTS("snes_cx4/cx4_mul/sig000000b3") MULTS("snes_cx4/cx4_mul/sig000000b2") MULTS("snes_cx4/cx4_mul/sig000000c8") MULTS("snes_cx4/cx4_mul/sig000000c7") MULTS("snes_cx4/cx4_mul/sig000000c6") MULTS("snes_cx4/cx4_mul/sig000000c5") MULTS("snes_cx4/cx4_mul/sig000000c4") MULTS("snes_cx4/cx4_mul/sig000000c3") MULTS("snes_cx4/cx4_mul/sig000000c2") MULTS("snes_cx4/cx4_mul/sig000000c1") MULTS("snes_cx4/cx4_mul/sig000000bc") MULTS("snes_cx4/cx4_mul/sig000000b1") MULTS("snes_cx4/cx4_mul/sig000000a9") MULTS("snes_cx4/cx4_mul/sig000000a8") MULTS("snes_cx4/cx4_mul/sig000000a7") MULTS("snes_cx4/cx4_mul/sig000000a6") MULTS("snes_cx4/cx4_mul/sig000000a5") MULTS("snes_cx4/cx4_mul/sig000000a3") MULTS("snes_cx4/cx4_mul/sig000000a2") MULTS("snes_cx4/cx4_mul/sig000000a1") MULTS("snes_cx4/cx4_mul/sig000000a0") MULTS("snes_cx4/cx4_mul/sig0000009f") MULTS("snes_cx4/cx4_mul/sig0000009e") MULTS("snes_cx4/cx4_mul/sig0000009d") MULTS("snes_cx4/cx4_mul/sig0000009c") MULTS("snes_cx4/cx4_mul/sig0000009b") MULTS("snes_cx4/cx4_mul/sig0000009a") MULTS("snes_cx4/cx4_mul/sig00000098") MULTS("snes_cx4/cx4_mul/sig00000097") MULTS("snes_cx4/cx4_mul/sig00000096") MULTS("snes_cx4/cx4_mul/sig00000095") MULTS("snes_cx4/cx4_mul/sig00000094") MULTS("snes_cx4/cx4_mul/sig00000093") MULTS("snes_cx4/cx4_mul/sig00000092") MULTS("snes_cx4/cx4_mul/sig00000091") MULTS("snes_cx4/cx4_mul/sig00000090") MULTS("snes_cx4/cx4_mul/sig0000008f") MULTS("snes_cx4/cx4_mul/sig000000b0") MULTS("snes_cx4/cx4_mul/sig000000af") MULTS("snes_cx4/cx4_mul/sig000000ae") MULTS("snes_cx4/cx4_mul/sig000000ad") MULTS("snes_cx4/cx4_mul/sig000000ac") MULTS("snes_cx4/cx4_mul/sig000000ab") MULTS("snes_cx4/cx4_mul/sig000000aa") MULTS("snes_cx4/cx4_mul/sig000000a4") MULTS("snes_cx4/cx4_mul/sig00000099") MULTS("snes_cx4/cx4_mul/sig0000008e");
 TIMEGRP "CX4_MUL_FF" = FFS("snes_cx4/cx4_mul/sig00000129") FFS("snes_cx4/cx4_mul/sig00000128") FFS("snes_cx4/cx4_mul/sig00000127") FFS("snes_cx4/cx4_mul/sig00000126") FFS("snes_cx4/cx4_mul/sig00000124") FFS("snes_cx4/cx4_mul/sig00000123") FFS("snes_cx4/cx4_mul/sig00000122") FFS("snes_cx4/cx4_mul/sig00000121") FFS("snes_cx4/cx4_mul/sig00000120") FFS("snes_cx4/cx4_mul/sig0000011f") FFS("snes_cx4/cx4_mul/sig0000011e") FFS("snes_cx4/cx4_mul/sig0000011d") FFS("snes_cx4/cx4_mul/sig0000011c") FFS("snes_cx4/cx4_mul/sig0000011b") FFS("snes_cx4/cx4_mul/sig00000130") FFS("snes_cx4/cx4_mul/sig0000012f") FFS("snes_cx4/cx4_mul/sig0000012e") FFS("snes_cx4/cx4_mul/sig0000012d") FFS("snes_cx4/cx4_mul/sig0000012c") FFS("snes_cx4/cx4_mul/sig0000012b") FFS("snes_cx4/cx4_mul/sig0000012a") FFS("snes_cx4/cx4_mul/sig00000125") FFS("snes_cx4/cx4_mul/sig0000011a") FFS("snes_cx4/cx4_mul/sig00000119") FFS("snes_cx4/cx4_mul/sig00000111") FFS("snes_cx4/cx4_mul/sig00000110") FFS("snes_cx4/cx4_mul/sig0000010f") FFS("snes_cx4/cx4_mul/sig0000010e") FFS("snes_cx4/cx4_mul/sig0000010c") FFS("snes_cx4/cx4_mul/sig0000010b") FFS("snes_cx4/cx4_mul/sig0000010a") FFS("snes_cx4/cx4_mul/sig00000109") FFS("snes_cx4/cx4_mul/sig00000108") FFS("snes_cx4/cx4_mul/sig00000107") FFS("snes_cx4/cx4_mul/sig00000106") FFS("snes_cx4/cx4_mul/sig00000105") FFS("snes_cx4/cx4_mul/sig00000104") FFS("snes_cx4/cx4_mul/sig00000103") FFS("snes_cx4/cx4_mul/sig00000118") FFS("snes_cx4/cx4_mul/sig00000117") FFS("snes_cx4/cx4_mul/sig00000116") FFS("snes_cx4/cx4_mul/sig00000133") FFS("snes_cx4/cx4_mul/sig0000013e") FFS("snes_cx4/cx4_mul/sig0000013d") FFS("snes_cx4/cx4_mul/sig0000013c") FFS("snes_cx4/cx4_mul/sig0000013b") FFS("snes_cx4/cx4_mul/sig0000013a") FFS("snes_cx4/cx4_mul/sig000000fb") FFS("snes_cx4/cx4_mul/sig000000fa") FFS("snes_cx4/cx4_mul/sig000000f9") FFS("snes_cx4/cx4_mul/sig000000f8") FFS("snes_cx4/cx4_mul/sig000000f7") FFS("snes_cx4/cx4_mul/sig000000f6") FFS("snes_cx4/cpu_mul_result<13>") FFS("snes_cx4/cpu_mul_result<12>") FFS("snes_cx4/cpu_mul_result<11>") FFS("snes_cx4/cpu_mul_result<10>") FFS("snes_cx4/cpu_mul_result<9>") FFS("snes_cx4/cpu_mul_result<8>") FFS("snes_cx4/cx4_mul/sig00000115") FFS("snes_cx4/cx4_mul/sig00000114") FFS("snes_cx4/cx4_mul/sig00000113") FFS("snes_cx4/cx4_mul/sig00000112") FFS("snes_cx4/cx4_mul/sig0000010d") FFS("snes_cx4/cx4_mul/sig00000102") FFS("snes_cx4/cx4_mul/sig00000101") FFS("snes_cx4/cx4_mul/sig00000136") FFS("snes_cx4/cx4_mul/sig00000135") FFS("snes_cx4/cx4_mul/sig00000134") FFS("snes_cx4/cx4_mul/sig00000139") FFS("snes_cx4/cx4_mul/sig00000138") FFS("snes_cx4/cx4_mul/sig00000137") FFS("snes_cx4/cx4_mul/sig00000132") FFS("snes_cx4/cx4_mul/sig00000131") FFS("snes_cx4/cx4_mul/sig00000100") FFS("snes_cx4/cx4_mul/sig000000ff") FFS("snes_cx4/cx4_mul/sig000000fe") FFS("snes_cx4/cx4_mul/sig000000fd") FFS("snes_cx4/cx4_mul/sig000000fc") FFS("snes_cx4/cx4_mul/sig000000f5") FFS("snes_cx4/cx4_mul/sig000000f4") FFS("snes_cx4/cx4_mul/sig000000f3") FFS("snes_cx4/cx4_mul/sig000000f2") FFS("snes_cx4/cx4_mul/sig000000f1") FFS("snes_cx4/cx4_mul/sig000000f0") FFS("snes_cx4/cx4_mul/sig000000ef") FFS("snes_cx4/cpu_mul_result<16>") FFS("snes_cx4/cpu_mul_result<15>") FFS("snes_cx4/cpu_mul_result<14>") FFS("snes_cx4/cpu_mul_result<7>") FFS("snes_cx4/cpu_mul_result<6>") FFS("snes_cx4/cpu_mul_result<5>") FFS("snes_cx4/cpu_mul_result<4>") FFS("snes_cx4/cpu_mul_result<3>") FFS("snes_cx4/cpu_mul_result<2>") FFS("snes_cx4/cpu_mul_result<1>") FFS("snes_cx4/cpu_mul_result<0>") FFS("snes_cx4/Mmult__COND_15_Madd_cy<2>11_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_cy<2>11_FRB_1") FFS("snes_cx4/Mmult__COND_15_Madd_cy<3>11_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_cy<3>11_FRB_1") FFS("snes_cx4/Mmult__COND_15_Madd_lut<1>1_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_lut<1>1_FRB_1") FFS("snes_cx4/Mmult__COND_15_Madd_lut<1>1_FRB_2") FFS("snes_cx4/Mmult__COND_15_Madd_lut<2>1_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_lut<3>1_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_lut<3>1_FRB_1");
 #Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30
 TIMESPEC TS_CX4_MUL2 = FROM "MULTS" TO "cx4_cpu_idb" TS_CLK21 / 2;

verilog/sd2snes_cx4/main.v

@@ -23,7 +23,7 @@ module main(
   input CLKIN,
 
   /* SNES signals */
-  input [23:0] SNES_ADDR,
+  input [23:0] SNES_ADDR_IN,
   input SNES_READ,
   input SNES_WRITE,
   input SNES_CS,
@@ -38,7 +38,7 @@ module main(
   input [7:0] SNES_PA,
   input SNES_PARD,
   input SNES_PAWR,
-
+  
   /* SRAM signals */
   /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
   inout [15:0] ROM_DATA,
@@ -77,6 +77,19 @@ module main(
   output p113_out
 );
 
+wire CLK2;
+
+reg [23:0] SNES_ADDR_r [2:0];
+always @(posedge CLK2) begin
+  SNES_ADDR_r[2] <= SNES_ADDR_r[1];
+  SNES_ADDR_r[1] <= SNES_ADDR_r[0];
+  SNES_ADDR_r[0] <= SNES_ADDR_IN;
+end
+wire [23:0] SNES_ADDR = SNES_ADDR_r[2] & SNES_ADDR_r[1];
+
+wire [7:0] CX4_SNES_DATA_IN;
+wire [7:0] CX4_SNES_DATA_OUT;
+
 wire [7:0] spi_cmd_data;
 wire [7:0] spi_param_data;
 wire [7:0] spi_input_data;
@@ -92,7 +105,6 @@ wire [10:0] SD_DMA_PARTIAL_START;
 wire [10:0] SD_DMA_PARTIAL_END;
 
 wire [10:0] dac_addr;
-//wire [7:0] dac_volume;
 wire [7:0] msu_volumerq_out;
 wire [6:0] msu_status_out;
 wire [31:0] msu_addressrq_out;
@@ -104,9 +116,6 @@ wire [7:0] MSU_SNES_DATA_OUT;
 wire [5:0] msu_status_reset_bits;
 wire [5:0] msu_status_set_bits;
 
-wire [7:0] CX4_SNES_DATA_IN;
-wire [7:0] CX4_SNES_DATA_OUT;
-
 wire [23:0] MAPPED_SNES_ADDR;
 wire ROM_ADDR0;
 
@@ -239,9 +248,9 @@ mcu_cmd snes_mcu_cmd(
   .mcu_wrq(MCU_WRQ),
   .mcu_rq_rdy(MCU_RDY),
   .use_msu1(use_msu1),
-  .cx4_datrom_addr_out(cx4_datrom_addr), 
-  .cx4_datrom_data_out(cx4_datrom_data), 
-  .cx4_datrom_we_out(cx4_datrom_we), 
+  .cx4_datrom_addr_out(cx4_datrom_addr),
+  .cx4_datrom_data_out(cx4_datrom_data),
+  .cx4_datrom_we_out(cx4_datrom_we),
   .cx4_reset_out(cx4_reset),
   .region_out(mcu_region)
 );
@@ -256,33 +265,37 @@ my_dcm snes_dcm(
   .STATUS(DCM_STATUS)
 );
 
-my_dcm snes_dcm2(
-  .CLKIN(SNES_SYSCLK),
-  .CLKFX(SYSCLK2),
-  .RST(DCM_RST)
-);
-
 assign DCM_RST=0;
 
-reg [5:0] SNES_PARDr;
-reg [5:0] SNES_READr;
-reg [5:0] SNES_WRITEr;
-reg [5:0] SNES_CPU_CLKr;
+reg [7:0] SNES_PARDr;
+reg [7:0] SNES_PAWRr;
+reg [7:0] SNES_READr;
+reg [7:0] SNES_WRITEr;
+reg [7:0] SNES_CPU_CLKr;
 
-wire SNES_PARD_start = (SNES_PARDr == 6'b111110);
-wire SNES_RD_start = (SNES_READr == 6'b111110);
-wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
-wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
-wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
+wire SNES_FAKE_CLK = &SNES_CPU_CLKr[2:1];
+//wire SNES_FAKE_CLK = ~(SNES_READ & SNES_WRITE);
 
-always @(posedge SYSCLK2) begin
-  SNES_PARDr <= {SNES_PARDr[4:0], SNES_PARD};
+reg SNES_DEADr;
+initial SNES_DEADr = 0;
+
+wire SNES_PARD_start = (SNES_PARDr[7:1] == 7'b1111110);
+wire SNES_PAWR_start = (SNES_PAWRr[7:1] == 7'b0000001);
+wire SNES_RD_start = (SNES_READr[7:1] == 7'b1111110);
+wire SNES_WR_start = (SNES_WRITEr[7:1] == 7'b1111110);
+wire SNES_WR_end = (SNES_WRITEr[7:1] == 7'b0000001);
+wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000001);
+wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b111110);
+
+always @(posedge CLK2) begin
+  SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD};
 end
 
 always @(posedge CLK2) begin
-  SNES_READr <= {SNES_READr[4:0], SNES_READ};
-  SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
-  SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
+  SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR};
+  SNES_READr <= {SNES_READr[6:0], SNES_READ};
+  SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE};
+  SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK};
 end
 
 address snes_addr(
@@ -304,7 +317,11 @@ address snes_addr(
   //CX4
   .cx4_enable(cx4_enable),
   .cx4_vect_enable(cx4_vect_enable),
-  .r213f_enable(r213f_enable)
+  //region
+  .r213f_enable(r213f_enable),
+  //CMD Interface
+  .snescmd_rd_enable(snescmd_rd_enable),
+  .snescmd_wr_enable(snescmd_wr_enable)
 );
 
 reg [7:0] CX4_DINr;
@@ -313,9 +330,9 @@ wire [23:0] CX4_ADDR;
 cx4 snes_cx4 (
     .DI(CX4_SNES_DATA_IN), 
     .DO(CX4_SNES_DATA_OUT), 
-    .ADDR(SNES_ADDR[12:0]),
+    .ADDR(SNES_ADDR[12:0]), 
     .CS(cx4_enable), 
-    .SNES_VECT_EN(cx4_vect_enable),
+    .SNES_VECT_EN(cx4_vect_enable), 
     .nRD(SNES_READ), 
     .nWR(SNES_WRITE), 
     .CLK(CLK2), 
@@ -325,10 +342,10 @@ cx4 snes_cx4 (
     .BUS_DI(CX4_DINr), 
     .BUS_ADDR(CX4_ADDR), 
     .BUS_RRQ(CX4_RRQ), 
-    .BUS_RDY(CX4_RDY),
+    .BUS_RDY(CX4_RDY), 
     .cx4_active(cx4_active)
     );
-   
+	 
 parameter MODE_SNES = 1'b0;
 parameter MODE_MCU = 1'b1;
 
@@ -351,25 +368,28 @@ parameter ST_MCU_WR_WAIT2 = 21'b000001000000000000000;
 parameter ST_MCU_WR_END   = 21'b000010000000000000000;
 parameter ST_CX4_RD_ADDR  = 21'b000100000000000000000;
 parameter ST_CX4_RD_WAIT  = 21'b001000000000000000000;
-parameter ST_CX4_RD_WAIT2 = 21'b010000000000000000000;
-parameter ST_CX4_RD_END   = 21'b100000000000000000000;
+parameter ST_CX4_RD_END   = 21'b010000000000000000000;
 
-parameter ROM_RD_WAIT = 4'h4;
+parameter ROM_RD_WAIT = 4'h0;
 parameter ROM_RD_WAIT_MCU = 4'h6;
+parameter ROM_WR_WAIT = 4'h4;
 parameter ROM_WR_WAIT1 = 4'h2;
-parameter ROM_WR_WAIT2 = 4'h3;
-parameter ROM_WR_WAIT_MCU = 4'h6;
+parameter ROM_WR_WAIT2 = 4'h1;
+parameter ROM_WR_WAIT_MCU = 4'h5;
 parameter ROM_RD_WAIT_CX4 = 4'h6;
 
+parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
+
 reg [20:0] STATE;
 initial STATE = ST_IDLE;
 
+reg [7:0] SNES_DINr;
+reg [7:0] SNES_DOUTr;
+reg [7:0] ROM_DOUTr;
+
 assign MSU_SNES_DATA_IN = SNES_DATA;
 assign CX4_SNES_DATA_IN = SNES_DATA;
 
-reg [7:0] SNES_DINr;
-reg [7:0] ROM_DOUTr;
-
 reg [7:0] r213fr;
 reg r213f_forceread;
 reg [2:0] r213f_delay;
@@ -379,13 +399,15 @@ initial r213f_forceread = 0;
 initial r213f_state = 2'b01;
 initial r213f_delay = 3'b011;
 
-assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr
-                   :(!SNES_READ ^ r213f_forceread)
-                     ? (msu_enable ? MSU_SNES_DATA_OUT
-                       :cx4_enable ? CX4_SNES_DATA_OUT
-                       :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
-                       :SNES_DINr)
-                    : 8'bZ;
+reg[7:0] snescmd_regs[15:0];
+
+assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
+                   :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
+                   :(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
+                                ? (msu_enable ? MSU_SNES_DATA_OUT
+                                  :cx4_enable ? CX4_SNES_DATA_OUT
+											 :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
+                                  :SNES_DOUTr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
 
 reg [3:0] ST_MEM_DELAYr;
 reg MCU_RD_PENDr;
@@ -399,25 +421,61 @@ always @(posedge CLK2) begin
 end
 
 wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE;
-wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART & ~cx4_active;
-
-assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
-assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
-
-reg ROM_WEr;
-initial ROM_WEr = 1'b1;
 
 reg RQ_MCU_RDYr;
 initial RQ_MCU_RDYr = 1'b1;
 assign MCU_RDY = RQ_MCU_RDYr;
 
+reg RQ_CX4_RDYr;
+initial RQ_CX4_RDYr = 1'b1;
+assign CX4_RDY = RQ_CX4_RDYr;
+
+reg ROM_SAr;
+initial ROM_SAr = 1'b1;
+wire ROM_SA = ROM_SAr;
+
+reg ROM_CAr;
+initial ROM_CAr = 1'b0;
+wire ROM_CA = ROM_CAr;
+
+reg [23:0] CX4_ADDRr;
+
+assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : ROM_CA ? CX4_ADDRr[23:1] : ROM_SA ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
+assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : ROM_CA ? CX4_ADDRr[0] : ROM_SA ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
+
+reg ROM_WEr;
+initial ROM_WEr = 1'b1;
+reg ROM_DOUT_ENr;
+initial ROM_DOUT_ENr = 1'b0;
+
+reg[17:0] SNES_DEAD_CNTr;
+initial SNES_DEAD_CNTr = 0;
+
+always @(posedge CLK2) begin
+  if(cx4_active) begin
+    if(CX4_RRQ) begin
+	   CX4_RD_PENDr <= 1'b1;
+		RQ_CX4_RDYr <= 1'b0;
+		CX4_ADDRr <= CX4_ADDR;
+	 end else if(STATE == ST_CX4_RD_END) begin
+	   CX4_RD_PENDr <= 1'b0;
+		RQ_CX4_RDYr <= 1'b1;
+	 end
+  end else begin
+    CX4_RD_PENDr <= 1'b0;
+	 RQ_CX4_RDYr <= 1'b1;
+  end
+end
+
 always @(posedge CLK2) begin
   if(MCU_RRQ) begin
     MCU_RD_PENDr <= 1'b1;
     RQ_MCU_RDYr <= 1'b0;
+    ROM_ADDRr <= MCU_ADDR;
   end else if(MCU_WRQ) begin
     MCU_WR_PENDr <= 1'b1;
     RQ_MCU_RDYr <= 1'b0;
+    ROM_ADDRr <= MCU_ADDR;
   end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
     MCU_RD_PENDr <= 1'b0;
     MCU_WR_PENDr <= 1'b0;
@@ -425,157 +483,144 @@ always @(posedge CLK2) begin
   end
 end
 
-reg RQ_CX4_RDYr;
-initial RQ_CX4_RDYr = 1'b1;
-assign CX4_RDY = RQ_CX4_RDYr;
-
 always @(posedge CLK2) begin
-  if(CX4_RRQ) begin
-    CX4_RD_PENDr <= 1'b1;
-    RQ_CX4_RDYr <= 1'b0;
-  end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin
-    CX4_RD_PENDr <= 1'b0;
-    RQ_CX4_RDYr <= 1'b1;
-  end
+  if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
+  else SNES_DEAD_CNTr <= 17'h0;
 end
 
-reg snes_wr_cycle;
+always @(posedge CLK2) begin
+  if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
+  else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
+end
 
 always @(posedge CLK2) begin
-  if(SNES_cycle_start & IS_CART & ~cx4_active) begin
-    STATE <= ST_SNES_RD_ADDR;
-  end else if(SNES_WR_start & IS_CART & ~cx4_active) begin
-    STATE <= ST_SNES_WR_ADDR;
-  end else begin
-    case(STATE)
-      ST_IDLE: begin
-        ROM_ADDRr <= MAPPED_SNES_ADDR;
-        if(CX4_RD_PENDr) begin
-          STATE <= ST_CX4_RD_WAIT;
-          ROM_ADDRr <= CX4_ADDR;
-          ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
-        end else if(~cx4_active && ~ASSERT_SNES_ADDR) begin
-          if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
-          else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
-          else STATE <= ST_IDLE;
+  if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
+  else
+  case(STATE)
+    ST_IDLE: begin
+	   ROM_SAr <= 1'b1;
+		ROM_CAr <= 1'b0;
+		ROM_DOUT_ENr <= 1'b0;
+		if(cx4_active) begin
+        if(CX4_RD_PENDr) STATE <= ST_CX4_RD_ADDR;
+		end else if(SNES_cycle_start & ~SNES_WRITE) begin
+		  STATE <= ST_SNES_WR_ADDR;
+		  if(IS_SAVERAM | IS_WRITABLE) begin
+		    ROM_WEr <= 1'b0;
+          ROM_DOUT_ENr <= 1'b1;
         end
-        else STATE <= ST_IDLE;
-      end
-      ST_SNES_RD_ADDR: begin
-        STATE <= ST_SNES_RD_WAIT;
-        ST_MEM_DELAYr <= ROM_RD_WAIT;
-      end
-      ST_SNES_RD_WAIT: begin
-        ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-        if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
-        else STATE <= ST_SNES_RD_WAIT;
-        if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
-        else SNES_DINr <= ROM_DATA[15:8];
-      end
-      ST_SNES_RD_END: begin
-        STATE <= ST_IDLE;
-        if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
-        else SNES_DINr <= ROM_DATA[15:8];
-      end
-      ST_SNES_WR_ADDR: begin
-        ROM_WEr <= (!IS_WRITABLE);
-        snes_wr_cycle <= 1'b1;
-        STATE <= ST_SNES_WR_WAIT1;
-        ST_MEM_DELAYr <= ROM_WR_WAIT1;
-      end
-      ST_SNES_WR_WAIT1: begin
-        ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-        if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
-        else STATE <= ST_SNES_WR_WAIT1;
-      end
-      ST_SNES_WR_DATA: begin
-        ROM_DOUTr <= SNES_DATA;
-        ST_MEM_DELAYr <= ROM_WR_WAIT2;
+		end else if(SNES_cycle_start) begin
+//		  STATE <= ST_SNES_RD_ADDR;		  
+        STATE <= ST_SNES_RD_END;
+        SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
+		end else if(SNES_DEADr & MCU_RD_PENDr) begin
+		  STATE <= ST_MCU_RD_ADDR;
+		end else if(SNES_DEADr & MCU_WR_PENDr) begin
+		  STATE <= ST_MCU_WR_ADDR;
+		end
+	 end
+	 ST_SNES_RD_ADDR: begin
+	   ST_MEM_DELAYr <= ROM_RD_WAIT;
+		STATE <= ST_SNES_RD_WAIT;
+	 end
+	 ST_SNES_RD_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+//		if(ST_MEM_DELAYr == 0) begin
+//		end
+//		else STATE <= ST_SNES_RD_WAIT;
+	 end
+	 
+	 ST_SNES_WR_ADDR: begin
+	   ST_MEM_DELAYr <= ROM_WR_WAIT1;
+	   STATE <= ST_SNES_WR_WAIT1;
+	 end
+	 ST_SNES_WR_WAIT1: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+		  ST_MEM_DELAYr <= ROM_WR_WAIT2;
         STATE <= ST_SNES_WR_WAIT2;
-      end
-      ST_SNES_WR_WAIT2: begin
-        ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-        if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
-        else STATE <= ST_SNES_WR_WAIT2;
-      end
-      ST_SNES_WR_END: begin
-        STATE <= ST_IDLE;
-        ROM_WEr <= 1'b1;
-        snes_wr_cycle <= 1'b0;
-      end
-      ST_MCU_RD_ADDR: begin
-        ROM_ADDRr <= MCU_ADDR;
-        STATE <= ST_MCU_RD_WAIT;
-        ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
-      end
-      ST_MCU_RD_WAIT: begin
-        ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-        if(ST_MEM_DELAYr == 4'h0) begin
-          STATE <= ST_MCU_RD_WAIT2;
-          ST_MEM_DELAYr <= 4'h2;
-          if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
-          else MCU_DINr <= ROM_DATA[15:8];
-        end
-        else STATE <= ST_MCU_RD_WAIT;
-      end
-      ST_MCU_RD_WAIT2: begin
-        ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-        if(ST_MEM_DELAYr == 4'h0) begin
-          STATE <= ST_MCU_RD_END;
-        end else STATE <= ST_MCU_RD_WAIT2;
-      end
-      ST_MCU_RD_END: begin
-        STATE <= ST_IDLE;
-      end
-      ST_MCU_WR_ADDR: begin
-        ROM_ADDRr <= MCU_ADDR;
-        STATE <= ST_MCU_WR_WAIT;
-        ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
-        ROM_DOUTr <= MCU_DOUT;
-        ROM_WEr <= 1'b0;
-      end
-      ST_MCU_WR_WAIT: begin
-        ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-        if(ST_MEM_DELAYr == 4'h0) begin
-          ROM_WEr <= 1'b1;
-          STATE <= ST_MCU_WR_WAIT2;
-          ST_MEM_DELAYr <= 4'h2;
-        end
-        else STATE <= ST_MCU_WR_WAIT;
-      end
-      ST_MCU_WR_WAIT2: begin
-        ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-        if(ST_MEM_DELAYr == 4'h0) begin
-          STATE <= ST_MCU_WR_END;
-        end else STATE <= ST_MCU_WR_WAIT2;
-      end
-      ST_MCU_WR_END: begin
-        STATE <= ST_IDLE;
-      end
-
-      ST_CX4_RD_ADDR: begin
-        ROM_ADDRr <= CX4_ADDR;
-        STATE <= ST_CX4_RD_WAIT;
-        ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
-      end
-      ST_CX4_RD_WAIT: begin
-        ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-        if(ST_MEM_DELAYr == 4'h0) STATE <= ST_IDLE;
-        else STATE <= ST_CX4_RD_WAIT;
-        if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0];
-        else CX4_DINr <= ROM_DATA[15:8];
-      end
-      ST_CX4_RD_END: begin
-        STATE <= ST_IDLE;
-      end
-    endcase
-  end
+		  ROM_DOUTr <= SNES_DATA;
+		end
+		else STATE <= ST_SNES_WR_WAIT1;
+	 end
+	 ST_SNES_WR_WAIT2: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+        STATE <= ST_SNES_WR_END;
+		  ROM_WEr <= 1'b1;
+		end
+		else STATE <= ST_SNES_WR_WAIT2;
+    end
+	 ST_SNES_RD_END, ST_SNES_WR_END: begin
+	   ROM_DOUT_ENr <= 1'b0;		
+      if(MCU_RD_PENDr) begin
+        STATE <= ST_MCU_RD_ADDR;
+      end else if(MCU_WR_PENDr) begin
+        STATE <= ST_MCU_WR_ADDR;
+      end else STATE <= ST_IDLE;
+    end
+    ST_MCU_RD_ADDR: begin
+      ROM_SAr <= 1'b0;
+		ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
+		STATE <= ST_MCU_RD_WAIT;
+	 end
+	 ST_MCU_RD_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+        STATE <= ST_MCU_RD_END;
+		end
+		else STATE <= ST_MCU_RD_WAIT;
+	 end
+	 ST_MCU_RD_END: begin
+      MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
+	   STATE <= ST_IDLE;
+	 end
+	 
+	 ST_MCU_WR_ADDR: begin
+      ROM_DOUTr <= MCU_DOUT;
+      ROM_SAr <= 1'b0;
+	   ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
+		STATE <= ST_MCU_WR_WAIT;
+		ROM_DOUT_ENr <= 1'b1;
+		ROM_WEr <= 1'b0;
+	 end
+	 ST_MCU_WR_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+		  ROM_WEr <= 1'b1;
+		  STATE <= ST_MCU_WR_END;
+		end
+		else STATE <= ST_MCU_WR_WAIT;	 
+	 end
+	 ST_MCU_WR_END: begin
+		ROM_DOUT_ENr <= 1'b0;
+	   STATE <= ST_IDLE;
+	 end
+	 ST_CX4_RD_ADDR: begin
+	   ROM_CAr <= 1'b1;
+	   ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
+		STATE <= ST_CX4_RD_WAIT;
+	 end
+	 ST_CX4_RD_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+		  STATE <= ST_CX4_RD_END;
+		end
+		else STATE <= ST_CX4_RD_WAIT;
+	 end
+	 ST_CX4_RD_END: begin
+	   ROM_CAr <= 1'b0;
+	   CX4_DINr <= CX4_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
+	   STATE <= ST_IDLE;
+	 end
+	 
+  endcase
 end
 
-always @(posedge SYSCLK2) begin
-  if(SNES_PARD_start & r213f_enable) begin
-    r213f_forceread <= 1'b1;
-    r213f_delay <= 3'b001;
+always @(posedge CLK2) begin
+  if(SNES_cycle_end) r213f_forceread <= 1'b1;
+  else if(SNES_PARD_start & r213f_enable) begin
+    r213f_delay <= 3'b000;
     r213f_state <= 2'b10;
   end else if(r213f_state == 2'b10) begin
     r213f_delay <= r213f_delay - 1;
@@ -587,44 +632,109 @@ always @(posedge SYSCLK2) begin
   end
 end
 
+always @(posedge CLK2) begin
+  if(SNES_WR_end & snescmd_wr_enable) begin
+    snescmd_regs[SNES_ADDR[3:0]] <= SNES_DATA;
+  end
+end
+
+reg ROM_WE_1;
+reg MCU_WRITE_1;
+
+always @(posedge CLK2) begin
+  ROM_WE_1 <= ROM_WE;
+  MCU_WRITE_1<= MCU_WRITE;
+end
+
 assign ROM_DATA[7:0] = ROM_ADDR0
-                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                                        : (!ROM_WE ? ROM_DOUTr : 8'bZ)
+                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+							                   /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+                                        : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                         )
                        :8'bZ;
 
 assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
-                        :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                                         : (!ROM_WE ? ROM_DOUTr : 8'bZ)
+                        :(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+								                 /*:  ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+                                         : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                          );
 
 assign ROM_WE = SD_DMA_TO_ROM
                 ?MCU_WRITE
-                :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
+                :/*(SNES_FAKE_CLK & (IS_WRITABLE | IS_FLASHWR)) ? SNES_WRITE :*/ ROM_WEr;
 
 // OE always active. Overridden by WE when needed.
 assign ROM_OE = 1'b0;
 
 assign ROM_CE = 1'b0;
 
-assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
-assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
+assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
 
 assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
                          cx4_enable ? 1'b0 :
-                         (cx4_active & cx4_vect_enable) ? 1'b0 :
+								 (cx4_active & cx4_vect_enable) ? 1'b0 :
                          r213f_enable & !SNES_PARD ? 1'b0 :
-                         ((!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
-                          |(SNES_READ & SNES_WRITE)
+								 (snescmd_wr_enable | snescmd_rd_enable) & !SNES_PARD ? 1'b0 :
+                         ((IS_ROM & SNES_CS)
+                          |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
+                          |(SNES_READr[0] & SNES_WRITEr[0])
                          );
 
-assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & r213f_enable))
-                           ? 1'b1 ^ r213f_forceread
+assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescmd_rd_enable)))
+                           ? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
                            : 1'b0;
 
-assign IRQ_DIR = 1'b0;
-assign SNES_IRQ = 1'bZ;
+assign SNES_IRQ = 1'b0;
 
 assign p113_out = 1'b0;
 
+/*
+wire [35:0] CONTROL0;
+
+icon icon (
+    .CONTROL0(CONTROL0) // INOUT BUS [35:0]
+);
+
+ila ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SNES_ADDR), // IN BUS [23:0]
+    .TRIG1(SNES_DATA), // IN BUS [7:0]
+    .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, cx4_active, ROM_WE, ROM_DOUT_ENr, ROM_SA, CX4_RRQ, CX4_RDY, ROM_CA}), // IN BUS [15:0]
+    .TRIG3(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG4(CX4_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(CX4_DINr), // IN BUS [7:0]
+    .TRIG7(STATE) // IN BUS [21:0]
+);*/
+/*
+ila ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SNES_ADDR), // IN BUS [23:0]
+    .TRIG1(SNES_DATA), // IN BUS [7:0]
+    .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}),	 // IN BUS [15:0]
+    .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(spi_byte_cnt[3:0])
+);
+*/
+/*
+ila_srtc ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
+    .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
+    .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}),	 // IN BUS [15:0]
+    .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(ST_MEM_DELAYr)
+);
+*/
+
 endmodule

verilog/sd2snes_cx4/msu.v

@@ -38,7 +38,13 @@ module msu(
   input [5:0] status_set_bits,
   input status_reset_we,
   input [13:0] msu_address_ext,
-  input msu_address_ext_write
+  input msu_address_ext_write,
+  
+  output DBG_msu_reg_oe_rising,
+  output DBG_msu_reg_oe_falling,
+  output DBG_msu_reg_we_rising,
+  output [13:0] DBG_msu_address,
+  output DBG_msu_address_ext_write_rising
 );
 
 reg [2:0] reg_addr_r [3:0];
@@ -56,13 +62,15 @@ wire status_reset_en = (status_reset_we_r == 2'b01);
 
 reg [13:0] msu_address_r;
 wire [13:0] msu_address = msu_address_r;
+initial msu_address_r = 13'b0;
 
 wire [7:0] msu_data;
+reg [7:0] msu_data_r;
 
-reg [1:0] msu_address_ext_write_sreg;
+reg [2:0] msu_address_ext_write_sreg;
 always @(posedge clkin)
-  msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write};
-wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01);
+  msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
+wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
 
 reg [4:0] reg_enable_sreg;
 initial reg_enable_sreg = 5'b11111;
@@ -70,11 +78,12 @@ always @(posedge clkin) reg_enable_sreg <= {reg_enable_sreg[3:0], enable};
 
 reg [5:0] reg_oe_sreg;
 always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe};
-wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
+wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:1] == 5'b00001);
+wire reg_oe_falling = reg_enable_sreg[1] && (reg_oe_sreg[5:1] == 5'b11110);
 
 reg [5:0] reg_we_sreg;
 always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[4:0], reg_we};
-wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
+wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[5:1] == 5'b00001);
 
 reg [31:0] addr_out_r;
 assign addr_out = addr_out_r;
@@ -93,14 +102,27 @@ reg audio_busy_r;
 reg data_start_r;
 reg data_busy_r;
 reg ctrl_start_r;
+reg audio_error_r;
 reg [1:0] audio_ctrl_r;
 reg [1:0] audio_status_r;
 
 initial begin
-  audio_busy_r <= 1'b1;
-  data_busy_r <= 1'b1;
+  audio_busy_r = 1'b1;
+  data_busy_r = 1'b1;
+  audio_error_r = 1'b0;
+  volume_r = 8'h00;
+  addr_out_r = 32'h00000000;
+  track_out_r = 16'h0000;
+  data_start_r = 1'b0;
+  audio_start_r = 1'b0;
 end
 
+assign DBG_msu_address = msu_address;
+assign DBG_msu_reg_oe_rising = reg_oe_rising;
+assign DBG_msu_reg_oe_falling = reg_oe_falling;
+assign DBG_msu_reg_we_rising = reg_we_rising;
+assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
+
 assign status_out = {msu_address_r[13], // 6
                      audio_start_r,     // 5
                      data_start_r,      // 4
@@ -124,8 +146,8 @@ reg [7:0] data_out_r;
 assign reg_data_out = data_out_r;
 
 always @(posedge clkin) begin
-  case(reg_addr_r[3])
-    3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, 4'b0001};
+  case(reg_addr_r[1])
+    3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b001};
     3'h1: data_out_r <= msu_data;
     3'h2: data_out_r <= 8'h53;
     3'h3: data_out_r <= 8'h2d;
@@ -138,7 +160,7 @@ end
 
 always @(posedge clkin) begin
   if(reg_we_rising) begin
-    case(reg_addr_r[3])
+    case(reg_addr_r[1])
       3'h0: addr_out_r[7:0] <= reg_data_in;
       3'h1: addr_out_r[15:8] <= reg_data_in;
       3'h2: addr_out_r[23:16] <= reg_data_in;
@@ -173,7 +195,7 @@ always @(posedge clkin) begin
     data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
     if(status_reset_bits[4]) data_start_r <= 1'b0;
 
-//    volume_start_r <= (volume_start_r | status_set_bits[3]) & ~status_reset_bits[3];
+    audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
 
     audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
 

verilog/sd2snes_cx4/sd2snes_cx4.xise

@@ -9,95 +9,77 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
-    <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="cx4.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="ipcore_dir/cx4_datrom.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="ipcore_dir/cx4_datram.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="ipcore_dir/cx4_pgmrom.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="ipcore_dir/cx4_mul.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
-    <file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/msu_databuf.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/cx4_datrom.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/cx4_datram.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/cx4_pgmrom.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/cx4_mul.xise" xil_pn:type="FILE_COREGENISE">
+    <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
@@ -257,7 +239,7 @@
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
@@ -282,7 +264,7 @@
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -366,8 +348,8 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="11" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="11" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="3" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="3" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -438,9 +420,7 @@
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
 
-  <bindings>
-    <binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
-  </bindings>
+  <bindings/>
 
   <libraries/>
 

verilog/sd2snes_cx4/sd_dma.v

@@ -31,7 +31,10 @@ module sd_dma(
   input [10:0] SD_DMA_PARTIAL_START,
   input [10:0] SD_DMA_PARTIAL_END,
   input SD_DMA_START_MID_BLOCK,
-  input SD_DMA_END_MID_BLOCK
+  input SD_DMA_END_MID_BLOCK,
+  
+  output [10:0] DBG_cyclecnt,
+  output [2:0] DBG_clkcnt
 );
 
 reg [10:0] SD_DMA_STARTr;
@@ -74,7 +77,11 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
 reg [2:0] clkcnt;
 initial clkcnt = 3'b000;
 reg [1:0] SD_CLKr;
-always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
+initial SD_CLKr = 3'b111;
+always @(posedge CLK)
+  if(SD_DMA_EN_rising) SD_CLKr <= 3'b111;
+  else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
+
 assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
 
 always @(posedge CLK) begin
@@ -116,20 +123,20 @@ always @(posedge CLK) begin
   if(SD_DMA_STATUSr) begin
     case(clkcnt[2:0])
       3'h0: begin
-        SD_DMA_SRAM_WEr <= 1'b1;
         SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
         if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
       end
-      3'h1:
+      3'h1: begin
         SD_DMA_NEXTADDRr <= 1'b0;
-//  3'h2:
-      3'h3:
-        if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
+		end
+      3'h2: if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
+//  3'h3:
       3'h4:
         SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
 //  3'h5:
 //  3'h6:
-//  3'h7:
+      3'h7:
+		  SD_DMA_SRAM_WEr <= 1'b1;
     endcase
   end
 end

verilog/sd2snes_cx4/spi.v

@@ -39,15 +39,27 @@ module spi(
 reg [7:0] cmd_data_r;
 reg [7:0] param_data_r;
 
-reg [1:0] SSELr;  always @(posedge clk) SSELr <= {SSELr[0], SSEL};
+reg [2:0] SSELr;
+reg [2:0] SSELSCKr;
+
+always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
+always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
+
+wire SSEL_inactive = SSELr[1];
 wire SSEL_active = ~SSELr[1];  // SSEL is active low
-wire SSEL_startmessage = (SSELr[1:0]==2'b10);  // message starts at falling edge
-wire SSEL_endmessage = (SSELr[1:0]==2'b01);  // message stops at rising edge
+wire SSEL_startmessage = (SSELr[2:1]==2'b10);  // message starts at falling edge
+wire SSEL_endmessage = (SSELr[2:1]==2'b01);  // message stops at rising edge
 assign endmessage = SSEL_endmessage;
 assign startmessage = SSEL_startmessage;
 
 // bit count for one SPI byte + byte count for the message
 reg [2:0] bitcnt;
+initial bitcnt = 3'b000;
+wire bitcnt_msb = bitcnt[2];
+reg [2:0] bitcnt_wrap_r;
+always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
+wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
+
 reg [31:0] byte_cnt_r;
 
 reg byte_received;  // high when a byte has been received
@@ -56,23 +68,26 @@ reg [7:0] byte_data_received;
 assign bit_cnt = bitcnt;
 
 always @(posedge SCK) begin
-  if(SSEL) bitcnt <= 3'b000;
-  else begin
-    bitcnt <= bitcnt + 3'b001;
-    byte_data_received <= {byte_data_received[6:0], MOSI};
+  if(SSELSCKr[1]) bitcnt <= 3'b000;
+  else bitcnt <= bitcnt + 3'b001;
+end
+
+always @(posedge SCK) begin
+  if(~SSELSCKr[1]) begin
+	 byte_data_received <= {byte_data_received[6:0], MOSI};
   end
-  if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1;
+  if(~SSELSCKr[1] && bitcnt==3'b111) byte_received <= 1'b1;
   else byte_received <= 1'b0;
 end
 
-reg [1:0] byte_received_r;
-always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received};
-wire byte_received_sync = (byte_received_r == 2'b01);
+//reg [2:0] byte_received_r;
+//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
+//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
 
 always @(posedge clk) begin
-  if(~SSEL_active)
+  if(SSEL_inactive) begin
     byte_cnt_r <= 16'h0000;
-  else if(byte_received_sync) begin
+  end else if(byte_received_sync) begin
     byte_cnt_r <= byte_cnt_r + 16'h0001;
   end
 end

verilog/sd2snes_test/ipcore_dir/PA.xise

@@ -29,333 +29,27 @@
   </files>
 
   <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4Q" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4Q" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xa3s400" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4Q" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Module|PA" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="PA.ngc" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PA" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="PA" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="pqg208" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="PA_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="PA_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="PA_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="PA_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4Q" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="PA" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-12-09T21:37:02" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="174C961C9E58BF7E1425597A907CA194" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>

verilog/sd2snes_test/ipcore_dir/bram.xise

@@ -17,11 +17,11 @@
   <files>
     <file xil_pn:name="bram.ngc" xil_pn:type="FILE_NGC">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="bram.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
@@ -29,333 +29,27 @@
   </files>
 
   <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4Q" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4Q" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xa3s400" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4Q" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
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     <property xil_pn:name="Implementation Top" xil_pn:value="Module|bram" xil_pn:valueState="non-default"/>
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     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/bram" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="bram" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="bram_synthesis.v" xil_pn:valueState="default"/>
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     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4Q" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="bram" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-12-09T21:36:13" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F94BE6D78E22F09C3EE6D3E6B1E72FA5" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>

verilog/sd2snes_test/ipcore_dir/dac_buf.xise

@@ -29,333 +29,27 @@
   </files>
 
   <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4Q" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4Q" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xa3s400" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4Q" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Module|dac_buf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="dac_buf.ngc" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/dac_buf" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="dac_buf" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="pqg208" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="dac_buf_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="dac_buf_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="dac_buf_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="dac_buf_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4Q" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="dac_buf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-12-09T21:37:48" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3C43364A4F81B7B94D37233F81E51481" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>

verilog/sd2snes_test/main.ucf

@@ -1,5 +1,5 @@
 NET "CLKIN" TNM_NET = "CLKIN";
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24.05 MHz HIGH 50 %;
 //TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
 
 NET "p113_out" IOSTANDARD = LVCMOS33;
@@ -8,7 +8,7 @@ NET "p113_out" LOC = P113;
 NET "SPI_SCK" LOC = P71;
 NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
 NET "SPI_SCK" TNM_NET = "SPI_SCK";
-TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48MHz HIGH 50 %;
+TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48.1MHz HIGH 50 %;
 
 NET "SPI_SCK" IOSTANDARD = LVCMOS33;
 NET "SPI_SCK" DRIVE = 8;
@@ -535,6 +535,7 @@ NET "SD_DAT[3]" LOC = P63;
 # PlanAhead Generated IO constraints 
 
 NET "SD_CLK" IOSTANDARD = LVCMOS33;
+NET "SD_CLK" PULLUP;
 NET "SD_CMD" IOSTANDARD = LVCMOS33;
 NET "SD_DAT[0]" IOSTANDARD = LVCMOS33;
 NET "SD_DAT[1]" IOSTANDARD = LVCMOS33;

verilog/sd2snes_test/sd2snes_test.xise

@@ -99,17 +99,12 @@
     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
@@ -130,7 +125,6 @@
     <property xil_pn:name="Cross Clock Analysis" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
     <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xa3s400" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan3" xil_pn:valueState="non-default"/>
@@ -149,7 +143,6 @@
     <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Extra Effort" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
@@ -157,7 +150,6 @@
     <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
@@ -170,8 +162,6 @@
     <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
@@ -183,13 +173,10 @@
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="main.v" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
@@ -198,7 +185,6 @@
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
     <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
@@ -206,7 +192,6 @@
     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
@@ -214,9 +199,7 @@
     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
@@ -238,7 +221,6 @@
     <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
@@ -249,18 +231,14 @@
     <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
@@ -279,7 +257,6 @@
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
@@ -336,28 +313,24 @@
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.main" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="10" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="10" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="11" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="11" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
     <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -366,37 +339,26 @@
     <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->