PCB/Rev.E2: Add BOM

Develop

.gitignore

@@ -0,0 +1,22 @@
+*.cod
+*.hex
+*.lst
+*.o
+*.diff
+.DS_Store
+*.o65
+*.ips
+*.bin
+*.map
+*.o.d
+*.log
+*.smc
+*.sfc
+*~
+*.old
+*.elf
+*.img
+autoconf.h
+utils/rle
+utils/derle
+*.bit

CHANGELOG

@@ -0,0 +1,81 @@
+v0.1.1
+======
+
+ * initial public release
+
+
+v0.1.1a (bugfix release)
+========================
+
+ * Fixes:
+   - SuperCIC pair mode was erroneously enabled in firmware binary
+   - SNES menu crashed on empty database
+
+
+v0.1.2
+======
+
+ * New menu entry: "System Information"
+ * Auto region override (eliminate "This game pak is not designed..." messages)
+ * Improved mapper detection (fixes Batman vs. Joker and many PD ROMs)
+ * Improved data streaming performance
+   (should reduce MSU1 errors with some cards)
+ * A and B buttons swapped in menu to match common key mappings
+ * Fixes:
+   - MSU1: Stop audio playback on end of audio file
+
+
+v0.1.3
+======
+
+ * Updated logo gfx with new version from klaptra
+ * Updated font to distinguish between 1 and I
+ * Menu layout adjusted to move status line up by 4 scanlines
+ * Run previously loaded game by pressing Start in the menu
+ * Auto-scroll file names that do not fit the screen
+ * SD access time measurement on System Information screen (takes a while!)
+ * Cx4 memory map: mirror ROM to 40-7e/c0-ff (fixes MMX3 Zero patch)
+ * Some FPGA configuration error detection (mainly useful for hardware diag)
+ * Fixes:
+   - FPGA-side SD clock pullup (increases reliability with some cards)
+
+
+v0.1.4
+======
+
+ * SPC Player (contributed by necronomfive/blargg)
+ * System Information screen now shows CPU/PPU revision (contributed by necronomfive)
+ * Satellaview: basic data transmission packet support (makes some more games boot, thanks to LuigiBlood for assistance and sample data packets)
+ * Number of supported files increased to 50000 per card / 16380 per directory
+ * Slight speedup of menu text rendering
+ * Reduce load time of menu
+ * Adjust Cx4 timing to be more faithful
+   (Mega Man now defeats the boss in attract mode in Mega Man X2)
+ * adapt ROM mirroring size to file size if header information is invalid
+   (fixes Super Noah's Ark 3D, possibly others)
+ * MSU1 interface changes suggested by byuu:
+   - Data offset 0 and audio track 0 are automatically requested on reset.
+     This causes the busy flags to become 0 shortly after reset/startup.
+   - $2000 bit 3 is now "audio error", becomes valid after "audio busy" -> 0
+     set when an error occurred while preparing playback of the requested audio track
+ * write LED stays on when SRAM content changes constantly
+ * Fixes:
+   - fix empty save files on FAT16 / incorrect free cluster count on FAT32
+   - correct directory sorting (force parent directory at top of list)
+   - fix text corruption when entering a directory with a scrollable name
+   - fix files/dirs count in system information
+   - make 'sd2snes' directory hiding case-insensitive
+   - improve DAC I²S timing
+   - fix occasional palette corruption in menu
+   - fix SD clock glitch on ROM loading (occasional glitches/crashes)
+   - fix memory write timing on ROM loading (occasional glitches/crashes)
+   - fix SPI timing (ROMs not loading; System Information not working)
+   - properly synchronize SNES control signals (occasional glitches/crashes)
+   - fix floating IRQ output (occasional glitches/slowdowns)
+
+
+v0.1.4a (bugfix release)
+========================
+
+ * Fix DMA initialization in the menu (could cause sprite corruption in some games)
+

cic/supercic/supercic-key.asm

@@ -64,6 +64,7 @@ processor p12f629
 ;   0x4d		buffer for eeprom access
 ;   0x4e		loop variable for longwait
 ;   0x4f		loop variable for wait
+;   0x5c		GPIO buffer variable for pair mode allow
 ;   0x5d		0: SuperCIC pair mode available flag
 ;   0x5e                SuperCIC pair mode detect (phase 1)
 ;   0x5f                SuperCIC pair mode detect (phase 2)
@@ -90,8 +91,8 @@ isr
 	clrf	0x5f		; clear pair mode detect
 	bsf	0x5f, 1		;
 	clrf	0x5d		; clear pair mode available
-	nop
-	nop
+	clrf	0x5c		; clear pair mode allow buffer
+	bsf	0x5c, 3		; assume disallow
 	bsf	INTCON, 7	; re-enable interrupts (ISR will continue as main)
 	goto	main
 init
@@ -296,8 +297,8 @@ swapskip
 ; indirect access, no post increment, etc.
 mangle
 	call	mangle_lock
-	nop
-	nop
+	movf	GPIO, w	; buffer GPIO state
+	movwf	0x5c	; for pair mode "transaction"
 mangle_key
 	movf	0x2f, w
 	movwf	0x20	
@@ -459,7 +460,7 @@ mangle_key_withskip
 ;-------pair mode code-------
 	bcf	GPIO, 0
 	movf	GPIO, w
-	btfss	GPIO, 3
+	btfss	0x5c, 3
 	bsf	GPIO, 0
 	movwf	0x5e
 	movf	GPIO, w
@@ -642,7 +643,7 @@ mangle_lock_withskip
 	goto	scic_pair_skip1
 	btfsc	0x5f, 1
 	goto	scic_pair_skip2
-	btfsc	GPIO, 3
+	btfsc	0x5c, 3
 	goto	scic_pair_skip3
 	goto	supercic_pairmode
 scic_pair_skip1

pcb/kicad/RevE/fpga.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 29 Jul 2011 09:56:34 PM CEST
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:06 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A3 16535 11700
 encoding utf-8
 Sheet 6 6
 Title "sd2snes Mark II"
-Date "24 jul 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""

pcb/kicad/RevE/mcu.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 29 Jul 2011 09:56:34 PM CEST
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:06 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A4 11700 8267
 encoding utf-8
 Sheet 4 6
 Title "sd2snes Mark II"
-Date "24 jul 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""
@@ -1034,7 +1034,7 @@ L C C409
 U 1 1 4BEECBD1
 P 3100 6600
 F 0 "C409" H 3150 6700 50  0000 L CNN
-F 1 "22p" H 3150 6500 50  0000 L CNN
+F 1 "10p" H 3150 6500 50  0000 L CNN
 F 2 "SM0805_FIXEDMASK" H 3100 6600 60  0001 C CNN
 	1    3100 6600
 	1    0    0    -1  
@@ -1044,7 +1044,7 @@ L C C408
 U 1 1 4BEECBCD
 P 2500 6600
 F 0 "C408" H 2550 6700 50  0000 L CNN
-F 1 "22p" H 2550 6500 50  0000 L CNN
+F 1 "10p" H 2550 6500 50  0000 L CNN
 F 2 "SM0805_FIXEDMASK" H 2500 6600 60  0001 C CNN
 	1    2500 6600
 	1    0    0    -1  

pcb/kicad/RevE/memory.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 29 Jul 2011 09:56:34 PM CEST
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:05 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A4 11700 8267
 encoding utf-8
 Sheet 3 6
 Title "sd2snes Mark II"
-Date "24 jul 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""
@@ -322,7 +322,7 @@ L R R513
 U 1 1 4BF2FDAC
 P 9150 5700
 F 0 "R513" V 9230 5700 50  0000 C CNN
-F 1 "1k" V 9150 5700 50  0000 C CNN
+F 1 "100k" V 9150 5700 50  0000 C CNN
 F 2 "SM0805_FIXEDMASK" H 9150 5700 60  0001 C CNN
 	1    9150 5700
 	1    0    0    -1  

pcb/kicad/RevE/pwr_misc.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 29 Jul 2011 09:56:34 PM CEST
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:06 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A4 11700 8267
 encoding utf-8
 Sheet 5 6
 Title "sd2snes Mark II"
-Date "24 jul 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""
@@ -55,6 +55,8 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
+Text Notes 4900 5900 0    50   ~ 0
+Stuff with 0603 ferrite bead
 Wire Wire Line
 	5750 5500 5900 5500
 Wire Wire Line
@@ -334,7 +336,7 @@ L JUMPER JP341
 U 1 1 4DB35D41
 P 5450 5500
 F 0 "JP341" H 5450 5650 60  0000 C CNN
-F 1 "JUMPER" H 5450 5420 40  0000 C CNN
+F 1 "FB 0603" H 5450 5420 40  0000 C CNN
 	1    5450 5500
 	1    0    0    -1  
 $EndComp

pcb/kicad/RevE/sd2snes.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 29 Jul 2011 09:56:34 PM CEST
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:05 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A4 11700 8267
 encoding utf-8
 Sheet 1 6
 Title "sd2snes Mark II"
-Date "24 jul 2011"
+Date "9 dec 2011"
 Rev "E"
 Comp "Maximilian Rehkopf"
 Comment1 ""

pcb/kicad/RevE/snesslot.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 29 Jul 2011 09:56:34 PM CEST
+EESchema Schematic File Version 2  date Fri 09 Dec 2011 10:46:05 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -47,7 +47,7 @@ $Descr A3 16535 11700
 encoding utf-8
 Sheet 2 6
 Title "sd2snes Mark II"
-Date "24 jul 2011"
+Date "9 dec 2011"
 Rev "C"
 Comp "Maximilian Rehkopf"
 Comment1 ""
@@ -855,7 +855,7 @@ L R_PACK4 RA114
 U 1 1 4D97B45F
 P 15250 4750
 F 0 "RA114" H 15250 4600 40  0000 C CNN
-F 1 "220" H 15250 4950 40  0000 C CNN
+F 1 "100" H 15250 4950 40  0000 C CNN
 	1    15250 4750
 	1    0    0    -1  
 $EndComp
@@ -864,7 +864,7 @@ L R_PACK4 RA113
 U 1 1 4D97B45C
 P 15250 4350
 F 0 "RA113" H 15250 4800 40  0000 C CNN
-F 1 "220" H 15250 4550 40  0000 C CNN
+F 1 "100" H 15250 4550 40  0000 C CNN
 	1    15250 4350
 	1    0    0    -1  
 $EndComp
@@ -913,7 +913,7 @@ L R_PACK4 RA108
 U 1 1 4D963119
 P 4150 8350
 F 0 "RA108" H 4150 8300 40  0000 C CNN
-F 1 "220" H 4150 8550 40  0000 C CNN
+F 1 "100" H 4150 8550 40  0000 C CNN
 	1    4150 8350
 	-1   0    0    -1  
 $EndComp
@@ -922,7 +922,7 @@ L R_PACK4 RA107
 U 1 1 4D963117
 P 4150 7950
 F 0 "RA107" H 4150 8400 40  0000 C CNN
-F 1 "220" H 4150 8150 40  0000 C CNN
+F 1 "100" H 4150 8150 40  0000 C CNN
 	1    4150 7950
 	-1   0    0    -1  
 $EndComp
@@ -931,7 +931,7 @@ L R_PACK4 RA106
 U 1 1 4D963115
 P 4150 7350
 F 0 "RA106" H 4150 7300 40  0000 C CNN
-F 1 "220" H 4150 7550 40  0000 C CNN
+F 1 "100" H 4150 7550 40  0000 C CNN
 	1    4150 7350
 	-1   0    0    -1  
 $EndComp
@@ -940,7 +940,7 @@ L R_PACK4 RA105
 U 1 1 4D96310E
 P 4150 6950
 F 0 "RA105" H 4150 7400 40  0000 C CNN
-F 1 "220" H 4150 7150 40  0000 C CNN
+F 1 "100" H 4150 7150 40  0000 C CNN
 	1    4150 6950
 	-1   0    0    -1  
 $EndComp
@@ -949,7 +949,7 @@ L R_PACK4 RA112
 U 1 1 4D96310C
 P 4150 4650
 F 0 "RA112" H 4150 4600 40  0000 C CNN
-F 1 "220" H 4150 4850 40  0000 C CNN
+F 1 "100" H 4150 4850 40  0000 C CNN
 	1    4150 4650
 	1    0    0    -1  
 $EndComp
@@ -958,7 +958,7 @@ L R_PACK4 RA111
 U 1 1 4D96310A
 P 4150 4250
 F 0 "RA111" H 4150 4700 40  0000 C CNN
-F 1 "220" H 4150 4450 40  0000 C CNN
+F 1 "100" H 4150 4450 40  0000 C CNN
 	1    4150 4250
 	-1   0    0    -1  
 $EndComp
@@ -967,7 +967,7 @@ L R_PACK4 RA110
 U 1 1 4D963107
 P 4150 3650
 F 0 "RA110" H 4150 3600 40  0000 C CNN
-F 1 "220" H 4150 3850 40  0000 C CNN
+F 1 "100" H 4150 3850 40  0000 C CNN
 	1    4150 3650
 	-1   0    0    -1  
 $EndComp
@@ -976,7 +976,7 @@ L R_PACK4 RA109
 U 1 1 4D963103
 P 4150 3250
 F 0 "RA109" H 4150 3700 40  0000 C CNN
-F 1 "220" H 4150 3450 40  0000 C CNN
+F 1 "100" H 4150 3450 40  0000 C CNN
 	1    4150 3250
 	-1   0    0    -1  
 $EndComp
@@ -985,7 +985,7 @@ L R_PACK4 RA102
 U 1 1 4D9630F4
 P 12400 3750
 F 0 "RA102" H 12400 3700 40  0000 C CNN
-F 1 "220" H 12400 3950 40  0000 C CNN
+F 1 "100" H 12400 3950 40  0000 C CNN
 	1    12400 3750
 	1    0    0    -1  
 $EndComp
@@ -994,7 +994,7 @@ L R_PACK4 RA101
 U 1 1 4D9630F0
 P 12400 3350
 F 0 "RA101" H 12400 3800 40  0000 C CNN
-F 1 "220" H 12400 3550 40  0000 C CNN
+F 1 "100" H 12400 3550 40  0000 C CNN
 	1    12400 3350
 	1    0    0    -1  
 $EndComp
@@ -1005,7 +1005,7 @@ P 12400 4750
 AR Path="/4B6E16F2/4D95CDCD" Ref="RP?"  Part="1" 
 AR Path="/4B6E16F2/4D95CDD4" Ref="RA104"  Part="1" 
 F 0 "RA104" H 12400 4650 40  0000 C CNN
-F 1 "220" H 12400 4950 40  0000 C CNN
+F 1 "FB" H 12400 4950 40  0000 C CNN
 	1    12400 4750
 	1    0    0    -1  
 $EndComp
@@ -1014,7 +1014,7 @@ L R_PACK4 RA103
 U 1 1 4D95CDCD
 P 12400 4350
 F 0 "RA103" H 12400 4800 40  0000 C CNN
-F 1 "220" H 12400 4550 40  0000 C CNN
+F 1 "FB" H 12400 4550 40  0000 C CNN
 	1    12400 4350
 	1    0    0    -1  
 $EndComp
@@ -1125,7 +1125,7 @@ L R R102
 U 1 1 4C7EAEBF
 P 6850 8600
 F 0 "R102" V 6930 8600 50  0000 C CNN
-F 1 "1k" V 6850 8600 50  0000 C CNN
+F 1 "100k" V 6850 8600 50  0000 C CNN
 	1    6850 8600
 	1    0    0    -1  
 $EndComp

pcb/kicad/RevE2/memory.sch

@@ -0,0 +1,807 @@
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:snescart
+LIBS:misc-74
+LIBS:vreg
+LIBS:lpc1754
+LIBS:sd_card
+LIBS:cy62148ev30
+LIBS:mt45w8mw16
+LIBS:cs4344
+LIBS:double_sch_kcom
+LIBS:usb_minib
+LIBS:mic23250
+LIBS:sd2snes-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 3 6
+Title "sd2snes Mark II"
+Date "2 jan 2012"
+Rev "E2"
+Comp "Maximilian Rehkopf"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Text Label 7650 2000 0    50   ~ 0
+SRAM_Vcc
+Wire Wire Line
+	7650 4750 7650 5000
+Wire Wire Line
+	8350 5050 8350 5250
+Wire Wire Line
+	8350 5250 8500 5250
+Connection ~ 9150 5250
+Wire Wire Line
+	9150 5450 9150 5250
+Connection ~ 9600 2000
+Wire Wire Line
+	9600 2000 9600 3350
+Wire Wire Line
+	10500 2000 10350 2000
+Wire Wire Line
+	8400 1400 8400 1600
+Wire Wire Line
+	8400 1600 8050 1600
+Wire Wire Line
+	6800 4350 6300 4350
+Wire Wire Line
+	6800 4250 6300 4250
+Wire Wire Line
+	6800 4150 6300 4150
+Wire Wire Line
+	6800 4050 6300 4050
+Wire Wire Line
+	6800 3950 6300 3950
+Wire Wire Line
+	6800 3850 6300 3850
+Wire Wire Line
+	6800 3750 6300 3750
+Wire Wire Line
+	6800 3650 6300 3650
+Wire Wire Line
+	6800 3550 6300 3550
+Wire Wire Line
+	6800 3450 6300 3450
+Wire Wire Line
+	6800 3350 6300 3350
+Wire Wire Line
+	6800 3250 6300 3250
+Wire Wire Line
+	6800 3150 6300 3150
+Wire Wire Line
+	6800 3050 6300 3050
+Wire Wire Line
+	6800 2950 6300 2950
+Wire Wire Line
+	6800 2850 6300 2850
+Wire Wire Line
+	6800 2750 6300 2750
+Wire Wire Line
+	6800 2650 6300 2650
+Wire Wire Line
+	6800 2550 6300 2550
+Wire Wire Line
+	8500 3950 9000 3950
+Wire Wire Line
+	4750 4750 4250 4750
+Wire Wire Line
+	4250 4650 4750 4650
+Wire Wire Line
+	4250 4350 4750 4350
+Wire Wire Line
+	4250 4150 4750 4150
+Wire Wire Line
+	4250 4050 4750 4050
+Wire Wire Line
+	4250 3750 4750 3750
+Wire Wire Line
+	4250 3650 4750 3650
+Wire Wire Line
+	4250 3550 4750 3550
+Wire Wire Line
+	4250 3450 4750 3450
+Wire Wire Line
+	4250 3350 4750 3350
+Wire Wire Line
+	4250 3250 4750 3250
+Wire Wire Line
+	4250 3150 4750 3150
+Wire Wire Line
+	4250 3050 4750 3050
+Wire Wire Line
+	4250 2850 4750 2850
+Wire Wire Line
+	4250 2750 4750 2750
+Wire Wire Line
+	4250 2650 4750 2650
+Wire Wire Line
+	4250 2550 4750 2550
+Wire Wire Line
+	4250 2450 4750 2450
+Wire Wire Line
+	4250 2350 4750 2350
+Wire Wire Line
+	4250 2250 4750 2250
+Wire Wire Line
+	4250 2150 4750 2150
+Wire Wire Line
+	3550 6800 3550 6700
+Wire Wire Line
+	3400 5400 3400 5300
+Wire Wire Line
+	3300 5150 3300 5300
+Wire Wire Line
+	3300 1750 3300 1550
+Connection ~ 7650 2000
+Wire Wire Line
+	3500 1750 3500 1550
+Wire Wire Line
+	3500 5150 3500 5300
+Wire Wire Line
+	3500 5300 3300 5300
+Connection ~ 3400 5300
+Wire Wire Line
+	3550 7200 3550 7300
+Wire Wire Line
+	3250 7200 3250 7300
+Wire Wire Line
+	3250 6700 3250 6800
+Wire Wire Line
+	2550 2150 2050 2150
+Wire Wire Line
+	2550 2250 2050 2250
+Wire Wire Line
+	2550 2350 2050 2350
+Wire Wire Line
+	2550 2450 2050 2450
+Wire Wire Line
+	2550 2550 2050 2550
+Wire Wire Line
+	2550 2650 2050 2650
+Wire Wire Line
+	2550 2750 2050 2750
+Wire Wire Line
+	2550 2850 2050 2850
+Wire Wire Line
+	2550 2950 2050 2950
+Wire Wire Line
+	2550 3050 2050 3050
+Wire Wire Line
+	2550 3150 2050 3150
+Wire Wire Line
+	2550 3250 2050 3250
+Wire Wire Line
+	2550 3350 2050 3350
+Wire Wire Line
+	2550 3450 2050 3450
+Wire Wire Line
+	2550 3550 2050 3550
+Wire Wire Line
+	2550 3650 2050 3650
+Wire Wire Line
+	2550 3750 2050 3750
+Wire Wire Line
+	2550 3850 2050 3850
+Wire Wire Line
+	2550 3950 2050 3950
+Wire Wire Line
+	2550 4050 2050 4050
+Wire Wire Line
+	2550 4150 2050 4150
+Wire Wire Line
+	2550 4250 2050 4250
+Wire Wire Line
+	2550 4350 2050 4350
+Wire Wire Line
+	2550 4650 2050 4650
+Wire Wire Line
+	2550 4750 2050 4750
+Wire Wire Line
+	2550 4550 2050 4550
+Wire Wire Line
+	8500 4050 9000 4050
+Connection ~ 4750 4750
+Wire Wire Line
+	4750 4350 4750 5400
+Connection ~ 4750 4650
+Wire Wire Line
+	8500 2550 9000 2550
+Wire Wire Line
+	8500 2650 9000 2650
+Wire Wire Line
+	8500 2750 9000 2750
+Wire Wire Line
+	8500 2850 9000 2850
+Wire Wire Line
+	8500 2950 9000 2950
+Wire Wire Line
+	8500 3050 9000 3050
+Wire Wire Line
+	8500 3150 9000 3150
+Wire Wire Line
+	8500 3250 9000 3250
+Wire Wire Line
+	7250 1600 6900 1600
+Wire Wire Line
+	6900 1600 6900 1400
+Wire Wire Line
+	8500 3850 9600 3850
+Wire Wire Line
+	9600 3850 9600 5050
+Wire Wire Line
+	9000 5250 9300 5250
+Wire Wire Line
+	9150 5950 9150 6050
+Wire Wire Line
+	9150 6050 9600 6050
+Wire Wire Line
+	9600 6350 9600 5450
+Connection ~ 9600 6050
+Wire Wire Line
+	7650 2150 7650 1800
+Wire Wire Line
+	9950 2000 7650 2000
+$Comp
+L CY62148EV30-ZSXI U511
+U 1 1 4D49598F
+P 7650 3450
+F 0 "U511" H 7650 3550 60  0000 C CNN
+F 1 "CY62148EV30-ZSXI" H 7700 3450 60  0000 C CNN
+	1    7650 3450
+	1    0    0    -1  
+$EndComp
+Text Notes 7050 7000 0    250  ~ 50
+Memory
+Text Notes 7300 1300 0    50   ~ 0
+SRAM battery power
+Text Notes 9800 5300 0    50   ~ 0
+Battery power OE switch
+$Comp
+L +3.3V #PWR031
+U 1 1 4BF2FE97
+P 8350 5050
+F 0 "#PWR031" H 8350 5010 30  0001 C CNN
+F 1 "+3.3V" H 8350 5160 30  0000 C CNN
+	1    8350 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR032
+U 1 1 4BF2FE7B
+P 9600 6350
+F 0 "#PWR032" H 9600 6350 30  0001 C CNN
+F 1 "GND" H 9600 6280 30  0001 C CNN
+	1    9600 6350
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R511
+U 1 1 4BF2FDAF
+P 9600 3600
+F 0 "R511" V 9680 3600 50  0000 C CNN
+F 1 "20k" V 9600 3600 50  0000 C CNN
+F 2 "SM0805_FIXEDMASK" H 9600 3600 60  0001 C CNN
+	1    9600 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R513
+U 1 1 4BF2FDAC
+P 9150 5700
+F 0 "R513" V 9230 5700 50  0000 C CNN
+F 1 "100k" V 9150 5700 50  0000 C CNN
+F 2 "SM0805_FIXEDMASK" H 9150 5700 60  0001 C CNN
+	1    9150 5700
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R512
+U 1 1 4BF2FDA9
+P 8750 5250
+F 0 "R512" V 8830 5250 50  0000 C CNN
+F 1 "4k7" V 8750 5250 50  0000 C CNN
+F 2 "SM0805_FIXEDMASK" H 8750 5250 60  0001 C CNN
+	1    8750 5250
+	0    1    1    0   
+$EndComp
+$Comp
+L NPN Q511
+U 1 1 4BF2FD9F
+P 9500 5250
+F 0 "Q511" H 9500 5100 50  0000 R CNN
+F 1 "2N2222A" H 9500 5400 50  0000 R CNN
+F 2 "SOT23EBC" H 9500 5250 60  0001 C CNN
+	1    9500 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR033
+U 1 1 4BF1A006
+P 10500 2000
+F 0 "#PWR033" H 10500 2000 30  0001 C CNN
+F 1 "GND" H 10500 1930 30  0001 C CNN
+	1    10500 2000
+	0    -1   -1   0   
+$EndComp
+$Comp
+L +BATT #PWR034
+U 1 1 4BF19EA4
+P 8400 1400
+F 0 "#PWR034" H 8400 1350 20  0001 C CNN
+F 1 "+BATT" H 8400 1500 30  0000 C CNN
+	1    8400 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L +3.3V #PWR035
+U 1 1 4BF19E7A
+P 6900 1400
+F 0 "#PWR035" H 6900 1360 30  0001 C CNN
+F 1 "+3.3V" H 6900 1510 30  0000 C CNN
+	1    6900 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L DOUBLE_SCH_KCOM2 D511
+U 1 1 4BF19DCA
+P 7650 1600
+F 0 "D511" H 7800 1475 60  0000 C CNN
+F 1 "BAT54C" H 7650 1750 60  0000 C CNN
+F 2 "SOT23EBC" H 7650 1600 60  0001 C CNN
+	1    7650 1600
+	1    0    0    -1  
+$EndComp
+Text Label 8600 4050 0    50   ~ 0
+RAM_/WE
+Text Label 8600 3950 0    50   ~ 0
+RAM_/OE
+Text Label 8600 3850 0    50   ~ 0
+RAM_/CE
+Text Label 8600 3250 0    50   ~ 0
+RAM_DQ7
+Text Label 8600 3150 0    50   ~ 0
+RAM_DQ6
+Text Label 8600 3050 0    50   ~ 0
+RAM_DQ5
+Text Label 8600 2950 0    50   ~ 0
+RAM_DQ4
+Text Label 8600 2850 0    50   ~ 0
+RAM_DQ3
+Text Label 8600 2750 0    50   ~ 0
+RAM_DQ2
+Text Label 8600 2650 0    50   ~ 0
+RAM_DQ1
+Text Label 8600 2550 0    50   ~ 0
+RAM_DQ0
+Text Label 6400 4350 0    50   ~ 0
+RAM_A18
+Text Label 6400 4250 0    50   ~ 0
+RAM_A17
+Text Label 6400 4150 0    50   ~ 0
+RAM_A16
+Text Label 6400 4050 0    50   ~ 0
+RAM_A15
+Text Label 6400 3950 0    50   ~ 0
+RAM_A14
+Text Label 6400 3850 0    50   ~ 0
+RAM_A13
+Text Label 6400 3750 0    50   ~ 0
+RAM_A12
+Text Label 6400 3650 0    50   ~ 0
+RAM_A11
+Text Label 6400 3550 0    50   ~ 0
+RAM_A10
+Text Label 6400 3450 0    50   ~ 0
+RAM_A9
+Text Label 6400 3350 0    50   ~ 0
+RAM_A8
+Text Label 6400 3250 0    50   ~ 0
+RAM_A7
+Text Label 6400 3150 0    50   ~ 0
+RAM_A6
+Text Label 6400 3050 0    50   ~ 0
+RAM_A5
+Text Label 6400 2950 0    50   ~ 0
+RAM_A4
+Text Label 6400 2850 0    50   ~ 0
+RAM_A3
+Text Label 6400 2750 0    50   ~ 0
+RAM_A2
+Text Label 6400 2650 0    50   ~ 0
+RAM_A1
+Text Label 6400 2550 0    50   ~ 0
+RAM_A0
+Text Label 4350 4150 0    50   ~ 0
+ROM_/UB
+Text Label 4350 4050 0    50   ~ 0
+ROM_/LB
+Text Label 4350 3750 0    50   ~ 0
+ROM_DQ15
+Text Label 4350 3650 0    50   ~ 0
+ROM_DQ14
+Text Label 4350 3550 0    50   ~ 0
+ROM_DQ13
+Text Label 4350 3450 0    50   ~ 0
+ROM_DQ12
+Text Label 4350 3350 0    50   ~ 0
+ROM_DQ11
+Text Label 4350 3250 0    50   ~ 0
+ROM_DQ10
+Text Label 4350 3150 0    50   ~ 0
+ROM_DQ9
+Text Label 4350 3050 0    50   ~ 0
+ROM_DQ8
+Text Label 4350 2850 0    50   ~ 0
+ROM_DQ7
+Text Label 4350 2750 0    50   ~ 0
+ROM_DQ6
+Text Label 4350 2650 0    50   ~ 0
+ROM_DQ5
+Text Label 4350 2550 0    50   ~ 0
+ROM_DQ4
+Text Label 4350 2450 0    50   ~ 0
+ROM_DQ3
+Text Label 4350 2350 0    50   ~ 0
+ROM_DQ2
+Text Label 4350 2250 0    50   ~ 0
+ROM_DQ1
+Text Label 4350 2150 0    50   ~ 0
+ROM_DQ0
+Text Label 2100 4750 0    50   ~ 0
+ROM_/WE
+Text Label 2100 4650 0    50   ~ 0
+ROM_/OE
+Text Label 2100 4550 0    50   ~ 0
+ROM_/CE
+Text Label 2100 4350 0    50   ~ 0
+ROM_A22
+Text Label 2100 4250 0    50   ~ 0
+ROM_A21
+Text Label 2100 4150 0    50   ~ 0
+ROM_A20
+Text Label 2100 4050 0    50   ~ 0
+ROM_A19
+Text Label 2100 3950 0    50   ~ 0
+ROM_A18
+Text Label 2100 3850 0    50   ~ 0
+ROM_A17
+Text Label 2100 3750 0    50   ~ 0
+ROM_A16
+Text Label 2100 3650 0    50   ~ 0
+ROM_A15
+Text Label 2100 3550 0    50   ~ 0
+ROM_A14
+Text Label 2100 3450 0    50   ~ 0
+ROM_A13
+Text Label 2100 3350 0    50   ~ 0
+ROM_A12
+Text Label 2100 3250 0    50   ~ 0
+ROM_A11
+Text Label 2100 3150 0    50   ~ 0
+ROM_A10
+Text Label 2100 3050 0    50   ~ 0
+ROM_A9
+Text Label 2100 2950 0    50   ~ 0
+ROM_A8
+Text Label 2100 2850 0    50   ~ 0
+ROM_A7
+Text Label 2100 2750 0    50   ~ 0
+ROM_A6
+Text Label 2100 2650 0    50   ~ 0
+ROM_A5
+Text Label 2100 2550 0    50   ~ 0
+ROM_A4
+Text Label 2100 2450 0    50   ~ 0
+ROM_A3
+Text Label 2100 2350 0    50   ~ 0
+ROM_A2
+Text Label 2100 2250 0    50   ~ 0
+ROM_A1
+Text Label 2100 2150 0    50   ~ 0
+ROM_A0
+Text GLabel 2050 4550 0    50   Input ~ 0
+ROM_/CE
+Text GLabel 9000 4050 2    50   Input ~ 0
+RAM_/WE
+Text GLabel 9000 3950 2    50   Input ~ 0
+RAM_/OE
+Text GLabel 9000 3250 2    50   BiDi ~ 0
+RAM_DQ7
+Text GLabel 9000 3150 2    50   BiDi ~ 0
+RAM_DQ6
+Text GLabel 9000 3050 2    50   BiDi ~ 0
+RAM_DQ5
+Text GLabel 9000 2950 2    50   BiDi ~ 0
+RAM_DQ4
+Text GLabel 9000 2850 2    50   BiDi ~ 0
+RAM_DQ3
+Text GLabel 9000 2750 2    50   BiDi ~ 0
+RAM_DQ2
+Text GLabel 9000 2650 2    50   BiDi ~ 0
+RAM_DQ1
+Text GLabel 9000 2550 2    50   BiDi ~ 0
+RAM_DQ0
+Text GLabel 6300 4350 0    50   Input ~ 0
+RAM_A18
+Text GLabel 6300 4250 0    50   Input ~ 0
+RAM_A17
+Text GLabel 6300 4150 0    50   Input ~ 0
+RAM_A16
+Text GLabel 6300 4050 0    50   Input ~ 0
+RAM_A15
+Text GLabel 6300 3950 0    50   Input ~ 0
+RAM_A14
+Text GLabel 6300 3850 0    50   Input ~ 0
+RAM_A13
+Text GLabel 6300 3750 0    50   Input ~ 0
+RAM_A12
+Text GLabel 6300 3650 0    50   Input ~ 0
+RAM_A11
+Text GLabel 6300 3550 0    50   Input ~ 0
+RAM_A10
+Text GLabel 6300 3450 0    50   Input ~ 0
+RAM_A9
+Text GLabel 6300 3350 0    50   Input ~ 0
+RAM_A8
+Text GLabel 6300 3250 0    50   Input ~ 0
+RAM_A7
+Text GLabel 6300 3150 0    50   Input ~ 0
+RAM_A6
+Text GLabel 6300 3050 0    50   Input ~ 0
+RAM_A5
+Text GLabel 6300 2950 0    50   Input ~ 0
+RAM_A4
+Text GLabel 6300 2850 0    50   Input ~ 0
+RAM_A3
+Text GLabel 6300 2750 0    50   Input ~ 0
+RAM_A2
+Text GLabel 6300 2650 0    50   Input ~ 0
+RAM_A1
+Text GLabel 6300 2550 0    50   Input ~ 0
+RAM_A0
+Text GLabel 4750 4150 2    50   Input ~ 0
+ROM_/UB
+Text GLabel 4750 4050 2    50   Input ~ 0
+ROM_/LB
+Text GLabel 4750 3750 2    50   BiDi ~ 0
+ROM_DQ15
+Text GLabel 4750 3650 2    50   BiDi ~ 0
+ROM_DQ14
+Text GLabel 4750 3550 2    50   BiDi ~ 0
+ROM_DQ13
+Text GLabel 4750 3450 2    50   BiDi ~ 0
+ROM_DQ12
+Text GLabel 4750 3350 2    50   BiDi ~ 0
+ROM_DQ11
+Text GLabel 4750 3250 2    50   BiDi ~ 0
+ROM_DQ10
+Text GLabel 4750 3150 2    50   BiDi ~ 0
+ROM_DQ9
+Text GLabel 4750 3050 2    50   BiDi ~ 0
+ROM_DQ8
+Text GLabel 4750 2850 2    50   BiDi ~ 0
+ROM_DQ7
+Text GLabel 4750 2750 2    50   BiDi ~ 0
+ROM_DQ6
+Text GLabel 4750 2650 2    50   BiDi ~ 0
+ROM_DQ5
+Text GLabel 4750 2550 2    50   BiDi ~ 0
+ROM_DQ4
+Text GLabel 4750 2450 2    50   BiDi ~ 0
+ROM_DQ3
+Text GLabel 4750 2350 2    50   BiDi ~ 0
+ROM_DQ2
+Text GLabel 4750 2250 2    50   BiDi ~ 0
+ROM_DQ1
+Text GLabel 4750 2150 2    50   BiDi ~ 0
+ROM_DQ0
+Text GLabel 2050 4350 0    50   Input ~ 0
+ROM_A22
+Text GLabel 2050 4250 0    50   Input ~ 0
+ROM_A21
+Text GLabel 2050 4150 0    50   Input ~ 0
+ROM_A20
+Text GLabel 2050 4050 0    50   Input ~ 0
+ROM_A19
+Text GLabel 2050 3950 0    50   Input ~ 0
+ROM_A18
+Text GLabel 2050 3850 0    50   Input ~ 0
+ROM_A17
+Text GLabel 2050 3750 0    50   Input ~ 0
+ROM_A16
+Text GLabel 2050 3650 0    50   Input ~ 0
+ROM_A15
+Text GLabel 2050 3550 0    50   Input ~ 0
+ROM_A14
+Text GLabel 2050 3450 0    50   Input ~ 0
+ROM_A13
+Text GLabel 2050 3350 0    50   Input ~ 0
+ROM_A12
+Text GLabel 2050 3250 0    50   Input ~ 0
+ROM_A11
+Text GLabel 2050 3150 0    50   Input ~ 0
+ROM_A10
+Text GLabel 2050 3050 0    50   Input ~ 0
+ROM_A9
+Text GLabel 2050 2950 0    50   Input ~ 0
+ROM_A8
+Text GLabel 2050 2850 0    50   Input ~ 0
+ROM_A7
+Text GLabel 2050 2750 0    50   Input ~ 0
+ROM_A6
+Text GLabel 2050 2650 0    50   Input ~ 0
+ROM_A5
+Text GLabel 2050 2550 0    50   Input ~ 0
+ROM_A4
+Text GLabel 2050 2450 0    50   Input ~ 0
+ROM_A3
+Text GLabel 2050 2350 0    50   Input ~ 0
+ROM_A2
+Text GLabel 2050 2250 0    50   Input ~ 0
+ROM_A1
+Text GLabel 2050 2150 0    50   Input ~ 0
+ROM_A0
+NoConn ~ 4250 4550
+$Comp
+L GND #PWR036
+U 1 1 4BCA30BF
+P 4750 5400
+F 0 "#PWR036" H 4750 5400 30  0001 C CNN
+F 1 "GND" H 4750 5330 30  0001 C CNN
+	1    4750 5400
+	1    0    0    -1  
+$EndComp
+Text GLabel 2050 4750 0    50   Input ~ 0
+ROM_/WE
+Text GLabel 2050 4650 0    50   Input ~ 0
+ROM_/OE
+$Comp
+L C C502
+U 1 1 4BAD3D55
+P 3550 7000
+F 0 "C502" H 3600 7100 50  0000 L CNN
+F 1 "100n" H 3600 6900 50  0000 L CNN
+F 2 "SM0805_FIXEDMASK" H 3550 7000 60  0001 C CNN
+	1    3550 7000
+	1    0    0    -1  
+$EndComp
+$Comp
+L C C511
+U 1 1 4BAD3D53
+P 10150 2000
+F 0 "C511" H 10200 2100 50  0000 L CNN
+F 1 "100n" H 10200 1900 50  0000 L CNN
+F 2 "SM0805_FIXEDMASK" H 10150 2000 60  0001 C CNN
+	1    10150 2000
+	0    -1   1    0   
+$EndComp
+$Comp
+L C C501
+U 1 1 4BAD3D47
+P 3250 7000
+F 0 "C501" H 3300 7100 50  0000 L CNN
+F 1 "100n" H 3300 6900 50  0000 L CNN
+F 2 "SM0805_FIXEDMASK" H 3250 7000 60  0001 C CNN
+	1    3250 7000
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR037
+U 1 1 4BAD3D2B
+P 3550 7300
+F 0 "#PWR037" H 3550 7300 30  0001 C CNN
+F 1 "GND" H 3550 7230 30  0001 C CNN
+	1    3550 7300
+	1    0    0    -1  
+$EndComp
+$Comp
+L +1.8V #PWR038
+U 1 1 4BAD3D27
+P 3550 6700
+F 0 "#PWR038" H 3550 6840 20  0001 C CNN
+F 1 "+1.8V" H 3550 6810 30  0000 C CNN
+	1    3550 6700
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR039
+U 1 1 4BAD3D20
+P 3250 7300
+F 0 "#PWR039" H 3250 7300 30  0001 C CNN
+F 1 "GND" H 3250 7230 30  0001 C CNN
+	1    3250 7300
+	1    0    0    -1  
+$EndComp
+$Comp
+L +3.3V #PWR040
+U 1 1 4BAD3D0B
+P 3250 6700
+F 0 "#PWR040" H 3250 6660 30  0001 C CNN
+F 1 "+3.3V" H 3250 6810 30  0000 C CNN
+	1    3250 6700
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR041
+U 1 1 4BAD33A7
+P 3400 5400
+F 0 "#PWR041" H 3400 5400 30  0001 C CNN
+F 1 "GND" H 3400 5330 30  0001 C CNN
+	1    3400 5400
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR042
+U 1 1 4BAD339F
+P 7650 5000
+F 0 "#PWR042" H 7650 5000 30  0001 C CNN
+F 1 "GND" H 7650 4930 30  0001 C CNN
+	1    7650 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L +1.8V #PWR043
+U 1 1 4BAD32D2
+P 3300 1550
+F 0 "#PWR043" H 3300 1690 20  0001 C CNN
+F 1 "+1.8V" H 3300 1660 30  0000 C CNN
+	1    3300 1550
+	1    0    0    -1  
+$EndComp
+$Comp
+L +3.3V #PWR044
+U 1 1 4BAD32BE
+P 3500 1550
+F 0 "#PWR044" H 3500 1510 30  0001 C CNN
+F 1 "+3.3V" H 3500 1660 30  0000 C CNN
+	1    3500 1550
+	1    0    0    -1  
+$EndComp
+Text Notes 6300 5700 0    60   ~ 0
+4Mbits 45ns SRAM (battery RAM + custom chip work RAM)
+Text Notes 2650 5700 0    60   ~ 0
+128Mbits 70ns PSRAM (ROM area)
+$Comp
+L MT45W8MW16 U501
+U 1 1 4B868602
+P 3400 3450
+F 0 "U501" H 3400 3550 60  0000 C CNN
+F 1 "MT45W8MW16" H 3400 3450 60  0000 C CNN
+F 2 "VFBGA54" H 3400 3450 60  0001 C CNN
+	1    3400 3450
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC

pcb/kicad/RevE2/padreduce.sh

@@ -0,0 +1,17 @@
+cp "$1" "$1".bak
+
+sed -e 's/^%ADD\(..\)R/%ADD\1O/g' < "$1" > "$1".tmp1
+
+grep ^%ADD..O "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; Y=${ln:17:8}; X2=`echo $X-.001 | bc -l`; Y2=`echo $Y-.001 | bc -l`; echo $LS`printf '%01.6f' $X2`X`printf '%01.6f' $Y2`*%; done > "$1".tmp2
+
+grep ^%ADD..C "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; X2=`echo $X-.001 | bc -l`; echo $LS`printf '%01.6f' $X2`*%; done >> "$1".tmp2
+
+while read ln; do echo "$ln" | grep '^%ADD' >/dev/null && break; echo "$ln"; done < "$1".tmp1 > "$1"
+
+cat "$1".tmp2 >> "$1"
+
+grep -A100000 'G04 APERTURE END LIST\*' "$1".tmp1 >> "$1"
+
+rm "$1".tmp1 "$1".tmp2
+
+

pcb/kicad/RevE2/sd2snes.pro

@@ -0,0 +1,117 @@
+update=Sat 25 Feb 2012 11:51:50 PM CET
+version=1
+last_client=pcbnew
+[general]
+version=1
+[cvpcb]
+version=1
+NetIExt=net
+[cvpcb/libraries]
+EquName1=devcms
+[eeschema]
+version=1
+LibDir=../../kicad
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=50
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=libs/snescart
+LibName32=libs/misc-74
+LibName33=libs/vreg
+LibName34=libs/lpc1754
+LibName35=libs/sd_card
+LibName36=libs/cy62148ev30
+LibName37=libs/mt45w8mw16
+LibName38=libs/cs4344
+LibName39=libs/double_sch_kcom
+LibName40=libs/usb_minib
+LibName41=libs/mic23250
+[pcbnew]
+version=1
+PadDrlX=0
+PadDimH=197
+PadDimV=276
+BoardThickness=630
+TxtPcbV=800
+TxtPcbH=600
+TxtModV=600
+TxtModH=600
+TxtModW=120
+VEgarde=40
+DrawLar=70
+EdgeLar=40
+TxtLar=120
+MSegLar=79
+LastNetListRead=sd2snes.net
+[pcbnew/libraries]
+LibDir=../../kicad
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=libcms
+LibName7=display
+LibName8=valves
+LibName9=led
+LibName10=dip_sockets
+LibName11=libs/mypackages
+LibName12=libs/snescart
+LibName13=libs/sdcard
+LibName14=libs/snail
+LibName15=libs/snail2

pcb/kicad/RevE2/sd2snes.sch

@@ -0,0 +1,94 @@
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:snescart
+LIBS:misc-74
+LIBS:vreg
+LIBS:lpc1754
+LIBS:sd_card
+LIBS:cy62148ev30
+LIBS:mt45w8mw16
+LIBS:cs4344
+LIBS:double_sch_kcom
+LIBS:usb_minib
+LIBS:mic23250
+LIBS:sd2snes-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 6
+Title "sd2snes Mark II"
+Date "2 jan 2012"
+Rev "E2"
+Comp "Maximilian Rehkopf"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Notes Line
+	3650 4200 6150 4200
+Text Notes 3300 3250 0    100  ~ 0
+Changes from Rev.A / TODO:\n [x] remove FPGA from JTAG chain\n [x] remove SNES IRQ_DIR+IRQ, replace with IRQ_OE. IRQ is unidirectional cart -> console\n      (replace 1gate w/ transistor)\n [x] disconnect P2.10 from FPGA, using a different GPIO for IRQ / INIT_B\n [x] add pullup to P2.10\n [ ] add JTAG pullups\n [x] add series resistor for CPU_CLK\n [x] add a jumper in PIC MCLR line to MCU\n [x] change PIC to DIP8 type for easier preprogramming\n [x] change "P1" to "P401" in pin description in silk screen\n [x] filter CIC data lines\n [x] rearrange SD card interface/LEDs on MCU\n [x] RAs for SNES signals?\n [x] reroute/add decoupling capacitors\n [x] filter SNES control signals (RD, WR, PARD, PAWR, CPU_CLK, IRQ)\n [x] replace 4Mbit SRAM with much cheaper TSOP-II type\n [x] add inverse polarity protection\n [x] separate GND plane for DAC\n [ ] separate JTAG pads for FPGA\n [x] add USE_BATT jumper\n [x] move PROG_B to P1.15
+$Sheet
+S 1250 1250 1700 1250
+U 4B6E16F2
+F0 "SNES Slot" 60
+F1 "snesslot.sch" 60
+$EndSheet
+Text Notes 750  7700 0    500  ~ 100
+sd2snes Mark II
+$Sheet
+S 1250 3300 1600 1150
+U 4BAA6ABD
+F0 "Memory" 60
+F1 "memory.sch" 60
+$EndSheet
+$Sheet
+S 8050 1250 1600 1250
+U 4B6ED75B
+F0 "MCU" 60
+F1 "mcu.sch" 60
+$EndSheet
+$Sheet
+S 5900 1250 1600 1250
+U 4B6EC9C3
+F0 "Power Supply / Misc." 60
+F1 "pwr_misc.sch" 60
+$EndSheet
+$Sheet
+S 3650 1250 1650 1250
+U 4B6E18FC
+F0 "FPGA" 60
+F1 "fpga.sch" 60
+$EndSheet
+$EndSCHEMATC

pcb/kicad/libs/mypackages.mod

@@ -1,17 +1,21 @@
-PCBNEW-LibModule-V1  Wed 14 Sep 2011 12:39:55 AM CEST
+PCBNEW-LibModule-V1  Sun 26 Feb 2012 12:35:43 AM CET
 # encoding utf-8
 $INDEX
 BT_KEYSTONE_1059_20MM
 CP_TANTAL_SMD_D
 DIP-36
 HC49US
+HRS-DM1AA
 LED-3MM-FIXED
 LQFP80-.5
+L_4.2X4.2
 PAD_1x1mm
 PQFP208_ALTPADS
 QFN10-2x2
 QFN10-2x2_LONGPADS
 R_PACK_0804
+R_PACK_0804_LONGPADS
+R_PACK_1206
 SM0805_FIXEDMASK
 SM1210L
 SM1210L_NEW
@@ -23,8 +27,11 @@ TSOP40
 TSOPII-32
 TSOPII-44
 TSSOP10
+TSSOP10_LONGPADS
 TSSOP48
+TSSOP48_LONGPADS
 USB-MINIB-THT
+USB_MINIB_SMT
 VFBGA36
 VFBGA48
 VFBGA54
@@ -4107,41 +4114,6 @@ Of 0.000000 0.000000 0.000000
 Ro 0.000000 0.000000 0.000000
 $EndSHAPE3D
 $EndMODULE  SM1210L_NEW
-$MODULE LED-3MM-FIXED
-Po 0 0 0 15 4D251EA9 00000000 ~~
-Li LED-3MM-FIXED
-Cd LED 3mm - Lead pitch 100mil (2,54mm)
-Kw LED led 3mm 3MM 100mil 2,54mm
-Sc 00000000
-AR /4B6ED75B/4C0DA78D
-Op 0 0 0
-At VIRTUAL
-T0 -300 -2125 320 320 0 70 N V 21 N"D403"
-T1 25 3575 320 320 2700 70 N V 21 N"LED_2mA_1.7V,_red"
-DS 669 669 669 394 80 21
-DS 669 -669 669 -394 80 21
-DA 0 0 669 669 2700 80 21
-$PAD
-Sh "1" C 660 660 0 0 0
-Dr 400 0 0
-At STD N 00E8FFFF
-Ne 1 "+3.3V"
-Po -500 0
-$EndPAD
-$PAD
-Sh "2" C 660 660 0 0 0
-Dr 400 0 0
-At STD N 00E8FFFF
-Ne 2 "N-000262"
-Po 500 0
-$EndPAD
-$SHAPE3D
-Na "libs/led3_vertical_red.wrl"
-Sc 1.000000 1.000000 1.000000
-Of 0.000000 0.000000 0.000000
-Ro 0.000000 0.000000 0.000000
-$EndSHAPE3D
-$EndMODULE  LED-3MM-FIXED
 $MODULE HC49US
 Po 0 0 0 15 4D2590A9 00000000 ~~
 Li HC49US
@@ -5668,4 +5640,878 @@ Ne 33 "N-000035"
 Po -3828 1870
 $EndPAD
 $EndMODULE  TSOP40
+$MODULE R_PACK_1206
+Po 0 0 0 15 4EF2E0E8 00000000 ~~
+Li R_PACK_1206
+Sc 00000000
+AR R_PACK_1206
+Op 0 0 0
+T0 0 0 600 600 0 120 N V 21 N "R_PACK_1206"
+T1 0 0 600 600 0 120 N V 21 N "VAL**"
+DS -866 -827 866 -827 79 21
+DS 866 -827 866 827 79 21
+DS 866 827 -866 827 79 21
+DS -866 827 -866 -827 79 21
+$PAD
+Sh "1" R 248 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -510 384
+$EndPAD
+$PAD
+Sh "2" R 173 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -157 384
+$EndPAD
+$PAD
+Sh "3" R 173 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 157 384
+$EndPAD
+$PAD
+Sh "4" R 248 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 510 384
+$EndPAD
+$PAD
+Sh "5" R 248 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 510 -384
+$EndPAD
+$PAD
+Sh "6" R 173 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 157 -384
+$EndPAD
+$PAD
+Sh "7" R 173 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -157 -384
+$EndPAD
+$PAD
+Sh "8" R 248 453 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -510 -384
+$EndPAD
+$EndMODULE  R_PACK_1206
+$MODULE TSSOP10_LONGPADS
+Po 0 0 0 15 4EF2E58B 00000000 ~~
+Li TSSOP10_LONGPADS
+Sc 00000000
+AR
+Op 0 0 0
+T0 0 0 600 600 0 120 N V 21 N "Test"
+T1 0 0 600 600 0 120 N V 21 N "VAL**"
+DC -394 394 -315 394 60 21
+DS -590 -590 590 -590 60 21
+DS 590 -590 590 590 60 21
+DS -590 590 590 590 60 21
+DS -590 -590 -590 590 60 21
+$PAD
+Sh "1" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -393 965
+$EndPAD
+$PAD
+Sh "2" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -196 965
+$EndPAD
+$PAD
+Sh "3" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 0 965
+$EndPAD
+$PAD
+Sh "4" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 196 965
+$EndPAD
+$PAD
+Sh "5" R 118 551 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 393 965
+$EndPAD
+$PAD
+Sh "6" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 393 -965
+$EndPAD
+$PAD
+Sh "7" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 196 -965
+$EndPAD
+$PAD
+Sh "8" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 0 -965
+$EndPAD
+$PAD
+Sh "9" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -196 -965
+$EndPAD
+$PAD
+Sh "10" R 118 551 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -393 -965
+$EndPAD
+$EndMODULE  TSSOP10_LONGPADS
+$MODULE L_4.2X4.2
+Po 0 0 0 15 4EF777D2 00000000 ~~
+Li L_4.2X4.2
+Sc 00000000
+AR
+Op 0 0 0
+T0 0 0 600 600 0 120 N V 21 N "L_4.2X4.2"
+T1 0 0 600 600 0 120 N V 21 N "VAL**"
+DS -1024 -984 1024 -984 79 21
+DS 1024 -984 1024 984 79 21
+DS 1024 984 -1024 984 79 21
+DS -1024 984 -1024 -984 79 21
+$PAD
+Sh "1" R 591 1654 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -571 0
+$EndPAD
+$PAD
+Sh "2" R 591 1654 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 571 0
+$EndPAD
+$EndMODULE  L_4.2X4.2
+$MODULE LED-3MM-FIXED
+Po 0 0 0 15 4EF9035D 00000000 ~~
+Li LED-3MM-FIXED
+Cd LED 3mm - Lead pitch 100mil (2,54mm)
+Kw LED led 3mm 3MM 100mil 2,54mm
+Sc 00000000
+AR /4B6ED75B/4C0DA78D
+Op 0 0 0
+At VIRTUAL
+T0 -300 -2125 320 320 0 70 N V 21 N "D403"
+T1 25 3575 320 320 2700 70 N V 21 N "LED_2mA_1.7V,_red"
+DS 669 669 669 394 80 21
+DS 669 -669 669 -394 80 21
+DA 0 0 669 669 2700 80 21
+$PAD
+Sh "1" C 660 660 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 1 "+3.3V"
+Po -500 0
+$EndPAD
+$PAD
+Sh "2" C 660 660 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000262"
+Po 500 0
+$EndPAD
+$SHAPE3D
+Na "libs/led3_vertical_red.wrl"
+Sc 1.000000 1.000000 1.000000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  LED-3MM-FIXED
+$MODULE USB_MINIB_SMT
+Po 0 0 0 15 4F34EE0A 00000000 ~~
+Li USB_MINIB_SMT
+Sc 00000000
+AR /4B6ED75B/4BF00175
+Op 0 0 0
+T0 -2553 -147 320 320 0 70 N V 21 N "J421"
+T1 0 0 320 320 0 80 N I 21 N "USB_Mini-B_SMT"
+DS -1516 2047 1516 2047 79 21
+DS 1516 2047 1516 -1575 79 21
+DS 1516 -1575 -1516 -1575 79 21
+DS -1516 -1575 -1516 2047 79 21
+$PAD
+Sh "6" R 787 1299 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 1 "GND"
+Po -1752 -1161
+$EndPAD
+$PAD
+Sh "7" R 787 1299 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 1 "GND"
+Po 1752 -1161
+$EndPAD
+$PAD
+Sh "6" R 787 984 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 1 "GND"
+Po -1752 1161
+$EndPAD
+$PAD
+Sh "7" R 787 984 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 1 "GND"
+Po 1752 1161
+$EndPAD
+$PAD
+Sh "" C 354 354 0 0 0
+Dr 354 0 0
+At HOLE N 00E0FFFF
+Ne 0 ""
+Po -866 0
+$EndPAD
+$PAD
+Sh "" C 354 354 0 0 0
+Dr 354 0 0
+At HOLE N 00E0FFFF
+Ne 0 ""
+Po 866 0
+$EndPAD
+$PAD
+Sh "3" R 197 1496 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 3 "N-000315"
+Po 0 -1418
+$EndPAD
+$PAD
+Sh "4" R 197 1496 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 315 -1418
+$EndPAD
+$PAD
+Sh "5" R 197 1496 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 1 "GND"
+Po 630 -1418
+$EndPAD
+$PAD
+Sh "1" R 197 1496 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 4 "N-000328"
+Po -630 -1418
+$EndPAD
+$PAD
+Sh "2" R 197 1496 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 2 "N-000310"
+Po -315 -1418
+$EndPAD
+$EndMODULE  USB_MINIB_SMT
+$MODULE HRS-DM1AA
+Po 0 0 0 15 4F34F118 00000000 ~~
+Li HRS-DM1AA
+Sc 00000000
+AR /4B6ED75B/4BAA6A9C
+Op 0 0 0
+T0 -5000 -6425 320 320 0 70 N V 21 N "J411"
+T1 0 0 320 320 0 70 N V 21 N "Hirose_DM1AA"
+DS 4134 -5984 5512 -5984 120 21
+DS 5512 6024 -5512 6024 120 21
+DS -5512 -5984 -4685 -5984 120 21
+DS -5512 4685 -5512 6024 120 21
+DS 5511 6025 5511 4686 120 21
+DS 5511 -2637 5511 3584 120 21
+DS 5511 -5983 5511 -3779 120 21
+DS 4133 -5511 3779 -5511 120 21
+DS -4686 -5511 -4529 -5511 120 21
+DS -5512 2521 -5512 2796 120 21
+DS -5512 -983 -5512 1773 120 21
+DS -5512 -2637 -5512 -1731 120 21
+DS -5512 -5983 -5512 -3779 120 21
+DS -4686 -5983 -4686 -5511 120 21
+DS 4133 -5511 4133 -5983 120 21
+$PAD
+Sh "" C 512 512 0 0 0
+Dr 512 0 0
+At HOLE N 00E0FFFF
+Ne 0 ""
+Po -4686 -4999
+$EndPAD
+$PAD
+Sh "" C 512 512 0 0 0
+Dr 512 0 0
+At HOLE N 00E0FFFF
+Ne 0 ""
+Po 4133 -4999
+$EndPAD
+$PAD
+Sh "1" R 433 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 10 "SD_DAT3"
+Po 2391 -5865
+$EndPAD
+$PAD
+Sh "2" R 433 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 6 "SD_CMD"
+Po 1407 -5865
+$EndPAD
+$PAD
+Sh "3" R 433 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 2 "GND"
+Po 422 -5865
+$EndPAD
+$PAD
+Sh "4" R 433 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 1 "+3.3V"
+Po -562 -5865
+$EndPAD
+$PAD
+Sh "5" R 433 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 5 "SD_CLK"
+Po -1546 -5865
+$EndPAD
+$PAD
+Sh "6" R 433 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 2 "GND"
+Po -2530 -5865
+$EndPAD
+$PAD
+Sh "7" R 433 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 7 "SD_DAT0"
+Po -3485 -5865
+$EndPAD
+$PAD
+Sh "8" R 433 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 8 "SD_DAT1"
+Po -4155 -5865
+$EndPAD
+$PAD
+Sh "9" R 433 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 9 "SD_DAT2"
+Po 3375 -5865
+$EndPAD
+$PAD
+Sh "GND1" R 787 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 2 "GND"
+Po 5708 -3208
+$EndPAD
+$PAD
+Sh "GND1" R 787 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 2 "GND"
+Po 5708 4135
+$EndPAD
+$PAD
+Sh "GND1" R 787 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 2 "GND"
+Po -5710 -3208
+$EndPAD
+$PAD
+Sh "GND1" R 787 787 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 2 "GND"
+Po -5710 4135
+$EndPAD
+$PAD
+Sh "DT" R 787 394 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 4 "N-000318"
+Po -5552 -1377
+$EndPAD
+$PAD
+Sh "WP" R 787 394 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 3 "N-000295"
+Po -5552 2147
+$EndPAD
+$PAD
+Sh "GND2" R 787 394 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 2 "GND"
+Po -5552 3170
+$EndPAD
+$EndMODULE  HRS-DM1AA
+$MODULE R_PACK_0804_LONGPADS
+Po 0 0 0 15 4F496244 00000000 ~~
+Li R_PACK_0804_LONGPADS
+Sc 00000000
+AR /4B6E16F2/4D96310E
+Op 0 0 0
+T0 325 750 320 320 0 70 N V 21 N "RA105"
+T1 0 0 320 320 0 70 N V 21 N "100"
+DS -551 -472 -551 472 79 21
+DS 551 -472 551 472 79 21
+DS -551 -472 551 -472 79 21
+DS 551 472 -551 472 79 21
+$PAD
+Sh "7" R 118 276 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 5 "N-000012"
+Po -98 -236
+$EndPAD
+$PAD
+Sh "6" R 118 276 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 7 "N-000143"
+Po 98 -236
+$EndPAD
+$PAD
+Sh "2" R 118 276 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 2 "/SNES_Slot/SNES_EXT_/RD"
+Po -98 236
+$EndPAD
+$PAD
+Sh "3" R 118 276 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 3 "/SNES_Slot/SNES_EXT_/ROMSEL"
+Po 98 236
+$EndPAD
+$PAD
+Sh "8" R 197 276 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 8 "N-000147"
+Po -335 -236
+$EndPAD
+$PAD
+Sh "5" R 197 276 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 6 "N-000038"
+Po 335 -236
+$EndPAD
+$PAD
+Sh "4" R 197 276 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 4 "/SNES_Slot/SNES_EXT_A23"
+Po 335 236
+$EndPAD
+$PAD
+Sh "1" R 197 276 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 1 "/SNES_Slot/SNES_EXT_/IRQ"
+Po -335 236
+$EndPAD
+$EndMODULE  R_PACK_0804_LONGPADS
+$MODULE TSSOP48_LONGPADS
+Po 0 0 0 15 4F497040 00000000 ~~
+Li TSSOP48_LONGPADS
+Sc 00000000
+AR 
+Op 0 0 0
+T0 0 -551 320 320 0 70 N V 21 N "Test"
+T1 0 630 320 320 0 70 N V 21 N "VAL**"
+DS -2461 1161 -2461 -1161 79 21
+DS 2461 -1161 2461 1161 79 21
+DC -2205 906 -2087 906 79 21
+DS -2460 -1160 2460 -1160 79 21
+DS -2460 1160 2460 1160 79 21
+$PAD
+Sh "1" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -2263 1614
+$EndPAD
+$PAD
+Sh "2" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -2066 1614
+$EndPAD
+$PAD
+Sh "3" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1870 1614
+$EndPAD
+$PAD
+Sh "4" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1673 1614
+$EndPAD
+$PAD
+Sh "5" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1476 1614
+$EndPAD
+$PAD
+Sh "6" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1279 1614
+$EndPAD
+$PAD
+Sh "7" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1082 1614
+$EndPAD
+$PAD
+Sh "8" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -885 1614
+$EndPAD
+$PAD
+Sh "9" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -688 1614
+$EndPAD
+$PAD
+Sh "10" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -492 1614
+$EndPAD
+$PAD
+Sh "11" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -295 1614
+$EndPAD
+$PAD
+Sh "12" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -98 1614
+$EndPAD
+$PAD
+Sh "13" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 98 1614
+$EndPAD
+$PAD
+Sh "14" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 295 1614
+$EndPAD
+$PAD
+Sh "15" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 492 1614
+$EndPAD
+$PAD
+Sh "16" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 688 1614
+$EndPAD
+$PAD
+Sh "17" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 885 1614
+$EndPAD
+$PAD
+Sh "18" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1082 1614
+$EndPAD
+$PAD
+Sh "19" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1279 1614
+$EndPAD
+$PAD
+Sh "20" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1476 1614
+$EndPAD
+$PAD
+Sh "21" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1673 1614
+$EndPAD
+$PAD
+Sh "22" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1870 1614
+$EndPAD
+$PAD
+Sh "23" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 2066 1614
+$EndPAD
+$PAD
+Sh "24" R 118 630 0 0 1800
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 2263 1614
+$EndPAD
+$PAD
+Sh "25" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 2263 -1614
+$EndPAD
+$PAD
+Sh "26" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 2066 -1614
+$EndPAD
+$PAD
+Sh "27" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1870 -1614
+$EndPAD
+$PAD
+Sh "28" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1673 -1614
+$EndPAD
+$PAD
+Sh "29" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1476 -1614
+$EndPAD
+$PAD
+Sh "30" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1279 -1614
+$EndPAD
+$PAD
+Sh "31" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 1082 -1614
+$EndPAD
+$PAD
+Sh "32" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 885 -1614
+$EndPAD
+$PAD
+Sh "33" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 688 -1614
+$EndPAD
+$PAD
+Sh "34" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 492 -1614
+$EndPAD
+$PAD
+Sh "35" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 295 -1614
+$EndPAD
+$PAD
+Sh "36" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po 98 -1614
+$EndPAD
+$PAD
+Sh "37" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -98 -1614
+$EndPAD
+$PAD
+Sh "38" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -295 -1614
+$EndPAD
+$PAD
+Sh "39" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -492 -1614
+$EndPAD
+$PAD
+Sh "40" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -688 -1614
+$EndPAD
+$PAD
+Sh "41" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -885 -1614
+$EndPAD
+$PAD
+Sh "42" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1082 -1614
+$EndPAD
+$PAD
+Sh "43" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1279 -1614
+$EndPAD
+$PAD
+Sh "44" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1476 -1614
+$EndPAD
+$PAD
+Sh "45" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1673 -1614
+$EndPAD
+$PAD
+Sh "46" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -1870 -1614
+$EndPAD
+$PAD
+Sh "47" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -2066 -1614
+$EndPAD
+$PAD
+Sh "48" R 118 630 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 0 ""
+Po -2263 -1614
+$EndPAD
+$EndMODULE  TSSOP48_LONGPADS
 $EndLIBRARY

pcb/kicad/libs/sdcard.bak

@@ -1,7 +1,8 @@
-PCBNEW-LibModule-V1  Mon 26 Jul 2010 02:13:00 PM CEST
+PCBNEW-LibModule-V1  Tue 27 Dec 2011 12:52:27 PM CET
+# encoding utf-8
 $INDEX
-SD-RSMT-2-MQ-WF
 HRS-DM1AA
+SD-RSMT-2-MQ-WF
 $EndINDEX
 $MODULE SD-RSMT-2-MQ-WF
 Po 0 0 0 15 4C4D74E3 00000000 ~~
@@ -124,40 +125,39 @@ Po 3740 709
 $EndPAD
 $EndMODULE  SD-RSMT-2-MQ-WF
 $MODULE HRS-DM1AA
-Po 0 0 0 15 4C4D706D 00000000 ~~
+Po 0 0 0 15 4EF9108C 00000000 ~~
 Li HRS-DM1AA
 Sc 00000000
-AR 
+AR HRS-DM1AA
 Op 0 0 0
-T0 0 0 300 300 0 60 N V 21 N"HRS-DM1AA"
-T1 0 0 300 300 0 60 N V 21 N"VAL**"
-DS -5906 4725 -5906 4686 120 21
-DS 5905 6025 5905 4686 120 21
-DS 5905 -2637 5905 3584 120 21
-DS 5905 -5983 5905 -3779 120 21
+T0 0 0 300 300 0 60 N V 21 N "HRS-DM1AA"
+T1 0 0 300 300 0 60 N V 21 N "VAL**"
+DS 4134 -5984 5512 -5984 120 21
+DS 5512 6024 -5512 6024 120 21
+DS -5512 -5984 -4685 -5984 120 21
+DS -5512 4685 -5512 6024 120 21
+DS 5511 6025 5511 4686 120 21
+DS 5511 -2637 5511 3584 120 21
+DS 5511 -5983 5511 -3779 120 21
 DS 4133 -5511 3779 -5511 120 21
 DS -4686 -5511 -4529 -5511 120 21
-DS -5906 6025 -5906 4725 120 21
-DS -5906 2521 -5906 2796 120 21
-DS -5906 -983 -5906 1773 120 21
-DS -5906 -2637 -5906 -1731 120 21
-DS -5906 -5983 -5906 -3779 120 21
-DS -5906 -5983 -4686 -5983 120 21
+DS -5512 2521 -5512 2796 120 21
+DS -5512 -983 -5512 1773 120 21
+DS -5512 -2637 -5512 -1731 120 21
+DS -5512 -5983 -5512 -3779 120 21
 DS -4686 -5983 -4686 -5511 120 21
 DS 4133 -5511 4133 -5983 120 21
-DS 4133 -5983 5905 -5983 120 21
-DS 5905 6025 -5906 6025 120 21
 $PAD
 Sh "~" C 512 512 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At STD N 0000FFFF
 Ne 0 ""
 Po -4686 -4999
 $EndPAD
 $PAD
 Sh "~" C 512 512 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At STD N 0000FFFF
 Ne 0 ""
 Po 4133 -4999
 $EndPAD

pcb/kicad/libs/sdcard.mod

@@ -1,7 +1,8 @@
-PCBNEW-LibModule-V1  Mon 26 Jul 2010 09:33:33 PM CEST
+PCBNEW-LibModule-V1  Sun 26 Feb 2012 12:17:38 AM CET
+# encoding utf-8
 $INDEX
-SD-RSMT-2-MQ-WF
 HRS-DM1AA
+SD-RSMT-2-MQ-WF
 $EndINDEX
 $MODULE SD-RSMT-2-MQ-WF
 Po 0 0 0 15 4C4D74E3 00000000 ~~
@@ -124,13 +125,13 @@ Po 3740 709
 $EndPAD
 $EndMODULE  SD-RSMT-2-MQ-WF
 $MODULE HRS-DM1AA
-Po 0 0 0 15 4C4DE307 00000000 ~~
+Po 0 0 0 15 4F496C0E 00000000 ~~
 Li HRS-DM1AA
 Sc 00000000
-AR 
+AR HRS-DM1AA
 Op 0 0 0
-T0 0 0 300 300 0 60 N V 21 N"HRS-DM1AA"
-T1 0 0 300 300 0 60 N V 21 N"VAL**"
+T0 0 0 300 300 0 60 N V 21 N "HRS-DM1AA"
+T1 0 0 300 300 0 60 N V 21 N "VAL**"
 DS 4134 -5984 5512 -5984 120 21
 DS 5512 6024 -5512 6024 120 21
 DS -5512 -5984 -4685 -5984 120 21
@@ -147,16 +148,16 @@ DS -5512 -5983 -5512 -3779 120 21
 DS -4686 -5983 -4686 -5511 120 21
 DS 4133 -5511 4133 -5983 120 21
 $PAD
-Sh "~" C 512 512 0 0 0
+Sh "" C 512 512 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At HOLE N 00E0FFFF
 Ne 0 ""
 Po -4686 -4999
 $EndPAD
 $PAD
-Sh "~" C 512 512 0 0 0
+Sh "" C 512 512 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At HOLE N 00E0FFFF
 Ne 0 ""
 Po 4133 -4999
 $EndPAD

pcb/kicad/libs/snescart.bak

@@ -1,4 +1,4 @@
-PCBNEW-LibModule-V1  Mon 04 Jul 2011 12:35:33 AM CEST
+PCBNEW-LibModule-V1  Thu 09 Feb 2012 09:51:59 PM CET
 # encoding utf-8
 $INDEX
 SNESCART_EXT
@@ -537,7 +537,7 @@ Po 14331 -3780
 $EndPAD
 $EndMODULE  SNESCART_EXT
 $MODULE SNESCART_EXT2
-Po 0 0 0 15 4E0F6C87 00000000 ~~
+Po 0 0 0 15 4F3431E9 00000000 ~~
 Li SNESCART_EXT2
 Sc 00000000
 AR /4B6E16F2/4B6E1766
@@ -546,6 +546,18 @@ Op 0 0 0
 .SolderPaste -4
 T0 -4134 2953 600 600 0 120 N V 21 N "J101"
 T1 0 2953 600 600 0 120 N V 21 N "SNESCART_EXT"
+DS -20039 -5000 -20039 -8898 39 28
+DS -18465 -4016 -18465 -5000 39 28
+DS -19449 -2402 -19449 -4016 39 28
+DS -17717 -2402 -17717 1693 39 28
+DS 17717 -2402 17717 1693 39 28
+DS 19921 -4094 19921 -2402 39 28
+DS 19291 -29252 19291 -27756 39 28
+DS -19488 -29252 -19488 -27756 39 28
+DS -8524 -30709 -8524 -29252 39 28
+DS 8622 -29252 8622 -30709 39 28
+DS -20039 -24409 -20039 -12244 39 28
+DS -19488 -27087 -19488 -24409 39 28
 DC 1142 -11378 1929 -11378 79 20
 DC 1142 -11378 1929 -11339 79 21
 DS 19921 -24409 19921 -8976 39 28
@@ -556,46 +568,33 @@ DS 19291 -8189 19291 -6890 39 28
 DS 18307 -8189 19291 -8189 39 28
 DS 18307 -8976 18307 -8189 39 28
 DS 19921 -8976 18307 -8976 39 28
-DS -20039 -4803 -20039 -8898 39 28
-DS -20039 -24528 -20039 -12244 39 28
 DS -18465 -12244 -20039 -12244 39 28
 DS -18465 -11457 -18465 -12244 39 28
 DS -19449 -11457 -18465 -11457 39 28
 DS -19449 -8898 -19449 -11457 39 28
 DS -20039 -8898 -19449 -8898 39 28
-DS -19488 -27087 -19488 -24528 39 28
 DA -17441 1693 -17441 1969 900 39 28
 DA -13071 1693 -12795 1693 900 39 28
 DA -11535 1693 -11535 1969 900 39 28
 DA 11535 1693 11811 1693 900 39 28
 DA 13071 1693 13071 1969 900 39 28
 DA 17441 1693 17717 1693 900 39 28
-DS 8622 -29331 19291 -29331 40 28
+DS 8622 -29252 19291 -29252 40 28
 DS -8524 -30709 8622 -30709 40 28
-DS -19488 -29331 -8524 -29331 40 28
+DS -19488 -29252 -8524 -29252 40 28
 DC 2796 -17047 3583 -17047 75 20
 DC 2795 -17047 3582 -17047 75 21
-DS 8622 -29331 8622 -30709 40 28
-DS -8524 -30709 -8524 -29331 40 28
-DS -19488 -29331 -19488 -27756 40 28
 DS -19488 -27756 -18504 -27756 40 28
 DS -18504 -27756 -18504 -27087 40 28
 DS -18504 -27087 -19488 -27087 40 28
-DS -19488 -24528 -20039 -24528 40 28
-DS -20039 -4803 -18465 -4803 40 28
-DS -18465 -4803 -18465 -4016 40 28
+DS -19488 -24409 -20039 -24409 40 28
+DS -20039 -5000 -18465 -5000 40 28
 DS -18465 -4016 -19449 -4016 40 28
-DS -19449 -4016 -19449 -2205 40 28
-DS -19449 -2205 -17717 -2205 40 28
-DS -17717 -2205 -17717 -2165 40 28
+DS -19449 -2402 -17717 -2402 40 28
 DS 19291 -27087 18307 -27087 40 28
 DS 18307 -27087 18307 -27756 40 28
 DS 18307 -27756 19291 -27756 40 28
-DS 19291 -27756 19291 -29331 40 28
-DS 17717 1693 17717 -2165 40 28
-DS 17717 -2165 17717 -2205 40 28
-DS 17717 -2205 19921 -2205 40 28
-DS 19921 -2205 19921 -4094 40 28
+DS 17717 -2402 19921 -2402 40 28
 DS 19921 -4094 19291 -4094 40 28
 DS 19291 -4094 19291 -6102 40 28
 DS 19291 -6102 18307 -6102 40 28
@@ -604,7 +603,6 @@ DS 13071 1969 17441 1969 40 28
 DS 11811 1693 11811 -2480 40 28
 DS 11811 -2480 12795 -2480 40 28
 DS 12795 -2480 12795 1693 40 28
-DS -17717 1693 -17717 -2165 40 28
 DS -13071 1969 -17441 1969 40 28
 DS -11811 1693 -11811 -2480 40 28
 DS -11811 -2480 -12795 -2480 40 28
@@ -864,6 +862,7 @@ Dr 0 0 0
 At CONN N 00000001
 Ne 0 ""
 Po -16732 197
+Le -65794
 $EndPAD
 $PAD
 Sh "33" R 591 2756 0 0 0
@@ -871,6 +870,7 @@ Dr 0 0 0
 At CONN N 00000001
 Ne 49 "/SNES_Slot/SNES_EXT_REFRESH"
 Po -15748 197
+Le -197380
 $EndPAD
 $PAD
 Sh "34" R 591 2756 0 0 0

pcb/kicad/libs/snescart.mod

@@ -1,8 +1,9 @@
-PCBNEW-LibModule-V1  Mon 04 Jul 2011 12:37:18 AM CEST
+PCBNEW-LibModule-V1  Fri 10 Feb 2012 10:51:00 AM CET
 # encoding utf-8
 $INDEX
 SNESCART_EXT
 SNESCART_EXT2
+SNESCART_EXT2_SMTUSB
 $EndINDEX
 $MODULE SNESCART_EXT
 Po 0 0 0 15 4D200467 00000000 ~~
@@ -537,7 +538,7 @@ Po 14331 -3780
 $EndPAD
 $EndMODULE  SNESCART_EXT
 $MODULE SNESCART_EXT2
-Po 0 0 0 15 4E10EF0E 00000000 ~~
+Po 0 0 0 15 4F3431E9 00000000 ~~
 Li SNESCART_EXT2
 Sc 00000000
 AR /4B6E16F2/4B6E1766
@@ -546,6 +547,16 @@ Op 0 0 0
 .SolderPaste -4
 T0 -4134 2953 600 600 0 120 N V 21 N "J101"
 T1 0 2953 600 600 0 120 N V 21 N "SNESCART_EXT"
+DS -20039 -5000 -20039 -8898 39 28
+DS -18465 -4016 -18465 -5000 39 28
+DS -19449 -2402 -19449 -4016 39 28
+DS -17717 -2402 -17717 1693 39 28
+DS 17717 -2402 17717 1693 39 28
+DS 19921 -4094 19921 -2402 39 28
+DS 19291 -29252 19291 -27756 39 28
+DS -19488 -29252 -19488 -27756 39 28
+DS -8524 -30709 -8524 -29252 39 28
+DS 8622 -29252 8622 -30709 39 28
 DS -20039 -24409 -20039 -12244 39 28
 DS -19488 -27087 -19488 -24409 39 28
 DC 1142 -11378 1929 -11378 79 20
@@ -558,7 +569,6 @@ DS 19291 -8189 19291 -6890 39 28
 DS 18307 -8189 19291 -8189 39 28
 DS 18307 -8976 18307 -8189 39 28
 DS 19921 -8976 18307 -8976 39 28
-DS -20039 -4803 -20039 -8898 39 28
 DS -18465 -12244 -20039 -12244 39 28
 DS -18465 -11457 -18465 -12244 39 28
 DS -19449 -11457 -18465 -11457 39 28
@@ -570,32 +580,22 @@ DA -11535 1693 -11535 1969 900 39 28
 DA 11535 1693 11811 1693 900 39 28
 DA 13071 1693 13071 1969 900 39 28
 DA 17441 1693 17717 1693 900 39 28
-DS 8622 -29331 19291 -29331 40 28
+DS 8622 -29252 19291 -29252 40 28
 DS -8524 -30709 8622 -30709 40 28
-DS -19488 -29331 -8524 -29331 40 28
+DS -19488 -29252 -8524 -29252 40 28
 DC 2796 -17047 3583 -17047 75 20
 DC 2795 -17047 3582 -17047 75 21
-DS 8622 -29331 8622 -30709 40 28
-DS -8524 -30709 -8524 -29331 40 28
-DS -19488 -29331 -19488 -27756 40 28
 DS -19488 -27756 -18504 -27756 40 28
 DS -18504 -27756 -18504 -27087 40 28
 DS -18504 -27087 -19488 -27087 40 28
 DS -19488 -24409 -20039 -24409 40 28
-DS -20039 -4803 -18465 -4803 40 28
-DS -18465 -4803 -18465 -4016 40 28
+DS -20039 -5000 -18465 -5000 40 28
 DS -18465 -4016 -19449 -4016 40 28
-DS -19449 -4016 -19449 -2205 40 28
-DS -19449 -2205 -17717 -2205 40 28
-DS -17717 -2205 -17717 -2165 40 28
+DS -19449 -2402 -17717 -2402 40 28
 DS 19291 -27087 18307 -27087 40 28
 DS 18307 -27087 18307 -27756 40 28
 DS 18307 -27756 19291 -27756 40 28
-DS 19291 -27756 19291 -29331 40 28
-DS 17717 1693 17717 -2165 40 28
-DS 17717 -2165 17717 -2205 40 28
-DS 17717 -2205 19921 -2205 40 28
-DS 19921 -2205 19921 -4094 40 28
+DS 17717 -2402 19921 -2402 40 28
 DS 19921 -4094 19291 -4094 40 28
 DS 19291 -4094 19291 -6102 40 28
 DS 19291 -6102 18307 -6102 40 28
@@ -604,7 +604,6 @@ DS 13071 1969 17441 1969 40 28
 DS 11811 1693 11811 -2480 40 28
 DS 11811 -2480 12795 -2480 40 28
 DS 12795 -2480 12795 1693 40 28
-DS -17717 1693 -17717 -2165 40 28
 DS -13071 1969 -17441 1969 40 28
 DS -11811 1693 -11811 -2480 40 28
 DS -11811 -2480 -12795 -2480 40 28
@@ -1147,4 +1146,614 @@ Po 14331 -3780
 Le 23484672
 $EndPAD
 $EndMODULE  SNESCART_EXT2
+$MODULE SNESCART_EXT2_SMTUSB
+Po 0 0 0 15 4F34E870 00000000 ~~
+Li SNESCART_EXT2_SMTUSB
+Sc 00000000
+AR /4B6E16F2/4B6E1766
+Op 0 0 0
+.SolderMask 4
+.SolderPaste -4
+T0 -4134 2953 600 600 0 120 N V 21 N "J101"
+T1 0 2953 600 600 0 120 N V 21 N "SNESCART_EXT"
+DS 8858 -29252 19291 -29252 39 28
+DS 8622 -30709 8858 -30709 39 28
+DS -20039 -5000 -20039 -8898 39 28
+DS -18465 -4016 -18465 -5000 39 28
+DS -19449 -2402 -19449 -4016 39 28
+DS -17717 -2402 -17717 1693 39 28
+DS 17717 -2402 17717 1693 39 28
+DS 19921 -4094 19921 -2402 39 28
+DS 19291 -29252 19291 -27756 39 28
+DS -19488 -29252 -19488 -27756 39 28
+DS -8524 -30709 -8524 -29252 39 28
+DS 8858 -29252 8858 -30709 39 28
+DS -20039 -24409 -20039 -12244 39 28
+DS -19488 -27087 -19488 -24409 39 28
+DC 1142 -11378 1929 -11378 79 20
+DC 1142 -11378 1929 -11339 79 21
+DS 19921 -24409 19921 -8976 39 28
+DS 19291 -27087 19291 -24409 39 28
+DS 19291 -24409 19921 -24409 39 28
+DS 18307 -6890 19291 -6890 39 28
+DS 19291 -8189 19291 -6890 39 28
+DS 18307 -8189 19291 -8189 39 28
+DS 18307 -8976 18307 -8189 39 28
+DS 19921 -8976 18307 -8976 39 28
+DS -18465 -12244 -20039 -12244 39 28
+DS -18465 -11457 -18465 -12244 39 28
+DS -19449 -11457 -18465 -11457 39 28
+DS -19449 -8898 -19449 -11457 39 28
+DS -20039 -8898 -19449 -8898 39 28
+DA -17441 1693 -17441 1969 900 39 28
+DA -13071 1693 -12795 1693 900 39 28
+DA -11535 1693 -11535 1969 900 39 28
+DA 11535 1693 11811 1693 900 39 28
+DA 13071 1693 13071 1969 900 39 28
+DA 17441 1693 17717 1693 900 39 28
+DS -8524 -30709 8622 -30709 40 28
+DS -19488 -29252 -8524 -29252 40 28
+DC 2796 -17047 3583 -17047 75 20
+DC 2795 -17047 3582 -17047 75 21
+DS -19488 -27756 -18504 -27756 40 28
+DS -18504 -27756 -18504 -27087 40 28
+DS -18504 -27087 -19488 -27087 40 28
+DS -19488 -24409 -20039 -24409 40 28
+DS -20039 -5000 -18465 -5000 40 28
+DS -18465 -4016 -19449 -4016 40 28
+DS -19449 -2402 -17717 -2402 40 28
+DS 19291 -27087 18307 -27087 40 28
+DS 18307 -27087 18307 -27756 40 28
+DS 18307 -27756 19291 -27756 40 28
+DS 17717 -2402 19921 -2402 40 28
+DS 19921 -4094 19291 -4094 40 28
+DS 19291 -4094 19291 -6102 40 28
+DS 19291 -6102 18307 -6102 40 28
+DS 18307 -6102 18307 -6890 40 28
+DS 13071 1969 17441 1969 40 28
+DS 11811 1693 11811 -2480 40 28
+DS 11811 -2480 12795 -2480 40 28
+DS 12795 -2480 12795 1693 40 28
+DS -13071 1969 -17441 1969 40 28
+DS -11811 1693 -11811 -2480 40 28
+DS -11811 -2480 -12795 -2480 40 28
+DS -12795 -2480 -12795 1693 40 28
+DS -11535 1969 11535 1969 40 28
+$PAD
+Sh "1" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 50 "/SNES_Slot/SNES_EXT_SYS_CLK"
+Po -16732 197
+Le 19
+$EndPAD
+$PAD
+Sh "2" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 0 ""
+Po -15748 197
+Le 86
+$EndPAD
+$PAD
+Sh "3" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 47 "/SNES_Slot/SNES_EXT_PA6"
+Po -14764 197
+Le 98
+$EndPAD
+$PAD
+Sh "4" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 3 "/SNES_Slot/SNES_EXT_/PARD"
+Po -13780 197
+Le 353
+$EndPAD
+$PAD
+Sh "5" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 57 "GND"
+Po -10925 197
+Le 46326
+$EndPAD
+$PAD
+Sh "6" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 11 "/SNES_Slot/SNES_EXT_A11"
+Po -9843 197
+Le 41840
+$EndPAD
+$PAD
+Sh "7" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 10 "/SNES_Slot/SNES_EXT_A10"
+Po -8858 197
+Le 33
+$EndPAD
+$PAD
+Sh "8" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 31 "/SNES_Slot/SNES_EXT_A9"
+Po -7874 197
+Le 10
+$EndPAD
+$PAD
+Sh "9" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 30 "/SNES_Slot/SNES_EXT_A8"
+Po -6890 197
+Le 40686
+$EndPAD
+$PAD
+Sh "10" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 29 "/SNES_Slot/SNES_EXT_A7"
+Po -5906 197
+Le 32
+$EndPAD
+$PAD
+Sh "11" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 28 "/SNES_Slot/SNES_EXT_A6"
+Po -4921 197
+Le 26720752
+$EndPAD
+$PAD
+Sh "12" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 27 "/SNES_Slot/SNES_EXT_A5"
+Po -3937 197
+Le 44474
+$EndPAD
+$PAD
+Sh "13" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 26 "/SNES_Slot/SNES_EXT_A4"
+Po -2953 197
+Le 41300
+$EndPAD
+$PAD
+Sh "14" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 25 "/SNES_Slot/SNES_EXT_A3"
+Po -1969 197
+Le 26690192
+$EndPAD
+$PAD
+Sh "15" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 20 "/SNES_Slot/SNES_EXT_A2"
+Po -984 197
+Le 778140282
+$EndPAD
+$PAD
+Sh "16" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 9 "/SNES_Slot/SNES_EXT_A1"
+Po 0 197
+Le 45976
+$EndPAD
+$PAD
+Sh "17" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 8 "/SNES_Slot/SNES_EXT_A0"
+Po 984 197
+Le 26692384
+$EndPAD
+$PAD
+Sh "18" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 2 "/SNES_Slot/SNES_EXT_/IRQ"
+Po 1969 197
+Le 33
+$EndPAD
+$PAD
+Sh "19" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 33 "/SNES_Slot/SNES_EXT_D0"
+Po 2953 197
+Le 101
+$EndPAD
+$PAD
+Sh "20" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 34 "/SNES_Slot/SNES_EXT_D1"
+Po 3937 197
+Le 72
+$EndPAD
+$PAD
+Sh "21" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 35 "/SNES_Slot/SNES_EXT_D2"
+Po 4921 197
+Le 1362898584
+$EndPAD
+$PAD
+Sh "22" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 36 "/SNES_Slot/SNES_EXT_D3"
+Po 5906 197
+Le 193
+$EndPAD
+$PAD
+Sh "23" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 5 "/SNES_Slot/SNES_EXT_/RD"
+Po 6890 197
+Le 1
+$EndPAD
+$PAD
+Sh "24" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 56 "EXT_CIC_DATA1"
+Po 7874 197
+Le -268371600
+$EndPAD
+$PAD
+Sh "25" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 54 "CIC_RESET"
+Po 8858 197
+Le 44216
+$EndPAD
+$PAD
+Sh "26" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 58 "SNES_/RESET"
+Po 9843 197
+Le 26710224
+$EndPAD
+$PAD
+Sh "27" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 1 "+5VL"
+Po 10925 197
+Le -268358496
+$EndPAD
+$PAD
+Sh "28" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 41 "/SNES_Slot/SNES_EXT_PA0"
+Po 13780 197
+Le 40657
+$EndPAD
+$PAD
+Sh "29" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 43 "/SNES_Slot/SNES_EXT_PA2"
+Po 14764 197
+Le 42
+$EndPAD
+$PAD
+Sh "30" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 45 "/SNES_Slot/SNES_EXT_PA4"
+Po 15748 197
+Le 27776368
+$EndPAD
+$PAD
+Sh "31" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 51 "AUDIO_L"
+Po 16732 197
+Le 1376453976
+$EndPAD
+$PAD
+Sh "32" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 0 ""
+Po -16732 197
+Le -65794
+$EndPAD
+$PAD
+Sh "33" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 49 "/SNES_Slot/SNES_EXT_REFRESH"
+Po -15748 197
+Le -197380
+$EndPAD
+$PAD
+Sh "34" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 48 "/SNES_Slot/SNES_EXT_PA7"
+Po -14764 197
+Le 26706208
+$EndPAD
+$PAD
+Sh "35" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 4 "/SNES_Slot/SNES_EXT_/PAWR"
+Po -13780 197
+Le 48
+$EndPAD
+$PAD
+Sh "36" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 57 "GND"
+Po -10925 197
+Le 26698352
+$EndPAD
+$PAD
+Sh "37" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 12 "/SNES_Slot/SNES_EXT_A12"
+Po -9843 197
+Le 26703872
+$EndPAD
+$PAD
+Sh "38" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 13 "/SNES_Slot/SNES_EXT_A13"
+Po -8858 197
+Le 2513
+$EndPAD
+$PAD
+Sh "39" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 14 "/SNES_Slot/SNES_EXT_A14"
+Po -7874 197
+Le 48
+$EndPAD
+$PAD
+Sh "40" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 15 "/SNES_Slot/SNES_EXT_A15"
+Po -6890 197
+Le 14164224
+$EndPAD
+$PAD
+Sh "41" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 16 "/SNES_Slot/SNES_EXT_A16"
+Po -5906 197
+Le 14319616
+$EndPAD
+$PAD
+Sh "42" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 17 "/SNES_Slot/SNES_EXT_A17"
+Po -4921 197
+Le 14154752
+$EndPAD
+$PAD
+Sh "43" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 18 "/SNES_Slot/SNES_EXT_A18"
+Po -3937 197
+Le 192512
+$EndPAD
+$PAD
+Sh "44" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 19 "/SNES_Slot/SNES_EXT_A19"
+Po -2953 197
+Le 39524
+$EndPAD
+$PAD
+Sh "45" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 21 "/SNES_Slot/SNES_EXT_A20"
+Po -1969 197
+Le 1077956333
+$EndPAD
+$PAD
+Sh "46" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 22 "/SNES_Slot/SNES_EXT_A21"
+Po -984 197
+Le 39959
+$EndPAD
+$PAD
+Sh "47" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 23 "/SNES_Slot/SNES_EXT_A22"
+Po 0 197
+Le 1077938791
+$EndPAD
+$PAD
+Sh "48" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 24 "/SNES_Slot/SNES_EXT_A23"
+Po 984 197
+Le 40274
+$EndPAD
+$PAD
+Sh "49" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 6 "/SNES_Slot/SNES_EXT_/ROMSEL"
+Po 1969 197
+Le 40357
+$EndPAD
+$PAD
+Sh "50" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 37 "/SNES_Slot/SNES_EXT_D4"
+Po 2953 197
+Le 40449
+$EndPAD
+$PAD
+Sh "51" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 38 "/SNES_Slot/SNES_EXT_D5"
+Po 3937 197
+Le 1077956333
+$EndPAD
+$PAD
+Sh "52" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 39 "/SNES_Slot/SNES_EXT_D6"
+Po 4921 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "53" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 40 "/SNES_Slot/SNES_EXT_D7"
+Po 5906 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "54" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 7 "/SNES_Slot/SNES_EXT_/WR"
+Po 6890 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "55" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 55 "EXT_CIC_DATA0"
+Po 7874 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "56" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 53 "CIC_CLK"
+Po 8858 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "57" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 32 "/SNES_Slot/SNES_EXT_CPU_CLK"
+Po 9843 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "58" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 1 "+5VL"
+Po 10925 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "59" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 42 "/SNES_Slot/SNES_EXT_PA1"
+Po 13780 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "60" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 44 "/SNES_Slot/SNES_EXT_PA3"
+Po 14764 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "61" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 46 "/SNES_Slot/SNES_EXT_PA5"
+Po 15748 197
+Le 1077941145
+$EndPAD
+$PAD
+Sh "62" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 52 "AUDIO_R"
+Po 16732 197
+Le 23484672
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po -15256 394
+Le 23484672
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 15256 394
+Le 23484672
+$EndPAD
+$PAD
+Sh "" R 23622 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 0 394
+Le 23484672
+$EndPAD
+$PAD
+Sh "" R 2362 1969 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po -10945 -3819
+Le 23484672
+$EndPAD
+$PAD
+Sh "" R 2283 2362 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po 14331 -3780
+Le 23484672
+$EndPAD
+$EndMODULE  SNESCART_EXT2_SMTUSB
 $EndLIBRARY

snes/Makefile

@@ -1,19 +1,23 @@
-OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 # gfx.o65 # vars.o65
+OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 spc700.o65 spcplay.o65 # gfx.o65 # vars.o65
 
-all: menu.bin
+all: clean menu.bin map
 
 smc: menu.bin
 	cat menu.bin sd2snes.rom > menu.smc
+
+map: menu.bin
+	utils/mkmap.sh $(OBJS)
+
 menu.bin: $(OBJS)
-	sneslink -fsmc -o $@ $^
+	sneslink -fsmc -o $@ $^ 2>&1 | tee link.log
 
 # Generic rule to create .o65 out from .a65
 %.o65: %.a65
-	snescom -J -Wall -o $@ $<
+	snescom -J -Wall -o $@ $< 2>&1 | tee $@.log
 
 # Generic rule to create .ips out from .a65
 %.ips: %.a65
-	snescom -I -J -Wall -o $@ $<
+	snescom -I -J -Wall -o $@ $< 2>&1 | tee $@.log
 
 clean:
 	rm -f *.ips *.o65 *~ menu.bin

snes/const.a65

@@ -3,7 +3,7 @@ zero		.word	0
 bg2tile		.byt $20
 hdma_pal_src	.byt 44
 		.byt $60, $2d
-		.byt 14
+		.byt 10
 		.byt $00, $00
 		.byt 2
 		.byt $60, $2d
@@ -29,7 +29,7 @@ hdma_pal_src	.byt 44
 		.byt $20, $25
 		.byt 11
 		.byt $40, $29
-		.byt 31
+		.byt 29
 		.byt $60, $2d
 		.byt 2
 		.byt $20, $04
@@ -69,11 +69,11 @@ hdma_cg_addr_src
 		.byt $00, $00, $00, $00, $00, $00, $00, $00
 		.byt $00, $00, $00, $00, $00, $00, $00, $00
 		.byt $00
-hdma_mode_src	.byt 64, $03, $01, $05, $00
-hdma_scroll_src	.byt 64
-		.byt $00, $00, $ff, $0f
+hdma_mode_src	.byt 56, $03, $01, $05, $00
+hdma_scroll_src	.byt 56
+		.byt $00, $00, $ff, $03
 		.byt $01
-		.byt $fc, $00, $05, $00
+		.byt $fc, $00, $1f, $03
 		.byt $00
 ; colors:
 ; upper border: + #547fff -> 10,15,31
@@ -93,30 +93,31 @@ hdma_math_src	.byt 1 ; these are filled in...
 		.byt $00, $e0
 		.byt 0
 
-oam_data_l	.byt 75, 56, 31, $0e
-		.byt 83, 56, 1, $0e
-		.byt 91, 56, 2, $0e
-		.byt 99, 56, 3, $0e
-		.byt 107, 56, 4, $0e
-		.byt 115, 56, 5, $0e
-		.byt 123, 56, 6, $0e
-		.byt 131, 56, 7, $0e
-		.byt 75, 64, 8, $0e
-		.byt 83, 64, 9, $0e
-		.byt 91, 64, 10, $0e
-		.byt 99, 64, 11, $0e
-		.byt 107, 64, 12, $0e
-		.byt 115, 64, 13, $0e
-		.byt 123, 64, 14, $0e
-		.byt 131, 64, 15, $0e
-		.byt 75, 72, 16, $0e
-		.byt 83, 72, 17, $0e
-		.byt 91, 72, 18, $0e
-		.byt 99, 72, 19, $0e
-		.byt 75, 80, 24, $0e
-		.byt 83, 80, 25, $0e
-		.byt 91, 80, 26, $0e
-oam_data_h	.byt 0, 0, 0, 0, 0, 0, 0, 0
+oam_data_l	.byt 88, 56, 0, $08
+		.byt 96, 56, 1, $08
+		.byt 104, 56, 2, $08
+		.byt 112, 56, 3, $08
+		.byt 120, 56, 4, $08
+		.byt 128, 56, 5, $08
+		.byt 136, 56, 6, $08
+		.byt 88, 64, 7, $08
+		.byt 96, 64, 8, $08
+		.byt 104, 64, 9, $08
+		.byt 112, 64, 10, $08
+		.byt 88, 72, 14, $08
+		.byt 96, 72, 15, $08
+		.byt 157, 56, 21, $0a
+		.byt 171, 56, 22, $0c
+		.byt 179, 56, 23, $0c
+		.byt 171, 64, 24, $0c
+		.byt 171, 72, 26, $0c
+		.byt 171, 80, 28, $0c
+		.byt 171, 88, 30, $0c
+		.byt 171, 96, 32, $0c
+		.byt 193, 56, 34, $0e
+		.byt 193, 64, 35, $0e
+		.byt 193, 72, 36, $0e
+oam_data_h	.byt 0, 0, 0, 0, 0, 0, 0, 0, 0
 
 space64	.byt $20, $20, $20, $20, $20, $20, $20, $20
 	.byt $20, $20, $20, $20, $20, $20, $20, $20
@@ -136,8 +137,10 @@ window_nh	.byt 24
 window_sh	.byt 25
 window_wv	.byt 26
 window_ev	.byt 27
-text_clkset	.byt 28,"Please set the clock.", 29,0
-text_buttonB	.byt "Dpad: sel/chg, B: OK", 0
+window_tl	.byt 28
+window_tr	.byt 29
+text_clkset	.byt "Please set the clock.", 0
+text_buttonB	.byt "Dpad: sel/chg, A: OK", 0
 time_win_x	.byt 18
 time_win_y	.byt 15
 time_win_w	.byt 27
@@ -146,7 +149,15 @@ main_win_x	.byt 18
 main_win_y	.byt 11
 main_win_w	.byt 27
 main_win_h	.byt 13
-text_mainmenu	.byt 28,"Main Menu", 29, 0
+text_mainmenu	.byt "Main Menu", 0
+sysinfo_win_x	.byt 10
+sysinfo_win_y	.byt 9
+sysinfo_win_w	.byt 43
+sysinfo_win_h	.byt 17
+last_win_x	.byt 2
+last_win_y	.byt 12
+last_win_w	.byt 60
+last_win_h	.byt 5
 
 text_mm_file		.byt "File Browser", 0
 text_mm_last		.byt "Run last game", 0
@@ -154,5 +165,27 @@ text_mm_time		.byt "Set Clock", 0
 text_mm_scic		.byt "Enable SuperCIC", 0
 text_mm_vmode_menu	.byt "Menu video mode", 0
 text_mm_vmode_game	.byt "Game video mode", 0
+text_mm_sysinfo		.byt "System Information", 0
+text_statusbar_keys	.byt "A:Select B:Back X:Menu", 0
+text_last		.byt "Run previous ROM: Press Start again to confirm", 0
+text_system		.byt "CPU Rev.: x  PPU1 Rev.: y  PPU2 Rev.: z",0
 
-text_statusbar_keys	.byt "B:Select A:Back X:Menu", 0
+
+text_spcplay		.byt "SPC Music Player", 0
+spcplay_win_x		.byt 15
+spcplay_win_y		.byt 15
+spcplay_win_w		.byt 33
+spcplay_win_h		.byt 5
+
+text_spcload		.byt "Loading SPC data to SPC700...", 0
+text_spcstarta		.byt "**** Now playing SPC tune ****", 0
+text_spcstartb		.byt "Name:  ",0
+text_spcstartc		.byt "Song:  ",0
+text_spcstartd		.byt "Artist:",0
+
+spcstart_win_x		.byt 10
+spcstart_win_y		.byt 13
+spcstart_win_w		.byt 44
+spcstart_win_h		.byt 9
+
+text_spcid		.byt "SNES-SPC700"

snes/data.a65

@@ -1,19 +1,22 @@
+*=$7E0000
 .data
 ;don't anger the stack!
 dirptr_addr	.word	0
-dirptr_bank	.byt	0
+dirptr_bank	.word	0
 dirstart_addr	.word	0
-dirstart_bank	.byt	0
-dirend_addr	.word 	0
-dirend_bank	.byt	0
+dirstart_bank	.word	0
+dirend_addr	.word	0
+dirend_bank	.word	0
 dirend_idx	.word	0
 dirptr_idx	.word	0
-dirent_addr	.word 0
-dirent_bank	.byt 0
+dirent_addr	.word	0
+dirent_bank	.word	0
 dirent_type	.byt 0
 dirend_onscreen	.byt 0
 dirlog_idx	.byt 0,0,0 ; long ptr
-
+direntry_fits_idx
+		.byt 0,0
+longptr		.byt 0,0,0 ; general purpose long ptr
 ;----------parameters for text output----------
 print_x	.byt 0		;x coordinate
 	.byt 0
@@ -23,9 +26,10 @@ print_src	.word 0	;source data address
 print_bank	.byt 0	;source data bank
 print_pal	.word 0	;palette number for text output
 print_temp	.word 0 ;work variable
-print_count	.byt 0	;how many characters may be printed?
-print_count_tmp .byt 0	;work variable
-print_done	.word 0  ;how many characters were printed?
+print_ptr	.byt 0,0,0 ;read pointer
+print_count	.word 0	;how many characters may be printed?
+print_done	.word 0 ;how many characters were printed?
+print_over	.byt 0  ;was the string printed incompletely?
 ;----------parameters for dma----------
 dma_a_bank	.byt 0
 dma_a_addr	.word 0
@@ -77,6 +81,7 @@ time_y10	.byt 0
 time_y100	.byt 0
 time_sel	.byt 0
 time_exit	.byt 0
+time_cancel	.byt 0
 time_ptr	.byt 0
 time_tmp	.byt 0
 ;--
@@ -169,5 +174,27 @@ dirlog  .word	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
 	.word	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
 	.word	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
 
-infloop		.byt 0,0  ; to be filled w/ 80 FE
+direntry_fits
+	.byt	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.byt	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+direntry_xscroll_state
+	.word	0
+direntry_xscroll
+	.word	0
+direntry_xscroll_wait
+	.word	0
+infloop	.byt 0,0  ; to be filled w/ 80 FE
+tgt_bright
+	.byt 0
+cur_bright
+	.byt 0
+
+;------------------------
+saved_sp
+	.word 0
+warm_signature
+	.word 0
+snes_system_config
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+
 wram_fadeloop	.byt 0

snes/dma.a65

@@ -1,21 +1,4 @@
 
-dma0:
-	rep #$10 : .xl
-	sep #$20 : .as
-	lda dma_mode
-	sta $4300
-	lda dma_b_reg
-	sta $4301
-	lda dma_a_bank
-	ldx dma_a_addr
-	stx $4302
-	sta $4304
-	ldx dma_len
-	stx $4305
-	lda #$01
-	sta $420b
-	rts
-
 setup_hdma:
 	sep #$20 : .as
 	rep #$10 : .xl
@@ -67,8 +50,11 @@ setup_hdma:
 	sty $4352
 	sta $4354
 
-;	lda #$06
-;	sta $420c		;enable HDMA ch. 1+2
+	lda #$3a
+	sta $420c		;enable HDMA ch. 1+3+4+5
+	jsr waitblank
+	lda #$3e
+	sta $420c		;enable HDMA ch. 2 too
 	lda #$81		;VBlank NMI + Auto Joypad Read
 	sta $4200		;enable V-BLANK NMI
 	rts

snes/dma.i65

@@ -1,13 +1,22 @@
+#define hash #
+#define f(x) x
+#define imm(a) f(hash)a
+
 #define DMA0(mode, len, a_bank, a_addr, b_reg)\
-	lda mode \
-: 	sta dma_mode \
+	php \
+:	sep imm($20) : .as \
+:	rep imm($10) : .xl \
+:	lda mode \
+: 	sta $4300 \
 :	ldx a_addr \
 :	lda a_bank \
-:	stx dma_a_addr \
-:	sta dma_a_bank \
+:	stx $4302 \
+:	sta $4304 \
 :	ldx len \
-:	stx dma_len \
+:	stx $4305 \
 :	lda b_reg \
-:	sta dma_b_reg \
-:	jsr dma0
+:	sta $4301 \
+:	lda imm($01) \
+:	sta $420b \
+:	plp
 

snes/header.a65

@@ -1,6 +1,16 @@
-; This file is part of the snescom-asm demo - a demo of how to build a SNES program.
+; This file is a modified version of the header.a65 file from:
+; snescom-asm demo - a demo of how to build a SNES program.
 ; See http://bisqwit.iki.fi/source/snescom.html for details.
 
+; fill whole area beforehand so the linker does not create multiple
+; objects from it. (necessary for map creation)
+
+*= $C0FF00
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+
 ; Begin assembling to this address.
 *= $C0FF00
 

snes/logospr.a65

@@ -1,80 +1,69 @@
-logospr .byt  $00, $00, $00, $00, $00, $00, $00, $00
+logospr .byt  $50, $2f, $75, $2a, $7e, $21, $4a, $14
+        .byt  $6f, $3e, $5b, $1b, $60, $20, $54, $00
+        .byt  $10, $0f, $15, $0a, $1f, $00, $3e, $01
+        .byt  $1e, $01, $3a, $05, $01, $1e, $21, $1f
+        .byt  $f4, $8f, $fc, $83, $7f, $84, $fe, $05
+        .byt  $fe, $07, $fb, $07, $fe, $02, $fe, $00
+        .byt  $0c, $8b, $08, $0f, $03, $04, $83, $80
+        .byt  $03, $00, $07, $04, $00, $01, $01, $01
+        .byt  $0f, $f8, $4f, $b8, $f7, $00, $b7, $58
+        .byt  $af, $e0, $ff, $f0, $0f, $10, $df, $e0
+        .byt  $08, $f8, $40, $b8, $f8, $08, $f8, $08
+        .byt  $e0, $10, $f0, $10, $00, $e0, $c0, $c0
+        .byt  $ff, $00, $fb, $00, $f9, $00, $f8, $00
+        .byt  $f8, $00, $f0, $00, $f0, $00, $f0, $00
+        .byt  $00, $01, $03, $03, $00, $00, $00, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $00, $ff, $00, $7f, $fe, $61, $eb, $0a
+        .byt  $7f, $00, $1f, $00, $00, $00, $00, $00
+        .byt  $00, $ff, $00, $ff, $3f, $40, $35, $39
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $0f, $e0, $1f, $c0, $bf, $c0, $ff, $00
+        .byt  $ff, $00, $fe, $00, $70, $00, $00, $00
+        .byt  $10, $e0, $60, $80, $c0, $c0, $00, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $f0, $00, $e0, $00, $e0, $00, $c0, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $7f, $2b, $5e, $1f, $7e, $3f, $6b, $2b
+        .byt  $4f, $0f, $da, $1a, $c0, $22, $c0, $35
+        .byt  $0a, $1e, $3e, $1e, $00, $1e, $14, $0a
+        .byt  $30, $20, $25, $25, $1d, $1d, $0a, $0a
+        .byt  $ff, $00, $ff, $00, $ff, $00, $ff, $00
+        .byt  $ff, $00, $ff, $00, $ff, $00, $ff, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $ff, $00, $ff, $00, $83, $00, $00, $00
+        .byt  $80, $00, $80, $00, $80, $00, $80, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $e0, $00, $e0, $00, $80, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $e0, $a0, $a1, $a0, $41, $80, $01, $c0
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $de, $3f, $9e, $7f, $bf, $7f, $bf, $7f
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $ff, $ff, $fe, $ff, $01, $fe, $00, $fe
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $ff, $00, $ff, $00, $ff, $00, $fe, $01
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $00, $00, $80, $80, $00, $80, $80, $80
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $ff, $7f, $7f, $7f, $7f, $7f, $7f, $ff
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $2f, $07, $13, $07, $11, $02, $48, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $df, $d8, $cb, $cc, $cd, $ce, $87, $86
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $ff, $ff, $ff, $ff, $00, $ff, $c5, $3b
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $ff, $00, $ff, $00, $ff, $00, $7f, $83
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $c0, $e0, $a0, $e0, $00, $00, $80, $80
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $ff, $0f, $ff, $3f, $7f, $bf, $7f, $ff
+        .byt  $c0, $3f, $d5, $2a, $ff, $00, $7f, $00
+        .byt  $7f, $00, $7f, $00, $3f, $00, $0f, $00
+        .byt  $3f, $3f, $3f, $3f, $3f, $3f, $1e, $1e
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $04, $00, $08, $00, $10, $00, $10, $00
+        .byt  $ff, $00, $ff, $00, $ff, $00, $ff, $00
+        .byt  $ff, $00, $ff, $00, $fe, $00, $fc, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $f8, $f8, $f0, $f0, $e0, $e0, $e0, $e0
-        .byt  $7f, $20, $7f, $20, $60, $00, $00, $20
-        .byt  $00, $3f, $c0, $3f, $ff, $40, $ff, $00
-        .byt  $3f, $20, $3f, $20, $20, $3f, $40, $7f
-        .byt  $5f, $7f, $1f, $3f, $20, $7f, $20, $3f
-        .byt  $c1, $01, $80, $00, $01, $01, $40, $40
-        .byt  $00, $c0, $40, $c0, $c0, $40, $c0, $40
-        .byt  $ff, $7f, $ff, $3e, $7e, $be, $3f, $bf
-        .byt  $bf, $bf, $bf, $ff, $3f, $ff, $3f, $ff
-        .byt  $ff, $00, $ff, $00, $01, $01, $01, $81
-        .byt  $80, $fc, $5c, $4c, $00, $00, $18, $00
-        .byt  $fe, $01, $ff, $01, $01, $ff, $00, $fe
-        .byt  $3f, $fd, $bb, $db, $ff, $ff, $e7, $e7
-        .byt  $00, $00, $00, $00, $00, $00, $c0, $c0
-        .byt  $80, $80, $00, $00, $01, $00, $03, $00
-        .byt  $ff, $ff, $ff, $ff, $ff, $ff, $3f, $ff
-        .byt  $7f, $ff, $ff, $ff, $fe, $fe, $fc, $fc
-        .byt  $46, $00, $41, $00, $40, $00, $40, $00
-        .byt  $40, $00, $80, $00, $80, $00, $00, $00
-        .byt  $81, $81, $80, $80, $80, $80, $80, $80
-        .byt  $80, $80, $00, $00, $00, $00, $00, $00
-        .byt  $44, $44, $00, $00, $78, $00, $03, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $bb, $83, $ff, $ff, $07, $07, $00, $00
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $00, $00, $00, $00, $03, $00, $fc, $00
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $ff, $ff, $ff, $ff, $fc, $fc, $00, $00
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $60, $00, $c0, $00, $00, $00, $00, $00
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $80, $80, $00, $00, $00, $00, $00, $00
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $e0, $5f, $a0, $5f, $bf, $40, $bf, $60
-        .byt  $bf, $7f, $bf, $7f, $80, $40, $00, $40
-        .byt  $20, $7f, $20, $3f, $3f, $3f, $3f, $3f
-        .byt  $3f, $3f, $3f, $3f, $3f, $00, $bf, $80
-        .byt  $00, $80, $10, $c0, $c0, $40, $e0, $40
-        .byt  $c0, $c0, $e0, $e0, $60, $60, $00, $40
-        .byt  $7f, $ff, $2f, $af, $bf, $bf, $9f, $9f
-        .byt  $bf, $bf, $9f, $bf, $9f, $3f, $bf, $3f
-        .byt  $13, $00, $10, $00, $10, $00, $08, $00
-        .byt  $08, $00, $08, $00, $08, $00, $00, $00
-        .byt  $e0, $e0, $e0, $e0, $e0, $e0, $f0, $f0
-        .byt  $f0, $f0, $f0, $f0, $f0, $f0, $f8, $f8
-        .byt  $fc, $00, $00, $00, $00, $00, $00, $00
+        .byt  $80, $00, $80, $00, $80, $00, $80, $00
+        .byt  $80, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
@@ -93,36 +82,67 @@ logospr .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $3f, $7f, $3f, $7f, $c0, $7f, $80, $3f
-        .byt  $3f, $3f, $1f, $1f, $00, $00, $00, $00
-        .byt  $80, $80, $80, $80, $00, $40, $40, $40
-        .byt  $40, $7f, $60, $7f, $3f, $3f, $1f, $1f
-        .byt  $80, $c0, $80, $c0, $00, $c0, $40, $c0
-        .byt  $80, $80, $00, $00, $00, $00, $00, $00
-        .byt  $3f, $3f, $3f, $3f, $3f, $3f, $3f, $7f
-        .byt  $7f, $ff, $ff, $ff, $ff, $ff, $ff, $ff
-        .byt  $08, $00, $08, $00, $08, $00, $00, $00
-        .byt  $00, $00, $00, $00, $20, $00, $40, $00
-        .byt  $f0, $f0, $f0, $f0, $f0, $f0, $f0, $f0
-        .byt  $f0, $f0, $e0, $e0, $c0, $c0, $80, $80
+        .byt  $00, $20, $c0, $00, $80, $40, $c0, $40
+        .byt  $00, $80, $40, $c0, $c0, $c0, $40, $00
+        .byt  $00, $20, $40, $00, $40, $00, $40, $00
+        .byt  $00, $40, $40, $00, $40, $00, $00, $40
+        .byt  $7b, $06, $3a, $47, $3e, $43, $4c, $41
+        .byt  $0f, $00, $1f, $10, $0f, $10, $1f, $10
+        .byt  $06, $01, $06, $01, $02, $01, $30, $03
+        .byt  $08, $02, $05, $00, $0b, $00, $05, $00
+        .byt  $fc, $02, $d8, $7c, $80, $00, $80, $00
+        .byt  $80, $40, $c0, $40, $80, $80, $00, $00
+        .byt  $00, $00, $00, $40, $40, $00, $40, $40
+        .byt  $80, $00, $00, $00, $00, $80, $80, $00
+        .byt  $07, $19, $0e, $10, $14, $1a, $18, $16
+        .byt  $10, $0e, $02, $1c, $00, $1e, $10, $1e
+        .byt  $0e, $08, $0e, $00, $0e, $0a, $0e, $06
+        .byt  $1e, $1e, $0e, $0c, $0e, $0e, $0e, $0e
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $0b, $1f, $15, $1e, $1e, $1e, $06, $1e
+        .byt  $0f, $1f, $1f, $0f, $0f, $0f, $0f, $0f
+        .byt  $04, $0e, $0b, $0f, $01, $0f, $09, $0e
+        .byt  $09, $0f, $14, $1f, $0a, $0f, $05, $0f
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $0f, $1f, $0f, $0f, $05, $05, $0a, $0a
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $0f, $0f, $1f, $1f, $1f, $05, $1f, $0a
+        .byt  $1f, $08, $1f, $00, $1f, $0a, $1f, $15
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $00, $00, $00, $00, $00, $02, $00, $10
+        .byt  $00, $0e, $00, $15, $10, $0f, $10, $0f
+        .byt  $1f, $1f, $1f, $1f, $1d, $1d, $0f, $0f
+        .byt  $11, $11, $0a, $0a, $10, $10, $10, $10
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $0a, $05, $05, $0a, $0f, $00, $0f, $00
+        .byt  $0f, $0a, $07, $05, $00, $00, $00, $00
+        .byt  $0a, $0a, $05, $05, $0f, $0f, $0f, $0f
+        .byt  $05, $05, $02, $02, $00, $00, $00, $00
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $5f, $2f, $5f, $2f, $70, $2f, $40, $1f
         .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $1f, $00, $1f, $00, $1f, $00, $3f, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $00, $00, $00, $00, $00, $00, $00, $00
+        .byt  $09, $00, $01, $08, $0f, $08, $05, $00
+        .byt  $03, $05, $07, $05, $00, $02, $06, $00
+        .byt  $07, $00, $07, $00, $05, $02, $03, $00
+        .byt  $04, $03, $05, $02, $00, $06, $00, $02
+        .byt  $00, $06, $02, $04, $06, $04, $00, $02
+        .byt  $02, $00, $00, $02, $02, $00, $02, $00
+        .byt  $00, $02, $00, $02, $02, $06, $04, $06
+        .byt  $06, $06, $04, $06, $06, $06, $06, $06
+        .byt  $02, $04, $00, $06, $02, $04, $00, $06
+        .byt  $06, $06, $04, $06, $00, $04, $00, $00
+        .byt  $06, $06, $06, $06, $06, $06, $06, $06
+        .byt  $06, $06, $06, $04, $04, $02, $00, $06

snes/main.a65

@@ -4,13 +4,45 @@
 GAME_MAIN:
 	sep #$20 : .as
 	lda #$00
-	sta @AVR_CMD
+	sta @MCU_CMD		; clear MCU command register
 	rep #$20 : .al
 	lda #$0000
-	sta @AVR_PARAM
-	sta @AVR_PARAM+2
+	sta @MCU_PARAM		; clear MCU command parameters
+	sta @MCU_PARAM+2
 	sep #$20 : .as
 	stz $4200 ; inhibit VBlank NMI
+	rep #$20 : .al
+	lda @warm_signature	; Was CMD_RESET issued before reset?
+	cmp #$fa50		; If yes, then perform warm boot procedure
+	bne coldboot
+	lda #$0000
+	sta @warm_signature
+	lda @saved_sp		; Restore previous stack pointer
+	tcs
+	sep #$20 : .as
+
+	jsr killdma		; The following initialization processes must not touch memory
+	jsr waitblank		; structures used by the main menu !
+	jsr snes_init
+	cli
+	lda #$01
+	sta $420d 		; fast cpu
+	jsr setup_gfx
+	jsr colortest
+	jsr tests
+	jsr setup_hdma
+	lda #$0f
+	sta cur_bright
+	sta tgt_bright
+	sta $2100
+
+	jmp @set_bank		; Set bios bank, just to be sure
+set_bank:
+	plp			; Restore processor state
+	rts			; Jump to the routine which called the sub-routine issuing CMD_RESET
+
+coldboot:							; Regular, cold-start init
+	sep #$20 : .as
 	jsr killdma
 	jsr waitblank
 	jsr snes_init
@@ -18,9 +50,11 @@ GAME_MAIN:
 	sta $420d ; fast cpu
 	jsr setup_gfx
 	jsr colortest
-	jsr setup_hdma
 	jsr menu_init
 	jsr tests
+	jsr setup_hdma
+	jsr screen_on
+
 	sep #$20 : .as
 	lda @RTC_STATUS
 	beq +
@@ -32,50 +66,93 @@ GAME_MAIN:
 	jmp @infloop	;infinite loop in WRAM
 
 killdma:
-	stz $420b
-	stz $420c
+	stz $4300
+	stz $4301
+	stz $4302
+	stz $4303
+	stz $4304
+	stz $4305
+	stz $4306
+	stz $4307
+	stz $4308
+	stz $4309
+	stz $430a
+	stz $430b
 	stz $4310
 	stz $4311
 	stz $4312
 	stz $4313
 	stz $4314
+	stz $4315
+	stz $4316
+	stz $4317
+	stz $4318
+	stz $4319
+	stz $431a
+	stz $431b
 	stz $4320
 	stz $4321
 	stz $4322
 	stz $4323
 	stz $4324
+	stz $4325
+	stz $4326
+	stz $4327
+	stz $4328
+	stz $4329
+	stz $432a
+	stz $432b
 	stz $4330
 	stz $4331
 	stz $4332
 	stz $4333
 	stz $4334
+	stz $4335
+	stz $4336
+	stz $4337
+	stz $4338
+	stz $4339
+	stz $433a
+	stz $433b
 	stz $4340
 	stz $4341
 	stz $4342
 	stz $4343
 	stz $4344
+	stz $4345
+	stz $4346
+	stz $4347
+	stz $4348
+	stz $4349
+	stz $434a
+	stz $434b
 	stz $4350
 	stz $4351
 	stz $4352
 	stz $4353
 	stz $4354
-	stz $4360
-	stz $4361
-	stz $4362
-	stz $4363
-	stz $4364
+	stz $4355
+	stz $4356
+	stz $4357
+	stz $4358
+	stz $4359
+	stz $435a
+	stz $435b
+
+	stz $420b
+	stz $420c
 	rts
 
-
-
-
 waitblank:
+	php
+	sep #$30 : .as : .xs
 -	lda $4212
 	and #$80
 	bne -
 -	lda $4212
 	and #$80
 	beq -
+	plp
 	rts
 
 colortest:
@@ -91,21 +168,14 @@ setup_gfx:
 	stz $420b
 	stz $420c
 ;clear tilemap buffers
-	ldx #$0000
+	ldx #$8000
 	stx $2181
-	lda #$01
+	lda #$00
 	sta $2183
-	DMA0(#$08, #0, #^zero, #!zero, #$80)
+	DMA0(#$08, #$8000, #^zero, #!zero, #$80)
 
-;copy 2bpp font (can be used as 4-bit lores font!)
-	ldx #$4000
-	stx $2116
-	DMA0(#$01, #$2000, #^font2, #!font2, #$18)
-
-;copy 4bpp font
-	ldx #$0000
-	stx $2116
-	DMA0(#$01, #$4000, #^font4, #!font4, #$18)
+;generate fonts
+	jsr genfonts
 
 ;clear BG1 tilemap
 	ldx #BG1_TILE_BASE
@@ -127,27 +197,33 @@ setup_gfx:
 	stx $2116
 	DMA0(#$01, #$4000, #^logo, #!logo, #$18)
 
-;copy logo tilemap
+;generate logo tilemap
 	ldx #BG1_TILE_BASE
 	stx $2116
-	DMA0(#$01, #$280, #^logomap, #!logomap, #$18)
+	ldx #$0100
+-	stx $2118
+	inx
+	cpx #$01e0
+	bne -
+
 
 ;copy sprites tiles
 	ldx #OAM_TILE_BASE
 	stx $2116
-	DMA0(#$01, #$400, #^logospr, #!logospr, #$18)
+	DMA0(#$01, #$500, #^logospr, #!logospr, #$18)
 
 ;set OAM tables
 	ldx #$0000
 	stx $2102
-	DMA0(#$00, #$5C, #^oam_data_l, #!oam_data_l, #$04)
+	DMA0(#$00, #$60, #^oam_data_l, #!oam_data_l, #$04)
 	ldx #$0100
 	stx $2102
-	DMA0(#$00, #$08, #^oam_data_h, #!oam_data_h, #$04)
+	DMA0(#$00, #$09, #^oam_data_h, #!oam_data_h, #$04)
 
 ;set palette
 	stz $2121
 	DMA0(#$00, #$200, #^palette, #!palette, #$22)
+	stz $2121
 
 ;copy hdma tables so we can work "without" the cartridge
 ;palette
@@ -200,7 +276,7 @@ setup_gfx:
 tests:
 	sep #$20 : .as		;8-bit accumulator
 	rep #$10 : .xl		;16-bit index
-	lda #$03		;mode 3, mode 5 via HDMA :D
+	lda #$03		;mode 3, mode 5 via HDMA
 	sta $2105
 	lda #$58		;Tilemap addr 0xB000
 	ora #$02		;SC size 32x64
@@ -226,13 +302,19 @@ tests:
 	lda #$1f
 	sta $212e
 	sta $212f
-	stz $2121
-	lda #$0f
-	sta $2100		;screen on, full brightness
-	lda #9
+;	stz $2121
+	lda #8
 	sta bar_yl
+	stz cur_bright
+	stz tgt_bright
 	rts
-	
+
+screen_on:
+	stz $2100		;screen on, 0% brightness
+	lda #$0f
+	sta tgt_bright
+	rts
+
 snes_init:
 	sep #$20 : .as		;8-bit accumulator
 	rep #$10 : .xl		;16-bit index
@@ -250,6 +332,7 @@ snes_init:
 	stz $420a		;
 	stz $420b		;
 	stz $420c		;
+	stz $420d		;
 	lda #$8f
 	sta $2100		;INIDISP: force blank
 	lda #$03		; 8x8+16x16; name=0; base=3
@@ -283,7 +366,7 @@ snes_init:
 	stz $2113		;
 	stz $2114		;
 	stz $2114		;
-	lda #$80		
+	lda #$80
 	sta $2115		;
 	stz $2116		;
 	stz $2117		;
@@ -341,7 +424,7 @@ snes_init:
 
 fadeloop:
 	sep #$30 : .as : .xs
-	ldx #$0f
+	ldx cur_bright
 	and #$00
 	pha
 	plb
@@ -387,3 +470,59 @@ fadeloop_start
 
 fadeloop_end:
 	.byt $ff
+
+genfonts:
+	php
+	rep #$10 : .xl
+	sep #$20 : .as
+
+;clear VRAM font areas
+	ldx #$0000
+	stx $2116
+	DMA0(#$09, #$4000, #^zero, #!zero, #$18)
+
+	ldx #$4000
+	stx $2116
+	DMA0(#$09, #$2000, #^zero, #!zero, #$18)
+
+	sep #$10 : .xs
+	rep #$20 : .al
+
+	stz $2116
+	ldx #$01
+	stx $4300
+	ldx #^font
+	stx $4304
+	lda #!font
+	sta $4302
+	lda #$0010
+	sta $4305
+	ldx #$18
+	stx $4301
+	lda #$0000
+-	sta $2116
+	ldx #$10
+	stx $4305
+	ldx #$01
+	stx $420b
+	clc
+	adc #$20
+	cmp #$2000
+	bne -
+	ldx #^font
+	stx $4304
+	lda #!font
+	sta $4302
+	lda #$4000
+-	sta $2116
+	ldx #$10
+	stx $4305
+	ldx #$01
+	stx $420b
+	clc
+	adc #$10
+	cmp #$5000
+	bne -
+	plp
+	rts
+

snes/mainmenu.a65

@@ -1,6 +1,6 @@
 #include "memmap.i65"
 ;number of menu entries
-main_entries    .byt 1
+main_entries    .byt 2
 ;menu entry data
 main_enttab     ;Set Clock
 		.word !text_mm_time
@@ -8,6 +8,11 @@ main_enttab     ;Set Clock
                 .word !time_init-1
                 .byt ^time_init
                 .byt 1, 0
+                ;System Information
+                .word !text_mm_sysinfo
+                .byt ^text_mm_sysinfo
+                .word !show_sysinfo-1
+		.byt ^show_sysinfo
                 ;SuperCIC
 		.word !text_mm_scic
                 .byt ^text_mm_scic
@@ -115,13 +120,13 @@ mm_menuloop
 	and pad1trig+1
 	bne mmkey_b
 	bra mm_menuloop
-mmkey_a
+mmkey_b
 	jsr restore_screen
 	plp
 	rts
 
-mmkey_b
-	jsr mmkey_b_2
+mmkey_a
+	jsr mmkey_a_2
 	jmp mm_redraw
 
 mmkey_down
@@ -151,10 +156,10 @@ mmkey_up_2
 +
 	rts
 
-mmkey_b_2
+mmkey_a_2
 	jsr restore_screen
 	phk			; push return bank for subroutine
-	per mmkey_b_2_return-1	; push return addr for subroutine
+	per mmkey_a_2_return-1	; push return addr for subroutine
 	xba
 	lda #$00
 	xba
@@ -170,7 +175,7 @@ mmkey_b_2
 	pha			; push subroutine addr
 	sep #$20 : .as
 	rtl			; jump to subroutine
-mmkey_b_2_return
+mmkey_a_2_return
 	rts
 
 mm_do_refresh

snes/memmap.i65

@@ -6,19 +6,35 @@
 /* These must be defined as constants, because they're used
  * in calculation that is sent to PPU as parameters */
 
+#define APUIO0		$2140
+#define APUIO1		$2141
+#define APUIO2		$2142
+#define APUIO3		$2143
+
 #define BG1_TILE_BASE	$5800
 #define BG2_TILE_BASE	$5000
 
 #define OAM_TILE_BASE	$6000
 
-#define BG1_TILE_BUF	$7FB000
-#define BG2_TILE_BUF	$7FA000
+#define BG1_TILE_BUF	$7EB000
+#define BG2_TILE_BUF	$7EA000
 
-#define BG1_TILE_BAK	$7F9000
-#define BG2_TILE_BAK	$7F8000
+#define BG1_TILE_BAK	$7E9000
+#define BG2_TILE_BAK	$7E8000
 
-#define AVR_CMD		$307000
-#define AVR_PARAM	$307004
+#define MCU_CMD		$307000
+#define MCU_PARAM	$307004
 #define RTC_STATUS	$307100
+#define LAST_STATUS	$307101
+#define SYSINFO_BLK	$307200
+#define LAST_GAME	$307420
 
 #define ROOT_DIR	$C10000
+
+#define CMD_SYSINFO	$03
+#define CMD_LOADSPC	$05
+#define CMD_RESET	$06
+
+#define SPC_DATA	$FD0000
+#define SPC_HEADER	$FE0000
+#define SPC_DSP_REGS	$FE0100

snes/menu.a65

@@ -23,6 +23,8 @@ menu_init:
 	ldx #$0000
 	stx dirptr_idx
 	stx menu_sel
+	stx direntry_xscroll
+	stx direntry_xscroll_state
 	lda #$01
 	sta menu_dirty
 	rep #$20 : .al
@@ -40,13 +42,13 @@ menuloop_s1
 	lda isr_done
 	lsr
 	bcc menuloop_s1
-
 	stz isr_done
 	jsr printtime
 	jsr menu_updates	;update stuff, check keys etc
 	lda menu_dirty		;is there ANY reason to redraw the menu?
 	cmp #$01
 	beq menuloop_redraw 	;then do
+	jsr scroll_direntry
 	bra menuloop_s1
 menuloop_redraw
 	stz menu_dirty
@@ -126,6 +128,9 @@ menu_updates:
 	lda #$80
 	and pad1trig+1
 	bne key_b
+	lda #$10
+	and pad1trig+1
+	bne key_start
 	lda #$20
 	and pad1trig+1
 	bne key_select
@@ -157,10 +162,12 @@ key_a
 key_x
 	jsr menu_key_x
 	bra menuupd_out
-
 key_select
 	jsr menu_key_select
 	bra menuupd_out
+key_start
+	jsr menu_key_start
+	bra menuupd_out
 
 menuupd_out
 	lda #$09
@@ -179,6 +186,7 @@ menu_redraw_out
 redraw_filelist
 	ldy #$0000
 	sty dirptr_idx
+	sty direntry_fits_idx
 	stz dirend_idx
 	stz dirend_onscreen
 redraw_filelist_loop
@@ -188,52 +196,43 @@ redraw_filelist_loop
 	lsr
 	cmp listdisp
 	beq redraw_filelist_last
-	lda dirptr_bank
-	phb
-	pha
-	plb
 	rep #$20 : .al
-	lda (dirptr_addr), y
+	lda [dirptr_addr], y
 	sta @dirent_addr
 	iny
 	iny
 	sep #$20 : .as
-	lda (dirptr_addr), y       ; load fileinfo bank
+	lda [dirptr_addr], y	   ; load fileinfo bank
 	clc
 	adc #$c0                   ; add $C0 for memory map
 	sta @dirent_bank           ; store as current bank
 	cmp #$c0                   ; if bank was 0 -> dirend entry in DB
 	beq redraw_filelist_dirend ; handle dirend
 	iny
-	lda (dirptr_addr), y
+	lda [dirptr_addr], y
 	iny
 	sta @dirent_type
-	plb
 	sty dirptr_idx
 	jsr print_direntry
+	inc direntry_fits_idx
 	bra redraw_filelist_loop
 redraw_filelist_dirend
-	plb
 	dey                        ; recover last valid direntry number
 	dey                        ; (we had 2x iny of the direntry pointer above,
+	beq +
 	dey                        ;  so account for those too)
 	dey
 	dey
 	dey
-	sty dirend_idx             ; dirend_idx <- last valid directory entry.
++	sty dirend_idx             ; dirend_idx <- last valid directory entry.
 	lda #$01                   ; encountered during redraw, so must be on screen
 	sta dirend_onscreen
 	bra redraw_filelist_out
 redraw_filelist_last	;check if next offscreen item is end of dir
-	lda dirptr_bank
-	phb
-	pha
-	plb
 	iny
 	iny
-	lda (dirptr_addr), y
+	lda [dirptr_addr], y
 	beq redraw_filelist_dirend
-	plb
 redraw_filelist_out
 	ldx #$0000
 	stx dirptr_idx
@@ -272,6 +271,10 @@ dirent_is_file
 	lda #$0000
 	bra dirent_type_cont
 +
+	cmp #$0003  ;SPC -> palette 2
+	bne +
+	lda #$0002
+	bra dirent_type_cont
 	cmp #$0004	;IPS -> palette 2 (green)
 	bne +
         lda #$0002
@@ -294,6 +297,8 @@ dirent_type_cont
 	txa
 	clc
 	adc @fd_fnoff
+	clc
+	adc @direntry_xscroll
 	sta @fd_fnoff
 	plb
 
@@ -308,12 +313,14 @@ dirent_type_cont
 	lda dirent_bank
 	sta print_bank
 	jsr hiprint
-
 	lda cursor_x
 	clc
 	adc print_done
 	sta print_x
 
+	lda print_over
+	ldy direntry_fits_idx
+	sta !direntry_fits, y
 	lda #54
 	sec
 	sbc print_done
@@ -349,10 +356,11 @@ dirent_type_cont_2
 	rts
 
 menu_key_down:
+	jsr scroll_direntry_clean
 	lda listdisp
 	dec
 	cmp menu_sel
-	bne +
+	bne down_noscroll
 	lda #$01
 	sta menu_dirty
 	lda dirend_onscreen
@@ -361,10 +369,13 @@ menu_key_down:
 	lda dirptr_addr
 	clc
 	adc #$04
-	sta dirptr_addr
+	bcc +
+	inc dirptr_bank
++	sta dirptr_addr
 	sep #$20 : .as
 	rts
-+	lda dirend_onscreen
+down_noscroll
+	lda dirend_onscreen
 	beq +
 	lda dirend_idx
 	lsr
@@ -379,8 +390,9 @@ down_out
 	rts
 
 menu_key_up:
+	jsr scroll_direntry_clean
 	lda menu_sel
-	bne +
+	bne up_noscroll
 	lda #$01
 	sta menu_dirty
 	rep #$20 : .al
@@ -389,15 +401,19 @@ menu_key_up:
 	beq up_out
 	sec
 	sbc #$04
-	sta dirptr_addr
+	bcs +
+	dec dirptr_bank
++	sta dirptr_addr
 	bra up_out
-+	dec
+up_noscroll
+	dec
 	sta menu_sel
 up_out
 	sep #$20 : .as
 	rts
 
 menuupd_lastcursor
+	jsr scroll_direntry_clean
 	lda dirend_idx
 	lsr
 	lsr
@@ -406,6 +422,8 @@ menuupd_lastcursor
 
 ; go back one page
 menu_key_left:
+	stz direntry_xscroll
+	stz direntry_xscroll_state
 	lda #$01            ; must redraw afterwards
 	sta menu_dirty
 	rep #$20 : .al
@@ -431,6 +449,8 @@ menu_key_left:
 
 ; go forth one page
 menu_key_right:
+	stz direntry_xscroll
+	stz direntry_xscroll_state
 	sep #$20 : .as
 	lda dirend_onscreen
 	bne menuupd_lastcursor
@@ -446,29 +466,28 @@ menu_key_right:
 	sep #$20 : .as
 	rts
 
-menu_key_b:
+menu_key_a:
 	jsr select_item
 	rts
 
 menu_key_select:
-	lda barstep
-	beq do_setup448
-do_setup224
-	jsr setup_224
-	rts
-do_setup448
-	jsr setup_448
 	rts
 
-menu_key_a:
+menu_key_start:
+	jsr select_last_file
+	rts
+
+menu_key_b:
+	stz direntry_xscroll
+	stz direntry_xscroll_state
 	rep #$20 : .al
 	lda dirstart_addr
-	beq skip_key_a
+	beq skip_key_b
 	sta dirptr_addr
 	lda #$0000
 	sta menu_sel
 	bra select_item
-skip_key_a
+skip_key_b
 	sep #$20 : .as
 	rts
 
@@ -480,16 +499,14 @@ select_item:
 	asl
 	tay
 	sep #$20 : .as
-	lda dirptr_bank
-	phb
-	pha
-	plb
 	iny
 	iny
 	iny
-	lda (dirptr_addr), y
+	lda [dirptr_addr], y
 	cmp #$01
 	beq sel_is_file
+	cmp #$03
+	beq sel_is_spc
 	cmp #$04
 	beq sel_is_file
 	cmp #$80
@@ -497,7 +514,6 @@ select_item:
 	cmp #$81
 	beq sel_is_parent
 select_item_cont
-	plb
 	rts
 sel_is_file
 	jsr select_file
@@ -508,24 +524,28 @@ sel_is_parent
 sel_is_dir
 	jsr select_dir
 	bra select_item_cont
+sel_is_spc
+	jsr select_spc
+	bra select_item_cont
 
 select_file:
-	; have avr load the rom
+	; have MCU load the rom
 	dey
 	rep #$20 : .al
-	lda (dirptr_addr), y
+	lda [dirptr_addr], y
 	and #$00ff
-	sta @AVR_PARAM+2
+	sta @MCU_PARAM+2
 	dey
 	dey
-	lda (dirptr_addr), y
-	sta @AVR_PARAM
+	lda [dirptr_addr], y
+	sta @MCU_PARAM
 	sep #$20 : .as
-	lda #$01
-	sta @AVR_CMD
 	lda #$00
 	sta @$4200
 	sei
+	lda #$01
+	sta @MCU_CMD
+select_file_fade:
 	jsl @wram_fadeloop
 	rts
 
@@ -559,14 +579,14 @@ select_dir:
 ; y = direntry ptr
 	txy
 	dey
-	lda (dirptr_addr), y
+	lda [dirptr_addr], y
 	clc
 	adc #$c0
 	sta @dirent_bank
 	dey
 	dey
 	rep #$20 : .al
-	lda (dirptr_addr), y
+	lda [dirptr_addr], y
 	sta @dirent_addr
 	tax
 	sep #$20 : .as
@@ -585,6 +605,8 @@ select_dir:
 	sta @dirstart_addr
 	lda #$0000
 	sta @menu_sel
+	sta @direntry_xscroll
+	sta @direntry_xscroll_state
 	sep #$20 : .as
 	lda #$01
 	sta @menu_dirty
@@ -623,6 +645,27 @@ select_parent:
 	sta @menu_dirty
 	rts
 
+select_spc:
+	dey
+	rep #$20 : .al
+	lda [dirptr_addr], y
+	and #$00ff
+	sta @MCU_PARAM+2
+	dey
+	dey
+	lda [dirptr_addr], y
+	sta @MCU_PARAM
+	sep #$20 : .as
+	lda #CMD_LOADSPC
+	sta @MCU_CMD
+wait_spc:
+	lda @MCU_CMD
+	cmp #$00
+	bne wait_spc
+	jsr spcplayer
+	jsr restore_screen
+	rts
+
 menu_key_x:
 	jsr mainmenu
 	rts
@@ -641,10 +684,10 @@ setup_224_adjsel
 +
 	lda #18*64
 	sta textdmasize
-	lda #$0007
+	lda #$000b
 	sta hdma_scroll+8
 	sep #$20 : .as
-	lda #$07
+	lda #$0b
 	sta $2110
 	lda #$00
 	sta $2110
@@ -676,32 +719,6 @@ setup_224_adjsel
 	plp
 	rts
 
-setup_448:
-	php
-	rep #$30 : .xl : .al
-	lda #36
-	sta listdisp
-	lda #36*64
-	sta textdmasize
-	lda #$ffc6
-	sta hdma_scroll+8
-	sep #$20 : .as
-	lda #$c6
-	sta $2110
-	lda #$ff
-	sta $2110
-	lda #$01
-	sta barstep
-	ora #$08
-	sta $2133
-	lda #$04
-	sta hdma_math_selection
-	lda #$01
-	sta vidmode
-	sta menu_dirty
-	plp
-	rts
-
 menu_statusbar
 	pha
 	phx
@@ -732,3 +749,142 @@ menu_statusbar
 	pla
 	rts
 
+select_last_file:
+	php
+	sep #$20 : .as
+	rep #$10 : .xl
+	lda @LAST_STATUS
+	bne +
+	plp
+	rts
++	jsr backup_screen
+	lda #^text_last
+	sta window_tbank
+	ldx #!text_last
+	stx window_taddr
+	lda @last_win_x
+	sta window_x
+	inc
+	inc
+	sta bar_xl
+	pha
+	lda @last_win_y
+	sta window_y
+	inc
+	sta bar_yl
+	inc
+	pha
+	lda @last_win_w
+	sta window_w
+	lda @last_win_h
+	sta window_h
+	jsr draw_window
+	stz print_pal
+	lda #^LAST_GAME
+	ldx #!LAST_GAME
+	sta print_bank
+	stx print_src
+	stz print_pal
+	pla
+	sta print_y
+	pla
+	sta print_x
+	lda #56
+	sta bar_wl
+	sta print_count
+	jsr hiprint
+-	lda isr_done
+	lsr
+	bcc -
+	jsr printtime
+	jsr read_pad
+	lda #$80
+	and pad1trig+1
+	bne +
+	lda #$10
+	and pad1trig+1
+	beq -
+	lda #$04
+	sta @MCU_CMD
+	jmp select_file_fade
++	jsr restore_screen
+	plp
+	rts
+
+scroll_direntry_clean:
+	lda #$01
+	sta direntry_xscroll_state
+	stz direntry_xscroll
+	stz direntry_xscroll_wait
+	jsr scroll_direntry
+	stz direntry_xscroll_state
+	stz direntry_xscroll
+	rts
+
+scroll_direntry:
+	ldy menu_sel
+	lda direntry_xscroll_state
+	bne +
+	lda direntry_fits, y
+	bne scroll_direntry_enter
+;	stz direntry_xscroll_state
+	rts
+scroll_direntry_enter
+	lda #$01
+	sta direntry_xscroll_state
+	stz direntry_xscroll_wait
++	lda direntry_xscroll_wait
+	beq +
+	dec direntry_xscroll_wait
+	rts
+
++	lda direntry_xscroll
+	bne scroll_direntry_scrollfast
+	lda #$28
+	bra +
+scroll_direntry_scrollfast
+	lda #$10
++	sta direntry_xscroll_wait
+	tya
+	clc
+	adc #$09
+	sta cursor_y
+	lda #$02
+	sta cursor_x
+	rep #$20 : .al
+	lda menu_sel
+	asl
+	asl
+	tay
+	lda [dirptr_addr], y
+	sta @dirent_addr
+	iny
+	iny
+	sep #$20 : .as
+	lda [dirptr_addr], y	   ; load fileinfo bank
+	clc
+	adc #$c0                   ; add $C0 for memory map
+	sta @dirent_bank           ; store as current bank
+	iny
+	lda [dirptr_addr], y
+	iny
+	sta @dirent_type
+	ldy menu_sel
+	sty direntry_fits_idx
+	phy
+	jsr print_direntry
+	ply
+	lda direntry_fits, y
+	bne +
+	lda #$ff
+	sta direntry_xscroll_state
+	lda #$28
+	sta direntry_xscroll_wait
++	lda direntry_xscroll_state
+	clc
+	adc direntry_xscroll
+	sta direntry_xscroll
+	bne +
+	lda #$01
+	sta direntry_xscroll_state
++	rts

snes/palette.a65

@@ -1,77 +1,64 @@
-palette
-;8bit palette; 4bit palette0; 2bit palette0
-        .byt  $42, $08, $ff, $7f, $c6, $18, $18, $63
-;2bit palette1
-        .byt  $42, $08, $ff, $43, $c6, $0c, $18, $63
-;2bit palette2
-        .byt  $42, $08, $f0, $43, $c0, $0c, $18, $63
-;2bit palette3
+palette .byt  $1f, $7c, $ff, $7f, $c6, $18, $18, $63
+        .byt  $00, $00, $ff, $43, $c6, $0c, $18, $33
+        .byt  $00, $00, $f0, $43, $c3, $0c, $0c, $33
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $00, $00, $ff, $43, $c6, $0c, $18, $33
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $00, $00, $f0, $43, $c3, $0c, $0c, $33
+        .byt  $40, $08, $60, $0c, $80, $10, $80, $0c
+        .byt  $80, $14, $a0, $14, $05, $21, $30, $42
+        .byt  $0f, $3e, $cd, $3d, $c1, $18, $52, $4a
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $d6, $5a, $6b, $2d, $39, $67, $7a, $6b
+        .byt  $ce, $39, $46, $29, $94, $52, $ad, $35
+        .byt  $a2, $14, $aa, $35, $c0, $18, $18, $63
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $e0, $1c, $a0, $18, $c3, $18, $29, $25
+        .byt  $4a, $29, $ff, $7f, $21, $04, $bd, $73
+        .byt  $fe, $7b, $e7, $18, $42, $08, $00, $00
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $a5, $14, $79, $7b, $e6, $1c, $63, $0c
+        .byt  $de, $7f, $bd, $7f, $08, $21, $8c, $31
+        .byt  $6a, $2d, $08, $25, $61, $29, $00, $21
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $c4, $45, $45, $5a, $a5, $6e, $e6, $7e
+        .byt  $c7, $10, $b4, $66, $82, $35, $27, $35
+        .byt  $8b, $3d, $66, $59, $85, $69, $6f, $76
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $83, $75, $37, $7f, $46, $45, $0a, $7a
+        .byt  $9b, $7f, $d2, $7a, $15, $7f, $c0, $3c
+        .byt  $08, $11, $21, $25, $86, $52, $0e, $25
+        .byt  $d9, $1c, $f1, $1c, $9e, $14, $ef, $1c
+        .byt  $ca, $18, $9d, $14, $36, $29, $d3, $72
+        .byt  $50, $5a, $81, $28, $cd, $49, $6a, $26
+        .byt  $c7, $15, $63, $25, $4f, $23, $ac, $1e
+        .byt  $05, $0d, $0e, $2b, $25, $0d, $c4, $08
+        .byt  $62, $04, $e7, $29, $b2, $18, $6c, $0c
+        .byt  $82, $04, $ce, $19, $31, $1a, $ff, $17
+        .byt  $dd, $1b, $7b, $1f, $4a, $11, $d6, $1a
+        .byt  $29, $73, $4d, $63, $50, $4f, $d3, $26
+        .byt  $b8, $37, $26, $08, $fe, $20, $94, $3f
+        .byt  $a3, $04, $10, $42, $10, $42, $10, $42
         .byt  $10, $42, $10, $42, $10, $42, $10, $42
-;4bit palette1; 2bit palette4
-        .byt  $42, $08, $ff, $43, $c6, $0c, $18, $63
-;2bit palette5
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $1f, $7c, $1f, $7c, $1f, $7c, $1f, $7c
+        .byt  $1f, $74, $00, $00, $08, $21, $8c, $31
+        .byt  $ce, $39, $bd, $77, $7b, $6f, $39, $67
+        .byt  $d6, $5a, $94, $52, $ff, $7f, $10, $42
+        .byt  $4a, $29, $84, $10, $c6, $18, $52, $4a
+        .byt  $1f, $74, $45, $11, $e3, $10, $a1, $0c
+        .byt  $e8, $19, $4f, $27, $0e, $23, $ed, $22
+        .byt  $2e, $23, $09, $1a, $cc, $22, $24, $11
         .byt  $10, $42, $10, $42, $10, $42, $10, $42
-;2bit palette6
-        .byt  $10, $42, $10, $42, $10, $42, $10, $42
-;2bit palette7
-        .byt  $10, $42, $10, $42, $10, $42, $10, $42
-;4bit palette2
-        .byt  $10, $42, $f0, $43, $c0, $0c, $18, $63
-;logo
-        .byt  $00, $00, $00, $00, $20, $04, $20, $00
-        .byt  $20, $00, $21, $00, $21, $08, $40, $08
-        .byt  $40, $04, $42, $04, $42, $0c, $60, $0c
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $62, $0c, $61, $0c, $62, $00, $63, $0c
-        .byt  $63, $10, $62, $08, $80, $10, $64, $0c
-        .byt  $a0, $14, $84, $10, $a2, $0c, $a4, $0c
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $a4, $10, $c0, $18, $a4, $14, $a6, $14
-        .byt  $a5, $14, $89, $14, $e0, $1c, $c5, $10
-        .byt  $c6, $18, $e3, $0c, $e5, $1c, $00, $21
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $04, $0d, $ca, $18, $04, $11, $e7, $1c
-        .byt  $20, $25, $21, $1d, $5d, $0c, $08, $15
-        .byt  $40, $29, $08, $21, $5e, $10, $5d, $10
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $cf, $20, $7b, $10, $7e, $14, $27, $25
-        .byt  $60, $31, $28, $25, $44, $29, $61, $29
-        .byt  $46, $29, $29, $25, $62, $2d, $f3, $1c
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $66, $15, $d6, $18, $63, $31, $d8, $18
-        .byt  $0e, $25, $80, $35, $48, $29, $bb, $18
-        .byt  $4a, $29, $66, $2d, $4b, $29, $a3, $2d
-        .byt  $a0, $39, $f6, $20, $6a, $15, $6a, $19
-        .byt  $32, $21, $a1, $39, $a1, $41, $31, $29
-        .byt  $4e, $31, $a2, $39, $c0, $3d, $6b, $2d
-        .byt  $8a, $31, $6d, $2d, $c8, $19, $00, $42
-        .byt  $8c, $31, $e3, $3d, $ac, $19, $e3, $45
-        .byt  $ad, $15, $e3, $49, $02, $42, $e6, $2d
-        .byt  $20, $42, $ad, $35, $24, $46, $24, $4e
-        .byt  $28, $2e, $42, $46, $ee, $39, $45, $4a
-        .byt  $2a, $16, $48, $2e, $0f, $1e, $46, $56
-        .byt  $64, $4a, $44, $5e, $0f, $3e, $64, $4e
-        .byt  $65, $5a, $83, $4e, $67, $4e, $30, $42
-        .byt  $86, $4e, $32, $46, $6d, $2e, $52, $1a
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $00, $00, $00, $00, $00, $00, $00, $00
-        .byt  $8b, $22, $a5, $56, $51, $46, $ab, $1a
-        .byt  $a5, $6a, $a5, $6e, $c1, $76, $c7, $5a
-        .byt  $93, $16, $e0, $7a, $72, $4a, $cc, $26
-        .byt  $b0, $2a, $93, $4e, $e5, $7e, $e8, $5e
-        .byt  $b5, $1e, $ed, $1e, $e6, $7e, $b5, $16
-        .byt  $95, $52, $b3, $56, $b5, $56, $0a, $63
-        .byt  $2d, $1b, $29, $67, $2f, $23, $f4, $2a
-        .byt  $d6, $5a, $17, $1b, $4a, $6b, $4d, $67
-        .byt  $f7, $5e, $f8, $62, $39, $1f, $18, $63
-        .byt  $6c, $73, $78, $23, $39, $67, $7b, $1b
-        .byt  $5a, $6b, $7b, $6f, $de, $17, $9c, $73
-        .byt  $bd, $77, $ff, $13, $de, $7b, $ff, $7f
-;sprite palette 7
-        .byt  $3f, $7c, $20, $08, $84, $0c, $a5, $14
-        .byt  $08, $21, $5a, $6b, $bc, $73, $fe, $7b
-        .byt  $f7, $5e, $73, $4e, $10, $42, $42, $08
-        .byt  $00, $00, $ad, $35, $b5, $56, $6b, $2d
-
+        .byt  $1f, $74, $df, $17, $47, $15, $c3, $0c
+        .byt  $0e, $12, $7b, $13, $b9, $33, $06, $7f
+        .byt  $2c, $63, $75, $3b, $72, $4f, $93, $16
+        .byt  $aa, $15, $24, $15, $17, $13, $50, $16
+        .byt  $1f, $74, $0e, $21, $54, $29, $a6, $14
+        .byt  $7e, $14, $5a, $2d, $10, $21, $0d, $25
+        .byt  $eb, $20, $9c, $14, $99, $14, $37, $29
+        .byt  $f6, $1c, $96, $14, $d3, $1c, $f1, $1c

snes/reset.a65

@@ -39,6 +39,8 @@ NMI_ROUTINE:
 	php
 	txa
 	dec
+	dec
+	dec
 	plp
 	bne small_bar
 	asl
@@ -82,9 +84,29 @@ math_cont
 	clc
 	adc bar_x	; + X start coord
 	sta $2127	; window 1 right
-	lda #$3e	; ch. 1-5
-	sta @$420c	; trigger HDMA
-	lda #$01
+;	lda #$3e	; ch. 1-5
+;	sta @$420c	; trigger HDMA
+
+	lda cur_bright
+	cmp tgt_bright
+	beq +
+	bpl bright_down
+bright_up
+	inc
+	sta cur_bright
+	lda $2100
+	and #$f0
+	ora cur_bright
+	sta $2100
+	bra +
+bright_down
+	dec
+	sta cur_bright
+	lda $2100
+	and #$f0
+	ora cur_bright
+	sta $2100
++	lda #$01
 	sta isr_done
         rtl
 

snes/spc700.a65

@@ -0,0 +1,61 @@
+; All SPC700 routines in SPC700 machine code
+; SPC loader & transfer routines by Shay Green <gblargg@gmail.com>
+
+loader				; .org $0002
+	.byt $F8,$21		;	mov x,@loader_data
+	.byt $BD		;	mov sp,x
+	.byt $CD,$22		;	mov x,#@loader_data+1
+
+	; Push PC and PSW from SPC header
+	.byt $BF		;	mov a,(x)+
+	.byt $2D		;	push a
+	.byt $BF		;	mov a,(x)+
+	.byt $2D		;	push a
+	.byt $BF		;	mov a,(x)+
+	.byt $2D		;	push a
+
+	; Set FLG to $60 rather than value from SPC
+	.byt $E8,$60		;	mov a,#$60
+	.byt $D4,$6C		;	mov FLG+x,a
+
+	; Restore DSP registers
+	.byt $8D,$00		;	mov y,#0
+	.byt $BF		; next:	mov a,(x)+
+	.byt $CB,$F2		;	mov $F2,y
+	.byt $C4,$F3		;	mov $F3,a
+	.byt $FC		;	inc y
+	.byt $10,-8		;	bpl next
+
+	.byt $8F,$6C,$F2	;	mov $F2,#FLG	; set for later
+
+	; Rerun loader
+	.byt $5F,$C0,$FF	;	jmp $FFC0
+
+;---------------------------------------
+
+transfer			; .org $0002
+
+	.byt $CD,$FE		; mov x,#$FE		; transfer 254 pages
+
+	; Transfer four-byte chunks
+	.byt $8D,$3F		; page: mov y,#$3F
+	.byt $E4,$F4		; quad: mov a,$F4
+	.byt $D6,$00,$02	; mov0: mov !$0200+y,a
+	.byt $E4,$F5		;	mov a,$F5
+	.byt $D6,$40,$02	; mov1: mov !$0240+y,a
+	.byt $E4,$F6		;	mov a,$F6
+	.byt $D6,$80,$02	; mov2: mov !$0280+y,a
+	.byt $E4,$F7		;	mov a,$F7	; tell S-CPU we're ready for more
+	.byt $CB,$F7		;	mov $F7,Y
+	.byt $D6,$C0,$02	; mov3: mov !$02C0+y,a
+	.byt $DC 		;	dec y
+	.byt $10,-25		;	bpl quad
+	; Increment MSBs of addresses
+	.byt $AB,$0A		;	inc mov0+2
+	.byt $AB,$0F		;	inc mov1+2
+	.byt $AB,$14		;	inc mov2+2
+	.byt $AB,$1B		;	inc mov3+2
+	.byt $1D    		;	dec x
+	.byt $D0,-38		;	bne page
+	; Rerun loader
+	.byt $5F,$C0,$FF	;	jmp $FFC0

snes/spcplay.a65

@@ -0,0 +1,656 @@
+#include "memmap.i65"
+
+; SPC Player
+; SPC700 transfer and IO routines by Shay Green <gblargg@gmail.com>
+
+spcplayer:
+	php
+	sep #$30 : .as : .xs
+
+	ldx #$0a	; Check if SPC header is present
+-
+	lda @SPC_HEADER,x
+	cmp @text_spcid,x
+	beq +
+	jmp spc_exit
++
+	dey
+	bne -
+
+	rep #$10 : .xl	; Now draw lots of stuff
+
+	stz bar_wl
+	dec bar_wl
+	stz bar_xl
+	dec bar_xl
+	stz bar_yl
+	dec bar_yl
+	jsr backup_screen
+
+	lda #^text_spcplay	; Loading window
+	sta window_tbank
+	ldx #!text_spcplay
+	stx window_taddr
+	lda @spcplay_win_x
+	sta window_x
+	lda @spcplay_win_y
+	sta window_y
+	lda @spcplay_win_w
+	sta window_w
+	lda @spcplay_win_h
+	sta window_h
+	jsr draw_window
+
+	lda #^text_spcload	; Loading text
+	ldx #!text_spcload
+	sta print_bank
+	stx print_src
+	stz print_pal
+	lda #29
+	sta print_count
+	lda #17
+	sta print_y
+	lda #17
+	sta print_x
+	jsr hiprint
+
+	stz isr_done
+-
+	lda isr_done		; Wait until text is being printed...
+	beq -
+
+	jsr spc700_load		; Load SPC into SPC700
+
+	lda #^text_spcplay
+	sta window_tbank
+	ldx #!text_spcplay
+	stx window_taddr
+	lda @spcstart_win_x
+	sta window_x
+	lda @spcstart_win_y
+	sta window_y
+	lda @spcstart_win_w
+	sta window_w
+	lda @spcstart_win_h
+	sta window_h
+	jsr draw_window
+
+	lda #^text_spcstarta
+	ldx #!text_spcstarta
+	sta print_bank
+	stx print_src
+	lda #$01
+	sta print_pal
+	lda #30
+	sta print_count
+	lda #15
+	sta print_y
+	lda #17
+	sta print_x
+	jsr hiprint
+
+	lda #^text_spcstartb
+	ldx #!text_spcstartb
+	sta print_bank
+	stx print_src
+	lda #$01
+	sta print_pal
+	lda #07
+	sta print_count
+	lda #17
+	sta print_y
+	lda #12
+	sta print_x
+	jsr hiprint
+
+	lda #$fe
+	ldx #$004e
+	sta print_bank
+	stx print_src
+	stz print_pal
+	lda #32
+	sta print_count
+	lda #17
+	sta print_y
+	lda #20
+	sta print_x
+	jsr hiprint
+
+	lda #^text_spcstartc
+	ldx #!text_spcstartc
+	sta print_bank
+	stx print_src
+	lda #$01
+	sta print_pal
+	lda #07
+	sta print_count
+	lda #18
+	sta print_y
+	lda #12
+	sta print_x
+	jsr hiprint
+
+	lda #$fe
+	ldx #$002e
+	sta print_bank
+	stx print_src
+	stz print_pal
+	lda #32
+	sta print_count
+	lda #18
+	sta print_y
+	lda #20
+	sta print_x
+	jsr hiprint
+
+	lda #^text_spcstartd
+	ldx #!text_spcstartd
+	sta print_bank
+	stx print_src
+	lda #$01
+	sta print_pal
+	lda #07
+	sta print_count
+	lda #19
+	sta print_y
+	lda #12
+	sta print_x
+	jsr hiprint
+
+	lda #$fe
+	ldx #$00b0
+        sta longptr+2
+	sta print_bank
+        stx longptr
+        ldy #$00
+        lda [longptr], y
+        cmp #$41
+        bpl +
+        inx
++	stx print_src
+	stz print_pal
+	lda #32
+	sta print_count
+	lda #19
+	sta print_y
+	lda #20
+	sta print_x
+	jsr hiprint
+
+spc_playloop:
+	lda isr_done	; SPC player loop
+	lsr
+	bcc spc_playloop
+	jsr printtime
+	stz isr_done
+
+	jsr read_pad
+	lda #$80
+	and pad1trig+1
+	bne spc_key_b
+	bra spc_playloop
+
+spc_key_b:
+	rep #$20 : .al
+	tsc
+	sta saved_sp	; Save SP for later re-entry
+	lda #$fa50	; Write reset signature
+	sta @warm_signature
+	sep #$20 : .as
+
+	sei		; Blank screen & issue CMD_RESET command to Microcontroller...
+	stz $2100	; ...this is required, because there is no other way to stop S-SMP & S-DSP
+	lda #CMD_RESET
+	sta @MCU_CMD
+-
+	bra -		; At this point, the SNES waits for an external reset from the Microcontroller
+
+spc_exit:		; Return from player in case of wrong SPC file data
+	plp
+	rts
+
+;---------------------------------------
+spc700_load:
+	php
+	sep #$20 : .as
+	rep #$10 : .xl
+
+	sei			; Disable NMI & IRQ
+	stz $4200		; The SPC player code is really timing sensitive ;)
+	jsr upload_dsp_regs	; Upload S-DSP registers
+	jsr upload_high_ram	; Upload 63.5K of SPC700 ram
+	jsr upload_low_ram	; Upload rest of ram
+	jsr restore_final	; Restore SPC700 state & start execution
+
+	lda #$81		; VBlank NMI + Auto Joypad Read
+	sta $4200		; enable V-BLANK NMI
+	cli
+	plp
+	rts
+;---------------------------------------
+; Uploads DSP registers and some other setup code
+upload_dsp_regs:
+
+; ---- Begin upload
+
+	ldy #$0002
+	jsr spc_begin_upload
+
+; ---- Upload loader
+
+	ldx #$0000
+-
+	lda @loader,x
+	jsr spc_upload_byte
+	inx
+	cpy #31		; size of loader
+	bne -
+
+; ---- Upload SP, PC & PSW
+
+	lda @SPC_HEADER+43
+	jsr spc_upload_byte
+	lda @SPC_HEADER+38
+	jsr spc_upload_byte
+	lda @SPC_HEADER+37
+	jsr spc_upload_byte
+	lda @SPC_HEADER+42
+	jsr spc_upload_byte
+
+; ---- Upload DSP registers
+
+	ldx #$0000
+-
+	lda @SPC_DSP_REGS,x
+	jsr spc_upload_byte
+	inx
+	cpx #128
+	bne -
+
+; --- Upload fixed values for $F1-$F3
+
+	ldy #$00F1
+	jsr spc_next_upload
+
+	lda #$80        ; stop timers
+	jsr spc_upload_byte
+	lda #$6c        ; get dspaddr set for later
+	jsr spc_upload_byte
+	lda #$60
+	jsr spc_upload_byte
+
+; ---- Upload $f8-$1ff
+
+	ldy #$00F8
+	jsr spc_next_upload
+
+	ldx #$00F8
+-
+	lda @SPC_DATA,x
+	jsr spc_upload_byte
+	inx
+	cpx #$200
+	bne -
+
+; ---- Execute loader
+
+	ldy #$0002
+	jsr spc_execute
+	rts
+;---------------------------------------
+upload_high_ram:
+
+	ldy #$0002
+	jsr spc_begin_upload
+
+; ---- Upload transfer routine
+
+	ldx #$0000
+-
+	lda @transfer,x
+	jsr spc_upload_byte
+	inx
+	cpy #43		; size of transfer routine
+	bne -
+
+	ldx #$023f	; prepare transfer address
+
+; ---- Execute transfer routine
+
+	ldy #$0002
+	sty APUIO2
+	stz APUIO1
+	lda APUIO0
+	inc
+	inc
+	sta APUIO0
+; Wait for acknowledgement
+-
+	cmp APUIO0
+	bne -
+
+; ---- Burst transfer of 63.5K using custom routine
+
+outer_transfer_loop:
+	ldy #$003f		; 3
+inner_transfer_loop:
+	lda @SPC_DATA,x		; 5 |
+	sta APUIO0		; 4 |
+	lda @SPC_DATA+$40,x	; 5 |
+	sta APUIO1		; 4 |
+	lda @SPC_DATA+$80,x	; 5 |
+	sta APUIO2		; 4 |
+	lda @SPC_DATA+$C0,x	; 5 |
+	sta APUIO3		; 4 |
+	tya			; 2 >> 38 cycles
+-
+	cmp APUIO3		; 4 |
+	bne -			; 3 |
+	dex			; 2 |
+	dey			; 2 |
+	bpl inner_transfer_loop	; 3 >> 14 cycles
+
+	rep #$21 : .al		; 3 |
+	txa			; 2 |
+	adc #$140		; 3 |
+	tax			; 2 |
+	sep #$20 : .as		; 3 |
+	cpx #$003f		; 3 |
+	bne outer_transfer_loop	; 3 >> 19 cycles
+
+	rts
+
+;---------------------------------------
+upload_low_ram:
+
+; ---- Upload $0002-$00EF using IPL
+
+	ldy #$0002
+	jsr spc_begin_upload
+
+	ldx #$0002
+-
+	lda @SPC_DATA,x
+	jsr spc_upload_byte
+	inx
+	cpx #$00F0
+	bne -
+	rts
+;---------------------------------------
+; Executes final restoration code
+restore_final:
+	jsr start_exec_io ; prepare execution from I/O registers
+
+	stz $420d	; SPC700 I/O code requires SLOW timing
+
+; ---- Restore first two bytes of RAM
+
+	lda @SPC_DATA
+	xba
+	lda #$e8	; MOV A,#@SPC_DATA
+	tax
+	jsr exec_instr
+	ldx #$00C4	; MOV $00,A
+	jsr exec_instr
+
+	lda @SPC_DATA+1
+	xba
+	lda #$e8	; MOV A,#@SPC_DATA+1
+	tax
+	jsr exec_instr
+	ldx #$01C4	; MOV $01,A
+	jsr exec_instr
+
+; ---- Restore SP
+
+	lda @SPC_HEADER+43
+	sec
+	sbc #3
+	xba
+	lda #$cd	; MOV X,#@SPC_HEADER+43
+	tax
+	jsr exec_instr
+	ldx #$bd	; MOV SP,X
+	jsr exec_instr
+
+; ---- Restore X
+
+	lda @SPC_HEADER+40
+	xba
+	lda #$cd	; MOV X,#@SPC_HEADER+40
+	tax
+	jsr exec_instr
+
+; ---- Restore Y
+
+	lda @SPC_HEADER+41
+	xba
+	lda #$8d	; MOV Y,#@SPC_HEADER+41
+	tax
+	jsr exec_instr
+
+; ---- Restore DSP FLG register
+
+	lda @SPC_DSP_REGS+$6c
+	xba
+	lda #$e8	; MOV A,#@SPC_DSP_REGS+$6c
+	tax
+	jsr exec_instr
+	ldx #$f3C4	; MOV $f3,A -> $f2 has been set-up before by SPC700 loader
+	jsr exec_instr
+
+; ---- Restore DSP KON register
+
+	lda #$4C
+	xba
+	lda #$e8	; MOV A,#$4c
+	tax
+	jsr exec_instr
+	ldx #$f2C4	; MOV $f2,A
+	jsr exec_instr
+	lda @SPC_DSP_REGS+$4C
+	xba
+	lda #$e8	; MOV A,#@SPC_DSP_REGS+$4c
+	tax
+	jsr exec_instr
+	ldx #$f3C4	; MOV $f3,A
+	jsr exec_instr
+
+; ---- Restore DSP register address
+
+ 	lda @SPC_DATA+$F2
+	xba
+	lda #$e8	; MOV A,#@SPC_DATA+$F2
+	tax
+	jsr exec_instr
+	ldx #$f2C4	; MOV dest,A
+	jsr exec_instr
+
+; ---- Restore CONTROL register
+
+	lda @SPC_DATA+$F1
+	and #$CF	; don't clear input ports
+	xba
+	lda #$e8	; MOV A,#@SPC_DATA+$F1
+	tax
+	jsr exec_instr
+	ldx #$f1C4  	; MOV $F1,A
+	jsr exec_instr
+
+;---- Restore A
+
+	lda @SPC_HEADER+39
+	xba
+	lda #$e8	; MOV A,#@SPC_HEADER+39
+	tax
+	jsr exec_instr
+
+;---- Restore PSW and PC
+
+	ldx #$7F00	; NOP; RTI
+	stx APUIO0
+	lda #$FC	; Patch loop to execute instruction just written
+	sta APUIO3
+
+;---- restore IO ports $f4 - $f7
+
+	rep #$20 : .al
+	lda @SPC_DATA+$F4
+	tax
+	lda @SPC_DATA+$F6
+	sta APUIO2
+	stx APUIO0	; last to avoid overwriting RETI before run
+	sep #$20 : .as
+
+	lda #$01
+	sta $420d	; restore FAST CPU operation
+	rts
+;---------------------------------------
+spc_begin_upload:
+
+	sty APUIO2	; Set address
+
+	ldy #$BBAA	; Wait for SPC
+-
+	cpy APUIO0
+	bne -
+
+	lda #$CC	; Send acknowledgement
+	sta APUIO1
+	sta APUIO0
+
+-       		; Wait for acknowledgement
+	cmp APUIO0
+	bne -
+
+	ldy #0		; Initialize index
+	rts
+;---------------------------------------
+spc_upload_byte:
+	sta APUIO1
+
+	tya		; Signal it's ready
+	sta APUIO0
+-     			; Wait for acknowledgement
+	cmp APUIO0
+	bne -
+
+	iny
+
+	rts
+;---------------------------------------
+spc_next_upload:
+	sty APUIO2
+
+; Send command
+; Special case operation has been fully tested.
+	lda APUIO0
+	inc
+	inc
+	bne +
+	inc
++
+	sta APUIO1
+	sta APUIO0
+
+; Wait for acknowledgement
+-
+	cmp APUIO0
+	bne -
+
+	ldy #0
+	rts
+;---------------------------------------
+spc_execute:
+	sty APUIO2
+
+	stz APUIO1
+
+	lda APUIO0
+	inc
+	inc
+	sta APUIO0
+
+; Wait for acknowledgement
+-
+	cmp APUIO0
+	bne -
+
+	rts
+;---------------------------------------
+start_exec_io:
+; Set execution address
+	ldx #$00F5
+	stx APUIO2
+
+	stz APUIO1      ; NOP
+	ldx #$FE2F      ; BRA *-2
+
+; Signal to SPC that we're ready
+	lda APUIO0
+	inc
+	inc
+	sta APUIO0
+
+; Wait for acknowledgement
+-
+	cmp APUIO0
+	bne -
+
+; Quickly write branch
+	stx APUIO2
+
+	rts
+;---------------------------------------
+exec_instr:
+; Replace instruction
+	stx APUIO0
+	lda #$FC
+	sta APUIO3      ; 30
+
+        ; SPC BRA loop takes 4 cycles, so it reads
+        ; the branch offset every 4 SPC cycles (84 master).
+        ; We must handle the case where it read just before
+        ; the write above, and when it reads just after it.
+        ; If it reads just after, we have at least 7 SPC
+        ; cycles (147 master) to change restore the branch
+        ; offset.
+
+        ; 48 minimum, 90 maximum
+        ora #0
+        ora #0
+        ora #0
+        nop
+        nop
+        nop
+
+        ; 66 delay, about the middle of the above limits
+	phd ;4
+	pld ;5
+
+        ; Give plenty of extra time if single execution
+        ; isn't needed, as this avoids such tight timing
+        ; requirements.
+
+;	phd ;4
+;	pld ;5
+;	phd ;4
+;	pld ;5
+
+        ; Patch loop to skip first two bytes
+	lda #$FE        ; 16
+	sta APUIO3      ; 30
+
+        ; 38 minimum (assuming 66 delay above)
+	phd ; 4
+	pld ; 5
+
+        ; Give plenty of extra time if single execution
+        ; isn't needed, as this avoids such tight timing
+        ; requirements.
+
+	phd
+	pld
+	phd
+	pld
+	rts

snes/sysinfo.a65

@@ -0,0 +1,134 @@
+#include "memmap.i65"
+
+; sysinfo.a65: display sysinfo text block
+.byt "===SHOW_SYSINFO==="
+show_sysinfo:
+	php
+	sep #$20 : .as
+	rep #$10 : .xl
+	stz bar_wl
+	dec bar_wl
+	stz bar_xl
+	dec bar_xl
+	stz bar_yl
+	dec bar_yl
+	jsr backup_screen
+	lda #^text_mm_sysinfo
+	sta window_tbank
+	ldx #!text_mm_sysinfo
+	stx window_taddr
+	lda @sysinfo_win_x
+	sta window_x
+	inc
+	inc
+	pha
+	stz print_x+1
+	lda @sysinfo_win_y
+	sta window_y
+	inc
+	inc
+	pha
+	stz print_y+1
+	lda @sysinfo_win_w
+	sta window_w
+	lda @sysinfo_win_h
+	sta window_h
+	jsr draw_window
+	stz print_pal
+	
+	ldx #38
+copy_snes_system_text:
+	lda @text_system,x
+	sta @snes_system_config,x
+	dex
+	bpl copy_snes_system_text
+	
+sysinfo_printloop:
+	sep #$20 : .as
+	rep #$10 : .xl
+	lda #CMD_SYSINFO
+	sta @MCU_CMD
+	lda #^SYSINFO_BLK
+	ldx #!SYSINFO_BLK
+	sta print_bank
+	stx print_src
+	stz print_pal
+	pla
+	sta print_y
+	pla
+	sta print_x
+	lda #40
+	sta print_count
+	lda #12
+-	pha
+	jsr hiprint
+	inc print_y
+	rep #$20 : .al
+	lda print_src
+	clc
+	adc #40
+	sta print_src
+	sep #$20 : .as
+	pla
+	dec
+	bne -
+	
+	ldx #24
+	lda $213e
+	and #$0f
+	clc
+	adc #$30
+	sta @snes_system_config,x
+	
+	ldx #38
+	lda $213f
+	and #$0f
+	clc
+	adc #$30
+	sta @snes_system_config,x
+	
+	ldx #10
+	lda $4210
+	and #$0f
+	clc
+	adc #$30
+	sta @snes_system_config,x		
+	
+	lda #^snes_system_config		; System text
+	ldx #!snes_system_config
+	sta print_bank
+	stx print_src
+	stz print_pal
+	lda #39
+	sta print_count
+	lda #23
+	sta print_y
+	lda #12
+	sta print_x
+	jsr hiprint		
+	
+-	lda isr_done
+	lsr
+	bcc -
+	jsr printtime
+	jsr read_pad
+	lda #$80
+	and pad1trig
+	bne +
+	lda #$80
+	and pad1trig+1
+	bne +
+	lda @sysinfo_win_x
+	inc
+	inc
+	pha
+	lda @sysinfo_win_y
+	inc
+	inc
+	pha
+	jmp sysinfo_printloop
++	plp
+	jsr restore_screen
+	lda #$00
+	sta @MCU_CMD
+	rtl

snes/tests/Makefile

@@ -0,0 +1,17 @@
+OBJS = header.ips reset.o65 tests.o65
+
+all: test.bin
+
+test.bin: $(OBJS)
+	sneslink -fsmc -o $@ $^
+
+# Generic rule to create .o65 out from .a65
+%.o65: %.a65
+	snescom -J -Wall -o $@ $<
+
+# Generic rule to create .ips out from .a65
+%.ips: %.a65
+	snescom -I -J -Wall -o $@ $<
+
+clean:
+	rm -f *.ips *.o65 *~ test.bin

snes/tests/header.a65

@@ -0,0 +1,121 @@
+; This file is part of the snescom-asm demo - a demo of how to build a SNES program.
+; See http://bisqwit.iki.fi/source/snescom.html for details.
+
+; Begin assembling to this address.
+*= $C0F000
+LINETEST:
+	sei
+	clc
+	xce
+-	lda $0000
+	lda $2100
+	sta $2100
+	bra -
+
+*= $C0F100
+IRQTEST:
+	sei
+	clc
+	xce
+	cli
+	sep #$20 : .as
+	rep #$10 : .xl
+	lda #$0f
+	sta $2100
+	lda #$ff
+	sta $4209
+	lda #$ff
+	sta $420a
+	lda #$ff
+	sta $4200
+	lda #$01
+-	sta @$002222
+	bra -
+
+*= $C0F200
+BANKTEST:
+	sei
+	clc
+	xce
+	sep #$20 : .as
+	lda #$01
+	sta @$0055aa
+-	bra -
+
+*= $C0FF00
+
+RESET:
+        sei
+        clc
+        xce
+        rep #$20 : .al
+        lda #$1fff
+        tcs
+	lda #$00
+	sta @$003333
+        jmp @GAME_MAIN
+
+NMI_16bit:
+        php
+         rep #$30 : .al : .xl
+         pha: phx: phy: phd: phb
+         jsl @NMI_ROUTINE
+         rep #$30 : .al : .xl
+int_exit:
+         plb: pld: ply: plx: pla
+        plp
+        rti
+
+IRQ_16bit:
+ABT_8bit: ABT_16bit:
+        php
+         rep #$30 : .al : .xl
+         pha: phx: phy: phd: phb
+         jsl @IRQ_ROUTINE
+	 rep #$30 : .al : .xl
+         bra int_exit
+
+;error vectors
+BRK_8bit: BRK_16bit:
+COP_8bit: COP_16bit:
+IRQ_8bit:
+NMI_8bit:
+        - wai: lda $ABCDEF : bra -
+
+*= $C0FFB0
+        ; Zero the area from $FFB0 - $FFFF
+        ; to ensure that the linker won't get clever
+        ; and fill it with small pieces of code.
+        .word 0,0,0,0, 0,0,0,0
+        .word 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0
+        .word 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0
+
+*= $C0FFB0
+
+.byt "MR"         ;2 bytes - company id
+.byt "TEST"       ;4 bytes - rom id
+
+*= $C0FFC0
+.byt "SD2SNES TESTS        "
+     ;123456789012345678901; - max 21 chars
+
+*= $C0FFD5     .byt $31  ;rom speed
+*= $C0FFD6     .byt $02  ;rom type
+*= $C0FFD7     .byt $06  ;rom size   64 kByte
+*= $C0FFD8     .byt $03  ;sram size  8 kBit
+*= $C0FFD9     .byt $09  ;rom region 4 = Finland
+*= $C0FFDA     .byt $33  ;company id flag
+
+*= $C0FFDC     .word 0,0 ;checksums
+
+*= $C0FFE4     .word COP_16bit
+*= $C0FFE6     .word BRK_16bit
+*= $C0FFE8     .word ABT_16bit
+*= $C0FFEA     .word NMI_16bit
+*= $C0FFEE     .word IRQ_16bit
+*= $C0FFF4     .word COP_8bit
+*= $C0FFF8     .word ABT_8bit
+*= $C0FFFA     .word NMI_8bit
+*= $C0FFFC     .word RESET
+*= $C0FFFE     .word BRK_8bit
+*= $C0FFFE     .word IRQ_8bit

snes/tests/reset.a65

@@ -0,0 +1,29 @@
+; This file is part of the snescom-asm demo - a demo of how to build a SNES program.
+; See http://bisqwit.iki.fi/source/snescom.html for details.
+
+; NMI - called on VBlank
+NMI_ROUTINE:
+        sep #$20 : .as
+	rep #$10 : .xl
+	lda #$00
+	pha
+	plb
+
+	lda $4210	; ack interrupt
+
+        rtl
+
+; IRQ - called when triggered
+IRQ_ROUTINE:
+        sep #$20 : .as
+        lda $4211  ;Acknowledge irq
+	lda #$00
+	sta @$002121
+	lda #$ff
+	sta @$002122
+	lda #$01
+	sta @$002122
+	lda #$5A
+	sta @$F00000
+	rtl
+

snes/tests/tests.a65

@@ -0,0 +1,564 @@
+GAME_MAIN:
+	sep #$20 : .as
+	stz $4200 ; inhibit VBlank NMI
+	lda #$01
+	sta $420d ; fast cpu
+	jsr killdma
+	jsr waitblank
+	lda #$00
+	sta @$f00000
+	sta @$f00001
+	sta @$f00002
+	sta @$f00003
+	lda #$00
+	sta @$f01fff
+	jsr snes_init
+	jsr video_init
+	jsr linetest
+	jsr batest
+	jsr snes_init
+	jsr video_init
+	jsr copy_memtest
+	jsr irqtest
+	jsl $7e1800
+-	bra -
+
+copy_memtest:
+	rep #$30 : .al : .xl
+	lda #$0300
+	ldx #!memtest
+	ldy #$1800
+	mvn $7e, ^memtest
+	rts
+
+linetest
+	sep #$20 : .as
+	lda #$00
+	pha
+	plb
+-	lda $0000
+        lda $2100
+        sta $21ff
+	lda @$f01fff
+	cmp #$01
+	bne -
+	rts
+
+irqtest:
+	cli
+	sep #$20 : .as
+	rep #$10 : .xl
+	lda #$0f
+	sta $2100
+	lda #$ff
+	sta $4209
+	lda #$ff
+	sta $420a
+	lda #$ff
+	sta $4200
+	sta @$f00000
+	lda #$01
+	sta @$002222
+	rts
+
+batest:
+	sei
+	sep #$20 : .as
+	rep #$10 : .xl
+	lda #$00
+	ldx #$2100
+-	sta !$0, x
+	inx
+	inc
+	bne -
+	lda #$e0
+	pha
+	plb
+	lda #$00
+	ldx #$0000
+-	cmp !$0, x
+	bne batest_fail
+	inx
+	inc
+	bne -
+	lda #$5a
+	sta @$f00002
+	lda #$00
+	pha
+	plb
+	rts
+batest_fail:
+	lda #$ff
+	sta @$f00002
+	lda #$00
+	pha
+	plb
+	rts
+
+memtest:
+; test 4 areas: 00-3f:8000-ffff
+;               40-7d:0000-ffff
+;               80-bf:8000-ffff
+;               80-ff:0000-ffff
+	sep #$20 : .as
+	rep #$10 : .xl
+
+	lda #$01
+	sta @$003333 ; switch to linear memory mode
+	ldx #$8000
+	stx $00
+	ldx #$8000
+	stx $10
+	lda #$00
+	sta $03 ; bank no.
+mem0_writeloop0:
+; switch bank
+	pha
+	plb
+	lda #$01
+	sta @$003333
+-       lda $03
+	clc
+	adc $01
+	clc
+	adc $00
+	sta !$0000, x
+	inx
+	stx $00
+	bne -
+	ldx $10
+	inc $03
+	lda #$00
+	sta @$003333
+	lda $03
+	sta @$f00003
+	cmp #$40
+	bne mem0_writeloop0
+
+	ldx #$0000
+	stx $10
+mem0_writeloop1:
+; switch bank
+        lda #$01
+        sta @$003333
+	lda $03
+	pha
+	plb
+-	lda $03
+	clc
+	adc $01
+	clc
+	adc $00
+	sta !$0000, x
+	inx
+	stx $00
+	bne -
+	ldx $10
+	inc $03
+	lda #$00
+	sta @$003333
+	lda $03
+	sta @$f00003
+	cmp #$7e
+	bne mem0_writeloop1
+
+	ldx #$8000
+	stx $10
+	lda #$80
+	sta $03 ; bank no.
+mem0_writeloop2:
+; switch bank
+        lda #$01
+        sta @$003333
+	lda $03
+	pha
+	plb
+-	lda $03
+	clc
+	adc $01
+	clc
+	adc $00
+	sta !$0000, x
+	inx
+	stx $00
+	bne -
+	ldx $10
+	inc $03
+	lda #$00
+	sta @$003333
+	lda $03
+	sta @$f00003
+	cmp #$c0
+	bne mem0_writeloop2
+	ldx #$0000
+	stx $10
+mem0_writeloop3:
+; switch bank
+        lda #$01
+        sta @$003333
+	lda $03
+	pha
+	plb
+-	lda $03
+	clc
+	adc $01
+	clc
+	adc $00
+	sta !$0000, x
+	inx
+	stx $00
+	bne -
+	ldx $10
+	inc $03
+	lda #$00
+	sta @$003333
+	lda $03
+	sta @$f00003
+	bne mem0_writeloop3
+
+	lda #$00
+	sta @$002121
+	lda #$ff
+	sta @$002122
+	lda #$03
+	sta @$002122
+
+	ldx #$8000
+	stx $00
+	ldx #$8000
+	stx $10
+	lda #$00
+	sta $03 ; bank no.
+mem0_verifyloop0:
+; switch bank
+        lda #$01
+        sta @$f00001
+        lda #$01
+        sta @$003333
+	lda $03
+	pha
+	plb
+-	lda $03
+	clc
+	adc $01
+	clc
+	adc $00
+	cmp !$0000, x
+	bne mem0_fail
+	inx
+	stx $00
+	bne -
+	ldx $10
+	inc $03
+	lda #$00
+	sta @$003333
+	lda $03
+	sta @$f00003
+	cmp #$40
+	bne mem0_verifyloop0
+
+	ldx #$0000
+	stx $10
+mem0_verifyloop1:
+; switch bank
+        lda #$01
+        sta @$003333
+	lda $03
+	pha
+	plb
+-	lda $03
+	clc
+	adc $01
+	clc
+	adc $00
+	cmp !$0000, x
+	bne mem0_fail
+	inx
+	stx $00
+	bne -
+	ldx $10
+	inc $03
+	lda #$00
+	sta @$003333
+	lda $03
+	sta @$f00003
+	cmp #$7e
+	bne mem0_verifyloop1
+
+	ldx #$8000
+	stx $10
+	lda #$80
+	sta $03 ; bank no.
+        bra mem0_verifyloop2
+mem0_fail:
+	lda #$00
+	pha
+	plb
+	sta @$003333
+	rep #$20 : .al
+	lda $00
+	sta @$f00004
+	sep #$20 : .as
+	lda $03
+	sta @$f00006
+	lda #$ff
+	sta @$f00001
+	rtl
+mem0_verifyloop2:
+; switch bank
+        lda #$01
+        sta @$003333
+	lda $03
+	pha
+	plb
+-	lda $03
+	clc
+	adc $01
+	clc
+	adc $00
+	cmp !$0000, x
+	bne mem0_fail
+	inx
+	stx $00
+	bne -
+	ldx $10
+	inc $03
+	lda #$00
+	sta @$003333
+	lda $03
+	sta @$f00003
+	cmp #$c0
+	bne mem0_verifyloop2
+
+	ldx #$0000
+	stx $10
+mem0_verifyloop3:
+; switch bank
+        lda #$01
+        sta @$003333
+	lda $03
+	pha
+	plb
+-	lda $03
+	clc
+	adc $01
+	clc
+	adc $00
+	cmp !$0000, x
+	bne mem0_fail
+	inx
+	stx $00
+	bne -
+	ldx $10
+	inc $03
+	lda #$00
+	sta @$003333
+	lda $03
+	sta @$f00003
+	bne mem0_verifyloop3
+
+	lda #$00
+	sta @$002121
+	lda #$e0
+	sta @$002122
+	lda #$03
+	sta @$002122
+
+	lda #$00
+	pha
+	plb
+	sta @$003333
+	lda #$5a
+	sta @$f00001
+	rtl
+	rtl
+	rtl
+	rtl
+	rtl
+	rtl
+
+killdma:
+	stz $420b
+	stz $420c
+	stz $4310
+	stz $4311
+	stz $4312
+	stz $4313
+	stz $4314
+	stz $4320
+	stz $4321
+	stz $4322
+	stz $4323
+	stz $4324
+	stz $4330
+	stz $4331
+	stz $4332
+	stz $4333
+	stz $4334
+	stz $4340
+	stz $4341
+	stz $4342
+	stz $4343
+	stz $4344
+	stz $4350
+	stz $4351
+	stz $4352
+	stz $4353
+	stz $4354
+	stz $4360
+	stz $4361
+	stz $4362
+	stz $4363
+	stz $4364
+	rts
+
+
+
+
+waitblank:
+-	lda $4212
+	and #$80
+	bne -
+-	lda $4212
+	and #$80
+	beq -
+	rts
+
+video_init:
+	sep #$20 : .as		;8-bit accumulator
+	rep #$10 : .xl		;16-bit index
+	lda #$03		;mode 3, mode 5 via HDMA :D
+	sta $2105
+	lda #$58		;Tilemap addr 0xB000
+	ora #$02		;SC size 32x64
+	sta $2107		;for BG1
+	lda #$50		;Tilemap addr 0xA000
+	ora #$02		;SC size 32x64
+	sta $2108		;for BG2
+	lda #$40		;chr base addr:
+	sta $210b		;BG1=0x0000, BG2=0x8000
+	lda #$01		;cut off leftmost subscreen pixel garbage
+	sta $2126
+	lda #$fe
+	sta $2127
+	lda #$10
+	sta $2130
+	lda #$1f
+	sta $212e
+	sta $212f
+	stz $2121
+	lda #$0f
+	sta $2100		;screen on, full brightness
+	stz $2121
+	lda #$1f		;red background
+	sta $2122
+	stz $2122
+	rts
+
+snes_init:
+	sep #$20 : .as		;8-bit accumulator
+	rep #$10 : .xl		;16-bit index
+	stz $4200		;
+	lda #$ff
+	sta $4201		;
+	stz $4202		;
+	stz $4203		;
+	stz $4204		;
+	stz $4205		;
+	stz $4206		;
+	stz $4207		;
+	stz $4208		;
+	stz $4209		;
+	stz $420a		;
+	stz $420b		;
+	stz $420c		;
+	lda #$8f
+	sta $2100		;INIDISP: force blank
+	lda #$03		; 8x8+16x16; name=0; base=3
+	sta $2101		;
+	stz $2102		;
+	stz $2103		;
+;	stz $2104		; (OAM Data?!)
+;	stz $2104		; (OAM Data?!)
+	stz $2105		;
+	stz $2106		;
+	stz $2107		;
+	stz $2108		;
+	stz $2109		;
+	stz $210a		;
+	stz $210b		;
+	stz $210c		;
+	stz $210d		;
+	stz $210d		;
+	stz $210e		;
+	stz $210e		;
+	stz $210f		;
+	stz $210f		;
+	lda #$05
+	sta $2110		;
+	stz $2110		;
+	stz $2111		;
+	stz $2111		;
+	stz $2112		;
+	stz $2112		;
+	stz $2113		;
+	stz $2113		;
+	stz $2114		;
+	stz $2114		;
+	lda #$80		
+	sta $2115		;
+	stz $2116		;
+	stz $2117		;
+;	stz $2118		;(VRAM Data?!)
+;	stz $2119		;(VRAM Data?!)
+	stz $211a		;
+	stz $211b		;
+	lda #$01
+	sta $211b		;
+	stz $211c		;
+	stz $211c		;
+	stz $211d		;
+	stz $211d		;
+	stz $211e		;
+	sta $211e		;
+	stz $211f		;
+	stz $211f		;
+	stz $2120		;
+	stz $2120		;
+	stz $2121		;
+;	stz $2122		; (CG Data?!)
+;	stz $2122		; (CG Data?!)
+	stz $2123		;
+	stz $2124		;
+	stz $2125		;
+	stz $2126		;
+	stz $2127		;
+	stz $2128		;
+	stz $2129		;
+	stz $212a		;
+	stz $212b		;
+	stz $212c		;
+	stz $212d		;
+	stz $212e		;
+	stz $212f		;
+	lda #$30
+	sta $2130		;
+	stz $2131		;
+	lda #$e0
+	sta $2132		;
+	stz $2133		;
+;clear WRAM lower page
+;        ldx #$0200
+;        stx $2181
+;        lda #$00
+;        sta $2183
+;        DMA0(#$08, #$FF00, #^zero, #!zero, #$80)
+;        ldx #$0000
+;        stx $2181
+;	lda #$00
+;	sta $2183
+;        DMA0(#$08, #$1e0, #^zero, #!zero, #$80)
+
+	rts
+
+

snes/text.a65

@@ -1,133 +1,95 @@
 .text
 #include "memmap.i65"
+.byt "===HIPRINT==="
+; input:
+; print_count
+; print_x
+; print_y
+; print_src
+; print_bank
+; print_pal
+;
+; output:
+; print_done (# of chars printed)
+; print_over (char after print_count)
+
 hiprint:
+	php
 	sep #$20 : .as
-	lda print_count
-	sta print_count_tmp
-	rep #$30 : .xl : .al
-	stz print_done
-	lda print_x
-	and #$00ff
-	lsr
-	bcs print_bg1
-	ldx #!BG1_TILE_BUF ; for 2nd loop
-	phx
-	ldx #!BG2_TILE_BUF ; for 1st loop
-	phx
-	bra print_bg_cont
-print_bg1
-	ldx #!BG2_TILE_BUF+2 ; for 2nd loop
-	phx
-	ldx #!BG1_TILE_BUF ; for 1st loop da whoop
-	phx
-	bra print_bg_cont
-print_bg_cont
-	sta !print_temp
-	lda !print_y
-	and #$00ff
-	asl
-	asl
-	asl
-	asl
-	asl
-	clc
-	adc !print_temp
-	asl ; double the offset for WRAM addressing
-	tay	; zonday
-	plx
-	phy	; offset from tilemap start
-	stx !print_temp
-	clc
-	adc !print_temp
-; we need to transfer to WRAM and from there to VRAM via DMA during VBLANK
-; because VRAM can only be accessed during VBLANK and forced blanking.
-	sta $2181
-	sep #$20 : .as
-	lda #$7f ;we really only need bit 0. full bank given for clarity
-	sta $2183
-print_loop
-	ldx !print_src
-	lda !print_bank
-	pha
-	plb
-	phx	; source addr
-print_loop_inner
-	lda !0,x
-	asl
-	sta @$2180
-	lda @print_pal
-	asl
-	asl
-	adc #$00
-	ora #$20
-	sta @$2180
-	lda @print_done
-	inc
-	sta @print_done
-	inx
-	lda !0,x
-	beq print_loop2
-	inx
-	lda !0,x
-	beq print_loop2
-	lda @print_count_tmp
-	dec
-	dec
-	sta @print_count_tmp
-	beq print_loop2
-	bmi print_loop2
-	bra print_loop_inner
-print_loop2
-	lda @print_count
-	dec
-	sta @print_count_tmp
-	lda #$00
+	rep #$10 : .xl
+	ldx print_src
+	stx print_ptr
+	lda print_bank
+	sta print_ptr+2
+	phb
+	lda #$7e
 	pha
 	plb
 	rep #$30 : .al : .xl
-	ply	; source addr
-	iny
-	pla	; offset from tilemap start
-	plx	; other tilemap addr
-	stx !print_temp
+	lda print_pal
+	and #$00ff
+	xba
+	asl
+	asl
+	ora #$2000
+	sta print_temp
+	lda print_count
+	and #$00ff
+	beq hiprint_end
+	tay
+	lda print_x
+	and #$00ff
+	sta print_x
+	lda print_y
+	and #$00ff
+	asl
+	asl
+	asl
+	asl
+	asl
+	asl
 	clc
-	adc !print_temp ; tilemap+offset
-	sta $2181
-	tyx
+	adc print_x
+	and #$fffe
+	tax
+	lda print_x
+	lsr
+	bcs hiprint_bg1
+hiprint_bg2
+	lda [print_ptr]
+	and #$00ff
+	beq hiprint_end
+	inc print_ptr
+	asl
+	ora print_temp
+	sta !BG2_TILE_BUF, x
+	dey
+	beq hiprint_end
+hiprint_bg1
+	lda [print_ptr]
+	and #$00ff
+	beq hiprint_end
+	inc print_ptr
+	asl
+	ora print_temp
+	sta !BG1_TILE_BUF, x
+	inx
+	inx
+	dey
+	beq hiprint_end
+	bra hiprint_bg2
+hiprint_end
+	plb
 	sep #$20 : .as
-	lda print_bank
-	pha
-	plb
-print_loop2_inner
-	lda !0,x
-	asl
-	sta @$2180
-	lda @print_pal
-	asl
-	asl
-	adc #$00
-	ora #$20
-	sta @$2180
-	lda @print_done
+	lda [print_ptr]
+	sta print_over
+	tya
+	sec
+	sbc print_count
+	eor #$ff
 	inc
-	sta @print_done
-	inx
-	lda !0,x
-	beq print_end
-	inx
-	lda !0,x
-	beq print_end
-	lda @print_count_tmp
-	dec
-	dec
-	sta @print_count_tmp
-	beq print_end
-	bmi print_end
-	bra print_loop2_inner
-print_end
-	lda #$00
-	pha
-	plb
+	sta print_done
+	plp
 	rts
 
 
@@ -157,7 +119,7 @@ loprint:
 	sta $2183
 	ldx !print_src
 	lda !print_bank
-	pha 
+	pha
 	plb
 loprint_loop_inner
 	lda !0,x
@@ -257,16 +219,40 @@ draw_window:
 	jsr hiprint
 
 ; print window title
+	lda print_x
+	pha
 	inc print_x
 	inc print_x
+	lda #^window_tl
+	sta print_bank
+	ldx #!window_tl
+	stx print_src
+	lda #$01
+	sta print_count
+	jsr hiprint
+	inc print_x
 	lda window_tbank
 	sta print_bank
 	ldx window_taddr
 	stx print_src
+	lda window_w
+	sta print_count
 	jsr hiprint
-	dec print_x
-	dec print_x
-
+	lda print_done
+	clc
+	adc print_x
+	sta print_x
+	lda #^window_tr
+	sta print_bank
+	ldx #!window_tr
+	stx print_src
+	lda #$01
+	sta print_count
+	jsr hiprint
+	lda window_w
+	sta print_count
+	pla
+	sta print_x
 ; draw left+right borders + space inside window
 	lda #^stringbuf
 	sta print_bank

snes/time.a65

@@ -2,7 +2,7 @@
 #include "dma.i65"
 
 timebox_data
-        ; string offset, selection width, bcdtime offset, 1s limit, 10s limit
+        ; string offset, selection width, bcdtime offset
 	.byt  0, 4, 9
 	.byt  5, 2, 8
 	.byt  8, 2, 6
@@ -46,6 +46,7 @@ time_init:
 	jsr gettime
 	stz time_sel
 	stz time_exit
+	stz time_cancel
 	lda #^text_buttonB
 	sta print_bank
 	ldx #!text_buttonB
@@ -85,7 +86,7 @@ time_update
 	lda #$00
 	xba
 	tax
-	lda !timebox_data, x
+	lda @timebox_data, x
 	clc
 	adc #$04
 	adc @time_win_x
@@ -94,10 +95,10 @@ time_update
 	adc #$02
 	sta bar_yl
 	inx
-	lda !timebox_data, x
+	lda @timebox_data, x
 	sta bar_wl
 	inx
-	lda !timebox_data, x
+	lda @timebox_data, x
 	sta time_ptr
 timeloop1
 	lda isr_done
@@ -120,17 +121,29 @@ timeloop1
 	lda #$80
 	and pad1trig+1
 	bne tkey_b
+	lda #$80
+	and pad1trig
+	bne tkey_a
 	; do stuff
 	lda time_exit
-	beq timeloop1
+	bne timesave
 	; set clock
+	lda time_cancel
+	bne timenosave
+	beq timeloop1
+timesave
 	jsr settime
+timenosave
 	; restore text area
 	jsr restore_screen
 	plp
 	rtl
 
 tkey_b
+	inc time_cancel
+	jmp time_update
+
+tkey_a
 	inc time_exit
 	jmp time_update
 
@@ -250,12 +263,12 @@ time_inc_day
 	lda #$00
 	xba
 	tax
-	lda !time_month, x
+	lda @time_month, x
 	cmp time_d10
 	bne time_inc_day_normal
 	inx
 	jsr is_leapyear_feb
-	lda !time_month, x
+	lda @time_month, x
 	dec
 	adc #$00
 	cmp time_d1
@@ -296,13 +309,13 @@ time_adjust_mon
 	xba
 	tax
 	lda time_d10
-	cmp !time_month, x
+	cmp @time_month, x
 	bcs time_mon_adjust
 	rts
 time_mon_adjust
 	php
 	inx
-	lda !time_month, x
+	lda @time_month, x
 	pha
 	jsr is_leapyear_feb	; c=1 -> a leapyear february
 	pla
@@ -314,7 +327,7 @@ time_mon_adjust
 time_mon_doadjust
 	sta time_d1
 	dex
-	lda !time_month, x
+	lda @time_month, x
 	sta time_d10
 +
 	rts
@@ -433,10 +446,10 @@ time_dec_cont
 	asl
 	ldx #$0000
 	tax
-	lda !time_month, x
+	lda @time_month, x
 	sta time_d10
 	inx
-	lda !time_month, x
+	lda @time_month, x
 	pha
 	jsr is_leapyear_feb
 	pla
@@ -486,6 +499,8 @@ time_dec_y1_normal
 	rts
 
 gettime
+	php
+	sep #$20 : .as
 	lda #$0d
 	sta $2801
 	lda $2800
@@ -513,6 +528,7 @@ gettime
 	sta time_y10
 	lda $2800
 	sta time_y100
+	plp
 	rts
 
 rendertime
@@ -664,31 +680,31 @@ is_leapyear_400th
 
 settime
 	lda time_y100
-	sta @AVR_PARAM
+	sta @MCU_PARAM
 	lda time_y10
-	sta @AVR_PARAM+1
+	sta @MCU_PARAM+1
 	lda time_y1
-	sta @AVR_PARAM+2
+	sta @MCU_PARAM+2
 	lda time_mon
-	sta @AVR_PARAM+3
+	sta @MCU_PARAM+3
 	lda time_d10
-	sta @AVR_PARAM+4
+	sta @MCU_PARAM+4
 	lda time_d1
-	sta @AVR_PARAM+5
+	sta @MCU_PARAM+5
 	lda time_h10
-	sta @AVR_PARAM+6
+	sta @MCU_PARAM+6
 	lda time_h1
-	sta @AVR_PARAM+7
+	sta @MCU_PARAM+7
 	lda time_m10
-	sta @AVR_PARAM+8
+	sta @MCU_PARAM+8
 	lda time_m1
-	sta @AVR_PARAM+9
+	sta @MCU_PARAM+9
 	lda time_s10
-	sta @AVR_PARAM+10
+	sta @MCU_PARAM+10
 	lda time_s1
-	sta @AVR_PARAM+11
+	sta @MCU_PARAM+11
 	lda #$02 ; set clock
-	sta @AVR_CMD
+	sta @MCU_CMD
 	rts
 
 printtime:
@@ -697,8 +713,6 @@ printtime:
         lda listdisp
         clc
         adc #$0a
-        clc
-        adc vidmode
         sta print_y
         lda #$2b
         sta print_x

snes/utils/mkmap.sh

@@ -0,0 +1,24 @@
+#!/bin/bash
+
+args=("$@")
+objcount=0
+
+grep object_ link.log | \
+sed -e 's/object_//g; s/_code//g; s/_data//g' | \
+while read obj; do
+  objcount=$((objcount+1))
+  read base idx <<< "$obj"
+  base="0x${base}"
+  fn=${args[$idx-1]}
+  echo ======$fn, base=$base====== > ${fn%%.*}.map
+  sed -e '/^Externs/,$d;/^Labels/d' < $fn.log | \
+  while read line; do
+    read addr label <<< "$line"
+    addr="0x$addr"
+    decaddr=`printf "%d" $addr`
+    [ "$decaddr" -gt "65535" ] && base=0
+    ea=`printf "%X" $((base+addr))`
+    echo $ea $label >> ${fn%%.*}.map
+  done
+done
+

src/Makefile

@@ -55,7 +55,7 @@ TARGET = $(OBJDIR)/sd2snes
 
 
 # List C source files here. (C dependencies are automatically generated.)
-SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c crc16.c
+SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c crc16.c sysinfo.c cfg.c
 
 # usbcontrol.c usb_hid.c usbhw_lpc.c usbinit.c usbstdreq.c
 

src/README

@@ -25,6 +25,7 @@ b) Cortex M3 toolchain
     - libexpat-dev
     - make
     - gcc
+   Package names may differ for your distribution.
    Newer gccs complain when compiling binutils, so you may have to add
    '--disable-werror' to the compiler options for binutils in the Makefile.
    The Makefile will install immediately so make sure you can write to the

src/bootldr/Makefile

@@ -213,6 +213,8 @@ sym: $(TARGET).sym
 
 
 #	utils/lpcchksum $(TARGET).bin
+fresh: erase program
+
 program: bin
 	openocd -f openocd-usb.cfg -f lpc1754.cfg -f flash.cfg
 

src/bootldr/clock.c

@@ -14,8 +14,8 @@ void clock_disconnect() {
 
 void clock_init() {
 
-/* set flash access time to 5 clks (80<f<=100MHz) */
-  setFlashAccessTime(5);
+/* set flash access time to 6 clks (safe setting) */
+  setFlashAccessTime(6);
 
 /* setup PLL0 for ~44100*256*8 Hz
    Base clock: 12MHz
@@ -48,8 +48,7 @@ void clock_init() {
  */
   enableMainOsc();
   setClkSrc(CLKSRC_MAINOSC);
-// XXX  setPLL0MultPrediv(429, 19);
-  setPLL0MultPrediv(23, 2);
+  setPLL0MultPrediv(12, 1);
   enablePLL0();
   setCCLKDiv(3);
   connectPLL0();

src/bootldr/config.h

@@ -1,7 +1,7 @@
 #ifndef _CONFIG_H
 #define _CONFIG_H
 
-#define DEBUG_BL
+// #define DEBUG_BL
 // #define DEBUG_SD
 // #define DEBUG_IRQ
 
@@ -19,7 +19,7 @@
 #define DBG_BL while(0)
 #endif
 
-#define FW_START                  (0x00003000L)
+#define FW_START                  (0x00002000L)
 #define FLASH_SECTORS             (17)
 
 
@@ -51,11 +51,12 @@
 
 #define CONFIG_UART_NUM	          3
 // #define CONFIG_CPU_FREQUENCY      90315789
-#define CONFIG_CPU_FREQUENCY      (92000000L)
+#define CONFIG_CPU_FREQUENCY      (96000000L)
 //#define CONFIG_CPU_FREQUENCY      46000000
 #define CONFIG_UART_PCLKDIV       1
 #define CONFIG_UART_TX_BUF_SHIFT  8
 #define CONFIG_UART_BAUDRATE      921600
+//#define CONFIG_UART_BAUDRATE      115200
 #define CONFIG_UART_DEADLOCKABLE
 
 #define SSP_CLK_DIVISOR_FAST 2

src/bootldr/ffconf.h

@@ -14,7 +14,7 @@
 / Function and Buffer Configurations
 /----------------------------------------------------------------------------*/
 
-#define	_FS_TINY	0		/* 0:Normal or 1:Tiny */
+#define	_FS_TINY	1		/* 0:Normal or 1:Tiny */
 /* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
 /  object instead of the sector buffer in the individual file object for file
 /  data transfer. This reduces memory consumption 512 bytes each file object. */
@@ -57,7 +57,7 @@
 / Locale and Namespace Configurations
 /----------------------------------------------------------------------------*/
 
-#define _CODE_PAGE	1252
+#define _CODE_PAGE	1
 /* The _CODE_PAGE specifies the OEM code page to be used on the target system.
 /  Incorrect setting of the code page can cause a file open failure.
 /

src/bootldr/iap.c

@@ -72,10 +72,12 @@ FLASH_RES check_flash() {
 }
 
 IAP_RES iap_wrap(uint32_t *iap_cmd, uint32_t *iap_res) {
-  NVIC_DisableIRQ(RIT_IRQn);
-  NVIC_DisableIRQ(UART_IRQ);
+//  NVIC_DisableIRQ(RIT_IRQn);
+//  NVIC_DisableIRQ(UART_IRQ);
+  for(volatile int i=0; i<2048; i++);
   iap_entry(iap_cmd, iap_res);
-  NVIC_EnableIRQ(UART_IRQ);
+  for(volatile int i=0; i<2048; i++);
+//  NVIC_EnableIRQ(UART_IRQ);
   return iap_res[0];
 }
 
@@ -153,12 +155,16 @@ FLASH_RES flash_file(uint8_t *filename) {
 
     writeled(1);
     DBG_BL printf("erasing flash...\n");
+    DBG_UART uart_putc('P');
     if((res = iap_prepare_for_write(FW_START / 0x1000, FLASH_SECTORS)) != CMD_SUCCESS) {
       DBG_BL printf("error %ld while preparing for erase\n", res);
+      DBG_UART uart_putc('X');
       return ERR_FLASHPREP;
     };
+    DBG_UART uart_putc('E');
     if((res = iap_erase(FW_START / 0x1000, FLASH_SECTORS)) != CMD_SUCCESS) {
       DBG_BL printf("error %ld while erasing\n", res);
+      DBG_UART uart_putc('X');
       return ERR_FLASHERASE;
     }
     DBG_BL printf("writing... @%08lx\n", flash_addr);
@@ -174,18 +180,23 @@ FLASH_RES flash_file(uint8_t *filename) {
       DBG_BL printf("current_sec=%d flash_addr=%08lx\n", current_sec, flash_addr);
       DBG_UART uart_putc('.');
       if(current_sec < (FW_START / 0x1000)) return ERR_FLASH;
+      DBG_UART uart_putc(current_sec["0123456789ABCDEFGH"]);
+      DBG_UART uart_putc('p');
       if((res = iap_prepare_for_write(current_sec, current_sec)) != CMD_SUCCESS) {
         DBG_BL printf("error %ld while preparing sector %d for write\n", res, current_sec);
+        DBG_UART uart_putc('X');
         return ERR_FLASH;
       }
+      DBG_UART uart_putc('w');
       if((res = iap_ram2flash(flash_addr, file_buf, 512)) != CMD_SUCCESS) {
         DBG_BL printf("error %ld while writing to address %08lx (sector %d)\n", res, flash_addr, current_sec);
+        DBG_UART uart_putc('X');
         return ERR_FLASH;
       }
     }
-    if(total_read != file_header.size) {
+    if(total_read != (file_header.size + 0x100)) {
       DBG_BL printf("wrote less data than expected! (%08lx vs. %08lx)\n", total_read, file_header.size);
-      DBG_UART uart_putc('X');
+//      DBG_UART uart_putc('X');
       return ERR_FILECHK;
     }
     writeled(0);

src/bootldr/lpc1754boot.ld

@@ -10,7 +10,7 @@ ENTRY(_start)
 
 MEMORY
 {
-  flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x03000
+  flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x02000
   ram    (rwx) : ORIGIN = 0x10000000, LENGTH = 0x03fe0 /* leave room for IAP */
   ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x04000
 }

src/bootldr/main.c

@@ -23,13 +23,13 @@ int i;
 volatile enum diskstates disk_state;
 extern volatile tick_t ticks;
 
-int (*chain)(void) = (void*)(FW_START+0x000001c5);
+int (*chain)(void);
 
 int main(void) {
   SNES_CIC_PAIR_REG->FIODIR = BV(SNES_CIC_PAIR_BIT);
   BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
 /*  LPC_GPIO2->FIODIR = BV(0) | BV(1) | BV(2); */
-  LPC_GPIO0->FIODIR = BV(16);
+//  LPC_GPIO0->FIODIR = BV(16);
 
  /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */
   LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */
@@ -50,7 +50,7 @@ int main(void) {
   writeled(0);
  /* do this last because the peripheral init()s change PCLK dividers */
   clock_init();
-  LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
+//  LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
   sdn_init();
   DBG_BL printf("chksum=%08lx\n", *(uint32_t*)28);
   DBG_BL printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY);
@@ -61,7 +61,8 @@ DBG_BL printf("PCONP=%lx\n", LPC_SC->PCONP);
   LPC_TIM3->MCR=MR0R;
   LPC_TIM3->MR0=1;
   LPC_TIM3->TCR=1;
-
+  NVIC->ICER[0] = 0xffffffff;
+  NVIC->ICER[1] = 0xffffffff;
   FLASH_RES res = flash_file((uint8_t*)"/sd2snes/firmware.img");
   if(res == ERR_FLASHPREP || res == ERR_FLASHERASE || res == ERR_FLASH) {
     rdyled(0);
@@ -85,6 +86,16 @@ DBG_BL printf("PCONP=%lx\n", LPC_SC->PCONP);
   NVIC_DisableIRQ(UART_IRQ);
 
   SCB->VTOR=FW_START+0x00000100;
+  chain = (void*)(*((uint32_t*)(FW_START+0x00000104)));
+  uart_putc("0123456789abcdef"[((uint32_t)chain>>28)&15]);
+  uart_putc("0123456789abcdef"[((uint32_t)chain>>24)&15]);
+  uart_putc("0123456789abcdef"[((uint32_t)chain>>20)&15]);
+  uart_putc("0123456789abcdef"[((uint32_t)chain>>16)&15]);
+  uart_putc("0123456789abcdef"[((uint32_t)chain>>12)&15]);
+  uart_putc("0123456789abcdef"[((uint32_t)chain>>8)&15]);
+  uart_putc("0123456789abcdef"[((uint32_t)chain>>4)&15]);
+  uart_putc("0123456789abcdef"[((uint32_t)chain)&15]);
+  uart_putc('\n');
   chain();
   while(1);
 }

src/bootldr/timer.c

@@ -18,32 +18,6 @@ extern volatile int sd_changed;
 volatile tick_t ticks;
 volatile int wokefromrit;
 
-void __attribute__((weak,noinline)) SysTick_Hook(void) {
-  /* Empty function for hooking the systick handler */
-}
-
-/* Systick interrupt handler */
-void SysTick_Handler(void) {
-  ticks++;
-  static uint16_t sdch_state = 0;
-  sdch_state = (sdch_state << 1) | SDCARD_DETECT | 0xe000;
-  if((sdch_state == 0xf000) || (sdch_state == 0xefff)) {
-    sd_changed = 1;
-  }
-  sdn_changed();
-  SysTick_Hook();
-}
-
-void __attribute__((weak,noinline)) RIT_Hook(void) {
-}
-
-void RIT_IRQHandler(void) {
-  LPC_RIT->RICTRL = BV(RITINT);
-  NVIC_ClearPendingIRQ(RIT_IRQn);
-  wokefromrit = 1;
-  RIT_Hook();
-}
-
 void timer_init(void) {
   /* turn on power to RIT */
   BITBAND(LPC_SC->PCONP, PCRIT) = 1;
@@ -54,8 +28,6 @@ void timer_init(void) {
   /* PCLK = CCLK */
   BITBAND(LPC_SC->PCLKSEL1, 26) = 1;
   BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1;
-  /* enable SysTick */
-  SysTick_Config((SysTick->CALIB & SysTick_CALIB_TENMS_Msk));
 }
 
 void delay_us(unsigned int time) {
@@ -84,21 +56,3 @@ void delay_ms(unsigned int time) {
   LPC_RIT->RICTRL = 0;
 }
 
-void sleep_ms(unsigned int time) {
-
-  wokefromrit = 0;
-  /* Prepare RIT */
-  LPC_RIT->RICOUNTER = 0;
-  LPC_RIT->RICOMPVAL = (CONFIG_CPU_FREQUENCY / 1000) * time;
-  LPC_RIT->RICTRL    = BV(RITEN) | BV(RITINT);
-  NVIC_EnableIRQ(RIT_IRQn);
-
-  /* Wait until RIT signals an interrupt */
-//uart_putc(';');
-  while(!wokefromrit) {
-    __WFI();
-  }
-  NVIC_DisableIRQ(RIT_IRQn);
-  /* Disable RIT */
-  LPC_RIT->RICTRL = BV(RITINT);
-}

src/bootldr/uart.c

@@ -10,7 +10,7 @@
 #include "uart.h"
 #include "led.h"
 
-static uint8_t uart_lookupratio(float f_fr) {
+/*static uint8_t uart_lookupratio(float f_fr) {
   uint16_t errors[72]={0,67,71,77,83,91,100,111,125,
                        133,143,154,167,182,200,214,222,231,
                        250,267,273,286,300,308,333,357,364,
@@ -45,8 +45,8 @@ static uint8_t uart_lookupratio(float f_fr) {
   }
   return ratios[i_result];
 }
-
-static uint32_t baud2divisor(unsigned int baudrate) {
+*/
+/*static uint32_t baud2divisor(unsigned int baudrate) {
   uint32_t int_ratio;
   uint32_t error;
   uint32_t dl=0;
@@ -73,66 +73,15 @@ static uint32_t baud2divisor(unsigned int baudrate) {
     return ((fract_ratio<<16)&0xff0000) | dl;
   }
 }
-
-static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT];
+*/
+//static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT];
 static volatile unsigned int read_idx,write_idx;
 
-void UART_HANDLER(void) {
-  int iir = UART_REGS->IIR;
-  if (!(iir & 1)) {
-    /* Interrupt is pending */
-    switch (iir & 14) {
-#if CONFIG_UART_NUM == 1
-    case 0: /* modem status */
-      (void) UART_REGS->MSR; // dummy read to clear
-      break;
-#endif
-
-    case 2: /* THR empty - send */
-      if (read_idx != write_idx) {
-        int maxchars = 16;
-        while (read_idx != write_idx && --maxchars > 0) {
-          UART_REGS->THR = (unsigned char)txbuf[read_idx];
-          read_idx = (read_idx+1) & (sizeof(txbuf)-1);
-        }
-        if (read_idx == write_idx) {
-          /* buffer empty - turn off THRE interrupt */
-          BITBAND(UART_REGS->IER, 1) = 0;
-        }
-      }
-      break;
-      
-    case 12: /* RX timeout */
-    case  4: /* data received - not implemented yet */
-      (void) UART_REGS->RBR; // dummy read to clear
-      break;
-
-    case 6: /* RX error */
-      (void) UART_REGS->LSR; // dummy read to clear
-
-    default: break;
-    }
-  }
-}
-
 void uart_putc(char c) {
   if (c == '\n')
     uart_putc('\r');
-
-  unsigned int tmp = (write_idx+1) & (sizeof(txbuf)-1) ;
-
-  if (read_idx == write_idx && (BITBAND(UART_REGS->LSR, 5))) {
-    /* buffer empty, THR empty -> send immediately */
-    UART_REGS->THR = (unsigned char)c;
-  } else {
-#ifdef CONFIG_UART_DEADLOCKABLE
-    while (tmp == read_idx) ;
-#endif
-    BITBAND(UART_REGS->IER, 1) = 0; // turn off UART interrupt
-    txbuf[write_idx] = c;
-    write_idx = tmp;
-    BITBAND(UART_REGS->IER, 1) = 1;
-  }
+  while(!(UART_REGS->LSR & (0x20)));
+  UART_REGS->THR = c;
 }
 
 /* Polling version only */
@@ -170,7 +119,7 @@ void uart_init(void) {
 
   /* set baud rate - no fractional stuff for now */
   UART_REGS->LCR = BV(7) | 3; // always 8n1
-  div = baud2divisor(CONFIG_UART_BAUDRATE);
+  div = 0xF80022; //0x850004; // baud2divisor(CONFIG_UART_BAUDRATE);
 
   UART_REGS->DLL = div & 0xff;
   UART_REGS->DLM = (div >> 8) & 0xff;
@@ -183,10 +132,6 @@ void uart_init(void) {
   /* reset and enable FIFO */
   UART_REGS->FCR = BV(0);
 
-  /* enable transmit interrupt */
-  BITBAND(UART_REGS->IER, 1) = 1;
-  NVIC_EnableIRQ(UART_IRQ);
-
   UART_REGS->THR = '?';
 }
 

src/cfg.c

@@ -0,0 +1,59 @@
+#include "cfg.h"
+#include "config.h"
+#include "uart.h"
+#include "fileops.h"
+
+cfg_t CFG = {
+  .cfg_ver_maj = 1,
+  .cfg_ver_min = 0,
+  .last_game_valid = 0,
+  .vidmode_menu = VIDMODE_AUTO,
+  .vidmode_game = VIDMODE_AUTO,
+  .pair_mode_allowed = 0,
+  .bsx_use_systime = 0,
+  .bsx_time = 0x0619970301180530LL
+};
+
+int cfg_save() {
+  int err = 0;
+  file_open(CFG_FILE, FA_CREATE_ALWAYS | FA_WRITE);
+  if(file_writeblock(&CFG, 0, sizeof(CFG)) < sizeof(CFG)) {
+    err = file_res;
+  }
+  file_close();
+  return err;
+}
+
+int cfg_load() {
+  int err = 0;
+  file_open(CFG_FILE, FA_READ);
+  if(file_readblock(&CFG, 0, sizeof(CFG)) < sizeof(CFG)) {
+    err = file_res;
+  }
+  file_close();
+  return err;
+}
+
+int cfg_save_last_game(uint8_t *fn) {
+  int err = 0;
+  file_open(LAST_FILE, FA_CREATE_ALWAYS | FA_WRITE);
+  err = f_puts((const TCHAR*)fn, &file_handle);
+  file_close();
+  return err;
+}
+
+int cfg_get_last_game(uint8_t *fn) {
+  int err = 0;
+  file_open(LAST_FILE, FA_READ);
+  f_gets((TCHAR*)fn, 255, &file_handle);
+  file_close();
+  return err;
+}
+
+void cfg_set_last_game_valid(uint8_t valid) {
+  CFG.last_game_valid = valid;
+}
+
+uint8_t cfg_is_last_game_valid() {
+  return CFG.last_game_valid;
+}

src/cfg.h

@@ -0,0 +1,39 @@
+#ifndef _CFG_H
+#define _CFG_H
+
+#include <stdint.h>
+
+#define CFG_FILE ((const uint8_t*)"/sd2snes/sd2snes.cfg")
+#define LAST_FILE ((const uint8_t*)"/sd2snes/lastgame.cfg")
+
+typedef enum {
+  VIDMODE_AUTO = 0,
+  VIDMODE_60,
+  VIDMODE_50
+} cfg_vidmode_t;
+
+typedef struct _cfg_block {
+  uint8_t cfg_ver_maj;
+  uint8_t cfg_ver_min;
+  uint8_t last_game_valid;
+  uint8_t vidmode_menu;
+  uint8_t vidmode_game;
+  uint8_t pair_mode_allowed;
+  uint8_t bsx_use_systime;
+  uint64_t bsx_time;
+} cfg_t;
+
+int cfg_save(void);
+int cfg_load(void);
+
+int cfg_save_last_game(uint8_t *fn);
+int cfg_get_last_game(uint8_t *fn);
+
+cfg_vidmode_t cfg_get_vidmode_menu(void);
+cfg_vidmode_t cfg_get_vidmode_game(void);
+
+void cfg_set_last_game_valid(uint8_t);
+uint8_t cfg_is_last_game_valid(void);
+uint8_t cfg_is_pair_mode_allowed(void);
+
+#endif

src/cic.c

@@ -5,11 +5,16 @@
 #include "cic.h"
 
 char *cicstatenames[4] = { "CIC_OK", "CIC_FAIL", "CIC_PAIR", "CIC_SCIC" };
+char *cicstatefriendly[4] = {"Original or no CIC", "Original CIC(failed)", "SuperCIC enhanced", "SuperCIC detected, not used"};
 
 void print_cic_state() {
   printf("CIC state: %s\n", get_cic_statename(get_cic_state()));
 }
 
+inline char *get_cic_statefriendlyname(enum cicstates state) {
+  return cicstatefriendly[state];
+}
+
 inline char *get_cic_statename(enum cicstates state) {
   return cicstatenames[state];
 }

src/cic.h

@@ -13,6 +13,7 @@ enum cic_region { CIC_NTSC = 0, CIC_PAL };
 
 void print_cic_state(void);
 char *get_cic_statename(enum cicstates state);
+char *get_cic_statefriendlyname(enum cicstates state);
 enum cicstates get_cic_state(void);
 void cic_init(int allow_pairmode);
 

src/cli.c

@@ -58,8 +58,8 @@ static char *curchar;
 
 /* Word lists */
 static char command_words[] =
-  "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0";
-enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16 };
+  "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0rm\0mkdir\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0";
+enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_MKDIR, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16 };
 
 /* ------------------------------------------------------------------------- */
 /*   Parse functions                                                         */
@@ -134,7 +134,7 @@ static int8_t parse_wordlist(char *wordlist) {
     do {
       // If current word list character is \0: No match found
       if (c == 0) {
-        printf("Unknown word: %s\n",curchar);
+        printf("Unknown word: %s\n(use ? for help)",curchar);
         return -1;
       }
 
@@ -294,7 +294,8 @@ static void cmd_loadraw(void) {
 static void cmd_saveraw(void) {
   uint32_t address = parse_unsigned(0,16777216,16);
   uint32_t length = parse_unsigned(0,16777216,16);
-  save_sram((uint8_t*)curchar, length, address);
+  if(address != -1 && length != -1)
+    save_sram((uint8_t*)curchar, length, address);
 }
 
 static void cmd_d4(void) {
@@ -343,6 +344,16 @@ void cmd_put(void) {
   }
 }
 
+void cmd_rm(void) {
+  FRESULT res = f_unlink(curchar);
+  if(res) printf("Error %d removing %s\n", res, curchar);
+}
+
+void cmd_mkdir(void) {
+  FRESULT res = f_mkdir(curchar);
+  if(res) printf("Error %d creating directory %s\n", res, curchar);
+}
+
 void cmd_mapper(void) {
   int32_t mapper;
   mapper = parse_unsigned(0,7,10);
@@ -356,9 +367,7 @@ void cmd_sreset(void) {
     resetstate = parse_unsigned(0,1,10);
     snes_reset(resetstate);
   } else {
-    snes_reset(1);
-    delay_ms(20);
-    snes_reset(0);
+    snes_reset_pulse();
   }
 }
 void cmd_settime(void) {
@@ -509,6 +518,14 @@ void cli_loop(void) {
       cmd_saveraw();
       break;
 
+    case CMD_RM:
+      cmd_rm();
+      break;
+
+    case CMD_MKDIR:
+      cmd_mkdir();
+      break;
+
     case CMD_D4:
       cmd_d4();
       break;

src/clock.c

@@ -48,11 +48,9 @@ void clock_init() {
  */
   enableMainOsc();
   setClkSrc(CLKSRC_MAINOSC);
-// XXX  setPLL0MultPrediv(429, 19);
-// XXX  setPLL0MultPrediv(23, 2);
-  setPLL0MultPrediv(12, 1);
+  setPLL0MultPrediv(22, 1);
   enablePLL0();
-  setCCLKDiv(3);
+  setCCLKDiv(6);
   connectPLL0();
 }
 

src/config

@@ -1,3 +1,4 @@
-CONFIG_VERSION=0.0.1
-CONFIG_FWVER=16777214
+CONFIG_VERSION="0.1.4a"
+#FWVER=00010300
+CONFIG_FWVER=0x01010400
 CONFIG_MCU_FOSC=12000000

src/config.h

@@ -1,12 +1,13 @@
 #ifndef _CONFIG_H
 #define _CONFIG_H
 
+#include "autoconf.h"
+
 // #define DEBUG_FS
 // #define DEBUG_SD
 // #define DEBUG_IRQ
 // #define DEBUG_MSU1
 
-#define VER                       "0.0.1(NSFW)"
 #define IN_AHBRAM                 __attribute__ ((section(".ahbram")))
 
 #define SD_DT_INT_SETUP()         do {\
@@ -34,18 +35,15 @@
 
 #define CONFIG_UART_NUM	          3
 // #define CONFIG_CPU_FREQUENCY      90315789
-#define CONFIG_CPU_FREQUENCY      96000000
+#define CONFIG_CPU_FREQUENCY      88000000
 //#define CONFIG_CPU_FREQUENCY      46000000
 #define CONFIG_UART_PCLKDIV       1
 #define CONFIG_UART_TX_BUF_SHIFT  8
-#define CONFIG_UART_BAUDRATE      921600
+//#define CONFIG_UART_BAUDRATE      921600
+#define CONFIG_UART_BAUDRATE      115200
 #define CONFIG_UART_DEADLOCKABLE
 
-#define SSP_CLK_DIVISOR_FAST 2
-#define SSP_CLK_DIVISOR_SLOW 250
-
-#define SSP_CLK_DIVISOR_FPGA_FAST 6
-#define SSP_CLK_DIVISOR_FPGA_SLOW 20
+#define SSP_CLK_DIVISOR           2
 
 #define SNES_RESET_REG            LPC_GPIO1
 #define SNES_RESET_BIT            26
@@ -65,7 +63,10 @@
 #define FPGA_MCU_RDY_REG          LPC_GPIO2
 #define FPGA_MCU_RDY_BIT          9
 
-#define QSORT_MAXELEM             1024
+#define QSORT_MAXELEM             2048
+#define CLTBL_SIZE		  100
+
+#define DIR_FILE_MAX              16380
 
 #define SSP_REGS LPC_SSP0
 #define SSP_PCLKREG PCLKSEL1

src/diskio.h

@@ -55,7 +55,7 @@ DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
 #if	_READONLY == 0
 DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
 #endif
-#define disk_ioctl(a,b,c) RES_OK
+DRESULT disk_ioctl (BYTE, BYTE, void*);
 
 void disk_init(void);
 

src/ff.c

@@ -2198,7 +2198,6 @@ FRESULT f_read (
 #if !_FS_TINY
 #if !_FS_READONLY
 			if (fp->flag & FA__DIRTY) {				/* Write sector I/O buffer if needed */
-printf("DIRTY!?!\n");
 				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
 					ABORT(fp->fs, FR_DISK_ERR);
 				fp->flag &= ~FA__DIRTY;
@@ -2222,7 +2221,6 @@ printf("DIRTY!?!\n");
 			mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt);	/* Pick partial sector */
 #else
 			mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt);	/* Pick partial sector */
-			printf("final mem_cpy, rcnt=%d, rbuff-buff=%d\n", rcnt, (void*)rbuff-buff);
 		} else {
 			sd_offload_partial_start = fp->fptr % SS(fp->fs);
 			sd_offload_partial_end = sd_offload_partial_start + rcnt;
@@ -2376,7 +2374,6 @@ FRESULT f_sync (
 	res = validate(fp->fs, fp->id);		/* Check validity of the object */
 	if (res == FR_OK) {
 		if (fp->flag & FA__WRITTEN) {	/* Has the file been written? */
-printf("DIRTY?!?!?!\n");
 #if !_FS_TINY	/* Write-back dirty buffer */
 			if (fp->flag & FA__DIRTY) {
 				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
@@ -2642,8 +2639,16 @@ FRESULT f_lseek (
 						fp->flag &= ~FA__DIRTY;
 					}
 #endif
-					if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)
-						ABORT(fp->fs, FR_DISK_ERR);
+					if(!ff_sd_offload) {
+						sd_offload_partial=0;
+						if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)
+							ABORT(fp->fs, FR_DISK_ERR);
+					} else {
+						sd_offload_partial=1;
+						sd_offload_partial_start = fp->fptr % SS(fp->fs);
+					}
+//					if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)
+//						ABORT(fp->fs, FR_DISK_ERR);
 #endif
 					fp->dsect = dsc;
 				}
@@ -2822,6 +2827,46 @@ FRESULT f_readdir (
 }
 
 
+FRESULT l_opendirbycluster (
+  FATFS *fs,
+  DIR *dj,
+  const TCHAR *path,
+  DWORD clust
+)
+{
+  FRESULT res;
+  res = chk_mounted(&path, &fs, 0);
+  DEF_NAMEBUF;
+  INIT_BUF(*dj);
+  dj->sclust = clust;
+  dj->fs = fs;
+  dj->id = fs->id;
+  dj->dir = 0;
+  res = dir_sdi(dj, 0);
+  FREE_BUF();
+  return res;
+}
+
+FRESULT l_openfilebycluster (
+  FATFS *fs,           /* Pointer to file system object */
+  FIL *fp,             /* Pointer to the blank file object */
+  const TCHAR *path,
+  DWORD clust,         /* Cluster number to be opened */
+  DWORD fsize          /* File size to be assumed */
+)
+{
+  chk_mounted(&path, &fs, 0);
+  fp->flag = FA_READ;
+  fp->org_clust = clust;
+  fp->fsize = fsize;
+  fp->fptr = 0;
+  fp->dsect = 0;
+  fp->fs = fs;
+
+  return FR_OK;
+}
+
+
 
 #if _FS_MINIMIZE == 0
 /*-----------------------------------------------------------------------*/
@@ -2854,27 +2899,6 @@ FRESULT f_stat (
 	LEAVE_FF(dj.fs, res);
 }
 
-
-FRESULT l_openfilebycluster (
-  FATFS *fs,           /* Pointer to file system object */
-  FIL *fp,             /* Pointer to the blank file object */
-  const TCHAR *path,
-  DWORD clust,         /* Cluster number to be opened */
-  DWORD fsize          /* File size to be assumed */
-)
-{
-  chk_mounted(&path, &fs, 0);
-  fp->flag = FA_READ;
-  fp->org_clust = clust;
-  fp->fsize = fsize;
-  fp->fptr = 0;
-  fp->dsect = 0;
-  fp->fs = fs;
-
-  return FR_OK;
-}
-
-
 #if !_FS_READONLY
 /*-----------------------------------------------------------------------*/
 /* Get Number of Free Clusters                                           */
@@ -3620,6 +3644,7 @@ TCHAR* f_gets (
 		*p++ = c;
 		n++;
 		if (c == '\n') break;		/* Break on EOL */
+		if (c == 0) break;		/* Break on NUL */
 	}
 	*p = 0;
 	return n ? buff : 0;			/* When no data read (eof or error), return with error. */

src/ff.h

@@ -398,6 +398,7 @@ typedef enum {
 
 /* Low Level functions */
 FRESULT l_openfilebycluster(FATFS *fs, FIL *fp, const TCHAR *path, DWORD clust, DWORD fsize);   /* Open a file by its start cluster using supplied file size */
+FRESULT l_opendirbycluster (FATFS *fs, DIR *dj, const TCHAR *path, DWORD clust);
 
 /* application level functions */
 FRESULT f_mount (BYTE, FATFS*);						/* Mount/Unmount a logical drive */

src/ffconf.h

@@ -36,7 +36,7 @@
 /   3: f_lseek is removed in addition to 2. */
 
 
-#define	_USE_STRFUNC	0	/* 0:Disable or 1/2:Enable */
+#define	_USE_STRFUNC	1	/* 0:Disable or 1/2:Enable */
 /* To enable string functions, set _USE_STRFUNC to 1 or 2. */
 
 
@@ -48,7 +48,7 @@
 /* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
 
 
-#define	_USE_FASTSEEK	0	/* 0:Disable or 1:Enable */
+#define	_USE_FASTSEEK	1	/* 0:Disable or 1:Enable */
 /* To enable fast seek feature, set _USE_FASTSEEK to 1. */
 
 

src/fileops.c

@@ -47,11 +47,15 @@ void file_reinit(void) {
   file_init();
 }
 
+FRESULT dir_open_by_filinfo(DIR* dir, FILINFO* fno) {
+  return l_opendirbycluster(&fatfs, dir, (TCHAR*)"", fno->clust);
+}
+
 void file_open_by_filinfo(FILINFO* fno) {
   file_res = l_openfilebycluster(&fatfs, &file_handle, (TCHAR*)"", fno->clust, fno->fsize);
 }
 
-void file_open(uint8_t* filename, BYTE flags) {
+void file_open(const uint8_t* filename, BYTE flags) {
   if (disk_state == DISK_CHANGED) {
     file_reinit();
     newcard = 1;

src/fileops.h

@@ -40,7 +40,8 @@ uint16_t file_block_off, file_block_max;
 enum filestates file_status;
 
 void file_init(void);
-void file_open(uint8_t* filename, BYTE flags);
+void file_open(const uint8_t* filename, BYTE flags);
+FRESULT dir_open_by_filinfo(DIR* dir, FILINFO* fno_param);
 void file_open_by_filinfo(FILINFO* fno);
 void file_close(void);
 void file_seek(uint32_t offset);

src/filetypes.c

@@ -31,7 +31,7 @@
 #include "ff.h"
 #include "smc.h"
 #include "fileops.h"
-#include "crc32.h"
+#include "crc.h"
 #include "memory.h"
 #include "led.h"
 #include "sort.h"
@@ -53,20 +53,23 @@ uint16_t scan_flat(const char* path) {
   return numentries;
 }
 
-uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
+uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_tgt) {
   DIR dir;
   FILINFO fno;
   FRESULT res;
   uint8_t len;
   TCHAR* fn;
   static unsigned char depth = 0;
-  static uint32_t crc;
+  static uint32_t crc, fncrc;
   static uint32_t db_tgt;
   static uint32_t next_subdir_tgt;
   static uint32_t parent_tgt;
   static uint32_t dir_end = 0;
   static uint8_t was_empty = 0;
+  static uint16_t num_files_total = 0;
+  static uint16_t num_dirs_total = 0;
   uint32_t dir_tgt;
+  uint32_t switched_dir_tgt = 0;
   uint16_t numentries;
   uint32_t dirsize;
   uint8_t pass = 0;
@@ -74,6 +77,7 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
   char *size_units[3] = {" ", "k", "M"};
   uint32_t entry_fsize;
   uint8_t entry_unit_idx;
+  uint16_t entrycnt;
 
   dir_tgt = this_dir_tgt;
   if(depth==0) {
@@ -89,21 +93,35 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
   fno.lfsize = 255;
   fno.lfname = (TCHAR*)file_lfn;
   numentries=0;
-  for(pass = 0; pass < 2; pass++) {
+  for(pass = 0; pass < (mkdb ? 2 : 1); pass++) {
     if(pass) {
       dirsize = 4*(numentries);
+      if(((next_subdir_tgt + dirsize + 8) & 0xff0000) > (next_subdir_tgt & 0xff0000)) {
+        printf("switchdir! old=%lX ", next_subdir_tgt + dirsize + 4);
+        next_subdir_tgt &= 0xffff0000;
+        next_subdir_tgt += 0x00010004;
+        printf("new=%lx\n", next_subdir_tgt);
+        dir_tgt &= 0xffff0000;
+        dir_tgt += 0x00010004;
+      }
+      switched_dir_tgt = dir_tgt;
       next_subdir_tgt += dirsize + 4;
       if(parent_tgt) next_subdir_tgt += 4;
       if(next_subdir_tgt > dir_end) {
         dir_end = next_subdir_tgt;
       }
-      printf("path=%s depth=%d ptr=%lx entries=%d parent=%lx next subdir @%lx\n", path, depth, db_tgt, numentries, parent_tgt, next_subdir_tgt);
+      DBG_FS printf("path=%s depth=%d ptr=%lx entries=%d parent=%lx next subdir @%lx\n", path, depth, db_tgt, numentries, parent_tgt, next_subdir_tgt);
       if(mkdb) {
-        printf("d=%d Saving %lx to Address %lx  [end]\n", depth, 0L, next_subdir_tgt - 4);
+        num_dirs_total++;
+//        printf("d=%d Saving %lx to Address %lx  [end]\n", depth, 0L, next_subdir_tgt - 4);
         sram_writelong(0L, next_subdir_tgt - 4);
       }
     }
-    res = f_opendir(&dir, (TCHAR*)path);
+    if(fno_param) {
+      res = dir_open_by_filinfo(&dir, fno_param);
+    } else {
+      res = f_opendir(&dir, path);
+    }
     if (res == FR_OK) {
       if(pass && parent_tgt && mkdb) {
         /* write backlink to parent dir
@@ -114,6 +132,7 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
           db_tgt += 0x00010000;
           printf("new=%lx\n", db_tgt);
         }
+//        printf("writing link to parent, %lx to address %lx [../]\n", parent_tgt-SRAM_MENU_ADDR, db_tgt);
         sram_writelong((parent_tgt-SRAM_MENU_ADDR), db_tgt);
         sram_writebyte(0, db_tgt+sizeof(next_subdir_tgt));
         sram_writeblock("../\0", db_tgt+sizeof(next_subdir_tgt)+sizeof(len), 4);
@@ -122,7 +141,8 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
         dir_tgt += 4;
       }
       len = strlen((char*)path);
-      for (;;) {
+      /* scan at most DIR_FILE_MAX entries per directory */
+      for(entrycnt=0; entrycnt < DIR_FILE_MAX; entrycnt++) {
 //        toggle_read_led();
         res = f_readdir(&dir, &fno);
         if (res != FR_OK || fno.fname[0] == 0) {
@@ -132,19 +152,19 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
           break;
         }
         fn = *fno.lfname ? fno.lfname : fno.fname;
-        if ((*fn == '.') || !(memcmp(fn, SYS_DIR_NAME, sizeof(SYS_DIR_NAME)))) continue;
+        if ((*fn == '.') || !(strncasecmp(fn, SYS_DIR_NAME, sizeof(SYS_DIR_NAME)))) continue;
         if (fno.fattrib & AM_DIR) {
           depth++;
           if(depth < FS_MAX_DEPTH) {
             numentries++;
-            if(pass) {
+            if(pass && mkdb) {
               path[len]='/';
               strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
+              uint16_t pathlen = 0;
+              uint32_t old_db_tgt = 0;
               if(mkdb) {
-                uint16_t pathlen = strlen(path);
-                /* write element pointer to current dir structure */
-                printf("d=%d Saving %lx to Address %lx  [dir]\n", depth, db_tgt, dir_tgt);
-                sram_writelong((db_tgt-SRAM_MENU_ADDR)|((uint32_t)0x80<<24), dir_tgt);
+                pathlen = strlen(path);
+                DBG_FS printf("d=%d Saving %lx to Address %lx  [dir]\n", depth, db_tgt, dir_tgt);
                 /* save element:
                    - path name
                    - pointer to sub dir structure */
@@ -154,17 +174,31 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
                   db_tgt += 0x00010000;
                   printf("new=%lx\n", db_tgt);
                 }
-                printf("    Saving dir descriptor to %lx tgt=%lx, path=%s\n", db_tgt, next_subdir_tgt, path);
-                sram_writelong((next_subdir_tgt-SRAM_MENU_ADDR), db_tgt);
-                sram_writebyte(len+1, db_tgt+sizeof(next_subdir_tgt));
-                sram_writeblock(path, db_tgt+sizeof(next_subdir_tgt)+sizeof(len), pathlen);
-                sram_writeblock("/\0", db_tgt + sizeof(next_subdir_tgt) + sizeof(len) + pathlen, 2);
+                /* write element pointer to current dir structure */
+                sram_writelong((db_tgt-SRAM_MENU_ADDR)|((uint32_t)0x80<<24), dir_tgt);
+                /* save element:
+                   - path name
+                   - pointer to sub dir structure
+                   moved below */
+                old_db_tgt = db_tgt;
                 db_tgt += sizeof(next_subdir_tgt) + sizeof(len) + pathlen + 2;
               }
               parent_tgt = this_dir_tgt;
-              scan_dir(path, mkdb, next_subdir_tgt);
+              /* scan subdir before writing current dir element to account for bank switches */
+              uint32_t corrected_subdir_tgt = scan_dir(path, &fno, mkdb, next_subdir_tgt);
+              if(mkdb) {
+                DBG_FS printf("    Saving dir descriptor to %lx tgt=%lx, path=%s\n", old_db_tgt, corrected_subdir_tgt, path);
+                sram_writelong((corrected_subdir_tgt-SRAM_MENU_ADDR), old_db_tgt);
+                sram_writebyte(len+1, old_db_tgt+sizeof(next_subdir_tgt));
+                sram_writeblock(path, old_db_tgt+sizeof(next_subdir_tgt)+sizeof(len), pathlen);
+                sram_writeblock("/\0", old_db_tgt + sizeof(next_subdir_tgt) + sizeof(len) + pathlen, 2);
+              }
               dir_tgt += 4;
               was_empty = 0;
+            } else if(!mkdb) {
+              path[len]='/';
+              strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
+              scan_dir(path, &fno, mkdb, next_subdir_tgt);
             }
           }
           depth--;
@@ -175,6 +209,7 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
             numentries++;
             if(pass) {
               if(mkdb) {
+                num_files_total++;
 /*                snes_romprops_t romprops; */
                 path[len]='/';
                 strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
@@ -182,13 +217,7 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
                 switch(type) {
                   case TYPE_IPS:
                   case TYPE_SMC:
-/*                    file_open_by_filinfo(&fno);
-                    if(file_res){
-                      printf("ZOMG NOOOO %d\n", file_res);
-                    }
-                    smc_id(&romprops);
-                    file_close(); */
-
+                  case TYPE_SPC:
                     /* write element pointer to current dir structure */
                     DBG_FS printf("d=%d Saving %lX to Address %lX  [file %s]\n", depth, db_tgt, dir_tgt, path);
                     if((db_tgt&0xffff) > ((0x10000-(sizeof(len) + pathlen + sizeof(buf)-1 + 1))&0xffff)) {
@@ -222,27 +251,30 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
                   default:
                    break;
                 }
-                path[len]=0;
+                path[len] = 0;
 /*              printf("%s ", path);
                 _delay_ms(30); */
               }
             } else {
               TCHAR* fn2 = fn;
+              fncrc = 0;
               while(*fn2 != 0) {
-                crc += crc32_update(crc, *((unsigned char*)fn2++));
+                fncrc += crc_xmodem_update(fncrc, *((unsigned char*)fn2++));
               }
+              crc += fncrc;
             }
           }
-/*        printf("%s/%s\n", path, fn);
-          _delay_ms(50); */
         }
       }
     } else uart_putc(0x30+res);
   }
-//  printf("db_tgt=%lx dir_end=%lx\n", db_tgt, dir_end);
+  DBG_FS printf("db_tgt=%lx dir_end=%lx\n", db_tgt, dir_end);
   sram_writelong(db_tgt, SRAM_DB_ADDR+4);
   sram_writelong(dir_end, SRAM_DB_ADDR+8);
-  return crc;
+  sram_writeshort(num_files_total, SRAM_DB_ADDR+12);
+  sram_writeshort(num_dirs_total, SRAM_DB_ADDR+14);
+  if(depth==0) return crc;
+  else return switched_dir_tgt;
 }
 
 
@@ -257,18 +289,14 @@ SNES_FTYPE determine_filetype(char* filename) {
     ) {
     return TYPE_SMC;
   }
-  if(  (!strcasecmp(ext+1, "IPS"))
+/*  if(  (!strcasecmp(ext+1, "IPS"))
      ||(!strcasecmp(ext+1, "UPS"))
     ) {
     return TYPE_IPS;
-  }
-  /* later
-  if(!strcasecmp_P(ext+1, PSTR("SRM"))) {
-    return TYPE_SRM;
-  }
-  if(!strcasecmp_P(ext+1, PSTR("SPC"))) {
-    return TYPE_SPC;
   }*/
+  if(!strcasecmp(ext+1, "SPC")) {
+    return TYPE_SPC;
+  }
   return TYPE_UNKNOWN;
 }
 

src/filetypes.h

@@ -36,7 +36,7 @@
 #include "ff.h"
 
 #define FS_MAX_DEPTH	(10)
-#define SYS_DIR_NAME	((const uint8_t*)"sd2snes")
+#define SYS_DIR_NAME	((const char*)"sd2snes")
 typedef enum {
   TYPE_UNKNOWN = 0, /* 0 */
   TYPE_SMC,         /* 1 */
@@ -50,7 +50,7 @@ char fs_path[256];
 SNES_FTYPE determine_filetype(char* filename);
 //uint32_t scan_fs();
 uint16_t scan_flat(const char* path);
-uint32_t scan_dir(char* path, char mkdb, uint32_t this_subdir_tgt);
+uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_subdir_tgt);
 FRESULT get_db_id(uint32_t*);
 int get_num_dirent(uint32_t addr);
 void sort_all_dir(uint32_t endaddr);

src/flash.script

@@ -6,7 +6,7 @@
 #flash info 0
 
 reset init
-flash write_image erase unlock obj/firmware.img 12288
+flash write_image erase unlock obj/firmware.img 8192
 reset run
 shutdown
 

src/fpga.c

@@ -102,6 +102,10 @@ void fpga_pgm(uint8_t* filename) {
     i=0;
     timeout = getticks() + 100;
     fpga_set_prog_b(0);
+if(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) {
+  printf("PROGB is stuck high!\n");
+  led_panic();
+}
     uart_putc('P');
     fpga_set_prog_b(1);
     while(!fpga_get_initb()){
@@ -110,6 +114,10 @@ void fpga_pgm(uint8_t* filename) {
         led_panic();
       }
     };
+    if(fpga_get_done()) {
+      printf("DONE is stuck high!\n");
+      led_panic();
+    }
     LPC_GPIO2->FIOMASK1 = ~(BV(0));
     uart_putc('p');
 
@@ -160,6 +168,10 @@ void fpga_rompgm() {
         led_panic();
       }
     };
+    if(fpga_get_done()) {
+      printf("DONE is stuck high!\n");
+      led_panic();
+    }
     LPC_GPIO2->FIOMASK1 = ~(BV(0));
     uart_putc('p');
 

src/fpga_spi.c

@@ -47,9 +47,15 @@
                                 s: Bit 2 = partial, Bit 1:0 = target
                                 target: see above
 
-	60	sssseeee	set SD DMA partial transfer start+end
-				ssss = start offset (msb first)
-				eeee = end offset (msb first)
+	60	xsssyeee	set SD DMA partial transfer parameters
+				x: 0 = read from sector start (skip until
+				       start offset reached)
+				   8 = assume mid-sector position and read
+				       immediately
+				sss = start offset (msb first)
+				y: 0 = skip rest of SD sector
+				   8 = stop mid-sector if end offset reached
+				eee = end offset (msb first)
 
 	8p	-		read (RAM only)
 				p: 0 = no increment after read
@@ -80,6 +86,7 @@
 	EB	-		put DSP into reset
 	EC	-		release DSP from reset
 	ED	-		set feature enable bits (see below)
+	EE	-		set $213f override value (0=NTSC, 1=PAL)
 	F0	-		receive test token (to see if FPGA is alive)
 	F1	-		receive status (16bit, MSB first), see below
 
@@ -97,7 +104,7 @@
 	 15	SD DMA busy (0=idle, 1=busy)
 	 14	DAC read pointer MSB
 	 13	MSU read pointer MSB
-	 12	[TODO SD DMA CRC status (0=ok, 1=error); valid after bit 15 -> 0]
+	 12	reserved (0)
 	 11	reserved (0)
 	 10	reserved (0)
 	  9	reserved (0)
@@ -117,7 +124,7 @@
 	 7	-
 	 6	-
 	 5	-
-	 4	-
+	 4	enable $213F override
 	 3	enable MSU1 registers
 	 2	enable SRTC registers
 	 1	enable ST0010 mapping
@@ -133,9 +140,10 @@
 #include "spi.h"
 #include "fpga_spi.h"
 #include "timer.h"
+#include "sdnative.h"
 
 void fpga_spi_init(void) {
-  spi_init(SPI_SPEED_FAST);
+  spi_init();
   BITBAND(FPGA_MCU_RDY_REG->FIODIR, FPGA_MCU_RDY_BIT) = 0;
 }
 
@@ -191,7 +199,6 @@ void set_mapper(uint8_t val) {
 uint8_t fpga_test() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF0); /* TEST */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint8_t result = FPGA_RX_BYTE();
   FPGA_DESELECT();
   return result;
@@ -200,7 +207,6 @@ uint8_t fpga_test() {
 uint16_t fpga_status() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF1); /* STATUS */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint16_t result = (FPGA_RX_BYTE()) << 8;
   result |= FPGA_RX_BYTE();
   FPGA_DESELECT();
@@ -229,13 +235,15 @@ void fpga_sddma(uint8_t tgt, uint8_t partial) {
   FPGA_DESELECT();
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF1); /* STATUS */
-  FPGA_TX_BYTE(0x00); /* dummy */
+  DBG_SD printf("FPGA DMA request sent, wait for completion...");
   while((status=FPGA_RX_BYTE()) & 0x80) {
     FPGA_RX_BYTE(); /* eat the 2nd status byte */
     test++;
   }
+
+  DBG_SD printf("...complete\n");
   FPGA_DESELECT();
-  if(test<5)printf("loopy: %ld %02x\n", test, status);
+//  if(test<5)printf("loopy: %ld %02x\n", test, status);
   BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
 }
 
@@ -292,7 +300,6 @@ void set_msu_status(uint8_t set, uint8_t reset) {
 uint8_t get_msu_volume() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF4); /* MSU_VOLUME */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint8_t result = FPGA_RX_BYTE();
   FPGA_DESELECT();
   return result;
@@ -301,7 +308,6 @@ uint8_t get_msu_volume() {
 uint16_t get_msu_track() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF3); /* MSU_TRACK */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint16_t result = (FPGA_RX_BYTE()) << 8;
   result |= FPGA_RX_BYTE();
   FPGA_DESELECT();
@@ -311,7 +317,6 @@ uint16_t get_msu_track() {
 uint32_t get_msu_offset() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xF2); /* MSU_OFFSET */
-  FPGA_TX_BYTE(0x00); /* dummy */
   uint32_t result = (FPGA_RX_BYTE()) << 24;
   result |= (FPGA_RX_BYTE()) << 16;
   result |= (FPGA_RX_BYTE()) << 8;
@@ -323,8 +328,7 @@ uint32_t get_msu_offset() {
 uint32_t get_snes_sysclk() {
   FPGA_SELECT();
   FPGA_TX_BYTE(0xFE); /* GET_SYSCLK */
-  FPGA_TX_BYTE(0x00); /* dummy */
-  FPGA_TX_BYTE(0x00); /* dummy */
+  FPGA_TX_BYTE(0x00); /* dummy (copy current sysclk count to register) */
   uint32_t result = (FPGA_RX_BYTE()) << 24;
   result |= (FPGA_RX_BYTE()) << 16;
   result |= (FPGA_RX_BYTE()) << 8;
@@ -408,3 +412,11 @@ void fpga_set_features(uint8_t feat) {
   FPGA_DESELECT();
 }
 
+void fpga_set_213f(uint8_t data) {
+  printf("set 213f: %d\n", data);
+  FPGA_SELECT();
+  FPGA_TX_BYTE(0xee);
+  FPGA_TX_BYTE(data);
+  FPGA_DESELECT();
+}
+

src/fpga_spi.h

@@ -47,15 +47,14 @@
 #define FPGA_TX_BLOCK(x,y) spi_tx_block(x,y)
 #define FPGA_RX_BLOCK(x,y) spi_rx_block(x,y)
 
-#define FPGA_SPI_FAST()    spi_set_speed(SPI_SPEED_FPGA_FAST)
-#define FPGA_SPI_SLOW()    spi_set_speed(SPI_SPEED_FPGA_SLOW)
-
-#define FEAT_CX4           (1 << 4)
+#define FEAT_213F          (1 << 4)
 #define FEAT_MSU1          (1 << 3)
 #define FEAT_SRTC          (1 << 2)
 #define FEAT_ST0010        (1 << 1)
 #define FEAT_DSPX          (1 << 0)
 
+#define FEAT_CX4           (1 << 4)
+
 #define FPGA_WAIT_RDY()    do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)
 
 void fpga_spi_init(void);
@@ -90,4 +89,5 @@ void fpga_write_dspx_pgm(uint32_t data);
 void fpga_write_dspx_dat(uint16_t data);
 void fpga_dspx_reset(uint8_t reset);
 void fpga_set_features(uint8_t feat);
+void fpga_set_213f(uint8_t data);
 #endif

src/led.c

@@ -86,13 +86,16 @@ void toggle_write_led() {
 }
 
 void led_panic() {
+  led_std();
   while(1) {
-    LPC_GPIO2->FIODIR |= BV(4) | BV(5);
-    LPC_GPIO1->FIODIR |= BV(23);
-    delay_ms(350);
-    LPC_GPIO2->FIODIR &= ~(BV(4) | BV(5));
-    LPC_GPIO1->FIODIR &= ~BV(23);
-    delay_ms(350);
+    rdyled(1);
+    readled(1);
+    writeled(1);
+    delay_ms(100);
+    rdyled(0);
+    readled(0);
+    writeled(0);
+    delay_ms(100);
     cli_entrycheck();
   }
 }

src/lpc1754.ld

@@ -10,7 +10,7 @@ ENTRY(_start)
 
 MEMORY
 {
-  flash  (rx)  : ORIGIN = 0x00003100, LENGTH = 0x1cf00 /* leave room for bootldr + metadata */
+  flash  (rx)  : ORIGIN = 0x00002100, LENGTH = 0x1df00 /* leave room for bootldr + metadata */
   ram    (rwx) : ORIGIN = 0x10000000, LENGTH = 0x04000
   ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x04000
 }

src/main.c

@@ -26,6 +26,8 @@
 #include "smc.h"
 #include "msu1.h"
 #include "rtc.h"
+#include "sysinfo.h"
+#include "cfg.h"
 
 #define EMC0TOGGLE	(3<<4)
 #define MR0R		(1<<1)
@@ -34,6 +36,8 @@ int i;
 
 int sd_offload = 0, ff_sd_offload = 0, sd_offload_tgt = 0;
 int sd_offload_partial = 0;
+int sd_offload_start_mid = 0;
+int sd_offload_end_mid = 0;
 uint16_t sd_offload_partial_start = 0;
 uint16_t sd_offload_partial_end = 0;
 
@@ -42,8 +46,11 @@ extern volatile tick_t ticks;
 extern snes_romprops_t romprops;
 extern volatile int reset_changed;
 
+extern volatile cfg_t CFG;
+
 enum system_states {
-  SYS_RTC_STATUS = 0
+  SYS_RTC_STATUS = 0,
+  SYS_LAST_STATUS = 1
 };
 
 int main(void) {
@@ -75,7 +82,7 @@ int main(void) {
   LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
 led_pwm();
   sdn_init();
-  printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
+  printf("\n\nsd2snes mk.2\n============\nfw ver.: " CONFIG_VERSION "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
 printf("PCONP=%lx\n", LPC_SC->PCONP);
 
   file_init();
@@ -135,6 +142,11 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
     readled(0);
     writeled(0);
 
+    cfg_load();
+    cfg_save();
+    sram_writebyte(cfg_is_last_game_valid(), SRAM_STATUS_ADDR+SYS_LAST_STATUS);
+    cfg_get_last_game(file_lfn);
+    sram_writeblock(strrchr((const char*)file_lfn, '/')+1, SRAM_LASTGAME_ADDR, 256);
     *fs_path=0;
     uint32_t saved_dir_id;
     get_db_id(&saved_dir_id);
@@ -145,7 +157,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
     if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id) || (newcard)) {
       newcard = 0;
       /* generate fs footprint (interesting files only) */
-      uint32_t curr_dir_id = scan_dir(fs_path, 0, 0);
+      uint32_t curr_dir_id = scan_dir(fs_path, NULL, 0, 0);
       printf("curr dir id = %lx\n", curr_dir_id);
       /* files changed or no database found? */
       if((get_db_id(&saved_dir_id) != FR_OK)
@@ -154,7 +166,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
 	printf("saved dir id = %lx\n", saved_dir_id);
 	printf("rebuilding database...");
 	snes_bootprint("     rebuilding database ...    \0");
-	curr_dir_id = scan_dir(fs_path, 1, 0);
+	curr_dir_id = scan_dir(fs_path, NULL, 1, 0);
 	sram_writeblock(&curr_dir_id, SRAM_DB_ADDR, 4);
 	uint32_t endaddr, direndaddr;
 	sram_readblock(&endaddr, SRAM_DB_ADDR+4, 4);
@@ -167,25 +179,27 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
 	snes_bootprint("        saving database ...     \0");
 	save_sram((uint8_t*)"/sd2snes/sd2snes.db", endaddr-SRAM_DB_ADDR, SRAM_DB_ADDR);
 	save_sram((uint8_t*)"/sd2snes/sd2snes.dir", direndaddr-(SRAM_DIR_ADDR), SRAM_DIR_ADDR);
+        fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
 	printf("done\n");
       } else {
 	printf("saved dir id = %lx\n", saved_dir_id);
 	printf("different card, consistent db, loading db...\n");
-	load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
-	load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
+        fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
+	load_sram_offload((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
+	load_sram_offload((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
       }
       sram_writelong(curr_dir_id, SRAM_DIRID);
       sram_writelong(0x12345678, SRAM_SCRATCHPAD);
     } else {
       snes_bootprint("    same card, loading db...     \0");
       printf("same card, loading db...\n");
-      load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
-      load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
+      fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
+      load_sram_offload((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
+      load_sram_offload((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
     }
     /* cli_loop(); */
     /* load menu */
 
-    fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
     fpga_dspx_reset(1);
     uart_putc('(');
     load_rom((uint8_t*)"/sd2snes/menu.bin", SRAM_MENU_ADDR, 0);
@@ -200,24 +214,25 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
     if((rtc_state = rtc_isvalid()) != RTC_OK) {
       printf("RTC invalid!\n");
       sram_writebyte(0xff, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
-      set_bcdtime(0x20110401000000LL);
-      set_fpga_time(0x20110401000000LL);
+      set_bcdtime(0x20120701000000LL);
+      set_fpga_time(0x20120701000000LL);
       invalidate_rtc();
     } else {
       printf("RTC valid!\n");
       sram_writebyte(0x00, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
       set_fpga_time(get_bcdtime());
     }
-
+    sram_memset(SRAM_SYSINFO_ADDR, 13*40, 0x20);
     printf("SNES GO!\n");
     snes_reset(1);
-    delay_ms(1);
+    fpga_reset_srtc_state();
+    delay_ms(SNES_RESET_PULSELEN_MS);
+    sram_writebyte(32, SRAM_CMD_ADDR);
     snes_reset(0);
 
     uint8_t cmd = 0;
     uint64_t btime = 0;
     uint32_t filesize=0;
-    sram_writebyte(32, SRAM_CMD_ADDR);
     printf("test sram\n");
     while(!sram_reliable()) cli_entrycheck();
     printf("ok\n");
@@ -235,6 +250,9 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
 	case SNES_CMD_LOADROM:
 	  get_selected_name(file_lfn);
 	  printf("Selected name: %s\n", file_lfn);
+          cfg_save_last_game(file_lfn);
+          cfg_set_last_game_valid(1);
+          cfg_save();
 	  filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
 	  break;
 	case SNES_CMD_SETRTC:
@@ -243,8 +261,31 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
           /* set RTC */
           set_bcdtime(btime);
           set_fpga_time(btime);
-	  cmd=0; /* stay in loop */
+	  cmd=0; /* stay in menu loop */
 	  break;
+        case SNES_CMD_SYSINFO:
+          /* go to sysinfo loop */
+          sysinfo_loop();
+          cmd=0; /* stay in menu loop */
+          break;
+        case SNES_CMD_LOADSPC:
+          /* load SPC file */
+          get_selected_name(file_lfn);
+          printf("Selected name: %s\n", file_lfn);
+          filesize = load_spc(file_lfn, SRAM_SPC_DATA_ADDR, SRAM_SPC_HEADER_ADDR);
+          cmd=0; /* stay in menu loop */
+          break;
+        case SNES_CMD_RESET:
+          /* process RESET request from SNES */
+          printf("RESET requested by SNES\n");
+          snes_reset_pulse();
+          cmd=0; /* stay in menu loop */
+          break;
+        case SNES_CMD_LOADLAST:
+          cfg_get_last_game(file_lfn);
+          printf("Selected name: %s\n", file_lfn);
+          filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
+          break;
 	default:
 	  printf("unknown cmd: %d\n", cmd);
 	  cmd=0; /* unknown cmd: stay in loop */

src/memory.c

@@ -199,6 +199,8 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
   }
   set_mcu_addr(base_addr);
   file_open(filename, FA_READ);
+  ff_sd_offload=1;
+  sd_offload_tgt=0;
   f_lseek(&file_handle, romprops.offset);
   for(;;) {
     ff_sd_offload=1;
@@ -218,6 +220,8 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
     printf("BSX Flash cart image\n");
     printf("attempting to load BSX BIOS /sd2snes/bsxbios.bin...\n");
     load_sram_offload((uint8_t*)"/sd2snes/bsxbios.bin", 0x800000);
+    printf("attempting to load BS data file /sd2snes/bsxpage.bin...\n");
+    load_sram_offload((uint8_t*)"/sd2snes/bsxpage.bin", 0x900000);
     printf("Type: %02x\n", romprops.header.destcode);
     set_bsx_regs(0xc0, 0x3f);
     uint16_t rombase;
@@ -281,20 +285,97 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
   printf("done\n");
 
   romprops.fpga_features |= FEAT_SRTC;
+  romprops.fpga_features |= FEAT_213F;
 
+  fpga_set_213f(romprops.region);
   fpga_set_features(romprops.fpga_features);
 
   if(flags & LOADROM_WITH_RESET) {
     fpga_dspx_reset(1);
-    snes_reset(1);
-    delay_ms(10);
-    snes_reset(0);
+    snes_reset_pulse();
     fpga_dspx_reset(0);
   }
 
   return (uint32_t)filesize;
 }
 
+uint32_t load_spc(uint8_t* filename, uint32_t spc_data_addr, uint32_t spc_header_addr) {
+  DWORD filesize;
+  UINT bytes_read;
+  uint8_t data;
+  UINT j;
+
+  printf("%s\n", filename);
+
+  file_open(filename, FA_READ); /* Open SPC file */
+  if(file_res) return 0;
+  filesize = file_handle.fsize;
+  if (filesize < 65920) { /*  At this point, we care about filesize only */
+    file_close();         /* since SNES decides if it is an SPC file */
+    sram_writebyte(0, spc_header_addr);	/* If file is too small, destroy previous SPC header */
+    return 0;
+  }
+
+  set_mcu_addr(spc_data_addr);
+  f_lseek(&file_handle, 0x100L); /* Load 64K data segment */
+
+  for(;;) {
+    bytes_read = file_read();
+    if (file_res || !bytes_read) break;
+    FPGA_SELECT();
+    FPGA_TX_BYTE(0x98);
+    for(j=0; j<bytes_read; j++) {
+      FPGA_TX_BYTE(file_buf[j]);
+      FPGA_WAIT_RDY();
+    }
+    FPGA_DESELECT();
+  }
+
+  file_close();
+  file_open(filename, FA_READ); /* Reopen SPC file to reset file_getc state*/
+
+  set_mcu_addr(spc_header_addr);
+  f_lseek(&file_handle, 0x0L); /* Load 256 bytes header */
+
+  FPGA_SELECT();
+  FPGA_TX_BYTE(0x98);
+  for (j = 0; j < 256; j++) {
+    data = file_getc();
+    FPGA_TX_BYTE(data);
+    FPGA_WAIT_RDY();
+  }
+  FPGA_DESELECT();
+
+  file_close();
+  file_open(filename, FA_READ); /* Reopen SPC file to reset file_getc state*/
+
+  set_mcu_addr(spc_header_addr+0x100);
+  f_lseek(&file_handle, 0x10100L); /* Load 128 DSP registers */
+
+  FPGA_SELECT();
+  FPGA_TX_BYTE(0x98);
+  for (j = 0; j < 128; j++) {
+    data = file_getc();
+    FPGA_TX_BYTE(data);
+    FPGA_WAIT_RDY();
+  }
+  FPGA_DESELECT();
+  file_close(); /* Done ! */
+
+  /* clear echo buffer to avoid artifacts */
+  uint8_t esa = sram_readbyte(spc_header_addr+0x100+0x6d);
+  uint8_t edl = sram_readbyte(spc_header_addr+0x100+0x7d);
+  uint8_t flg = sram_readbyte(spc_header_addr+0x100+0x6c);
+  if(!(flg & 0x20) && (edl & 0x0f)) {
+    int echo_start = esa << 8;
+    int echo_length = (edl & 0x0f) << 11;
+    printf("clearing echo buffer %04x-%04x...\n", echo_start, echo_start+echo_length-1);
+    sram_memset(spc_data_addr+echo_start, echo_length, 0);
+  }
+
+  return (uint32_t)filesize;
+}
+
 uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr) {
   set_mcu_addr(base_addr);
   UINT bytes_read;

src/memory.h

@@ -30,24 +30,31 @@
 #include <arm/NXP/LPC17xx/LPC17xx.h>
 #include "smc.h"
 
-#define SRAM_ROM_ADDR (0x000000L)
-#define SRAM_SAVE_ADDR (0xE00000L)
+#define SRAM_ROM_ADDR           (0x000000L)
+#define SRAM_SAVE_ADDR          (0xE00000L)
 
-#define SRAM_MENU_ADDR (0xE00000L)
-#define SRAM_DB_ADDR (0xE20000L)
-#define SRAM_DIR_ADDR (0xE10000L)
-#define SRAM_CMD_ADDR (0xFF1000L)
-#define SRAM_PARAM_ADDR (0xFF1004L)
-#define SRAM_STATUS_ADDR (0xFF1100L)
-#define SRAM_MENU_SAVE_ADDR (0xFF0000L)
-#define SRAM_SCRATCHPAD (0xFFFF00L)
-#define SRAM_DIRID (0xFFFFF0L)
-#define SRAM_RELIABILITY_SCORE (0x100)
+#define SRAM_MENU_ADDR          (0xC00000L)
+#define SRAM_DIR_ADDR           (0xC10000L)
+#define SRAM_DB_ADDR            (0xC80000L)
+
+#define SRAM_SPC_DATA_ADDR      (0xFD0000L)
+#define SRAM_SPC_HEADER_ADDR    (0xFE0000L)
+
+#define SRAM_MENU_SAVE_ADDR     (0xFF0000L)
+#define SRAM_CMD_ADDR           (0xFF1000L)
+#define SRAM_PARAM_ADDR         (0xFF1004L)
+#define SRAM_STATUS_ADDR        (0xFF1100L)
+#define SRAM_SYSINFO_ADDR       (0xFF1200L)
+#define SRAM_LASTGAME_ADDR      (0xFF1420L)
+#define SRAM_SCRATCHPAD         (0xFFFF00L)
+#define SRAM_DIRID              (0xFFFFF0L)
+#define SRAM_RELIABILITY_SCORE  (0x100)
 
 #define LOADROM_WITH_SRAM	(1)
 #define LOADROM_WITH_RESET	(2)
 
 uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags);
+uint32_t load_spc(uint8_t* filename, uint32_t spc_data_addr, uint32_t spc_header_addr);
 uint32_t load_sram(uint8_t* filename, uint32_t base_addr);
 uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr);
 uint32_t load_sram_rle(uint8_t* filename, uint32_t base_addr);

src/msu1.c

@@ -13,22 +13,132 @@
 #include "smc.h"
 
 FIL msufile;
+FRESULT msu_res;
+DWORD msu_cltbl[CLTBL_SIZE] IN_AHBRAM;
+DWORD pcm_cltbl[CLTBL_SIZE] IN_AHBRAM;
+UINT msu_audio_bytes_read = 1024;
+UINT msu_data_bytes_read = 1;
+
 extern snes_romprops_t romprops;
+uint32_t msu_loop_point = 0;
+uint32_t msu_page1_start = 0x0000;
+uint32_t msu_page2_start = 0x2000;
+uint32_t msu_page_size = 0x2000;
+uint16_t fpga_status_prev;
+uint16_t fpga_status_now;
+
+enum msu_reset_state { MSU_RESET_NONE = 0, MSU_RESET_SHORT, MSU_RESET_LONG };
+
+void prepare_audio_track(uint16_t msu_track) {
+  /* open file, fill buffer */
+  char suffix[11];
+  f_close(&file_handle);
+  snprintf(suffix, sizeof(suffix), "-%d.pcm", msu_track);
+  strcpy((char*)file_buf, (char*)file_lfn);
+  strcpy(strrchr((char*)file_buf, (int)'.'), suffix);
+  DBG_MSU1 printf("filename: %s\n", file_buf);
+  if(f_open(&file_handle, (const TCHAR*)file_buf, FA_READ) == FR_OK) {
+    file_handle.cltbl = pcm_cltbl;
+    pcm_cltbl[0] = CLTBL_SIZE;
+    f_lseek(&file_handle, CREATE_LINKMAP);
+    f_lseek(&file_handle, 4L);
+    f_read(&file_handle, &msu_loop_point, 4, &msu_audio_bytes_read);
+    DBG_MSU1 printf("loop point: %ld samples\n", msu_loop_point);
+    ff_sd_offload=1;
+    sd_offload_tgt=1;
+    f_lseek(&file_handle, 8L);
+    set_dac_addr(0);
+    dac_pause();
+    dac_reset();
+    ff_sd_offload=1;
+    sd_offload_tgt=1;
+    f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE, &msu_audio_bytes_read);
+    /* clear busy bit */
+    set_msu_status(0x00, 0x28); /* set no bits, reset audio_busy + audio_error */
+  } else {
+    f_close(&file_handle);
+    set_msu_status(0x08, 0x20); /* reset audio_busy, set audio_error */
+  }
+}
+
+void prepare_data(uint32_t msu_offset) {
+  DBG_MSU1 printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start);
+  if(   ((msu_offset < msu_page1_start)
+     || (msu_offset >= msu_page1_start + msu_page_size))
+     && ((msu_offset < msu_page2_start)
+     || (msu_offset >= msu_page2_start + msu_page_size))) {
+    DBG_MSU1 printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start,
+           msu_page1_start+msu_page_size-1, msu_page2_start, msu_page2_start+msu_page_size-1);
+    /* "cache miss" */
+    /* fill buffer */
+    set_msu_addr(0x0);
+    sd_offload_tgt=2;
+    ff_sd_offload=1;
+    msu_res = f_lseek(&msufile, msu_offset);
+    DBG_MSU1 printf("seek to %08lx, res = %d\n", msu_offset, msu_res);
+    sd_offload_tgt=2;
+    ff_sd_offload=1;
+    msu_res = f_read(&msufile, file_buf, 16384, &msu_data_bytes_read);
+    DBG_MSU1 printf("read res = %d\n", msu_res);
+    DBG_MSU1 printf("read %d bytes\n", msu_data_bytes_read);
+    msu_reset(0x0);
+    msu_page1_start = msu_offset;
+    msu_page2_start = msu_offset + msu_page_size;
+  } else {
+    if (msu_offset >= msu_page1_start && msu_offset <= msu_page1_start + msu_page_size) {
+      msu_reset(0x0000 + msu_offset - msu_page1_start);
+      DBG_MSU1 printf("inside page1, new offset: %08lx\n", 0x0000 + msu_offset-msu_page1_start);
+      if(!(msu_page2_start == msu_page1_start + msu_page_size)) {
+        set_msu_addr(0x2000);
+        sd_offload_tgt=2;
+        ff_sd_offload=1;
+        f_read(&msufile, file_buf, 8192, &msu_data_bytes_read);
+        DBG_MSU1 printf("next page dirty (was: %08lx), loaded page2 (start now: ", msu_page2_start);
+        msu_page2_start = msu_page1_start + msu_page_size;
+        DBG_MSU1 printf("%08lx)\n", msu_page2_start);
+      }
+    } else if (msu_offset >= msu_page2_start && msu_offset <= msu_page2_start + msu_page_size) {
+      DBG_MSU1 printf("inside page2, new offset: %08lx\n", 0x2000 + msu_offset-msu_page2_start);
+      msu_reset(0x2000 + msu_offset - msu_page2_start);
+      if(!(msu_page1_start == msu_page2_start + msu_page_size)) {
+        set_msu_addr(0x0);
+        sd_offload_tgt=2;
+        ff_sd_offload=1;
+        f_read(&msufile, file_buf, 8192, &msu_data_bytes_read);
+        DBG_MSU1 printf("next page dirty (was: %08lx), loaded page1 (start now: ", msu_page1_start);
+        msu_page1_start = msu_page2_start + msu_page_size;
+        DBG_MSU1 printf("%08lx)\n", msu_page1_start);
+      }
+    } else printf("!!!WATWATWAT!!!\n");
+  }
+  /* clear bank bit to mask bank reset artifact */
+  fpga_status_now &= ~0x2000;
+  fpga_status_prev &= ~0x2000;
+  /* clear busy bit */
+  set_msu_status(0x00, 0x10);
+}
 
 int msu1_check_reset(void) {
   static tick_t rising_ticks;
 
   static uint8_t resbutton=0, resbutton_prev=0;
+  int result = MSU_RESET_NONE;
   resbutton = get_snes_reset();
   if(resbutton && !resbutton_prev) { /* push */
     rising_ticks = getticks();
   } else if(resbutton && resbutton_prev) { /* hold */
     if(getticks() > rising_ticks + 99) {
-      return 1;
+      result = MSU_RESET_LONG;
     }
+  } else if(!resbutton && resbutton_prev) { /* release */
+    if(getticks() < rising_ticks + 99) {
+      result = MSU_RESET_SHORT;
+    }
+  } else {
+    result = MSU_RESET_NONE;
   }
   resbutton_prev = resbutton;
-  return 0;
+  return result;
 }
 
 int msu1_check(uint8_t* filename) {
@@ -40,29 +150,40 @@ int msu1_check(uint8_t* filename) {
     printf("MSU datafile not found\n");
     return 0;
   }
+  msufile.cltbl = msu_cltbl;
+  msu_cltbl[0] = CLTBL_SIZE;
+  if(f_lseek(&msufile, CREATE_LINKMAP)) {
+    printf("Error creating FF linkmap for MSU file!\n");
+  }
   romprops.fpga_features |= FEAT_MSU1;
   return 1;
 }
 
 int msu1_loop() {
 /* it is assumed that the MSU file is already opened by calling msu1_check(). */
-  UINT bytes_read = 1024;
-  UINT bytes_read2 = 1;
-  FRESULT res;
   set_dac_vol(0x00);
   while(fpga_status() & 0x4000);
-  uint16_t fpga_status_prev = fpga_status();
-  uint16_t fpga_status_now = fpga_status();
   uint16_t dac_addr = 0;
   uint16_t msu_addr = 0;
   uint8_t msu_repeat = 0;
   uint16_t msu_track = 0;
   uint32_t msu_offset = 0;
-  uint32_t msu_loop_point = 0;
+  fpga_status_prev = fpga_status();
+  fpga_status_now = fpga_status();
+  int msu_res;
 
-  uint32_t msu_page1_start = 0x0000;
-  uint32_t msu_page2_start = 0x2000;
-  uint32_t msu_page_size = 0x2000;
+/*  set_msu_addr(0x0);
+  msu_reset(0x0);
+  ff_sd_offload=1;
+  sd_offload_tgt=2;
+  f_lseek(&msufile, 0L);
+  ff_sd_offload=1;
+  sd_offload_tgt=2;
+  f_read(&msufile, file_buf, 16384, &msu_data_bytes_read);
+*/
+  set_dac_addr(dac_addr);
+  dac_pause();
+  dac_reset();
 
   set_msu_addr(0x0);
   msu_reset(0x0);
@@ -71,13 +192,12 @@ int msu1_loop() {
   f_lseek(&msufile, 0L);
   ff_sd_offload=1;
   sd_offload_tgt=2;
-  f_read(&msufile, file_buf, 16384, &bytes_read2);
+  f_read(&msufile, file_buf, 16384, &msu_data_bytes_read);
 
-  set_dac_addr(dac_addr);
-  dac_pause();
-  dac_reset();
+  prepare_audio_track(0);
+  prepare_data(0);
 /* audio_start, data_start, 0, audio_ctrl[1:0], ctrl_start */
-  while(1){
+  while((msu_res = msu1_check_reset()) == MSU_RESET_NONE){
     cli_entrycheck();
     fpga_status_now = fpga_status();
 
@@ -86,171 +206,99 @@ int msu1_loop() {
       DBG_MSU1 printf("data\n");
       uint8_t pageno = 0;
       if(fpga_status_now & 0x2000) {
-	msu_addr = 0x0;
-	msu_page1_start = msu_page2_start + msu_page_size;
-	pageno = 1;
+        msu_addr = 0x0;
+        msu_page1_start = msu_page2_start + msu_page_size;
+        pageno = 1;
       } else {
-	msu_addr = 0x2000;
-	msu_page2_start = msu_page1_start + msu_page_size;
-	pageno = 2;
+        msu_addr = 0x2000;
+        msu_page2_start = msu_page1_start + msu_page_size;
+        pageno = 2;
       }
       set_msu_addr(msu_addr);
       sd_offload_tgt=2;
       ff_sd_offload=1;
-      res = f_read(&msufile, file_buf, 8192, &bytes_read2);
-      DBG_MSU1 printf("data buffer refilled. res=%d page1=%08lx page2=%08lx\n", res, msu_page1_start, msu_page2_start);
+      msu_res = f_read(&msufile, file_buf, 8192, &msu_data_bytes_read);
+      DBG_MSU1 printf("data buffer refilled. res=%d page1=%08lx page2=%08lx\n", msu_res, msu_page1_start, msu_page2_start);
     }
 
     /* Audio buffer refill */
     if((fpga_status_now & 0x4000) != (fpga_status_prev & 0x4000)) {
       if(fpga_status_now & 0x4000) {
-	dac_addr = 0;
+        dac_addr = 0;
       } else {
-	dac_addr = MSU_DAC_BUFSIZE/2;
+        dac_addr = MSU_DAC_BUFSIZE/2;
       }
       set_dac_addr(dac_addr);
       sd_offload_tgt=1;
       ff_sd_offload=1;
-      f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE/2, &bytes_read);
+      f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE/2, &msu_audio_bytes_read);
     }
 
     if(fpga_status_now & 0x0020) {
-      char suffix[11];
-
       /* get trackno */
       msu_track = get_msu_track();
-      printf("Audio requested! Track=%d\n", msu_track);
+      DBG_MSU1 printf("Audio requested! Track=%d\n", msu_track);
 
-      /* open file, fill buffer */
-      f_close(&file_handle);
-      snprintf(suffix, sizeof(suffix), "-%d.pcm", msu_track);
-      strcpy((char*)file_buf, (char*)file_lfn);
-      strcpy(strrchr((char*)file_buf, (int)'.'), suffix);
-      printf("filename: %s\n", file_buf);
-      f_open(&file_handle, (const TCHAR*)file_buf, FA_READ);
-      f_lseek(&file_handle, 4L);
-      f_read(&file_handle, &msu_loop_point, 4, &bytes_read);
-      printf("loop point: %ld samples\n", msu_loop_point);
-      ff_sd_offload=1;
-      sd_offload_tgt=1;
-      f_lseek(&file_handle, 8L);
-      set_dac_addr(0);
-      dac_pause();
-      dac_reset();
-      ff_sd_offload=1;
-      sd_offload_tgt=1;
-      f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE, &bytes_read);
-
-      /* clear busy bit */
-      set_msu_status(0x00, 0x20); /* set no bits, reset bit 5 */
+      prepare_audio_track(msu_track);
     }
 
     if(fpga_status_now & 0x0010) {
       /* get address */
       msu_offset=get_msu_offset();
-      printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start);
-      if(   ((msu_offset < msu_page1_start)
-	 || (msu_offset >= msu_page1_start + msu_page_size))
-	 && ((msu_offset < msu_page2_start)
-	 || (msu_offset >= msu_page2_start + msu_page_size))) {
-	printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start,
-	       msu_page1_start+msu_page_size-1, msu_page2_start, msu_page2_start+msu_page_size-1);
-	/* "cache miss" */
-	/* fill buffer */
-	set_msu_addr(0x0);
-	sd_offload_tgt=2;
-	ff_sd_offload=1;
-        res = f_lseek(&msufile, msu_offset);
-	DBG_MSU1 printf("seek to %08lx, res = %d\n", msu_offset, res);
-	sd_offload_tgt=2;
-	ff_sd_offload=1;
-
-        res = f_read(&msufile, file_buf, 16384, &bytes_read2);
-	DBG_MSU1 printf("read res = %d\n", res);
-	DBG_MSU1 printf("read %d bytes\n", bytes_read2);
-	msu_reset(0x0);
-	msu_page1_start = msu_offset;
-	msu_page2_start = msu_offset + msu_page_size;
-      } else {
-	if (msu_offset >= msu_page1_start && msu_offset <= msu_page1_start + msu_page_size) {
-	  msu_reset(0x0000 + msu_offset - msu_page1_start);
-	  DBG_MSU1 printf("inside page1, new offset: %08lx\n", 0x0000 + msu_offset-msu_page1_start);
-	  if(!(msu_page2_start == msu_page1_start + msu_page_size)) {
-	    set_msu_addr(0x2000);
-	    sd_offload_tgt=2;
-	    ff_sd_offload=1;
-	    f_read(&msufile, file_buf, 8192, &bytes_read2);
-	    DBG_MSU1 printf("next page dirty (was: %08lx), loaded page2 (start now: ", msu_page2_start);
-	    msu_page2_start = msu_page1_start + msu_page_size;
-	    DBG_MSU1 printf("%08lx)\n", msu_page2_start);
-	  }
-	} else if (msu_offset >= msu_page2_start && msu_offset <= msu_page2_start + msu_page_size) {
-	  DBG_MSU1 printf("inside page2, new offset: %08lx\n", 0x2000 + msu_offset-msu_page2_start);
-	  msu_reset(0x2000 + msu_offset - msu_page2_start);
-	  if(!(msu_page1_start == msu_page2_start + msu_page_size)) {
-	    set_msu_addr(0x0);
-	    sd_offload_tgt=2;
-	    ff_sd_offload=1;
-	    f_read(&msufile, file_buf, 8192, &bytes_read2);
-	    DBG_MSU1 printf("next page dirty (was: %08lx), loaded page1 (start now: ", msu_page1_start);
-	    msu_page1_start = msu_page2_start + msu_page_size;
-	    DBG_MSU1 printf("%08lx)\n", msu_page1_start);
-	  }
-	} else printf("!!!WATWATWAT!!!\n");
-      }
-      /* clear bank bit to mask bank reset artifact */
-      fpga_status_now &= ~0x2000;
-      fpga_status_prev &= ~0x2000;
-      /* clear busy bit */
-      set_msu_status(0x00, 0x10);
+      prepare_data(msu_offset);
     }
 
     if(fpga_status_now & 0x0001) {
       if(fpga_status_now & 0x0004) {
-	msu_repeat = 1;
-	set_msu_status(0x04, 0x01); /* set bit 2, reset bit 0 */
-	printf("Repeat set!\n");
+        msu_repeat = 1;
+        set_msu_status(0x04, 0x01); /* set bit 2, reset bit 0 */
+        DBG_MSU1 printf("Repeat set!\n");
       } else {
-	msu_repeat = 0;
-	set_msu_status(0x00, 0x05); /* set no bits, reset bit 0+2 */
-	printf("Repeat clear!\n");
+        msu_repeat = 0;
+        set_msu_status(0x00, 0x05); /* set no bits, reset bit 0+2 */
+        DBG_MSU1 printf("Repeat clear!\n");
       }
 
       if(fpga_status_now & 0x0002) {
-	printf("PLAY!\n");
-	set_msu_status(0x02, 0x01); /* set bit 0, reset bit 1 */
-	dac_play();
+        DBG_MSU1 printf("PLAY!\n");
+        set_msu_status(0x02, 0x01); /* set bit 0, reset bit 1 */
+        dac_play();
       } else {
-	printf("PAUSE!\n");
-	set_msu_status(0x00, 0x03); /* set no bits, reset bit 1+0 */
-	dac_pause();
+        DBG_MSU1 printf("PAUSE!\n");
+        set_msu_status(0x00, 0x03); /* set no bits, reset bit 1+0 */
+        dac_pause();
       }
     }
 
     fpga_status_prev = fpga_status_now;
 
     /* handle loop / end */
-    if(bytes_read < MSU_DAC_BUFSIZE / 2) {
+    if(msu_audio_bytes_read < MSU_DAC_BUFSIZE / 2) {
       ff_sd_offload=0;
       sd_offload=0;
       if(msu_repeat) {
-	printf("loop\n");
-	ff_sd_offload=1;
-	sd_offload_tgt=1;
-	f_lseek(&file_handle, 8L+msu_loop_point*4);
-	ff_sd_offload=1;
-	sd_offload_tgt=1;
-	f_read(&file_handle, file_buf, (MSU_DAC_BUFSIZE / 2) - bytes_read, &bytes_read);
+        DBG_MSU1 printf("loop\n");
+        ff_sd_offload=1;
+        sd_offload_tgt=1;
+        f_lseek(&file_handle, 8L+msu_loop_point*4);
+        ff_sd_offload=1;
+        sd_offload_tgt=1;
+        f_read(&file_handle, file_buf, (MSU_DAC_BUFSIZE / 2) - msu_audio_bytes_read, &msu_audio_bytes_read);
       } else {
-	set_msu_status(0x00, 0x02); /* clear play bit */
+        set_msu_status(0x00, 0x02); /* clear play bit */
+        dac_pause();
       }
-      bytes_read = MSU_DAC_BUFSIZE;
-    }
-    if(msu1_check_reset()) {
-      f_close(&msufile);
-      f_close(&file_handle);
-      return 1;
+      msu_audio_bytes_read = MSU_DAC_BUFSIZE;
     }
   }
+  f_close(&file_handle);
+  DBG_MSU1 printf("Reset ");
+  if(msu_res == MSU_RESET_LONG) {
+    f_close(&msufile);
+    DBG_MSU1 printf("to menu\n");
+    return 1;
+  }
+  DBG_MSU1 printf("game\n");
+  return 0;
 }
 /* END OF MSU1 STUFF */

src/sdnative.c

@@ -12,6 +12,7 @@
 #include "fileops.h"
 #include "bits.h"
 #include "fpga_spi.h"
+#include "memory.h"
 
 #define MAX_CARDS 1
 
@@ -111,14 +112,17 @@
 uint8_t cmd[6]={0,0,0,0,0,0};
 uint8_t rsp[17];
 uint8_t csd[17];
+uint8_t cid[17];
+diskinfo0_t di;
 uint8_t ccs=0;
 uint32_t rca;
 
-enum trans_state { TRANS_NONE = 0, TRANS_READ, TRANS_WRITE };
+enum trans_state { TRANS_NONE = 0, TRANS_READ, TRANS_WRITE, TRANS_MID };
 enum cmd_state { CMD_RSP = 0, CMD_RSPDAT, CMD_DAT };
 
 int during_blocktrans = TRANS_NONE;
 uint32_t last_block = 0;
+uint16_t last_offset = 0;
 
 volatile int sd_changed;
 
@@ -158,6 +162,17 @@ static uint32_t getbits(void *buffer, uint16_t start, int8_t bits) {
   return result;
 }
 
+void sdn_checkinit(BYTE drv) {
+  if(disk_state == DISK_CHANGED) {
+    disk_initialize(drv);
+  }
+}
+
+uint8_t* sdn_getcid() {
+  sdn_checkinit(0);
+  return cid;
+}
+
 static inline void wiggle_slow_pos(uint16_t times) {
   while(times--) {
     delay_us(2);
@@ -347,7 +362,7 @@ int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){
     default:
       rsplen = 6;
   }
-  if(dat && (buf==NULL)) {
+  if(dat && (buf==NULL) && !sd_offload) {
     printf("send_command_fast error: buf is null but data transfer expected.\n");
     return 0;
   }
@@ -374,7 +389,7 @@ int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){
   BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 0;
 
   if(rsplen) {
-    uint32_t timeout=2000000;
+    uint32_t timeout=200000;
     /* wait for response */
     while((BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) && --timeout) {
       wiggle_fast_neg1();
@@ -383,7 +398,6 @@ int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){
       printf("CMD%d timed out\n", cmdno);
       return 0; /* no response within timeout */
     }
-
     i=rsplen;
     uint8_t cmddata=0, datdata=0;
     while(i--) { /* process response */
@@ -448,18 +462,31 @@ int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){
       state=CMD_DAT;
       j=datcnt;
       datshift=8;
+      timeout=2000000;
       DBG_SD printf("response over, waiting for data...\n");
+      /* wait for data start bit on DAT0 */
       while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) {
         wiggle_fast_neg1();
       }
+// printf("%ld\n", timeout);
+      if(!timeout) printf("timed out!\n");
       wiggle_fast_neg1(); /* eat the start bit */
       if(sd_offload) {
         if(sd_offload_partial) {
+          if(sd_offload_partial_start != 0) {
+            if(during_blocktrans == TRANS_MID) sd_offload_partial_start |= 0x8000;
+          }
+          if(sd_offload_partial_end != 512) {
+            sd_offload_partial_end |= 0x8000;
+          }
+          DBG_SD printf("new partial %d - %d\n", sd_offload_partial_start, sd_offload_partial_end);
           fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end);
           fpga_sddma(sd_offload_tgt, 1);
-          sd_offload_partial=0;
+//          sd_offload_partial=0;
+          last_offset=sd_offload_partial_end;
         } else {
           fpga_sddma(sd_offload_tgt, 0);
+          last_offset=0;
         }
         state=CMD_RSP;
         return rsplen;
@@ -576,27 +603,31 @@ int acmd_fast(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* r
   return cmd_fast(cmd, param, crc, dat, rsp);
 }
 
-void sdn_checkinit(BYTE drv) {
-  if(disk_state == DISK_CHANGED) {
-    disk_initialize(drv);
-  }
-}
-
 int stream_datablock(uint8_t *buf) {
 //  uint8_t datshift=8;
   int j=512;
   uint8_t datdata=0;
   uint32_t timeout=1000000;
 
-  while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) {
-    wiggle_fast_neg1();
+  DBG_SD printf("stream_datablock: wait for ready...\n");
+  if(during_blocktrans != TRANS_MID) {
+    while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) {
+      wiggle_fast_neg1();
+    }
+    DBG_SD if(!timeout) printf("timeout!\n");
+    wiggle_fast_neg1(); /* eat the start bit */
   }
-  wiggle_fast_neg1(); /* eat the start bit */
   if(sd_offload) {
     if(sd_offload_partial) {
+      if(sd_offload_partial_start != 0) {
+        if(during_blocktrans == TRANS_MID) sd_offload_partial_start |= 0x8000;
+      }
+      if(sd_offload_partial_end != 512) {
+        sd_offload_partial_end |= 0x8000;
+      }
+      DBG_SD printf("str partial %d - %d\n", sd_offload_partial_start, sd_offload_partial_end);
       fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end);
       fpga_sddma(sd_offload_tgt, 1);
-      sd_offload_partial=0;
     } else {
       fpga_sddma(sd_offload_tgt, 0);
     }
@@ -748,6 +779,7 @@ void send_datablock(uint8_t *buf) {
 }
 
 void read_block(uint32_t address, uint8_t *buf) {
+  DBG_SD printf("read_block addr=%08lx last_addr=%08lx  offld=%d/%d offst=%04x offed=%04x last_off=%04x\n", address, last_block, sd_offload, sd_offload_partial, sd_offload_partial_start, sd_offload_partial_end, last_offset);
   if(during_blocktrans == TRANS_READ && (last_block == address-1)) {
 //uart_putc('r');
 #ifdef CONFIG_SD_DATACRC
@@ -761,7 +793,21 @@ void read_block(uint32_t address, uint8_t *buf) {
 #else
     stream_datablock(buf);
 #endif
-    last_block=address;
+    last_block = address;
+    last_offset = sd_offload_partial_end & 0x1ff;
+    if(sd_offload_partial && sd_offload_partial_end != 512) {
+      during_blocktrans = TRANS_MID;
+    }
+    sd_offload_partial = 0;
+  } else if (during_blocktrans == TRANS_MID
+             && last_block == address
+             && last_offset == sd_offload_partial_start
+             && sd_offload_partial) {
+    sd_offload_partial_start |= 0x8000;
+    stream_datablock(buf);
+    during_blocktrans = TRANS_READ;
+    last_offset = sd_offload_partial_end & 0x1ff;
+    sd_offload_partial = 0;
   } else {
     if(during_blocktrans) {
 //      uart_putc('_');
@@ -769,7 +815,8 @@ void read_block(uint32_t address, uint8_t *buf) {
       /* send STOP_TRANSMISSION to end an open READ/WRITE_MULTIPLE_BLOCK */
       cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp);
     }
-    last_block=address;
+    during_blocktrans = TRANS_READ;
+    last_block = address;
     if(!ccs) {
       address <<= 9;
     }
@@ -781,8 +828,9 @@ void read_block(uint32_t address, uint8_t *buf) {
 #else
     cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp);
 #endif
-    during_blocktrans = TRANS_READ;
+    sd_offload_partial = 0;
   }
+//  printf("trans state = %d\n", during_blocktrans);
 }
 
 void write_block(uint32_t address, uint8_t* buf) {
@@ -809,10 +857,38 @@ void write_block(uint32_t address, uint8_t* buf) {
   }
 }
 
+/* send STOP_TRANSMISSION after multiple block write
+ * and reset during_blocktrans status */
+
+void flush_write(void) {
+  cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp);
+  wait_busy();
+  during_blocktrans = TRANS_NONE;
+}
+
 //
 // Public functions
 //
 
+DRESULT sdn_ioctl(BYTE drv, BYTE cmd, void *buffer) {
+  DRESULT res;
+  if(drv >= MAX_CARDS) {
+    res = STA_NOINIT|STA_NODISK;
+  } else {
+    switch(cmd) {
+      case CTRL_SYNC:
+        flush_write();
+        res = RES_OK;
+        break;
+
+      default:
+        res = RES_PARERR;
+    }
+  }
+  return res;
+}
+DRESULT disk_ioctl(BYTE drv, BYTE cmd, void *buffer) __attribute__ ((weak, alias("sdn_ioctl")));
+
 DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) {
   uint8_t sec;
   if(drv >= MAX_CARDS) {
@@ -828,7 +904,7 @@ DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) {
 }
 DRESULT disk_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) __attribute__ ((weak, alias("sdn_read")));
 
-DRESULT sdn_initialize(BYTE drv) {
+DSTATUS sdn_initialize(BYTE drv) {
 
   uint8_t rsp[17]; /* space for response */
   int rsplen;
@@ -867,6 +943,9 @@ DRESULT sdn_initialize(BYTE drv) {
     if(rsp[1]&0x80) break;
   }
 
+  BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0;
+  BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1;
+
   ccs = (rsp[1]>>6) & 1; /* SDHC/XC */
 
   cmd_slow(ALL_SEND_CID, 0, 0x4d, NULL, rsp);
@@ -879,7 +958,11 @@ DRESULT sdn_initialize(BYTE drv) {
   }
 
   /* record CSD for getinfo */
-  cmd_slow(SEND_CSD, rca, 0, NULL, rsp);
+  cmd_slow(SEND_CSD, rca, 0, NULL, csd);
+  sdn_getinfo(drv, 0, &di);
+
+  /* record CID */
+  cmd_slow(SEND_CID, rca, 0, NULL, cid);
 
   /* select the card */
   if(cmd_slow(SELECT_CARD, rca, 0, NULL, rsp)) {
@@ -919,6 +1002,7 @@ void sdn_init(void) {
   BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
   BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1;
   BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN) = 1;
+  LPC_PINCON->PINMODE0 &= ~(BV(14) | BV(15));
   LPC_GPIO2->FIOPIN0 = 0x00;
   LPC_GPIO2->FIOMASK0 = ~0xf;
 }
@@ -1005,3 +1089,55 @@ void sdn_changed() {
   }
 }
 
+/* measure sd access time */
+void sdn_gettacc(uint32_t *tacc_max, uint32_t *tacc_avg) {
+  uint32_t sec1 = 0;
+  uint32_t sec2 = 0;
+  uint32_t time, time_max = 0;
+  uint32_t time_avg = 0LL;
+  uint32_t numread = 16384;
+  int i;
+  int sec_step = di.sectorcount / numread - 1;
+  if(disk_state == DISK_REMOVED) return;
+  sdn_checkinit(0);
+  for (i=0; i < 128; i++) {
+    sd_offload_tgt=2;
+    sd_offload=1;
+    sdn_read(0, NULL, 0, 1);
+    sd_offload_tgt=2;
+    sd_offload=1;
+    sdn_read(0, NULL, i*sec_step, 1);
+  }
+  for (i=0; i < numread && sram_readbyte(SRAM_CMD_ADDR) != 0x00 && disk_state != DISK_REMOVED; i++) {
+  /* reset timer */
+    LPC_RIT->RICTRL = 0;
+    sd_offload_tgt=2;
+    sd_offload=1;
+    sdn_read(0, NULL, sec1, 2);
+    sec1 += 2;
+  /* start timer */
+    LPC_RIT->RICOUNTER = 0;
+    LPC_RIT->RICTRL = BV(RITEN);
+    sd_offload_tgt=2;
+    sd_offload=1;
+    sdn_read(0, NULL, sec2, 1);
+  /* read timer */
+    time = LPC_RIT->RICOUNTER;
+/*    sd_offload_tgt=2;
+    sd_offload=1;
+    sdn_read(0, NULL, sec2, 15);*/
+    time_avg += time/16;
+    if(time > time_max) {
+      time_max = time;
+    }
+    sec2 += sec_step;
+  }
+  time_avg = time_avg / (i+1) * 16;
+  sd_offload=0;
+  LPC_RIT->RICTRL = 0;
+  if(disk_state != DISK_REMOVED) {
+    *tacc_max = time_max/(CONFIG_CPU_FREQUENCY / 1000000)-114;
+    *tacc_avg = time_avg/(CONFIG_CPU_FREQUENCY / 1000000)-114;
+  }
+}
+

src/sdnative.h

@@ -22,8 +22,10 @@ DSTATUS sdn_initialize(BYTE drv);
 DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count);
 DRESULT sdn_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count);
 DRESULT sdn_getinfo(BYTE drv, BYTE page, void *buffer);
+DRESULT sdn_ioctl(BYTE drv, BYTE cmd, void *buffer);
 
 void    sdn_changed(void);
-
+uint8_t* sdn_getcid(void);
+void    sdn_gettacc(uint32_t *tacc_max, uint32_t *tacc_avg);
 #endif
 

src/smc.c

@@ -34,28 +34,6 @@
 snes_romprops_t romprops;
 
 uint32_t hdr_addr[6] = {0xffb0, 0x101b0, 0x7fb0, 0x81b0, 0x40ffb0, 0x4101b0};
-uint8_t countAllASCII(uint8_t* data, int size) {
-  uint8_t res = 0;
-  do {
-    size--;
-    if(data[size] >= 0x20 && data[size] <= 0x7e) {
-      res++;
-    }
-  } while (size);
-  return res;
-}
-
-uint8_t countAllJISX0201(uint8_t* data, int size) {
-  uint8_t res = 0;
-  do {
-    size--;
-    if((data[size] >= 0x20 && data[size] <= 0x7e)
-       ||(data[size] >= 0xa1 && data[size] <= 0xdf)) {
-      res++;
-    }
-  } while (size);
-  return res;
-}
 
 uint8_t isFixed(uint8_t* data, int size, uint8_t value) {
   uint8_t res = 1;
@@ -72,7 +50,7 @@ uint8_t checkChksum(uint16_t cchk, uint16_t chk) {
   uint32_t sum = cchk + chk;
   uint8_t res = 0;
   if(sum==0x0000ffff) {
-    res = 0x10;
+    res = 1;
   }
   return res;
 }
@@ -87,32 +65,13 @@ void smc_id(snes_romprops_t* props) {
   props->fpga_features = 0;
   props->fpga_conf = NULL;
   for(uint8_t num = 0; num < 6; num++) {
-    if(!file_readblock(header, hdr_addr[num], sizeof(snes_header_t))
-       || file_res) {
-      score = 0;
-    } else {
-      score = smc_headerscore(header)/(1+(num&1));
-      if((file_handle.fsize & 0x2ff) == 0x200) {
-        if(num&1) {
-          score+=20;
-        } else {
-          score=0;
-        }
-      } else {
-        if(!(num&1)) {
-          score+=20;
-        } else {
-          score=0;
-        }
-      }
-    }
-//printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */
+    score = smc_headerscore(hdr_addr[num], header);
+    printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */
     if(score>=maxscore) {
       score_idx=num;
       maxscore=score;
     }
   }
-
   if(score_idx & 1) {
     props->offset = 0x200;
   } else {
@@ -135,6 +94,7 @@ void smc_id(snes_romprops_t* props) {
           props->romsize_bytes = 0x100000;
           props->expramsize_bytes = 0;
           props->mapper_id = 3; /* BS-X Memory Map */
+          props->region = 0; /* BS-X only existed in Japan */
           return;
         }
       }
@@ -163,7 +123,7 @@ void smc_id(snes_romprops_t* props) {
           (header->map == 0x30 && header->carttype == 0x05 && header->licensee != 0xb2)) {
         props->has_dspx = 1;
         props->fpga_features |= FEAT_DSPX;
-        // Pilotwings uses DSP1 instead of DSP1B
+        /* Pilotwings uses DSP1 instead of DSP1B */
         if(!memcmp(header->name, "PILOTWINGS", 10)) {
           props->dsp_fw = DSPFW_1;
         } else {
@@ -227,7 +187,14 @@ void smc_id(snes_romprops_t* props) {
       }
   }
   if(header->romsize == 0 || header->romsize > 13) {
-    header->romsize = 13;
+    props->romsize_bytes = 1024;
+    header->romsize = 0;
+    if(file_handle.fsize >= 1024) {
+      while(props->romsize_bytes < file_handle.fsize-1) {
+        header->romsize++;
+        props->romsize_bytes <<= 1;
+      }
+    }
   }
   props->ramsize_bytes = (uint32_t)1024 << header->ramsize;
   props->romsize_bytes = (uint32_t)1024 << header->romsize;
@@ -236,17 +203,86 @@ void smc_id(snes_romprops_t* props) {
   if(props->ramsize_bytes > 32768 || props->ramsize_bytes < 2048) {
     props->ramsize_bytes = 0;
   }
+  props->region = (header->destcode <= 1 || header->destcode >= 13) ? 0 : 1;
+
 /*dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); */
 }
 
-uint8_t smc_headerscore(snes_header_t* header) {
-  uint8_t score=0;
-  score += countAllASCII(header->maker, sizeof(header->maker));
-  score += countAllASCII(header->gamecode, sizeof(header->gamecode));
-  score += isFixed(header->fixed_00, sizeof(header->fixed_00), 0x00);
-  score += countAllJISX0201(header->name, sizeof(header->name));
-  score += 3*isFixed(&header->licensee, sizeof(header->licensee), 0x33);
-  score += checkChksum(header->cchk, header->chk);
+uint8_t smc_headerscore(uint32_t addr, snes_header_t* header) {
+  int score=0;
+  uint8_t reset_inst;
+  uint16_t header_offset;
+  if((addr & 0xfff) == 0x1b0) {
+    header_offset = 0x200;
+  } else {
+    header_offset = 0;
+  }
+  if((file_readblock(header, addr, sizeof(snes_header_t)) < sizeof(snes_header_t))
+     || file_res) {
+    return 0;
+  }
+  uint8_t mapper = header->map & ~0x10;
+  uint16_t resetvector = header->vect_reset; /* not endian safe! */
+  uint32_t file_addr = (((addr - header_offset) & ~0x7fff) | (resetvector & 0x7fff)) + header_offset;
+  if(resetvector < 0x8000) return 0;
+
+  score += 2*isFixed(&header->licensee, sizeof(header->licensee), 0x33);
+  score += 4*checkChksum(header->cchk, header->chk);
+  if(header->carttype < 0x08) score++;
+  if(header->romsize < 0x10) score++;
+  if(header->ramsize < 0x08) score++;
+  if(header->destcode < 0x0e) score++;
+
+  if((addr-header_offset) == 0x007fc0 && mapper == 0x20) score += 2;
+  if((addr-header_offset) == 0x00ffc0 && mapper == 0x21) score += 2;
+  if((addr-header_offset) == 0x007fc0 && mapper == 0x22) score += 2;
+  if((addr-header_offset) == 0x40ffc0 && mapper == 0x25) score += 2;
+
+  file_readblock(&reset_inst, file_addr, 1);
+  switch(reset_inst) {
+    case 0x78: /* sei */
+    case 0x18: /* clc */
+    case 0x38: /* sec */
+    case 0x9c: /* stz abs */
+    case 0x4c: /* jmp abs */
+    case 0x5c: /* jml abs */
+      score += 8;
+      break;
+
+    case 0xc2: /* rep */
+    case 0xe2: /* sep */
+    case 0xad: /* lda abs */
+    case 0xae: /* ldx abs */
+    case 0xac: /* ldy abs */
+    case 0xaf: /* lda abs long */
+    case 0xa9: /* lda imm */
+    case 0xa2: /* ldx imm */
+    case 0xa0: /* ldy imm */
+    case 0x20: /* jsr abs */
+    case 0x22: /* jsl abs */
+      score += 4;
+      break;
+
+    case 0x40: /* rti */
+    case 0x60: /* rts */
+    case 0x6b: /* rtl */
+    case 0xcd: /* cmp abs */
+    case 0xec: /* cpx abs */
+    case 0xcc: /* cpy abs */
+      score -= 4;
+      break;
+
+    case 0x00: /* brk */
+    case 0x02: /* cop */
+    case 0xdb: /* stp */
+    case 0x42: /* wdm */
+    case 0xff: /* sbc abs long indexed */
+      score -= 8;
+      break;
+  }
+
+  if(score && addr > 0x400000) score += 4;
+  if(score < 0) score = 0;
   return score;
 }
 

src/smc.h

@@ -54,6 +54,19 @@ typedef struct _snes_header {
   uint8_t ver;          /* 0xDB */
   uint16_t cchk;        /* 0xDC */
   uint16_t chk;         /* 0xDE */
+  uint32_t pad1;        /* 0xE0 */
+  uint16_t vect_cop16;	/* 0xE4 */
+  uint16_t vect_brk16;  /* 0xE6 */
+  uint16_t vect_abt16;  /* 0xE8 */
+  uint16_t vect_nmi16;  /* 0xEA */
+  uint16_t vect_irq16;  /* 0xEE */
+  uint16_t pad2;        /* 0xF0 */
+  uint16_t vect_cop8;   /* 0xF4 */
+  uint32_t pad3;        /* 0xF6 */
+  uint16_t vect_abt8;   /* 0xF8 */
+  uint16_t vect_nmi8;   /* 0xFA */
+  uint16_t vect_reset;  /* 0xFC */
+  uint16_t vect_brk8;   /* 0xFE */
 } snes_header_t;
 
 typedef struct _snes_romprops {
@@ -66,14 +79,15 @@ typedef struct _snes_romprops {
   const uint8_t* dsp_fw;      /* DSP (NEC / Hitachi) ROM filename */
   const uint8_t* fpga_conf;   /* FPGA config file to load (default: base) */
   uint8_t has_dspx;           /* DSP[1-4] presence flag */
-  uint8_t has_st0010;         /* st0010 presence flag (additional to dspx)*/
+  uint8_t has_st0010;         /* st0010 presence flag (additional to dspx) */
   uint8_t has_msu1;           /* MSU1 presence flag */
   uint8_t has_cx4;            /* CX4 presence flag */
   uint8_t fpga_features;      /* feature/peripheral enable bits*/
+  uint8_t region;             /* game region (derived from destination code) */
   snes_header_t header;       /* original header from ROM image */
 } snes_romprops_t;
 
 void smc_id(snes_romprops_t*);
-uint8_t smc_headerscore(snes_header_t*);
+uint8_t smc_headerscore(uint32_t addr, snes_header_t* header);
 
 #endif